A fast transient response high power supply rejection off-chip capacitor-free multi-loop control LDO

Abstract

The application discloses a slice-out-capacitor-free multi-loop control LDO with fast transient response and high power supply rejection, which comprises a fast loop, a slow loop and an RC module. P The fast loop is nested in the slow loop; the slow loop comprises an AB class error amplifier A1, a power tube M P and a full-differential error amplifier A2; the AB class error amplifier is used as the input of the gate of the power tube M P , and the charging and discharging current size of the power tube gate capacitor can change with the size of the differential input of the AB class error amplifier A1. Therefore, a higher conversion rate can be achieved, and the transient response performance of the LDO is improved; the current source of the AB class error amplifier in the fast loop is controlled by the slow loop. The slow loop makes the PSR performance of the overall circuit more dependent on the full-differential error amplifier A2 of the slow loop, so that the fast transient response can be achieved while still having high power supply rejection characteristics.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a fast transient response, high power supply rejection, capacitor-free multi-loop control LDO. Background Technology

[0002] Power management integrated circuits play a crucial role in portable electronic devices such as smartphones, tablets, and other digital-assisted processing devices. These system-on-chip applications often require different types of power management units. Switching power supply regulators, due to their high efficiency, are commonly used as power storage interfaces; however, this generates significant switching noise. To filter out this noise and provide a clean power supply to the module, low-dropout linear regulators (LDOs) are typically cascaded after the switching power supply regulator. Traditional capacitorless LDOs have significant deficiencies in transient response and power rejection characteristics, thus requiring circuit design to improve these features.

[0003] Existing techniques for improving power supply rejection characteristics include loop gain enhancement and noise current replication. However, these techniques can only improve transient response or power supply rejection characteristics in one aspect. Therefore, in current LDOs without external capacitors, it is impossible to achieve fast transient response while still maintaining high power supply rejection characteristics at a certain power consumption. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a capacitorless, multi-loop controlled LDO with fast transient response and high power supply rejection. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A fast transient response, high power supply rejection, capacitor-free, multi-loop controlled LDO, comprising:

[0006] Fast loop, slow loop, and RC module; among them,

[0007] The fast loop includes: a Class AB error amplifier A1 and a power transistor M. P ;

[0008] The fast loop is nested within the slow loop; the slow loop includes: the Class AB error amplifier A1 and the power transistor M. P and fully differential error amplifier A2;

[0009] In the fast loop, the Class AB error amplifier A1 calculates the output V. OUT The voltage and the reference voltage V REF The difference is used to output an error current, and this error current is used as the power transistor M. P The charging and discharging current of the gate capacitor is used to improve the power transistor M. PThe switching rate of the gate capacitance enables a fast transient response;

[0010] In the slow loop, the fully differential error amplifier A2 calculates the output V. OUT The voltage and the reference voltage V REF The difference is used to obtain an error voltage, which is then converted into the gate voltage of the current source controlling the Class AB error amplifier A1. This voltage is used to control and change the error current, thereby controlling and changing the charging and discharging current, and ultimately changing the power transistor M. P The gate voltage of the power transistor M P The overdrive voltage and the power transistor M P The current flowing through it causes the output terminal V to... OUT The voltage recovers to the reference voltage V. REF The size of the power supply is adjusted to achieve the purpose of power suppression;

[0011] The RC module includes a Miller capacitor CC and a resistor RZ; the RC module uses the Miller capacitor CC for frequency compensation and the resistor RZ for zero-point compensation to improve the phase margin and stability of the fast loop.

[0012] In one embodiment of the present invention, the Miller capacitance C C The first end is connected to the power transistor M P The gate connection, the Miller capacitor C C The second terminal is connected to the resistor R Z The first end is connected;

[0013] The resistor R Z The second terminal is connected to the power transistor M P The drain connection.

[0014] In one embodiment of the present invention, the RC module utilizes the Miller capacitance C in the RC module. C Frequency compensation is performed using the resistor R in the RC module. Z Zero-point compensation includes:

[0015] In the power transistor M P The gate and drain terminals utilize Miller capacitance C C Frequency compensation is performed so that the power transistor M P The gate terminal node serves as the dominant pole of the fast loop, and the output terminal V OUT As the secondary dominant pole of the fast loop, it simultaneously reduces the output impedance, pushing both the dominant and secondary poles to higher frequencies and increasing the phase margin; utilizing the resistor R Z Zero-point compensation will be performed due to the Miller capacitance C CThe generated right-half-plane zeros are converted into left-half-plane zeros, increasing the phase margin and thus improving stability.

[0016] In one embodiment of the present invention, the circuit connection relationship of the fast loop includes:

[0017] The inverting input of the class AB error amplifier A1 is connected to the reference voltage V. REF The positive input terminal of the class AB error amplifier A1 is connected to the output terminal V. OUT The output terminal of the Class AB error amplifier A1 is connected to the power transistor M. P The gate connection is such that the first input terminal of the class AB error amplifier A1 is connected to the positive output terminal of the fully differential error amplifier A2 in the slow loop, and the second input terminal of the class AB error amplifier A1 is connected to the inverted output terminal of the fully differential error amplifier A2 in the slow loop.

[0018] The power transistor M P The source of the power transistor M is connected to VDD. P The drain and the output terminal V OUT connect.

[0019] In one embodiment of the present invention, the class AB error amplifier A1 includes:

[0020] Input transistor GmL, input transistor GmH, auxiliary operational amplifier module, and current summing circuit.

[0021] In one embodiment of the present invention, the auxiliary operational amplifier module includes: an auxiliary operational amplifier A. AUX and MOSFET M AUX ;in,

[0022] The auxiliary operational amplifier A AUX The inverting input terminal is connected to the reference voltage V. REF The auxiliary operational amplifier A AUX The positive input terminal of the MOS transistor M AUX The drain connection of the auxiliary operational amplifier A AUX The output terminal is connected to the MOS transistor M AUX Gate connection;

[0023] The MOS transistor M AUX The source is connected to the VDD.

[0024] In one embodiment of the present invention, the input tube GmL includes: MOS transistor M5 and MOS transistor M6; wherein,

[0025] The source of the MOS transistor M5 is connected to the source of the MOS transistor M... AUXThe drain of the MOSFET M5 is connected to the gate of the MOSFET M6.

[0026] The source of the MOSFET M6 is connected to the output terminal V. OUT The gate of the MOS transistor M6 is connected to the drain of the MOS transistor M6.

[0027] In one embodiment of the present invention, the input transistor GmH includes: MOSFET M7 and MOSFET M8; wherein,

[0028] The source of the MOSFET M7 is connected to the MOSFET M AUX The drain of the MOS transistor M7 is connected to the gate of the MOS transistor M7.

[0029] The source of the MOSFET M8 is connected to the output terminal V. OUT The gate of the MOS transistor M8 is connected to the gate of the MOS transistor M7.

[0030] In one embodiment of the present invention, the current summing circuit includes:

[0031] MOSFET M1, MOSFET M2, MOSFET M3, MOSFET M4, MOSFET M9, MOSFET M 10 MOSFET M 11 and MOSFET M 12 ;in,

[0032] The gate voltage is the gate voltage of MOS transistors M1 and M2, which serve as current sources in the Class AB error amplifier A1.

[0033] The source of the MOS transistor M1 is grounded, the gate of the MOS transistor M1 is connected to the inverting output terminal of the fully differential error amplifier A2, and the drain of the MOS transistor M1 is connected to the drain of the MOS transistor M6.

[0034] The source of the MOS transistor M2 is grounded, the gate of the MOS transistor M2 is connected to the positive output terminal of the fully differential error amplifier A2, and the drain of the MOS transistor M2 is connected to the drain of the MOS transistor M7.

[0035] The source of the MOS transistor M3 is grounded, the gate of the MOS transistor M3 is connected to the drain of the MOS transistor M3, and the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M5.

[0036] The source of the MOS transistor M4 is grounded, the gate of the MOS transistor M4 is connected to the drain of the MOS transistor M4, and the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M8.

[0037] The source of MOSFET M9 is grounded, the gate of MOSFET M9 is connected to the gate of MOSFET M4, and the drain of MOSFET M9 is connected to the gate of MOSFET M4. 11 Drain connection;

[0038] The MOS transistor M 10 The source of the MOS transistor is grounded. 10 The gate of the transistor is connected to the gate of the MOS transistor M3. 10 The drain of the power transistor M P Gate connection;

[0039] The MOS transistor M 11 The source of the MOSFET is connected to VDD. 11 The gate of the MOS transistor M 11 Drain connection;

[0040] The MOS transistor M 12 The source of the MOSFET is connected to VDD. 12 The gate of the MOS transistor M 11 The gate connection of the MOS transistor M 12 The drain of the power transistor M P The gate connection.

[0041] In one embodiment of the present invention, the operation of a fast transient response, high power supply rejection, capacitor-free, multi-loop controlled LDO includes:

[0042] When the load changes from light load to heavy load, the output terminal V OUT As the voltage decreases, the class AB error amplifier A1 outputs the error current, while the fully differential error amplifier A2 outputs its gate voltage to control the increase of the error current. The power transistor M... P The gate discharge current increases, causing the power transistor M... P As the gate voltage decreases, the power transistor M P As the overdrive voltage increases, the power transistor M... P The increased current at the output terminal V OUT The voltage recovers to the reference voltage V. REF Size;

[0043] When the load changes from heavy load to light load, the output terminal V OUT As the voltage increases, the class AB error amplifier A1 outputs the error current, while the fully differential error amplifier A2 outputs its gate voltage to control the increase of the error current. The power transistor M... P The increased charging current at the gate causes the power transistor M to...P As the gate voltage increases, the power transistor M P The overdrive voltage decreases, and the power transistor M P The current flowing through decreases, causing the output terminal V to... OUT The voltage recovers to the reference voltage V. REF Size.

[0044] The beneficial effects of this invention are:

[0045] This invention employs multi-loop control, consisting of a slow loop based on a fully differential error amplifier A2 and a fast loop based on a class AB error amplifier A1. The class AB error amplifier A1 is used as the power transistor M. P The charging and discharging current of the power transistor's gate capacitor varies with the magnitude of the differential input of the Class AB error amplifier A1. Therefore, a high slew rate can be achieved with low quiescent power consumption, improving the transient response performance of the LDO. Furthermore, this invention uses a fully differential error amplifier A2 as a slow loop to control the current source of the Class AB error amplifier A1 in the fast loop. The added slow loop makes the overall circuit's PSR (Power Supply Rejection) performance more dependent on the fully differential error amplifier A2 in the slow loop, thus achieving fast transient response while maintaining high power supply rejection characteristics at low power consumption. Attached Figure Description

[0046] Figure 1 The circuit structure diagram of the FVF LDO using the existing method is shown below;

[0047] Figure 2 This is a system architecture diagram of a fast transient response, high power supply rejection, capacitor-free, multi-loop controlled LDO provided in an embodiment of the present invention;

[0048] Figure 3 This is a circuit diagram of a fast transient response, high power supply rejection, capacitor-free, multi-loop controlled LDO provided in an embodiment of the present invention.

[0049] Figure 4 A transient response waveform diagram of an LDO circuit provided in an embodiment of the present invention;

[0050] Figure 5 Bode plot of a fast loop of an LDO circuit under different load currents, provided in an embodiment of the present invention;

[0051] Figure 6 Bode plot of a slow loop of an LDO circuit under different load currents, provided in an embodiment of the present invention;

[0052] Figure 7The PSR simulation diagrams of an LDO circuit with slow loop access and slow loop not accessed, provided in an embodiment of the present invention, show different loads. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] To facilitate understanding, the existing technology will be introduced first.

[0055] See Figure 1 This diagram shows the main block diagram of an FVF (Flipped Voltage Follower) LDO circuit in existing capacitorless LDO technology, which features high transient response. Compared to traditional on-chip LDOs, the FVF structure adds a fast loop to regulate the output Vout. MOSFET M1 senses transient changes in Vout and quickly transmits the error to the gate of the power transistor, thereby rapidly regulating the power transistor current. The slow loop of this structure is formed by an EA (Error Amplifier). The output Vout is divided by a feedback resistor and transmitted to the input of EA. EA senses the error between the divided input voltage and Vref, regulating the gate of M1 to change the output voltage. The bandwidth of the fast loop is generally higher than that of the slow loop, thus accelerating the circuit's response to the output and achieving better transient performance. However, under certain power consumption conditions, it cannot achieve a fast transient response while still maintaining high power supply rejection characteristics.

[0056] This invention provides a fast transient response, high power supply rejection, capacitor-free, multi-loop control LDO, such as... Figure 2 As shown, it includes:

[0057] Fast loop, slow loop, and RC module; among them,

[0058] The fast loop includes: Class AB error amplifier A1 and power transistor M. P ;

[0059] The fast loop is nested within the slow loop; the slow loop includes: Class AB error amplifier A1 and power transistor M. P and fully differential error amplifier A2;

[0060] In a fast loop, the class AB error amplifier A1 calculates the output V...OUT The voltage and the reference voltage V REF The difference is used to output the error current, and the error current is used as the power transistor M. P The charging and discharging current of the gate capacitor is used to improve the power transistor M. P The switching rate of the gate capacitance enables a fast transient response;

[0061] In the slow loop, the fully differential error amplifier A2 calculates the output V. OUT The voltage and the reference voltage V REF The difference is used to obtain an error voltage, which is then converted into the gate voltage of the current source controlling the Class AB error amplifier A1. This voltage is used to control and change the error current, thereby controlling and changing the charging and discharging current, and ultimately changing the power transistor M. P Gate voltage, power transistor M P Overdrive voltage and power transistor M P The current flowing through it causes the output terminal V to... OUT The voltage recovers to the reference voltage V. REF The size of the power supply is adjusted to achieve the purpose of power suppression;

[0062] The RC module includes Miller capacitors C C and resistance R Z The RC module utilizes Miller capacitance C. C Frequency compensation is performed using resistor R. Z Zero-point compensation is performed to improve the phase margin and stability of the fast loop.

[0063] This invention employs multi-loop control, consisting of a slow-response loop based on a fully differential error amplifier A2 and a fast loop based on a class AB error amplifier A1. The class AB error amplifier A1 is used as the power transistor M. P The charging and discharging current of the power transistor's gate capacitor varies with the magnitude of the differential input of the Class AB error amplifier A1. Therefore, a high slew rate can be achieved with low quiescent power consumption, improving the transient response performance of the LDO. Furthermore, this invention uses a fully differential error amplifier A2 as a slow loop to control the current source of the Class AB error amplifier A1 in the fast loop. The added slow loop makes the overall circuit's PSR performance more dependent on the fully differential error amplifier A2 in the slow loop, thus achieving fast transient response while maintaining high power supply rejection characteristics at low power consumption.

[0064] For ease of understanding, the embodiments of the present invention will be described in three parts below: fast loop, slow loop, and RC module.

[0065] RC module

[0066] Please see Figure 2The RC module includes: Miller capacitor C C and resistance R Z ;in,

[0067] Miller capacitance C C The first terminal is connected to the power transistor M P Gate connection, Miller capacitance C C The second terminal is connected to resistor R Z The first end is connected;

[0068] resistor R Z The second terminal is connected to the power transistor M P The drain connection.

[0069] In this embodiment of the invention, the RC module utilizes the Miller capacitor C in the RC module. C Frequency compensation is performed using resistor R in the RC module. Z Zero-point compensation includes:

[0070] In power transistor M P The gate and drain terminals utilize Miller capacitance C C Perform frequency compensation so that the power transistor M P The gate node is used as the dominant pole of the fast loop, and the output V OUT As the secondary dominant pole of the fast loop, it simultaneously reduces the output impedance, pushing both the dominant and secondary poles to higher frequencies and increasing the phase margin; utilizing resistor R Z Zero-point compensation will be performed due to the Miller capacitance C C The generated right-half-plane zeros are converted into left-half-plane zeros, increasing the phase margin and thus improving stability.

[0071] Specifically, Miller capacitor C is used at the gate and drain terminals of the power transistor. C Perform frequency compensation so that the power transistor M P The gate node serves as the dominant pole of the fast loop, and the output terminal serves as the secondary dominant pole. Simultaneously, reducing the output impedance pushes the secondary dominant pole away to a higher frequency, increasing the phase margin. A resistor R is added. Z As a zero-point compensation, the right-half-plane zeros caused by Miller capacitance are converted to left-half-plane zeros, increasing the phase margin. Increased phase margin makes the loop more stable, and appropriately increasing the phase margin can also reduce the settling time.

[0072] Fast Ring Road

[0073] Please see Figure 2 The circuit connections of the fast loop include:

[0074] The inverting input of the Class AB error amplifier A1 is connected to a reference voltage V. REF The positive input terminal and output terminal V of the class AB error amplifier A1OUT Connection: The output of Class AB error amplifier A1 is connected to the power transistor M. P The gate connection is such that the first input terminal of the AB class error amplifier A1 is connected to the positive output terminal of the fully differential error amplifier A2 in the slow loop, and the second input terminal of the AB class error amplifier A1 is connected to the inverted output terminal of the fully differential error amplifier A2 in the slow loop.

[0075] Power transistor M P The source of the power transistor M is connected to VDD. P The drain and output terminal V OUT connect.

[0076] The LDO circuit diagram of this invention embodiment is as follows: Figure 3 As shown, the following is a detailed explanation.

[0077] See Figure 3 The Class AB error amplifier A1 includes:

[0078] Input transistor GmL, input transistor GmH, auxiliary operational amplifier module, and current summing circuit.

[0079] The auxiliary operational amplifier module includes: auxiliary operational amplifier A AUX and MOSFET M AUX ;in,

[0080] Auxiliary operational amplifier A AUX The inverting input terminal is connected to the reference voltage V. REF Auxiliary operational amplifier A AUX The positive input terminal of the MOSFET M AUX The drain connection, auxiliary operational amplifier A AUX The output terminal of the MOSFET M AUX Gate connection;

[0081] MOSFET M AUX The source is connected to VDD.

[0082] See Figure 3 The input transistor GmL includes: MOS transistor M5 and MOS transistor M6; among which,

[0083] The source of MOSFET M5 and MOSFET M AUX The drain of MOSFET M5 is connected to the gate of MOSFET M6.

[0084] The source and output terminals V of MOSFET M6 OUT The gate of MOSFET M6 is connected to the drain of MOSFET M6.

[0085] See Figure 3The input transistors GmH include: MOSFET M7 and MOSFET M8; among them,

[0086] The source of MOSFET M7 and MOSFET M AUX The drain of MOSFET M7 is connected to the gate of MOSFET M7.

[0087] The source and output terminals V of MOSFET M8 OUT The gate of MOSFET M8 is connected to the gate of MOSFET M7.

[0088] Auxiliary operational amplifier A AUX Provide bias for the Class AB error amplifier A1, with a bias voltage of V. MIR .

[0089] See Figure 3 The current summing circuit includes:

[0090] MOSFET M1, MOSFET M2, MOSFET M3, MOSFET M4, MOSFET M9, MOSFET M 10 MOSFET M 11 and MOSFET M 12 Wherein, the gate voltage is the gate voltage of MOS transistors M1 and M2, which serve as current sources in the class AB error amplifier A1;

[0091] The source of MOSFET M1 is grounded, the gate of MOSFET M1 is connected to the inverting output of the fully differential error amplifier A2, and the drain of MOSFET M1 is connected to the drain of MOSFET M6.

[0092] The source of MOSFET M2 is grounded, the gate of MOSFET M2 is connected to the positive output terminal of the fully differential error amplifier A2, and the drain of MOSFET M2 is connected to the drain of MOSFET M7.

[0093] The source of MOSFET M3 is grounded, the gate of MOSFET M3 is connected to the drain of MOSFET M3, and the drain of MOSFET M3 is connected to the drain of MOSFET M5.

[0094] The source of MOSFET M4 is grounded, the gate of MOSFET M4 is connected to the drain of MOSFET M4, and the drain of MOSFET M4 is connected to the drain of MOSFET M8.

[0095] The source of MOSFET M9 is grounded, the gate of MOSFET M9 is connected to the gate of MOSFET M4, and the drain of MOSFET M9 is connected to the gate of MOSFET M4. 11 Drain connection;

[0096] MOSFET M 10 The source of the MOSFET is grounded. 10The gate of the transistor is connected to the gate of MOSFET M3. 10 The drain and power transistor M P Gate connection;

[0097] MOSFET M 11 The source of the MOSFET is connected to VDD. 11 The gate and MOSFET M 11 Drain connection;

[0098] MOSFET M 12 The source of the MOSFET is connected to VDD. 12 The gate and MOSFET M 11 Gate connection, MOSFET M 12 The drain and power transistor M P The gate connection.

[0099] slow loop

[0100] The fast loop is nested within the slow loop; the slow loop includes: Class AB error amplifier A1 and power transistor M. P And the fully differential error amplifier A2.

[0101] In the slow loop, the fully differential error amplifier A2 is a folded cascode amplifier with PMOS transistors as input pairs, thereby increasing the output impedance of the fully differential error amplifier A2 and making the output node the dominant pole of the slow loop. Furthermore, the fully differential error amplifier A2 will have its output V... OUT Voltage and reference voltage V REF The difference is used as input to regulate the current source of the fast loop to improve the power supply suppression capability.

[0102] The operation of a fast transient response, high power supply rejection, capacitor-free, multi-loop controlled LDO includes:

[0103] When the load changes from light load to heavy load, the output V OUT As the voltage decreases, the AB class error amplifier A1 outputs error current, while the fully differential error amplifier A2 outputs gate voltage that controls the increase of error current, and the power transistor M... P The increased gate discharge current causes the power transistor M to... P As the gate voltage decreases, the power transistor M... P The overdrive voltage increases, and the power transistor M... P The increased current at the output terminal V OUT The voltage recovers to the reference voltage V. REF Size;

[0104] When the load changes from heavy load to light load, the output V OUTAs the voltage increases, the AB class error amplifier A1 outputs an error current, and simultaneously, the gate voltage of the fully differential error amplifier A2 controls the increase of the error current, causing the power transistor M... P The increased gate charging current causes the power transistor M to... P As the gate voltage increases, the power transistor M P The overdrive voltage decreases, and the power transistor M P The decrease in current reduces the output voltage V. OUT The voltage recovers to the reference voltage V. REF Size.

[0105] Figure 4 The transient response waveform diagram of this invention shows that when the load jumps from 500uA to 50mA in 50ns, the maximum undershoot voltage of the output voltage is 118mV, and the settling time is 120ns. When the load jumps from 50mA to 500uA in 50ns, the maximum overshoot voltage of the output voltage is 60mV, and the settling time is 140ns, demonstrating good transient response performance.

[0106] Figure 5 The Bode plots for the fast loop of the present invention are shown under light load (500µA) and heavy load (50mA). It can be seen that under both light and heavy load conditions, the phase margin of the fast loop is sufficient to keep the entire loop stable.

[0107] Figure 6 The Bode plots for the slow loop of the present invention are shown under light load (500µA) and heavy load (50mA). It can be seen that under both light and heavy load conditions, the phase margin of the slow loop is sufficient to keep the entire loop stable.

[0108] Figure 7 This is a PSR simulation diagram showing the power supply rejection characteristics of the LDO under light load (500uA) and heavy load (50mA) conditions, with and without the slow loop connected to the overall loop. The slow loop connection significantly enhances the power supply rejection characteristics of the LDO.

[0109] This invention employs multi-loop control, consisting of a slow-response loop based on a fully differential error amplifier A2 and a fast loop based on a class AB error amplifier A1. The class AB error amplifier A1 is used as the power transistor M. PThe charging and discharging current of the power transistor's gate capacitor varies with the magnitude of the differential input of the Class AB error amplifier A1. Therefore, a high slew rate can be achieved with low quiescent power consumption, improving the transient response performance of the LDO. Furthermore, this invention uses a fully differential error amplifier A2 as a slow loop to control the current source of the Class AB error amplifier A1 in the fast loop. The added slow loop makes the overall circuit's PSR performance more dependent on the fully differential error amplifier A2 in the slow loop, thus achieving fast transient response while maintaining high power supply rejection characteristics at low power consumption.

[0110] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0111] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A fast transient response, high power supply rejection, capacitor-free, multi-loop controlled LDO, characterized in that, include: Fast loop, slow loop, and RC module; among them, The fast loop includes: a Class AB error amplifier A1 and a power transistor M. P ; The fast loop is nested within the slow loop; the slow loop includes: the Class AB error amplifier A1 and the power transistor M. P and fully differential error amplifier A2; In the fast loop, the Class AB error amplifier A1 calculates the output V. OUT The voltage and the reference voltage V REF The difference is used to output an error current, and this error current is used as the power transistor M. P The charging and discharging current of the gate capacitor is used to improve the power transistor M. P The switching rate of the gate capacitance enables a fast transient response; In the slow loop, the fully differential error amplifier A2 calculates the output V. OUT The voltage and the reference voltage V REF The difference is used to obtain an error voltage, which is then converted into the gate voltage of the current source controlling the Class AB error amplifier A1. This voltage is used to control and change the error current, thereby controlling and changing the charging and discharging current, and ultimately changing the power transistor M. P The gate voltage of the power transistor M P The overdrive voltage and the power transistor M P The current flowing through it causes the output terminal V to... OUT The voltage recovers to the reference voltage V. REF The size of the [something] is used to achieve the purpose of power supply suppression; The RC module includes a Miller capacitor CC and a resistor RZ; the RC module uses the Miller capacitor CC for frequency compensation and the resistor RZ for zero-point compensation to improve the phase margin and stability of the fast loop.

2. The fast transient response, high power supply rejection, capacitor-free multi-loop control LDO according to claim 1, characterized in that, The Miller capacitor C C The first end is connected to the power transistor M P The gate connection, the Miller capacitor C C The second terminal is connected to the resistor R Z The first end is connected; The resistor R Z The second terminal is connected to the power transistor M P The drain connection.

3. The fast transient response, high power supply rejection, capacitor-free multi-loop control LDO according to claim 2, characterized in that, The RC module utilizes the Miller capacitance C in the RC module. C Frequency compensation is performed using the resistor R in the RC module. Z Zero-point compensation includes: In the power transistor M P The gate and drain terminals utilize Miller capacitance C C Frequency compensation is performed so that the power transistor M P The gate terminal node serves as the dominant pole of the fast loop, and the output terminal V OUT As the secondary dominant pole of the fast loop, it simultaneously reduces the output impedance, pushing the dominant and secondary dominant poles to higher frequencies and increasing the phase margin; utilizing the resistor R Z Zero-point compensation will be performed due to the Miller capacitance C. C The generated right-half-plane zeros are converted into left-half-plane zeros, increasing the phase margin and thus improving stability.

4. The fast transient response, high power supply rejection, capacitor-free multi-loop control LDO according to claim 1, characterized in that, The circuit connection relationships of the fast loop include: The inverting input of the class AB error amplifier A1 is connected to the reference voltage V. REF The positive input terminal of the class AB error amplifier A1 is connected to the output terminal V. OUT The output terminal of the Class AB error amplifier A1 is connected to the power transistor M. P The gate connection is such that the first input terminal of the class AB error amplifier A1 is connected to the positive output terminal of the fully differential error amplifier A2 in the slow loop, and the second input terminal of the class AB error amplifier A1 is connected to the inverted output terminal of the fully differential error amplifier A2 in the slow loop. The power transistor M P The source of the power transistor M is connected to VDD. P The drain and the output terminal V OUT connect.

5. The fast transient response, high power supply rejection, capacitor-free multi-loop control LDO according to claim 4, characterized in that, The Class AB error amplifier A1 includes: Input transistor GmL, input transistor GmH, auxiliary operational amplifier module, and current summing circuit.

6. The fast transient response, high power supply rejection, capacitor-free multi-loop control LDO according to claim 5, characterized in that, The auxiliary operational amplifier module includes: auxiliary operational amplifier A AUX and MOSFET M AUX ;in, The auxiliary operational amplifier A AUX The inverting input terminal is connected to the reference voltage V. REF The auxiliary operational amplifier A AUX The positive input terminal of the MOS transistor M AUX The drain connection of the auxiliary operational amplifier A AUX The output terminal is connected to the MOS transistor M AUX Gate connection; The MOS transistor M AUX The source is connected to the VDD.

7. The fast transient response, high power supply rejection, capacitor-free multi-loop control LDO according to claim 6, characterized in that, The input tube GmL includes: MOS tube M5 and MOS tube M6; wherein... The source of the MOS transistor M5 is connected to the source of the MOS transistor M... AUX The drain of the MOSFET M5 is connected to the gate of the MOSFET M6. The source of the MOSFET M6 is connected to the output terminal V. OUT The gate of the MOS transistor M6 is connected to the drain of the MOS transistor M6.

8. The fast transient response, high power supply rejection, capacitor-free multi-loop control LDO according to claim 7, characterized in that, The input transistor GmH includes: MOSFET M7 and MOSFET M8; wherein... The source of the MOSFET M7 is connected to the source of the MOSFET M... AUX The drain of the MOS transistor M7 is connected to the gate of the MOS transistor M7. The source of the MOSFET M8 is connected to the output terminal V. OUT The gate of the MOS transistor M8 is connected to the gate of the MOS transistor M7.

9. The fast transient response, high power supply rejection, capacitor-free multi-loop control LDO according to claim 8, characterized in that, The current summing circuit includes: MOSFET M1, MOSFET M2, MOSFET M3, MOSFET M4, MOSFET M9, MOSFET M 10 MOSFET M 11 and MOSFET M 12 ;in, The gate voltage is the gate voltage of MOS transistors M1 and M2, which serve as current sources in the Class AB error amplifier A1. The source of the MOS transistor M1 is grounded, the gate of the MOS transistor M1 is connected to the inverting output terminal of the fully differential error amplifier A2, and the drain of the MOS transistor M1 is connected to the drain of the MOS transistor M6. The source of the MOS transistor M2 is grounded, the gate of the MOS transistor M2 is connected to the positive output terminal of the fully differential error amplifier A2, and the drain of the MOS transistor M2 is connected to the drain of the MOS transistor M7. The source of the MOS transistor M3 is grounded, the gate of the MOS transistor M3 is connected to the drain of the MOS transistor M3, and the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M5. The source of the MOS transistor M4 is grounded, the gate of the MOS transistor M4 is connected to the drain of the MOS transistor M4, and the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M8. The source of MOSFET M9 is grounded, the gate of MOSFET M9 is connected to the gate of MOSFET M4, and the drain of MOSFET M9 is connected to the gate of MOSFET M4. 11 Drain connection; The MOS transistor M 10 The source of the MOS transistor is grounded. 10 The gate of the transistor is connected to the gate of the MOS transistor M3. 10 The drain of the power transistor M P Gate connection; The MOS transistor M 11 The source of the MOSFET is connected to VDD. 11 The gate of the MOS transistor M 11 Drain connection; The MOS transistor M 12 The source of the MOSFET is connected to VDD. 12 The gate of the MOS transistor M 11 The gate connection of the MOS transistor M 12 The drain of the power transistor M P The gate connection.

10. A fast transient response, high power supply rejection, capacitor-free, multi-loop controlled LDO according to claim 9, characterized in that, The operation of the fast transient response, high power supply rejection, capacitor-free, multi-loop controlled LDO includes: When the load changes from light load to heavy load, the output terminal V OUT As the voltage decreases, the class AB error amplifier A1 outputs the error current, while the fully differential error amplifier A2 outputs its gate voltage to control the increase of the error current. The power transistor M... P The gate discharge current increases, causing the power transistor M... P As the gate voltage decreases, the power transistor M P As the overdrive voltage increases, the power transistor M P The increased current at the output terminal V OUT The voltage recovers to the reference voltage V. REF Size; When the load changes from heavy load to light load, the output terminal V OUT As the voltage increases, the class AB error amplifier A1 outputs the error current, while the fully differential error amplifier A2 outputs its gate voltage to control the increase of the error current. The power transistor M... P The increased charging current at the gate causes the power transistor M to... P As the gate voltage increases, the power transistor M P The overdrive voltage decreases, and the power transistor M P The current flowing through decreases, causing the output terminal V to... OUT The voltage recovers to the reference voltage V. REF Size.

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