A high-order trimming circuit and method suitable for high-precision SAR ADC
By introducing coarse quantization and fine quantization switch arrays, decoder modules and PN modules into high-precision SAR ADCs, the capacitor position is dynamically adjusted using pseudo-random codes, capacitance mismatch error is solved, and high-precision analog-to-digital converter is realized. High-order error correction enhances the linearity and accuracy of the circuit.
Patent Information
- Application Number
- CN202311278178.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-07
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2043-10-07
AI Technical Summary
The prior art is difficult to effectively solve the high-order error problem of capacitor mismatching in high-precision SAR ADCs, especially in analog-to-digital converters with resolutions exceeding 20 bits, resulting in insufficient error correction.
A high-order adjustment circuit is designed, including coarse quantized switch array, fine quantized switch array, SAR module, decoder module and PN module. The capacitor position is dynamically adjusted through pseudo-random code to achieve digital correction of capacitor mismatch.
Without changing the original SAR ADC main architecture, the newly added auxiliary module only adds low-power digital circuits, solving the problem of capacitor mismatch error, and can improve linearity according to different encoder choices.
Smart Images
Figure CN117240295B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a high-order trimming circuit and method suitable for high-precision SAR ADC. Background Art
[0002] With the rapid development of electronic information technology, analog-to-digital converters (ADCs) used to connect the analog world and the digital world have become essential components in various electronic products. Designing high-speed, high-precision and low-power analog-to-digital converters is also the goal and direction that the academic and industrial circles have been pursuing. Due to its simple quantization structure and high dependence on digital circuits, the successive approximation register analog-to-digital converter (SAR ADC) has shown superior performance in low-power electronic applications. SAR ADC can use low-power comparator junctions and majority voting technology to reduce comparator power consumption, or it can use subranging structure combined with check skip algorithm to reduce capacitor switching energy.
[0003] Among them, high-precision analog-to-digital converters with a resolution of more than 18 bits will introduce the concept of coarse and fine quantization to ensure a compromise between speed and accuracy. The main error of this type of SAR ADC is capacitor mismatch, which is mainly caused by layout, manufacturing process, and ambient temperature. In order to improve the performance of SAR ADC, various capacitor mismatch error calibration technologies have been proposed, and they are usually chosen to be filled in the digital domain. For example, front-end digital calibration is an option that the industry prefers, but front-end calibration will interrupt the normal operation of SAR ADC and will also be affected by PVT. This method is simple to implement, but it mainly performs first-order linear error correction. When it is necessary to design an analog-to-digital converter with a higher resolution (more than 20 bits), the higher-order errors of capacitor mismatch must be taken into consideration.
[0004] In view of this, there is an urgent need for a technical solution for a high-order trimming circuit suitable for a high-precision SAR ADC. Summary of the invention
[0005] The present application proposes a high-order trimming circuit and method suitable for a high-precision SAR ADC, which solves the high-order error problem of capacitor mismatch in the high-precision SAR ADC in the prior art.
[0006] In order to achieve the above-mentioned purpose, this application specifically adopts the following technical solutions:
[0007] A high-order trimming circuit suitable for a high-precision SAR ADC, the high-order trimming circuit comprising:
[0008] A coarse quantization switch array, wherein the first input terminal is connected to the input signal Vin, the second input terminal is connected to the reference signal Vref, the third input terminal is connected to the output terminal of the SAR module, and the output terminal is connected to the input terminal of the 4-bit coarse quantization ADC module;
[0009] A fine quantization switch array, wherein the first input terminal is connected to the input signal Vin, the second input terminal is connected to the reference signal Vref, the third input terminal is connected to the output terminal of the SAR module, the fourth input terminal is connected to the output terminal of the decoder module, and the output terminal is connected to the input terminal of the 16-bit fine quantization ADC module;
[0010] The SAR module has a first input terminal connected to a 4-bit coarse quantization ADC module, a second input terminal connected to a 16-bit fine quantization ADC module, a third output terminal connected to a decoder module, a first output terminal connected to a coarse quantization switch array module, a second output terminal connected to a fine quantization switch array module, and a third output terminal connected to a capacitor mismatch digital correction module;
[0011] A decoder module, wherein the first input terminal is connected to the output terminal of the SAR module, the second input terminal is connected to the output terminal of the PN module, and the output is connected to the fine quantization switch array module;
[0012] The PN module outputs a pseudo-random code, and the output terminal is connected to the input terminal of the decoder module;
[0013] The 4-bit output signal input from the 4-bit coarse quantization ADC module to the SAR module is decoded by a pseudo-random code, and the decoding result is connected to the input end of the fine quantization switch array module via the output end.
[0014] As an optional technical solution, the value of N in the 4-bit coarse quantization ADC module is 4.
[0015] As an optional technical solution, the value of M in the 16-bit fine quantization ADC module is 16.
[0016] As an optional technical solution, the decoder module adopts a 3-8 decoder.
[0017] A high-order trimming method is applied to a high-order trimming circuit suitable for a high-precision SAR ADC, the method comprising:
[0018] Step S1: the 4-bit coarse quantization ADC module generates a digital code and sends it to the SAR module. After receiving the digital code, the SAR module sends it to the coarse quantization switch array again. The first input terminal of the coarse quantization switch array is connected to the input signal Vin, and the second input terminal is connected to the reference signal Vref. The output terminal of the coarse quantization switch array is connected to the 4-bit coarse quantization ADC module, forming a cycle of the coarse quantization ADC module, the SAR module and the 4-bit coarse quantization switch array until the 4-bit coarse quantization ADC module generates the digital code.
[0019] Step S2: The SAR module sends the digital code generated by the 4-bit coarse quantization ADC module to the decoder. The decoder randomizes the digital code by receiving the pseudo-random code generated by the PN module, and then decodes the digital code and sends it to the fine quantization switch array.
[0020] Step S3: The 16-bit fine quantization ADC module generates a digital code and sends it to the SAR module. After receiving the digital code, the SAR module sends it to the fine quantization switch array again. The first input terminal of the fine quantization switch array is connected to the input signal Vin, and the second input terminal is connected to the reference signal Vref. The output terminal of the fine quantization switch array is connected to the 16-bit fine quantization ADC module, forming a cycle of the fine quantization ADC module, the SAR module and the 16-bit fine quantization switch array until the digital code generated by the 16-bit fine quantization ADC module and the 4-bit coarse quantization ADC module generated digital code decoded in step S2 are transmitted;
[0021] Step S4: The output terminal of the SAR module is connected to the capacitor mismatch digital correction module, and the process ends.
[0022] As an optional technical solution, the decoder module adopts a 3-8 decoder.
[0023] As an optional technical solution, the 4-bit coarse quantization ADC module generates a digital code: D3 / D2 / D1 / D0, and the total calculation selects the capacitance number of 15 unit capacitors, and controls the capacitors with unit capacitance numbers of 8 / 4 / 2 / 1 respectively, among which D0 controls the capacitor with a capacitance number of 1.
[0024] As an optional technical solution, when the 4-bit coarse quantization ADC generates the digital code D3D2D1=001, the capacitor pseudo-random scheme is executed and the total number of capacitors is planned, totaling: 15 unit capacitors; among which, C6=C5=C4=C3=C2=C1=C0=2C, C represents the unit capacitance value.
[0025] As an optional technical solution, when the PN module stops working, the output code D3D2D1=001 of the 4-bit coarse quantization ADC is connected to the power ground after the 3-8 decoder, and the capacitors C6, C5, C4, C2, C1 and C0 in the fine quantization switch array are connected to the power supply voltage, and the capacitor C3 is connected to the power supply voltage.
[0026] As an optional technical solution, when the PN module is turned on, the output code D3D2D1=001 of the 4-bit coarse quantization ADC is added with pseudo-random coding. After the 3-8 decoder, the capacitors C6, C5, C4, C3, C2, C1 and C0 in the fine quantization switch array are connected to the power ground by 6 out of 7, and the other capacitor is connected to the power supply voltage; D0 selects the remaining unit capacitor.
[0027] The beneficial effects of this application include:
[0028] Without changing the main architecture of the original SAR ADC, only two auxiliary modules are added. Therefore, the layout changes are small and the new power consumption is low. The newly added modules are all composed of digital circuits, which are not restricted by the process and have a wide range of applications. Different encoders can be selected as needed to improve linearity.
[0029] Other beneficial effects or advantages of the present application will be described in detail in conjunction with the specific structure in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative labor. In addition, it should be understood that the proportional relationship of the various components in the drawings of this specification does not represent the proportional relationship in the actual material selection and design, which is only a schematic diagram of the structure or position, where:
[0031] Figure 1 Schematic diagram of the structure of the SAR ADC in Example 1 of the present application. DETAILED DESCRIPTION
[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0033] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0034] In the description of this application, it should be noted that the terms used, such as "top" and "bottom", refer to the part of this application that is close to the top when in use as the top, and the part that is close to the bottom as the bottom; the terms used, such as "first" and "second", are only used to distinguish expressions, and do not indicate or imply that they have a difference in importance or order; the terms used, such as "inside" and "outside", refer to the inside and outside of a specific contour. The use of the above terms is only to facilitate a clear and simple description of the technical solution of this application, and cannot be understood as a limitation on this application.
[0035] Embodiment 1:
[0036] A high-order trimming circuit suitable for a high-precision SAR ADC, the high-order trimming circuit comprising:
[0037] A coarse quantization switch array, wherein the first input terminal is connected to the input signal Vin, the second input terminal is connected to the reference signal Vref, the third input terminal is connected to the output terminal of the SAR module, and the output terminal is connected to the input terminal of the 4-bit coarse quantization ADC module;
[0038] A fine quantization switch array, wherein the first input terminal is connected to the input signal Vin, the second input terminal is connected to the reference signal Vref, the third input terminal is connected to the output terminal of the SAR module, the fourth input terminal is connected to the output terminal of the decoder module, and the output terminal is connected to the input terminal of the 16-bit fine quantization ADC module;
[0039] The SAR module has a first input terminal connected to a 4-bit coarse quantization ADC module, a second input terminal connected to a 16-bit fine quantization ADC module, a third output terminal connected to a decoder module, a first output terminal connected to a coarse quantization switch array module, a second output terminal connected to a fine quantization switch array module, and a third output terminal connected to a capacitor mismatch digital correction module;
[0040] A decoder module, wherein the first input terminal is connected to the output terminal of the SAR module, the second input terminal is connected to the output terminal of the PN module, and the output is connected to the fine quantization switch array module;
[0041] The PN module outputs a pseudo-random code, and the output terminal is connected to the input terminal of the decoder module;
[0042] The 4-bit output signal input from the 4-bit coarse quantization ADC module to the SAR module is decoded by a pseudo-random code, and the decoding result is connected to the input end of the fine quantization switch array module via the output end.
[0043] Through the above technical solution, on one hand, through the high-order trimming circuit mentioned in the present application, the 4-bit coarse quantization ADC module generates a digital code and sends it to the decoder through the SAR module, and the decoder then generates a pseudo-random code through the receiving PN module, and after randomizing the digital code, the decoder decodes it and sends it to the fine quantization switch array, so that the selected capacitor position is not fixed but pseudo-random, and is executed according to the pre-arranged capacitor pseudo-random scheme, which greatly solves the problem of capacitor mismatch error;
[0044] It is understandable that: without changing the main structure of the original SAR ADC, only two auxiliary modules (decoder module and PN module) are added to solve the shortcomings of the existing technology. Therefore, the layout change is small, the new power consumption is low, and the newly added modules are all composed of digital circuits, which are not restricted by the process and have a wide range of applications. Different encoders can be selected as needed to improve linearity;
[0045] Finally, the 16-bit fine-quantization ADC module uniformly sends all the digital codes in the circuit to the SAR module, and the output of the SAR module is connected to the capacitor mismatch digital correction module, and the process ends.
[0046] In order to facilitate the understanding of those skilled in the art: it is necessary to explain the traditional method, without a decoder and a PN module, only the 4-bit coarse quantization ADC module and the 16-bit fine quantization ADC module can output each other's digital codes together, resulting in: the selected capacitor position is fixed and unchanged, and there is a capacitor mismatch error problem;
[0047] From the traditional method and the method recorded in this application, it can be concluded that the solution recorded in this application solves the shortcomings of the prior art.
[0048] In one implementation of the present application, the decoder module uses a 3-8 decoder.
[0049] According to the second aspect of the present application, the present application also provides a high-order trimming method, which is applied to the high-order trimming circuit suitable for high-precision SAR ADC, and the method includes: step S1: a 4-bit coarse quantization ADC module generates a digital code and sends it to the SAR module, and the SAR module sends it to the coarse quantization switch array again after receiving it, the first input terminal of the coarse quantization switch array is connected to the input signal Vin, the second input terminal is connected to the reference signal Vref, and the output terminal of the coarse quantization switch array is connected to the 4-bit coarse quantization ADC module, forming a cycle of the coarse quantization ADC module, the SAR module and the 4-bit coarse quantization switch array, until the 4-bit coarse quantization ADC module generates the digital code; step S2: the SAR module sends the digital code generated by the 4-bit coarse quantization ADC module to the decoder, the decoder randomizes the digital code by receiving the pseudo-random code generated by the PN module, and then sends it to the fine quantization switch array after decoding by the decoder; step S3: The 16-bit fine quantization ADC module generates a digital code and sends it to the SAR module. After receiving the digital code, the SAR module sends it to the fine quantization switch array again. The first input terminal of the fine quantization switch array is connected to the input signal Vin, and the second input terminal is connected to the reference signal Vref. The output terminal of the fine quantization switch array is connected to the 16-bit fine quantization ADC module, forming a cycle of the fine quantization ADC module, the SAR module and the 16-bit fine quantization switch array until the digital code generated by the 16-bit fine quantization ADC module and the digital code generated by the 4-bit coarse quantization ADC module after decoding in step S2 are transmitted; step S4: the output terminal of the SAR module is connected to the capacitor mismatch digital correction module, and the process ends.
[0050] In one embodiment of the present application, Figure 1 As shown:
[0051] When the PN module stops working, the coarse quantization ADC outputs 4-bit codes D3 / D2 / D1 / D0 in sequence. After the coarse quantization is completed, the codes D3 / D2 / D1 pass through the 3-8 decoder and enter the fine quantization switch array to control the capacitors with unit capacitance numbers of 8 / 4 / 2 respectively, and D0 controls the capacitor with capacitance number of 1 to generate the residual signal; a total of 15 unit capacitance numbers are selected, and the selected capacitor positions are fixed.
[0052] When the PN module is turned on, the coarse quantized 4-bit outputs D3 / D2 / D1 / D0, D3 / D2 / D1 are randomized by the pseudo-random signal generated by the PN, and then provided with 3-8 decoding by the decoder, and enter the fine quantization switch array to control the capacitors with unit capacitance numbers of 8 / 4 / 2 respectively, and D0 controls the capacitor with capacitance number of 1 to generate the residual signal; however, at this time, the selected capacitor position is no longer fixed, but pseudo-random, and is executed according to the pre-arranged capacitor pseudo-random scheme.
[0053] Correspondingly, as shown in Table 1, a capacitor pseudo-random scheme that can be optionally implemented when the coarse quantization ADC output code D3D2D1=001 is provided, and the selection of randomized capacitors is as follows:
[0054]
[0055] Table 1
[0056] There are 15 unit capacitors in total, among which C6=C5=C4=C3=C2=C1=C0=2C, where C represents the unit capacitance value;
[0057] When the PN module stops working, the output code D3D2D1 of the coarse quantization ADC is 001. After the 3-8 decoder, the capacitors C6, C5, C4, C2, C1 and C0 in the fine quantization switch array are connected to the power ground, and the capacitor C3 is connected to the power supply voltage.
[0058] When the PN module is turned on, the output code D3D2D1=001 of the coarse quantization ADC is added with pseudo-random code. After the 3-8 decoder, the capacitors C6, C5, C4, C3, C2, C1 and C0 in the fine quantization switch array are connected to the power ground by 7-choose-6, and the other capacitor is connected to the power supply voltage.
[0059] D0 selects the remaining unit capacitance.
[0060] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims
1. A high-order trimming circuit suitable for high-precision SAR ADC, It is characterized in that The high-order trimming circuit comprises: A coarse quantization switch array, wherein the first input terminal is connected to the input signal Vin, the second input terminal is connected to the reference signal Vref, the third input terminal is connected to the output terminal of the SAR module, and the output terminal is connected to the input terminal of the 4-bit coarse quantization ADC module; A fine quantization switch array, wherein the first input terminal is connected to the input signal Vin, the second input terminal is connected to the reference signal Vref, the third input terminal is connected to the output terminal of the SAR module, the fourth input terminal is connected to the output terminal of the decoder module, and the output terminal is connected to the input terminal of the 16-bit fine quantization ADC module; 4-bit coarse quantization ADC module, the input end is connected to the coarse quantization switch array module, and the output end is connected to the SAR module; 16-bit fine quantization ADC module, the input end is connected to the fine quantization switch array module, and the output end is connected to the SAR module; The SAR module has a first input terminal connected to a 4-bit coarse quantization ADC module, a second input terminal connected to a 16-bit fine quantization ADC module, a third output terminal connected to a decoder module, a first output terminal connected to a coarse quantization switch array module, a second output terminal connected to a fine quantization switch array module, and a third output terminal connected to a capacitor mismatch digital correction module; A decoder module, wherein the first input terminal is connected to the output terminal of the SAR module, the second input terminal is connected to the output terminal of the PN module, and the output is connected to the fine quantization switch array module; The PN module outputs a pseudo-random code, and the output terminal is connected to the input terminal of the decoder module; The 4-bit output signal input from the 4-bit coarse quantization ADC module to the SAR module is decoded by a pseudo-random code, and the decoding result is connected to the input end of the fine quantization switch array module via the output end.
2. A high-order trimming circuit suitable for high-precision SAR ADC as claimed in claim 1, Features: The decoder module adopts a 3-8 decoder.
3. A high-level tuning method, Features: Applied to a high-order trimming circuit suitable for a high-precision SAR ADC as described in any one of claims 1-2, the method comprising: Step S1: the 4-bit coarse quantization ADC module generates a digital code and sends it to the SAR module. After receiving the digital code, the SAR module sends it to the coarse quantization switch array again. The first input terminal of the coarse quantization switch array is connected to the input signal Vin, and the second input terminal is connected to the reference signal Vref. The output terminal of the coarse quantization switch array is connected to the 4-bit coarse quantization ADC module, forming a cycle of the coarse quantization ADC module, the SAR module and the 4-bit coarse quantization switch array until the 4-bit coarse quantization ADC module generates the digital code. Step S2: The SAR module sends the digital code generated by the 4-bit coarse quantization ADC module to the decoder. The decoder randomizes the digital code by receiving the pseudo-random code generated by the PN module, and then decodes the digital code and sends it to the fine quantization switch array. Step S3: The 16-bit fine quantization ADC module generates a digital code and sends it to the SAR module. After receiving the digital code, the SAR module sends it to the fine quantization switch array again. The first input terminal of the fine quantization switch array is connected to the input signal Vin, and the second input terminal is connected to the reference signal Vref. The output terminal of the fine quantization switch array is connected to the 16-bit fine quantization ADC module, forming a cycle of the fine quantization ADC module, the SAR module and the 16-bit fine quantization switch array until the digital code generated by the 16-bit fine quantization ADC module and the 4-bit coarse quantization ADC module generated digital code decoded in step S2 are transmitted; Step S4: The output terminal of the SAR module is connected to the capacitor mismatch digital correction module, and the process ends.
4. A high-level adjustment method as claimed in claim 3, Features: The decoder module adopts a 3-8 decoder.
5. A high-level adjustment method as claimed in claim 4, Features: The digital code generated by the 4-bit coarse quantization ADC module is: D3 / D2 / D1 / D0. The total calculation selects the capacitance numbers of 15 unit capacitors, and controls the capacitors with unit capacitance numbers of 8 / 4 / 2 / 1 respectively, among which D0 controls the capacitor with capacitance number of 1.
6. A high-level adjustment method as claimed in claim 5, Features: When the 4-bit coarse quantization ADC generates a digital code D3D2D1=001, the capacitor pseudo-random scheme is executed and the total number of capacitors is planned, which is: 15 unit capacitors; among which, C6=C5=C4=C3=C2=C1=C0=2C, and C represents the unit capacitance value.
7. A high-level adjustment method as claimed in claim 5, Features: When the PN module stops working, the output code D3D2D1=001 of the 4-bit coarse quantization ADC is passed through the 3-8 decoder, and the capacitors C6, C5, C4, C2, C1 and C0 in the fine quantization switch array are connected to the power ground, and the capacitor C3 is connected to the power supply voltage.
8. A high-level adjustment method as claimed in claim 5, Features: When the PN module is turned on, the output code D3D2D1=001 of the 4-bit coarse quantization ADC is added with pseudo-random code. After the 3-8 decoder, the capacitors C6, C5, C4, C3, C2, C1 and C0 in the fine quantization switch array are connected to the power ground by 6 out of 7, and the other capacitor is connected to the power supply voltage; D0 selects the remaining unit capacitor.