A circuit

Abstract

The application relates to the technical field of display, and provides a circuit, which comprises transistors T1-T24 and a capacitor C1; a gate of the transistor T18 is connected with a pre-charge control end, a source is connected with a VGL signal end, and a drain is connected with a P1 point; a gate of the transistor T19 is connected with the pre-charge control end, a source is connected with the VGL signal end, and a drain is connected with a P2 point; a gate of the transistor T20 is connected with a release control end, a source is connected with a display signal output end, and a drain is connected with the VGL signal end; and a gate of the transistor T21 is connected with a Q point, a source is connected with a CK signal input end, and a drain is connected with a stage transmission signal output end. The application has the advantages that the signal output end of the GIP circuit is divided into the display signal output end and the stage transmission signal output end which do not interfere with each other, and when the display signal output end appears abnormality such as noise or short circuit or open circuit, the work of the stage transmission signal output end is not interfered.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a circuit for driving a display using GIP. Background Technology

[0002] The display in a liquid crystal display (LCD) is achieved by controlling the TFT pixels within the LCD panel. Specifically, this is done by horizontally arranged gate lines controlling the on / off state of the TFT pixels, and vertically arranged source lines writing the desired data voltage. The gate line signals are generated by gate driving circuits on both sides of the panel, referred to as GIP (Gate In Panel) circuits. Multiple GIP circuits are cascaded together. The output signal of a GIP circuit at a given stage is not only transmitted to the display area as the gate line signal for the corresponding row of TFT pixels, but also participates in the operation of GIP circuits before and after it.

[0003] As LCD displays are used more widely and in more diverse scenarios, the required temperature range performance also increases. The design of medium and large-sized display panels is particularly complex, requiring consideration not only of the panel bezel size but also the ability to operate for extended periods in extreme high-temperature conditions. Compared to room temperature, the higher the temperature, the weaker the turn-on capability of TFT thin-film transistors. Under high-temperature conditions, continuous operation of TFT devices can lead to excessive energy consumption and abnormalities such as short circuits and open circuits.

[0004] See Figure 1 This is a schematic diagram of a traditional GIP circuit based on 17T1C. The Gn signal output terminal of this GIP circuit is not only connected to the gate line of the corresponding row pixel TFT in the display area, but also participates in the operation of the GIP circuits before and after it. Under high temperature and extreme weather conditions, noise, short circuits, open circuits, and other abnormalities are prone to occur in the connection line between the Gn signal output terminal and the pixel TFT in the display area, which directly interferes with the transmission function of the GIP circuit after it is in the subsequent stage, resulting in the inability to transmit the normal display image.

[0005] Therefore, how to separate the signal output terminals of GIP circuits into display signal output terminals and transmission signal output terminals that do not interfere with each other is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a circuit in which the signal output terminal of the GIP circuit is divided into a display signal output terminal and a transmission signal output terminal that do not interfere with each other.

[0007] The present invention is implemented as follows: a circuit comprising:

[0008] Transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, and T24, and capacitor C1;

[0009] The gate and source of transistor T1 are connected to the precharge control terminal, and the drain is connected to point Q.

[0010] The gate of transistor T2 is connected to point Q, the source is connected to point P1, and the drain is connected to the VGL signal terminal.

[0011] The gate of transistor T3 is connected to point P1, the source is connected to point Q, and the drain is connected to the VGL signal terminal.

[0012] The gate of transistor T4 is connected to point Q, the source is connected to the CK signal input terminal, and the drain is connected to the display signal output terminal.

[0013] The gate of transistor T5 is connected to point P1, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal.

[0014] The gate of transistor T6 is connected to point P2, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal.

[0015] The gate of transistor T7 is connected to the release control terminal, the source is connected to the VGL signal terminal, and the drain is connected to the Q point.

[0016] The gate and source of transistor T8 are connected to the V1 signal terminal, and the drain is connected to point P1.

[0017] The gate and drain of transistor T9 are connected to the V2 signal terminal, and the source is connected to point P2.

[0018] The gate of transistor T10 is connected to the V2 signal terminal, the source is connected to point P1, and the drain is connected to the VGL signal terminal.

[0019] The gate of transistor T11 is connected to the V1 signal terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P2.

[0020] The gate of transistor T12 is connected to point Q, the source is connected to the VGL signal terminal, and the drain is connected to point P2.

[0021] The gate of transistor T13 is connected to point P2, the source is connected to the VGL signal terminal, and the drain is connected to point Q.

[0022] The gate of transistor T14 is connected to the CLR_P signal terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P2.

[0023] The gate of transistor T15 is connected to the CLR_P signal terminal, the source is connected to point P1, and the drain is connected to the VGL signal terminal.

[0024] The gate of transistor T16 is connected to the CLR signal terminal, the source is connected to the VGL signal terminal, and the drain is connected to the Q point.

[0025] The gate of transistor T17 is connected to the CLR signal terminal, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal.

[0026] The gate of transistor T18 is connected to the precharge control terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P1.

[0027] The gate of transistor T19 is connected to the precharge control terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P2.

[0028] The gate of transistor T20 is connected to the release control terminal, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal.

[0029] The gate of transistor T21 is connected to point Q, the source is connected to the CK signal input terminal, and the drain is connected to the stage signal output terminal.

[0030] The gate of transistor T22 is connected to point P1, the source is connected to the stage signal output terminal, and the drain is connected to the VGL signal terminal.

[0031] The gate of transistor T23 is connected to point P2, the source is connected to the stage signal output terminal, and the drain is connected to the VGL signal terminal.

[0032] The gate of transistor T24 is connected to the CLR signal terminal, the source is connected to the stage signal output terminal, and the drain is connected to the VGL signal terminal.

[0033] The left end of capacitor C1 is connected to point Q, and the right end is connected to the display signal output terminal.

[0034] Furthermore, the cascade signal output terminal is the Xn signal output terminal of the nth stage GIP circuit, the precharge control terminal is connected to the Xn-4 signal output terminal of the (n-4)th stage GIP circuit, and the release control terminal is connected to the Xn+4 signal output terminal of the (n+4)th stage GIP circuit.

[0035] Furthermore, the display signal output terminal is the Gn signal output terminal of the nth stage GIP circuit, and is also connected to the nth row gate line of the display area of ​​the LCD panel.

[0036] Furthermore, in the first four GIP circuits, the precharge control terminal is connected to the STV signal terminal, and in the last four GIP circuits, the release control terminal is connected to the RST signal terminal.

[0037] Furthermore, it also includes a driver IC, which is connected to the CK signal input terminal, VGL signal terminal, V1 signal terminal, V2 signal terminal, CLR signal terminal, CLR_P signal terminal, STV signal terminal, and RST signal terminal.

[0038] Furthermore, transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, and T24 are all TFT thin-film transistors.

[0039] Furthermore, transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, and T24, along with capacitor C1, are all fixedly mounted on the LCD panel.

[0040] The advantages of this invention are: 1. It sets up a 24T1C GIP circuit, and the signal output terminals of the GIP circuit are divided into a display signal output terminal and a transmission signal output terminal that do not interfere with each other. When the connection line of the display signal output terminal has noise or abnormalities such as short circuit or open circuit, it does not interfere with the operation of the transmission signal output terminal, and the GIP circuit continues to perform normal transmission operation; it enhances the transmission and output capabilities of the GIP circuit and improves the product reliability of the display in high-temperature weather.

[0041] 2. By utilizing the functions of transistors T18 / T19, when transistor T1 is turned on to precharge point Q, points P1 / P2 can be pulled to a low potential simultaneously. This prevents the voltage of point Q from being continuously affected by the pull-down effect of points P1 / P2, which would reduce the turn-on capability of transistors T4 and T21 as output devices. This is beneficial to the output display of the GIP circuit of this invention.

[0042] 3. When transistor T7 ages due to prolonged operation, it cannot turn on stably, reducing its ability to pull down the Q point voltage. This causes transistor T4 to not turn off stably, resulting in the display signal output terminal not being fully pulled down to a low potential. Noise is present at the display signal output terminal, which in turn affects the display function. Setting transistor T20 to turn on simultaneously with transistor T7 helps to pull down the voltage at the display signal output terminal. Attached Figure Description

[0043] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0044] Figure 1 This is a schematic diagram of a GIP circuit based on 17T1C in the background technology.

[0045] Figure 2 This is a schematic diagram of the circuit of the present invention.

[0046] Figure 3 This is a comparison diagram of the high-temperature waveforms of the circuit of the present invention and the GIP circuit of the prior art. Detailed Implementation

[0047] This invention provides a circuit that overcomes the shortcomings of the prior art where, under high temperature and extreme weather conditions, the connection line between the Gn signal output terminal and the pixel TFT in the display area is prone to noise, short circuits, open circuits, or other abnormalities, which directly interfere with the cascading function of the subsequent GIP circuit and cause the screen to fail to display properly. This invention achieves the technical effect of dividing the signal output terminal of the GIP circuit into a display signal output terminal and a cascading signal output terminal that do not interfere with each other, thereby enhancing the cascading and output capabilities of the GIP circuit.

[0048] The overall concept of the technical solution of this invention is as follows:

[0049] An improvement is made to the traditional 17T1C GIP circuit by adding transistors T18 to T24, forming a 24T1C GIP circuit, which has 24 transistors and 1 capacitor. The signal output terminals of the GIP circuit are divided into a display signal output terminal and a cascade signal output terminal, which do not interfere with each other. Transistors T4, T5, T6, and T17 are involved in the operation of the display signal output terminal, while transistors T21, T22, T23, and T24 are involved in the operation of the cascade signal output terminal. The display signal output terminal is connected to the gate line of the corresponding row pixel TFT in the display area, and the cascade signal output terminal participates in the operation of the preceding and following GIP circuits. When noise, short circuit, open circuit, or other abnormalities occur in the connection line between the display signal output terminal and the pixel TFT, the GIP circuit still continues to operate normally in cascade mode.

[0050] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0051] See Figures 1 to 3 The preferred embodiment of the present invention.

[0052] A circuit comprising:

[0053] Transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, and T24, and capacitor C1;

[0054] The gate and source of transistor T1 are connected to the precharge control terminal, and the drain is connected to point Q.

[0055] The gate of transistor T2 is connected to point Q, the source is connected to point P1, and the drain is connected to the VGL signal terminal.

[0056] The gate of transistor T3 is connected to point P1, the source is connected to point Q, and the drain is connected to the VGL signal terminal.

[0057] The gate of transistor T4 is connected to point Q, the source is connected to the CK signal input terminal, and the drain is connected to the display signal output terminal.

[0058] The gate of transistor T5 is connected to point P1, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal.

[0059] The gate of transistor T6 is connected to point P2, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal.

[0060] The gate of transistor T7 is connected to the release control terminal, the source is connected to the VGL signal terminal, and the drain is connected to the Q point.

[0061] The gate and source of transistor T8 are connected to the V1 signal terminal, and the drain is connected to point P1.

[0062] The gate and drain of transistor T9 are connected to the V2 signal terminal, and the source is connected to point P2.

[0063] The gate of transistor T10 is connected to the V2 signal terminal, the source is connected to point P1, and the drain is connected to the VGL signal terminal.

[0064] The gate of transistor T11 is connected to the V1 signal terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P2.

[0065] The gate of transistor T12 is connected to point Q, the source is connected to the VGL signal terminal, and the drain is connected to point P2.

[0066] The gate of transistor T13 is connected to point P2, the source is connected to the VGL signal terminal, and the drain is connected to point Q.

[0067] The gate of transistor T14 is connected to the CLR_P signal terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P2.

[0068] The gate of transistor T15 is connected to the CLR_P signal terminal, the source is connected to point P1, and the drain is connected to the VGL signal terminal.

[0069] The gate of transistor T16 is connected to the CLR signal terminal, the source is connected to the VGL signal terminal, and the drain is connected to the Q point.

[0070] The gate of transistor T17 is connected to the CLR signal terminal, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal.

[0071] The gate of transistor T18 is connected to the precharge control terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P1.

[0072] The gate of transistor T19 is connected to the precharge control terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P2.

[0073] The gate of transistor T20 is connected to the release control terminal, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal.

[0074] The gate of transistor T21 is connected to point Q, the source is connected to the CK signal input terminal, and the drain is connected to the stage signal output terminal.

[0075] The gate of transistor T22 is connected to point P1, the source is connected to the stage signal output terminal, and the drain is connected to the VGL signal terminal.

[0076] The gate of transistor T23 is connected to point P2, the source is connected to the stage signal output terminal, and the drain is connected to the VGL signal terminal.

[0077] The gate of transistor T24 is connected to the CLR signal terminal, the source is connected to the stage signal output terminal, and the drain is connected to the VGL signal terminal.

[0078] The left end of capacitor C1 is connected to point Q, and the right end is connected to the display signal output terminal.

[0079] Compared with the 17T1C GIP circuit of the prior art, the circuit of the present invention adds transistors T18 to T24 to form a 24T1C GIP circuit, that is, the GIP circuit of the present invention has 24 transistors and 1 capacitor; the signal output terminal of the GIP circuit is divided into a display signal output terminal and a transmission signal output terminal that do not interfere with each other. Transistors T4, T5, T6, and T17 participate in the operation of the display signal output terminal, and transistors T21, T22, T23, and T24 participate in the operation of the transmission signal output terminal. The display signal output terminal is connected to the gate line of the corresponding row pixel TFT of the display area, and the transmission signal output terminal participates in the operation of the front and rear stage GIP circuits. When the connection line between the display signal output terminal and the pixel TFT has noise or abnormalities such as short circuit or open circuit, it does not interfere with the operation of the transmission signal output terminal, and the GIP circuit continues to operate normally.

[0080] By utilizing the pull-down function of transistors T18 / T19, when transistor T1 is turned on to precharge point Q, points P1 / P2 can be pulled to a low potential simultaneously. This prevents the voltage of point Q from being continuously affected by the pull-down effect of points P1 / P2, thus reducing the turn-on capability of transistors T4 and T21 as output devices. This contributes to the output display of the GIP circuit of this invention. Because the turn-on capability of transistors T4 and T21 is weak under high-temperature conditions, and because points P1 / P2 also synchronously pull down the voltage of point Q during the operation of the GIP circuit, the output capability of the display signal output terminal and the cascade signal output terminal is reduced. This invention, by adding a pull-down circuit composed of transistors T18 and T19, can simultaneously pull points P1 / P2 to a low potential when transistor T1 is turned on, allowing transistors T3 and T13 to remain in a better off state. This prevents point Q from being pulled down during precharging, thus reducing the turn-on capability of transistors T4 and T21 as output devices, and consequently affecting the output display. Therefore, it can improve the driving capability of the GIP circuit under low-temperature conditions.

[0081] When transistor T7 ages due to prolonged operation, it becomes unstable and loses its ability to pull down the Q-point voltage. This prevents transistor T4 from turning off stably, resulting in the display signal output terminal not being fully pulled to a low potential, causing noise at the display signal output terminal and affecting the display function. The simultaneous activation of transistor T20 and transistor T7 helps pull down the voltage at the display signal output terminal. When transistor T7 is activated, the Q-point voltage is released, pulling down the voltage and turning off transistor T4. If transistor T4 is not fully turned off, the CK signal will be transmitted to the display signal output terminal, affecting the gate line voltage of the corresponding row in the display area. When transistor T20 is activated, the display signal output terminal is connected to the VGL signal terminal, helping to pull down the voltage at the display signal output terminal, keeping the display signal output terminal and the gate line of the corresponding row in the display area at a low voltage state.

[0082] The cascade signal output terminal is the Xn signal output terminal of the nth stage GIP circuit, the precharge control terminal is connected to the Xn-4 signal output terminal of the (n-4)th stage GIP circuit, and the release control terminal is connected to the Xn+4 signal output terminal of the (n+4)th stage GIP circuit.

[0083] The display signal output terminal is the Gn signal output terminal of the nth level GIP circuit, and is also connected to the nth row gate line of the display area of ​​the LCD panel.

[0084] In the first four GIP circuits, the precharge control terminal is connected to the STV signal terminal, and in the last four GIP circuits, the release control terminal is connected to the RST signal terminal.

[0085] It also includes a driver IC, which is connected to the CK signal input terminal, VGL signal terminal, V1 signal terminal, V2 signal terminal, CLR signal terminal, STV signal terminal, and RST signal terminal. The driver IC generates the corresponding signals.

[0086] The CK signal input is connected to the clock voltage signal; the VGL signal is connected to a negative or zero voltage signal; the V1 and V2 signal inputs are alternately connected to positive voltage signals. When the V1 signal is active and pulls up the voltage of P1, the V2 signal is at zero voltage; when the V1 signal is at zero voltage, the V2 signal is active and pulls up the voltage of P2. The CLR and CLR_P signal inputs are two other sets of clock voltage signals. After the display stage transmission is completed, the CLR signal continuously pulls down the Q points, display signal outputs, and stage transmission signal outputs of each stage of the GIP circuit to a low voltage state; the CLR_P signal continuously pulls down the P1 and P2 points of the GIP circuit to a low voltage state. The STV signal is connected to a positive voltage signal to turn on the first four stages of the GIP circuit, and the RST signal is connected to a positive voltage signal to turn off the last four stages of the GIP circuit.

[0087] Transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, and T24 are all TFT thin-film transistors. These TFT thin-film transistors operate on the same principle as N-type MOSFETs.

[0088] Transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, and T24, along with capacitor C1, are all fixedly mounted on the LCD panel.

[0089] How the circuit of this invention operates:

[0090] (1) During the pre-charge stage, the stage output signal terminal of the front-stage GIP circuit outputs a high voltage, that is, Xn-4 is a high voltage and acts on the gate of transistor T1, the gate of transistor T18, and the gate of transistor T19. At the same time, transistors T1, T18, and T19 are turned on to pre-charge the Q point. The gates of transistors T4, T21, T2, and T12 are connected to a high voltage. At this time, the CK signal input terminal is a low voltage. Since both P1 and P2 are connected to the VGL signal terminal, both P1 and P2 are in a low voltage state. Transistors T3 and T13 are in a closed state to avoid leakage of the Q point voltage through transistors T3 and T13 during the Q point pre-charge process. After capacitor C1 is fully charged, transistors T4 and T21 remain in the open state. Since the CK signal input terminal is a low voltage, there is no output signal at the display signal output terminal Gn and the stage output signal terminal Xn.

[0091] In the background technology, the GIP circuit does not have transistors T18 and T19. Therefore, when Xn-4 is at a high voltage and acts on the gate of transistor T1, transistor T1 is turned on. Since the TFT device itself has a weak turn-on capability at high temperatures, during the pre-charge Q point, when transistors T2 and T12 are not stably turned on, points P1 and P2 are not connected to the VGL signal terminal. However, if the V1 signal terminal provides a high voltage to point P1, or the V2 signal terminal provides a high voltage to point P2, transistor T3 or transistor T13 will be turned on. The Q point voltage leakage reduces the turn-on capability of transistors T4 and T21, which are output devices.

[0092] Therefore, transistors T18 and T19 provided in this invention help the output display of the GIP circuit and can improve the driving capability of the GIP circuit under low temperature conditions.

[0093] During the output phase, transistors T4 and T21 are in the ON state, the CK signal input terminal becomes high voltage, and the display signal output terminal and the stage transmission signal output terminal change from no output signal to output high voltage. Due to the coupling effect of the capacitor, the voltage at point Q rises further, ensuring that transistors T4 and T21, as well as transistors T2 and T12, are fully ON. Points P1 and P2 are connected to the VGL signal terminal through transistors T2 and T12 respectively. During this phase, Xn-4 becomes low voltage, and transistors T1, T18, and T19 are in the OFF state. The display signal output terminal supplies high voltage to the gate line of the corresponding row in the display area, and the stage transmission signal output terminal supplies high voltage to the subsequent GIP circuit.

[0094] During the shutdown phase, the stage transmission output signal terminal of the subsequent GIP circuit outputs a high voltage, i.e., Xn+4 is high and acts on transistors T7 and T20; simultaneously, transistors T7 and T20 are turned on. At this time, point Q is connected to the VGL signal terminal through transistor T7, capacitor C1 releases its charge, pulling down the voltage at point Q. Then, transistors T4, T21, T2, and T12 are all turned off, and neither the display signal output terminal nor the stage transmission signal output terminal outputs the CK signal. Since the display signal output terminal and the stage transmission signal output terminal do not interfere with each other, when there is noise, short circuit, open circuit, or other abnormal signals in the connection line between the display signal output terminal and the pixel TFT, these abnormal signals will not be transmitted to the stage transmission signal output terminal, thus not interfering with the operation of the stage transmission signal output terminal. The GIP circuit continues to operate normally, enhancing the stage transmission and output capabilities of the GIP circuit and improving the product reliability of the display in high-temperature weather. This technical approach is even more advantageous when applied to circuits with dual-side drive.

[0095] The signal output terminal of the background technology's GIP circuit not only connects to the gate line of the corresponding row in the display area but also participates in the operation of subsequent GIP circuits. Under high-temperature and extreme weather conditions, noise, short circuits, open circuits, and other abnormal signals are prone to occur in the connection lines between the Gn signal output terminal and the pixel TFT in the display area. These abnormal signals will interfere with the function of the subsequent GIP circuits, resulting in the inability to display images normally. Furthermore, in the background technology's GIP circuit, when transistor T7 ages due to prolonged operation, it cannot turn on stably, reducing its ability to pull down the Q-point voltage. This causes transistor T4 to not turn off stably, resulting in the display signal output terminal not being fully pulled to a low potential, leading to noise at the display signal output terminal and thus affecting the display function.

[0096] In this invention, in addition to the transistor T7 originally set for pulling down the Q point, a transistor T20 is added as a pull-down device for the display signal output terminal. The transistor T20 and transistor T7 are turned on simultaneously. When transistor T4 is not stably turned off, the display signal output terminal is connected to the VGL signal terminal through transistor T20, which helps to pull down the voltage of the display signal output terminal. This technical approach can enhance the cascading capability of the GIP circuit, avoid transistor T7 aging, reduce the ability to pull down the Q point, and prevent noise and repetitive output at the display signal output terminal.

[0097] During the voltage regulation stage, Xn+4 becomes low voltage, and transistors T7 and T20 are in the off state. Since transistors T2 and T12 were both off in the previous stage, P1 or P2 is in a high voltage state under the action of the V1 and V2 signal terminals. Transistor T3 or T13 is in the on state, keeping the Q point connected to the VGL signal terminal. Transistor T5 or T6 is in the on state, keeping the display signal output terminal Gn connected to the VGL signal terminal. Transistor T22 or T23 is in the on state, keeping the stage transmission signal output terminal Xn connected to the VGL signal terminal.

[0098] After the display transmission is completed, the CLR signal continuously pulls the Q points, display signal output terminals, and transmission signal output terminals of each stage of the GIP circuit to a low voltage state. The CLR_P signal continuously pulls the P1 and P2 points of each stage of the GIP circuit to a low voltage state. That is, the Q point is connected to the VGL signal terminal through transistor T16, the P1 point is connected to the VGL signal terminal through transistor T15, the P2 point is connected to the VGL signal terminal through transistor T14, the display signal output terminal is connected to the VGL signal terminal through transistor T17, and the transmission signal output terminal is connected to the VGL signal terminal through transistor T24.

[0099] Combination Figure 3 The image shows a comparison of the high-temperature waveforms of the circuit of this invention and the GIP circuit of the prior art. The pre-charge voltage of the GIP circuit of the 24T1C of this invention is higher than that of the GIP circuit of the 17T1C of the prior art. Therefore, the GIP circuit of the 24T1C of this invention can solve the problem of the low pre-charge voltage of the old circuit and enhance the pre-charge capability. In high-temperature environments, the 17T1C of the prior art exhibits significant leakage current at the Q-point, while the GIP circuit of the 24T1C of this invention has no significant leakage current. Therefore, the GIP circuit of the 24T1C of this invention can solve the problem of the weak voltage regulation capability of the old circuit. In summary, the GIP circuit of the 24T1C of this invention can enhance the circuit's stage transmission and output capabilities, and improve the long-term reliability of the panel.

[0100] The circuit of this invention can be widely used in medium and large-size display applications and in scenarios where it operates for extended periods in extreme weather. It is also compatible with a-Si, Metal Oxide, LTPS and other processes, improving the flexibility of applications for various products.

[0101] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A circuit, characterized in that, include: Transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, and T24, and capacitor C1; The gate and source of transistor T1 are connected to the precharge control terminal, and the drain is connected to point Q. The gate of transistor T2 is connected to point Q, the source is connected to point P1, and the drain is connected to the VGL signal terminal. The gate of transistor T3 is connected to point P1, the source is connected to point Q, and the drain is connected to the VGL signal terminal. The gate of transistor T4 is connected to point Q, the source is connected to the CK signal input terminal, and the drain is connected to the display signal output terminal. The gate of transistor T5 is connected to point P1, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal. The gate of transistor T6 is connected to point P2, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal. The gate of transistor T7 is connected to the release control terminal, the source is connected to the VGL signal terminal, and the drain is connected to the Q point. The gate and source of transistor T8 are connected to the V1 signal terminal, and the drain is connected to point P1. The gate and drain of transistor T9 are connected to the V2 signal terminal, and the source is connected to point P2. The gate of transistor T10 is connected to the V2 signal terminal, the source is connected to point P1, and the drain is connected to the VGL signal terminal. The gate of transistor T11 is connected to the V1 signal terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P2. The gate of transistor T12 is connected to point Q, the source is connected to the VGL signal terminal, and the drain is connected to point P2. The gate of transistor T13 is connected to point P2, the source is connected to the VGL signal terminal, and the drain is connected to point Q. The gate of transistor T14 is connected to the CLR_P signal terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P2. The gate of transistor T15 is connected to the CLR_P signal terminal, the source is connected to point P1, and the drain is connected to the VGL signal terminal. The gate of transistor T16 is connected to the CLR signal terminal, the source is connected to the VGL signal terminal, and the drain is connected to the Q point. The gate of transistor T17 is connected to the CLR signal terminal, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal. The gate of transistor T18 is connected to the precharge control terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P1. The gate of transistor T19 is connected to the precharge control terminal, the source is connected to the VGL signal terminal, and the drain is connected to point P2. The gate of transistor T20 is connected to the release control terminal, the source is connected to the display signal output terminal, and the drain is connected to the VGL signal terminal. The gate of transistor T21 is connected to point Q, the source is connected to the CK signal input terminal, and the drain is connected to the stage signal output terminal. The gate of transistor T22 is connected to point P1, the source is connected to the stage signal output terminal, and the drain is connected to the VGL signal terminal. The gate of transistor T23 is connected to point P2, the source is connected to the stage signal output terminal, and the drain is connected to the VGL signal terminal. The gate of transistor T24 is connected to the CLR signal terminal, the source is connected to the stage signal output terminal, and the drain is connected to the VGL signal terminal. The left end of capacitor C1 is connected to point Q, and the right end is connected to the display signal output terminal.

2. The circuit according to claim 1, characterized in that, The cascade signal output terminal is the Xn signal output terminal of the nth stage GIP circuit, the precharge control terminal is connected to the Xn-4 signal output terminal of the (n-4)th stage GIP circuit, and the release control terminal is connected to the Xn+4 signal output terminal of the (n+4)th stage GIP circuit.

3. The circuit according to claim 2, characterized in that, The display signal output terminal is the Gn signal output terminal of the nth level GIP circuit, and is also connected to the nth row gate line of the display area of ​​the LCD panel.

4. The circuit according to claim 2, characterized in that, In the first four GIP circuits, the precharge control terminal is connected to the STV signal terminal, and in the last four GIP circuits, the release control terminal is connected to the RST signal terminal.

5. The circuit according to claim 4, characterized in that, Also includes: The driver IC is connected to the CK signal input terminal, VGL signal terminal, V1 signal terminal, V2 signal terminal, CLR signal terminal, CLR_P signal terminal, STV signal terminal, and RST signal terminal.

6. The circuit according to claim 1, characterized in that, Transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, and T24 are all TFT thin-film transistors.

7. The circuit according to claim 1, characterized in that, Transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, and T24, along with capacitor C1, are all fixedly mounted on the LCD panel.

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