Wide range current regulating circuit

Abstract

The application discloses a wide-range current regulating circuit, comprising a current source, a first current regulating unit, a second current regulating unit, a second current regulating unit, an output tube and a control circuit. According to the wide-range current regulating circuit, the first mirror current is output by the first current regulating unit, the first mirror current is copied by the second current regulating unit to generate the second mirror current and adjust the size of the second mirror current, meanwhile, the current on the first current regulating unit is increased based on the second mirror current, the current on the first current regulating unit is copied by the second current regulating unit to generate the third mirror current and adjust the size of the third mirror current, meanwhile, the current on the first current regulating unit is reduced, and the current is output by the output tube, so that the greater calibration range can be obtained under the premise of ensuring the precision and the same calibration bit number compared with the traditional regulating circuit, and the greater safety margin is obtained.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a wide-range current regulation circuit. Background Technology

[0002] Current references are a commonly used and crucial component within chips. Due to parameter offsets and mismatches inherent in semiconductor devices, the generated reference current will deviate from our expected value. Trimming circuits can adjust the reference current to a certain extent to achieve our desired value. Traditional trimming circuits, such as... Figure 1 As shown, the principle of this circuit is as follows:

[0003] Iref is the reference current generated by the internal module. Iout1 is the output terminal that provides the reference current to the external circuit. Due to the aforementioned process deviations, the reference current Iref will deviate from the expected value, and therefore the mirrored output current Iout1 will also deviate from the expected value.

[0004] Clearly, MOSFETs MN0, MN1, MN2, MS3…MN(n-1) and MNA form a current mirror. MS0, MS1, MS2, MS3~MS(n-2), and MS(n-1) are N-channel MOSFETs, controlled by external trimming signals T0, T1, T2, T3~T(n-2), and T(n-1). Since MOSFET MPA and MOSFET MPout form a 1:1 current mirror, ideally, the mirror ratio of the output current Iout1 to the reference current Iref depends only on the number of MOSFETs MN0, MN1, MN2, MS3…MN(n-1) that are turned on. Therefore, the magnitude of the final output current Iout1 can be controlled by controlling the number of MOSFETs MN0, MN1, MN2, MS3…MN(n-1) that are turned on. The width-to-length ratio of MOSFET MN0 to MOSFET MNA determines the minimum current that can be controlled by the least significant trimming bit, which can be adjusted via the trimming signal T1; this is the current trimming step size. With a fixed number of trimming bits, the output current Iout1 can be determined by the following formula:

[0005]

[0006]

[0007] Clearly, the adjustment range of the output current Iout1 of this circuit is:

[0008]

[0009] If the current variation range caused by the process itself is too large, we will need more calibration bits to ensure sufficient calibration capability, which will also consume more registers.

[0010] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0011] The purpose of this invention is to provide a wide-range current regulation circuit that can achieve a larger calibration range without reducing calibration accuracy or increasing the number of calibration bits.

[0012] To achieve the above objectives, embodiments of the present invention provide a wide-range current regulation circuit, comprising:

[0013] A current source is used to provide a reference current;

[0014] A current mirror unit has a control terminal and a first output terminal. The control terminal of the current mirror unit is connected to a current source to form a connection node. The current mirror unit is used to replicate a reference current and output a first mirror current at its first output terminal.

[0015] The first current regulating unit has a first control terminal and an input terminal. The first control terminal of the first current regulating unit is connected to the first output terminal of the current mirror unit and is used to proportionally replicate the first mirror current to generate a second mirror current, and to adjust the magnitude of the second mirror current based on the control of the first adjustment signal. The input terminal of the first current regulating unit is connected to a connection node to adjust the current on the current mirror unit based on the second mirror current.

[0016] The second current adjustment unit has a second control terminal and a second output terminal. The second control terminal of the second current adjustment unit is connected to the connection node and is used to proportionally replicate the current on the current mirror unit to generate a third mirror current, and to adjust the magnitude of the third mirror current based on the control of the second adjustment signal. The second output terminal of the second current adjustment unit is connected to the connection node to adjust the current on the current mirror unit based on the third mirror current.

[0017] The output transistor, whose control terminal is connected to the control terminal of the current mirror unit, is used to output an output current proportional to the current in the current mirror unit; and

[0018] The control circuit is connected to the connection node, the input terminal of the first current regulating unit, and the second output terminal of the second current regulating unit. It is used to control the connection and disconnection between the input terminal of the first current regulating unit and the connection node, and to control the connection and disconnection between the second output terminal of the second current regulating unit and the connection node.

[0019] In one or more embodiments of the present invention, the first current regulating unit increases the current on the current mirror unit based on the second mirror current, and the second current regulating unit decreases the current on the current mirror unit based on the third mirror current.

[0020] In one or more embodiments of the present invention, the first current regulation unit includes a first MOS transistor connected in common gate and connected to the first output terminal of the current mirror unit, and a plurality of second MOS transistors. The drain of the first MOS transistor is connected to the gate of the first MOS transistor. A first switching transistor for controlling the on and off is provided between the drain of the second MOS transistor and the control circuit. The first switching transistor is turned on and off based on the control of a first adjustment signal.

[0021] In one or more embodiments of the present invention, the width-to-length ratio of each of the second MOS transistors increases progressively from the least significant bit to the most significant bit in power of 2, where n is a natural number.

[0022] In one or more embodiments of the present invention, the second current regulation unit includes a plurality of third MOS transistors connected in a common gate configuration and connected to a connection node. A second switching transistor for controlling the on / off state is provided between the drain of each third MOS transistor and the control circuit. The second switching transistor is turned on and off based on the control of a second adjustment signal.

[0023] In one or more embodiments of the present invention, the aspect ratio of each of the third MOS transistors increases progressively from the least significant bit to the most significant bit in power of 2, where n is a natural number.

[0024] In one or more embodiments of the present invention, the control circuit controls the connection between the input terminal of the first current regulating unit and the connection node based on a control signal, or controls the connection between the second output terminal of the second current regulating unit and the connection node.

[0025] In one or more embodiments of the present invention, the control circuit includes a third switch and a fourth switch. The source of the third switch is connected to the input terminal of the first current regulation unit, the drain of the third switch is connected to the drain of the fourth switch and a connection node, the source of the fourth switch is connected to the second output terminal of the second current regulation unit, the gate of the third switch receives a first control signal, and the gate of the fourth switch receives a second control signal.

[0026] In one or more embodiments of the present invention, the first control signal and the second control signal are opposite signals.

[0027] In one or more embodiments of the present invention, the first trimming signal and the second trimming signal are opposite signals.

[0028] Compared with the prior art, the wide-range current regulation circuit according to the embodiments of the present invention replicates the reference current through a current mirror unit and outputs a first mirror current at its first output terminal. The first current regulation unit replicates the first mirror current proportionally to generate a second mirror current and adjusts the magnitude of the second mirror current based on the control of a first trimming signal. At the same time, the current on the current mirror unit is increased based on the second mirror current. The second current regulation unit replicates the current on the current mirror unit proportionally to generate a third mirror current and adjusts the magnitude of the third mirror current based on the control of a second trimming signal. At the same time, the current on the current mirror unit is decreased based on the third mirror current. An output current proportional to the current on the current mirror unit is output through an output transistor. Thus, while ensuring accuracy, and even with the same number of calibration bits compared with traditional regulation circuits, a larger calibration range can be obtained, with a larger safety margin. Attached Figure Description

[0029] Figure 1 It is a circuit diagram of a current regulation circuit based on existing technology.

[0030] Figure 2 This is a circuit diagram of a wide-range current regulation circuit according to an embodiment of the present invention. Detailed Implementation

[0031] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0032] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0033] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0034] like Figure 2 As shown, a wide-range current regulation circuit includes: a current source A, a current mirror unit 10, a first current regulation unit 20, a second current regulation unit 30, an output transistor MPout, and a control circuit 40.

[0035] In one embodiment, current source A is used to provide a reference current Iref; current mirror unit 10 has a control terminal and a first output terminal, the control terminal of current mirror unit 10 is connected to current source A, and current mirror unit 10 is used to replicate the reference current Iref and output a first mirror current at its first output terminal; the current mirror ratio of current mirror unit 10 is 1:1. In other embodiments, the current mirror ratio of current mirror unit 10 can be set as needed.

[0036] Specifically, the current mirror unit 10 includes a first transistor MPA and a second transistor MPB. In one embodiment, both the first transistor MPA and the second transistor MPB are P-channel MOSFETs. The sources of the first transistor MPA and the second transistor MPB are connected to the power supply voltage. The drain of the first transistor MPA is connected to its gate and the gate of the second transistor MPB to form a control terminal. The control terminal of the current mirror unit 10 is connected to the first terminal of the current source A to form a connection node O. The drain of the second transistor MPB forms a first output terminal. In other embodiments, the first transistor MPA and the second transistor MPB can be N-channel MOSFETs.

[0037] Meanwhile, the first current adjustment unit 20 has a first control terminal and an input terminal. The first control terminal of the first current adjustment unit 20 is connected to the first output terminal of the current mirror unit 10. The first current adjustment unit 20 is used to proportionally replicate the first mirror current to generate a second mirror current, and to adjust the magnitude of the second mirror current based on the control of the first trimming signals T0, T1, T2, T3 ~ T(n-2). The input terminal of the first current adjustment unit 20 is also connected to the connection node O to adjust the current on the current mirror unit 10 based on the second mirror current. In one embodiment, the first current adjustment unit 20 increases the current on the current mirror unit 10 based on the second mirror current.

[0038] In one embodiment, the first current regulation unit 20 includes a first MOSFET MNA connected in a common-gate configuration and connected to the first output terminal of the current mirror unit 10, and a plurality of second MOSFETs MN0, MN1, MN2, MN3~MN(n-2). The first MOSFET MNA and the plurality of second MOSFETs MN0, MN1, MN2, MN3~MN(n-2) are all N-channel MOSFETs. The drain of the first MOSFET MNA is connected to its gate to form the first control terminal of the first current regulation unit 20 and is also connected to the drain of the second transistor MPB. The source of the first MOSFET MNA and the sources of each of the second MOSFETs MN0, MN1, MN2, MN3~MN(n-2) are connected to ground.

[0039] Each of the drains of the second MOSFETs MN0, MN1, MN2, MN3~MN(n-2) is connected to the control circuit 40 via a corresponding first switching transistor NS0, NS1, NS2, NS3~NS(n-2) for controlling the on / off state. All first switching transistors NS0, NS1, NS2, NS3~NS(n-2) are N-channel MOSFETs. The drains of ~NS(n-2) are connected to form the input terminal of the first current regulation unit 20 and are connected to the control circuit 40. The source of each first switch NS0, NS1, NS2, NS3~NS(n-2) is connected to the drain of the corresponding second MOS transistor MN0, MN1, MN2, MN3~MN(n-2). The gate of each first switch NS0, NS1, NS2, NS3~NS(n-2) is used to receive the corresponding first trimming signals T0, T1, T2, T3~T(n-2). Each first switch NS0, NS1, NS2, NS3~NS(n-2) is turned on and off by the control of the corresponding first trimming signals T0, T1, T2, T3~T(n-2).

[0040] When the first adjustment signals T0, T1, T2, T3 ~ T(n-2) are high-level signals, each of the first switching transistors NS1, NS2, NS3, NS4 ~ NS(n-2) is turned on; when the first adjustment signals T0, T1, T2, T3 ~ T(n-2) are low-level signals, each of the first switching transistors NS0, NS1, NS2, NS3 ~ NS(n-2) is turned off. In other embodiments, the second MOSFETs MN0, MN1, MN2, MN3 ~ MN(n-2) and the first switching transistors NS0, NS1, NS2, NS3 ~ NS(n-2) can be P-channel MOSFETs.

[0041] The aspect ratio of each of the second MOS transistors MN0, MN1, MN2, MN3 to MN(n-2) increases progressively from the least significant bit to the most significant bit in a power of 2, where n is a natural number. In one embodiment, the aspect ratio of the second MOS transistors MN0, MN1, MN2, MN3 to MN(n-2) is 2^n. 0 =1、2 1 =2、2 2 =4、2 3 =8、~2 (n-2) The first MOSFET MNA and multiple second MOSFETs MN0, MN1, MN2, MN3~MN(n-2) constitute a current mirror. If the width-to-length ratio of the first MOSFET MNA is 1, then the current mirror ratio of this current mirror is 1:1:2. 0 :2 1 :2 2 :2 3 ~2 (n-2) In other embodiments, the aspect ratio of the first MOSFET MNA can be other values, and the current mirror ratio of the current mirror can be other ratios.

[0042] Additionally, the second current adjustment unit 30 has a second control terminal and a second output terminal. The second control terminal of the second current adjustment unit 30 is connected to the connection node O. The second current adjustment unit 30 is used to proportionally replicate the current on the current mirror unit 10 to generate a third mirror current, and to adjust the magnitude of the third mirror current based on the control of the second trimming signals NT0, NT1, NT2, NT3 ~ NT(n-2). The second output terminal of the second current adjustment unit 30 is also connected to the connection node O to adjust the current on the current mirror unit 10 based on the third mirror current. In one embodiment, the second current adjustment unit 30 reduces the current on the current mirror unit 10 based on the third mirror current.

[0043] Specifically, the second current regulation unit 30 includes multiple third MOSFETs MP0, MP1, MP2, MP3~MP(n-2) connected in a common-gate configuration and connected to the control terminal of the current mirror unit 10. The third MOSFETs MP0, MP1, MP2, MP3~MP(n-2) are connected in a common-gate configuration to form the second control terminal of the second current regulation unit 30. The third MOSFETs MP0, MP1, MP2, MP3~MP(n-2) are P-channel MOSFETs. The gates of the third MOSFETs MP0, MP1, MP2, MP3~MP(n-2) are connected to connection node O, and the sources of the third MOSFETs MP0, MP1, MP2, MP3~MP(n-2) are connected to the power supply voltage. The first transistor MPA and the third MOSFETs MP0, MP1, MP2, MP3~MP(n-2) also constitute a current mirror, with a current mirror ratio of 1:1:2. 0 :2 1 :2 2 :2 3 ~2 (n-2) In other embodiments, the current mirror ratio of the current mirror can be other ratios.

[0044] Each of the drains of the third MOSFETs MP0, MP1, MP2, MP3 ~ MP(n-2) is provided with a second switching transistor PS0, PS1, PS2, PS3 ~ PS(n-2) for controlling the on / off state between the drain and the control circuit 40. The second switching transistors PS0, PS1, PS2, PS3 ~ PS(n-2) are turned on and off by the control of the second adjustment signals NT0, NT1, NT2, NT3 ~ NT(n-2). The drains of each of the second switching transistors PS0, PS1, PS2, PS3 ~ PS(n-2) are connected to form the second output terminal of the second current regulation unit 30 and are connected to the control circuit 40. The source of each of the second switching transistors PS0, PS1, PS2, PS3 ~ PS(n-2) is connected to the drain of the corresponding third MOS transistors MP0, MP1, MP2, MP3 ~ MP(n-2). The gate of each of the second switching transistors PS0, PS1, PS2, PS3 ~ PS(n-2) is used to receive the corresponding second adjustment signals NT0, NT1, NT2, NT3 ~ NT(n-2). Each of the second switching transistors PS0, PS1, PS2, PS3 ~ PS(n-2) is turned on and off by the control of the corresponding second adjustment signals NT0, NT1, NT2, NT3 ~ NT(n-2).

[0045] When the second adjustment signals NT0, NT1, NT2, NT3 ~ NT(n-2) are high-level signals, each of the second switches PS0, PS1, PS2, PS3 ~ PS(n-2) is turned off; when the second adjustment signals NT0, NT1, NT2, NT3 ~ NT(n-2) are low-level signals, each of the second switches PS0, PS1, PS2, PS3 ~ PS(n-2) is turned on. In other embodiments, the third MOSFETs MP0, MP1, MP2, MP3 ~ MP(n-2) and the second switches PS0, PS1, PS2, PS3 ~ PS(n-2) can be N-channel MOSFETs.

[0046] The aspect ratios of the third MOSFETs MP0, MP1, MP2, MP3 to MP(n-2) increase progressively from the least significant bit to the most significant bit in a power of 2, where n is a natural number. In one embodiment, the aspect ratios of the third MOSFETs MP0, MP1, MP2, MP3 to MP(n-2) are 2, respectively. 0 =1、2 1 =2、2 2 =4、2 3 =8、~2 (n-2) In other embodiments, other weights can be used to configure the width-to-length ratio of the third MOS transistors MP0, MP1, MP2, MP3 to MP(n-2), such as the width-to-length ratio increasing to the power of other values ​​or increasing linearly, or the width-to-length ratio being 1 for all of them.

[0047] In one embodiment, the first adjustment signals T0, T1, T2, T3 ~ T(n-2) and the second adjustment signals NT0, NT1, NT2, NT3, NT4 ~ NT(n-2) are opposite signals. That is, at the same time, when the first adjustment signal T1 is a high-level signal, the corresponding second adjustment signal NT1 is inverted to a low-level signal; when the first adjustment signal T2 is a low-level signal, the corresponding second adjustment signal T2 is inverted to a high-level signal. In other words, at the same time, the first switch NS1 and the second switch PS1 will not be turned on simultaneously, the first switch NS2 and the second switch PS2 will not be turned on simultaneously, the first switch NS3 and the second switch PS3 will not be turned on simultaneously, the first switch NS4 and the second switch PS4 will not be turned on simultaneously, and the first switch NS(n-2) and the second switch PS(n-2) will not be turned on simultaneously.

[0048] like Figure 2As shown, the control terminal of the output transistor MPout is connected to the control terminal of the current mirror unit 10 (i.e., the gate and drain of the first transistor MPA). The second terminal of the output transistor MPout is connected to the power supply voltage. The first terminal of the output transistor MPout is used to output an output current Iout2 proportional to the current on the current mirror unit 10. The output transistor MPout is a P-channel MOSFET, with the control terminal of MPout serving as the gate, the first terminal as the drain, and the second terminal as the source. In one embodiment, the output transistor MPout and the current mirror unit 10 also form a current mirror with a mirror ratio of 1:1:1, or other values. In other embodiments, the output transistor MPout can also be an N-channel MOSFET connected to the first output terminal of the current mirror unit 10.

[0049] like Figure 2 As shown, the control circuit 40 is connected to the connection node O, the input terminal of the first current regulating unit 20, and the second output terminal of the second current regulating unit 30. The control circuit 40 is used to control the connection between the input terminal of the first current regulating unit 20 and the connection node O, and to control the connection between the second output terminal of the second current regulating unit 30 and the connection node O. In one embodiment, the control circuit 40 controls the connection between the input terminal of the first current regulating unit 20 and the connection node O, or controls the connection between the second output terminal of the second current regulating unit 30 and the connection node O, based on the control signal T(n-1). That is, at any given time, the connection between the input terminal of the first current regulating unit 20 and the connection node O, and the connection between the second output terminal of the second current regulating unit 30 and the connection node O, cannot be simultaneously established.

[0050] Specifically, the control circuit 40 includes a third switch NS(n-1) and a fourth switch PS(n-1). The third switch NS(n-1) is an N-channel MOSFET, and the fourth switch PS(n-1) is a P-channel MOSFET. The source of the third switch NS(n-1) is connected to the input terminal of the first current regulation unit 20, and the drain of the third switch NS(n-1) is connected to the drain of the fourth switch PS(n-1) and the connection node O. The source of the fourth switch PS(n-1) is connected to the second output terminal of the second current regulation unit 30. The gates of the third switch NS(n-1) and the fourth switch PS(n-1) are used to receive the control signal T(n-1). Since the third switch NS(n-1) and the fourth switch PS(n-1) are MOSFETs with different types of conductive channels, they will not be turned on simultaneously under the control of the same control signal T(n-1). In other embodiments, if the third switch NS(n-1) and the fourth switch PS(n-1) are MOS transistors of the same type with the same conductive channel, then the control signals received by the gates of the third switch NS(n-1) and the fourth switch PS(n-1) are opposite control signals. Of course, depending on actual needs, the third switch NS(n-1) and the fourth switch PS(n-1) can also be turned on simultaneously under the control of different or the same control signals.

[0051] Turning on the third switch NS(n-1) connects the input terminal of the first current regulating unit 20 to the connection node O, meaning a second mirror current flows into the first current regulating unit 20 from the connection node O where the current source A and the control terminal of the current mirror unit 10 are connected. Turning on the fourth switch PS(n-1) connects the second output terminal of the second current regulating unit 30 to the connection node O, meaning a third mirror current flows into the connection node O where the current source A and the control terminal of the current mirror unit 10 are connected.

[0052] Assuming that the width-to-length ratio of the second MOSFET MN1 to the first MOSFET MNA, and the width-to-length ratio of the third MOSFET MP1 to the first transistor MPA, are both step (expected step size and less than 1), consistent with the step value in conventional circuits in the background art, the actual output range of the output current Iout2 can be calculated with the reference current Iref remaining relatively constant.

[0053] If the third switch NS(n-1) is turned on (at which time the fourth switch PS(n-1) is turned off), the output current Iout2 will be adjusted to increase, specifically:

[0054]

[0055]

[0056] If the fourth switch PS(n-1) is turned on (at which time the third switch NS(n-1) is turned off), the output current Iout2 will be adjusted to be smaller, specifically:

[0057]

[0058]

[0059] The actual adjustable range of the output current Iout2 of this circuit is:

[0060]

[0061] (2)

[0062] In one embodiment, it can be seen from combining formula (1) and formula (2):

[0063] The step represents the minimum trimming step size, which generally depends on the required trimming accuracy. The current generated by the current mirror source of the branch we need to trim is the output current Iout2 itself, which makes the actual trimming step size larger as the output offset increases. However, the minimum adjustment step size still ensures minimum accuracy depending on the aspect ratio of the current mirror, exhibiting the characteristics of non-linear step size trimming.

[0064] In practical applications, the reference current Iref will deviate by about 30% to 50% due to process deviations. For current accuracy requirements, 3%, 5%, and 10% are some typical accuracy requirements.

[0065] Following the worst-case principle, assuming the reference current Iref error is 50%, we perform calculations with step values ​​of 0.03, 0.05, and 0.1 respectively. It should be clarified that, given a fixed offset and accuracy, we can determine the actual trimming bits required in the traditional mode, i.e., 2^32 bits. n It should be equal to the offset divided by the step size (or the offset percentage divided by the accuracy percentage). Considering that redundant bits are generally reserved, in the traditional calibration mode, the actual calibration (trimming) bit number n for accuracies of 3%, 5%, and 10% should be 6, 5, and 4, respectively.

[0066] The table below lists the function values ​​for the two modes at different steps and different n (depending on the actual application requirements mentioned above).

[0067]

[0068] Clearly, under the accuracy requirements of practical applications, this scheme has a larger calibration range compared to the traditional mode, which can save calibration bits to a certain extent, or provide a greater safety margin with the same calibration bits.

[0069] The present invention also discloses a chip including the wide-range current regulation circuit described above.

[0070] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings; the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments and various different choices and modifications of the invention without departing from the scope and spirit of the invention. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A wide-range current regulation circuit, characterized in that, include: A current source is used to provide a reference current; A current mirror unit has a control terminal and a first output terminal. The control terminal of the current mirror unit is connected to a current source to form a connection node. The current mirror unit is used to replicate a reference current and output a first mirror current at its first output terminal. The first current regulating unit has a first control terminal and an input terminal. The first control terminal of the first current regulating unit is connected to the first output terminal of the current mirror unit and is used to proportionally replicate the first mirror current to generate a second mirror current, and to adjust the magnitude of the second mirror current based on the control of the first adjustment signal. The input terminal of the first current regulating unit is connected to a connection node to adjust the current on the current mirror unit based on the second mirror current. The second current adjustment unit has a second control terminal and a second output terminal. The second control terminal of the second current adjustment unit is connected to the connection node and is used to proportionally replicate the current on the current mirror unit to generate a third mirror current, and to adjust the magnitude of the third mirror current based on the control of the second adjustment signal. The second output terminal of the second current adjustment unit is connected to the connection node to adjust the current on the current mirror unit based on the third mirror current. The output transistor has its control terminal connected to the control terminal of the current mirror unit, and is used to output an output current that is proportional to the current on the current mirror unit. as well as The control circuit is connected to the connection node, the input terminal of the first current regulating unit, and the second output terminal of the second current regulating unit. It is used to control the connection and disconnection between the input terminal of the first current regulating unit and the connection node, and to control the connection and disconnection between the second output terminal of the second current regulating unit and the connection node.

2. The wide-range current regulation circuit as described in claim 1, characterized in that, The first current regulating unit increases the current on the current mirror unit based on the second mirror current, and the second current regulating unit decreases the current on the current mirror unit based on the third mirror current.

3. The wide-range current regulation circuit as described in claim 1, characterized in that, The first current regulation unit includes a first MOSFET connected in common gate and connected to the first output terminal of the current mirror unit, and a plurality of second MOSFETs. The drain of the first MOSFET is connected to the gate of the first MOSFET. The drain of each of the second MOSFETs is provided with a first switch for controlling the on and off states between it and the control circuit. The first switch is turned on and off based on the control of a first adjustment signal.

4. The wide-range current regulation circuit as described in claim 3, characterized in that, The width-to-length ratio of each of the second MOS transistors increases progressively from the least significant bit to the most significant bit in power of 2, where n is a natural number.

5. The wide-range current regulation circuit as described in claim 1, characterized in that, The second current regulation unit includes a plurality of third MOS transistors connected in a common gate configuration and connected to a connection node. A second switching transistor for controlling the on / off state is provided between the drain of each third MOS transistor and the control circuit. The second switching transistor is turned on and off based on the control of a second adjustment signal.

6. The wide-range current regulation circuit as described in claim 5, characterized in that, The width-to-length ratio of each of the third MOS transistors increases progressively from the least significant bit to the most significant bit in power of 2, where n is a natural number.

7. The wide-range current regulation circuit as described in claim 1, characterized in that, The control circuit controls the connection between the input terminal of the first current regulating unit and the connection node based on the control signal, or controls the connection between the second output terminal of the second current regulating unit and the connection node.

8. The wide-range current regulation circuit as described in claim 1, characterized in that, The control circuit includes a third switch and a fourth switch. The source of the third switch is connected to the input terminal of the first current regulation unit, the drain of the third switch is connected to the drain of the fourth switch and the connection node, and the source of the fourth switch is connected to the second output terminal of the second current regulation unit. The gates of the third switch and the fourth switch are used to receive control signals.

9. The wide-range current regulation circuit as described in claim 8, characterized in that, The gates of the third and fourth switches are used to receive two opposite control signals.

10. The wide-range current regulation circuit as described in claim 1, characterized in that, The first adjustment signal and the second adjustment signal are opposite signals.

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