Semiconductor device and semiconductor memory device

Abstract

Embodiments of the present application relate to a semiconductor device and a semiconductor memory device. The semiconductor device of the embodiments includes a first electrode including a metal oxide, a second electrode including a metal oxide, an oxide semiconductor layer between the first electrode and the second electrode, a gate electrode surrounding the oxide semiconductor layer, a gate insulating layer including silicon (Si) and nitrogen (N), a first insulating layer between the first electrode and the gate electrode, a second insulating layer between the second electrode and the gate electrode, a first conductive layer in contact with a surface of the first electrode on a side opposite to the oxide semiconductor layer, a second conductive layer in contact with a surface of the second electrode on a side opposite to the oxide semiconductor layer, a first layer surrounding the first electrode and in contact with the first conductive layer, a second layer surrounding the second electrode and in contact with the second conductive layer, a third insulating layer between the first electrode and the first insulating layer and in contact with the gate insulating layer and the first layer, and a fourth insulating layer between the second electrode and the second insulating layer and in contact with the gate insulating layer and the second layer.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2022-099891 (filed on June 21, 2022). This application includes all contents of the said basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device. Background Technology

[0004] Oxide-semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer possess the excellent characteristic of extremely low channel leakage current during disconnection. Therefore, for example, OSTs can be used as switching transistors in memory cells of dynamic random access memory (DRAM). Summary of the Invention

[0005] The semiconductor device of the embodiment includes: a first electrode comprising a metal oxide; a second electrode comprising a metal oxide; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode surrounding the oxide semiconductor layer; a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, comprising silicon (Si) and nitrogen (N); a first insulating layer disposed between the first electrode and the gate electrode; a second insulating layer disposed between the second electrode and the gate electrode; and a first conductive layer contacting the surface of the first electrode opposite to the oxide semiconductor layer, comprising selective... At least one conductor selected from the group consisting of free metals, metal nitrides, and metal carbides; a second conductive layer, in contact with the surface of the second electrode opposite to the oxide semiconductor layer, comprising at least one conductor selected from the group consisting of free metals, metal nitrides, and metal carbides; a first layer, surrounding the first electrode in a first cross-section perpendicular to a first direction from the first electrode toward the second electrode, in contact with the first conductive layer, comprising a material selected from aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride. The first electrode is formed by at least one insulator selected from the group consisting of metals, metal nitrides, and metal carbides; the second electrode is surrounded in a second cross-section perpendicular to the first direction and connected to the second conductive layer, comprising at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride, or at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; the third insulating layer is disposed between the first electrode and the first insulating layer. Between the second electrode and the second insulating layer, and in contact with the gate insulating layer and the first layer, there is at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride; and a fourth insulating layer, disposed between the second electrode and the second insulating layer, and in contact with the gate insulating layer and the second layer, includes at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride.

[0006] According to this embodiment, a semiconductor device with excellent transistor characteristics can be provided. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0010] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0011] Figure 5 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0012] Figure 6 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0013] Figure 7 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0014] Figure 8 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0015] Figure 9 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0016] Figure 10 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0017] Figure 11 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0018] Figure 12 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0019] Figure 13 This is a schematic cross-sectional view of a comparative example semiconductor device.

[0020] Figure 14 This is an explanatory diagram of a problem with a comparative example semiconductor device.

[0021] Figure 15 This is a schematic cross-sectional view of a semiconductor device according to a first variation of the first embodiment.

[0022] Figure 16 This is a schematic cross-sectional view of a semiconductor device in the second variation of the first embodiment.

[0023] Figure 17This is a schematic cross-sectional view of a semiconductor device in the third variation of the first embodiment.

[0024] Figure 18 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0025] Figure 19 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0026] Figure 20 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0027] Figure 21 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0028] Figure 22 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0029] Figure 23 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0030] Figure 24 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0031] Figure 25 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0032] Figure 26 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0033] Figure 27 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0034] Figure 28 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0035] Figure 29 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0036] Figure 30 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0037] Figure 31 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0038] Figure 32This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0039] Figure 33 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0040] Figure 34 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0041] Figure 35 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0042] Figure 36 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0043] Figure 37 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0044] Figure 38 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0045] Figure 39 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0046] Figure 40 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0047] Figure 41 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0048] Figure 42 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0049] Figure 43 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0050] Figure 44 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0051] Figure 45 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0052] Figure 46 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0053] Figure 47This is an equivalent circuit diagram of the semiconductor memory device according to the fourth embodiment.

[0054] Figure 48 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment. Detailed Implementation

[0055] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same symbols, and descriptions of components that have already been described once will be appropriately omitted.

[0056] In addition, this specification uses terms such as "upper," "lower," "upper part," "lower part," "above," or "below" for convenience. These terms are used to indicate relative positional relationships within the accompanying drawings, and not to specify positional relationships relative to gravity.

[0057] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor devices and semiconductor memory devices described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). Additionally, for example, transmission electron microscopy (TEM) can be used to determine the thickness, inter-component distance, and crystal grain size of the components constituting the semiconductor devices and semiconductor memory devices.

[0058] (First Embodiment)

[0059] The semiconductor device of the first embodiment includes: a first electrode comprising a metal oxide; a second electrode comprising a metal oxide; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode surrounding the oxide semiconductor layer; a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, comprising silicon (Si) and nitrogen (N); a first insulating layer disposed between the first electrode and the gate electrode; a second insulating layer disposed between the second electrode and the gate electrode; and a first conductive layer contacting the surface of the first electrode opposite to the oxide semiconductor layer, comprising a metal selected from metals. At least one conductor selected from the group consisting of nitrides and metal carbides; a second conductive layer, in contact with the side opposite to the oxide semiconductor layer of the second electrode, comprising at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; a first layer, surrounding the first electrode in a first cross-section perpendicular to a first direction from the first electrode toward the second electrode, in contact with the first conductive layer, comprising at least one conductor selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride. The first electrode is surrounded by an insulator or at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; the second layer surrounds the second electrode in a second cross-section perpendicular to the first direction and is in contact with the second conductive layer, comprising at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride, or at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; the third insulating layer is disposed between the first electrode and the first insulating layer. Between the layers, connected to the gate insulating layer and the first layer, the fourth insulating layer comprises at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride; and a fifth insulating layer disposed between the second electrode and the second insulating layer, connected to the gate insulating layer and the second layer, comprising at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride.

[0060] Figure 1 , Figure 2 , Figure 3 and Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 yes Figure 1 AA' sectional view. Figure 3 yes Figure 1 BB' sectional view. Figure 4 yes Figure 1 CC' section view. Figure 1 In this context, the up-down direction is referred to as the first direction. Figure 1 In this context, the left and right directions are referred to as the second direction. The second direction is perpendicular to the first direction.

[0061] Section BB' is an example of section 1. Section CC' is an example of section 2.

[0062] The semiconductor device in the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. In the transistor 100, a gate electrode is disposed surrounding the oxide semiconductor layer forming the channel. The transistor 100 is a so-called gate-all-around transistor (SGT). The transistor 100 is a so-called vertical transistor.

[0063] The transistor 100 includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a lower insulating layer 22, an upper insulating layer 24, a lower barrier conductive layer 26, an upper barrier conductive layer 28, a first sidewall barrier layer 30, a second sidewall barrier layer 32, a lower barrier insulating layer 34, an upper barrier insulating layer 36, a metal layer 38, a lower interlayer insulating layer 40, and an upper interlayer insulating layer 42. The gate insulating layer 20 includes a first gate insulating film 20a and a second gate insulating film 20b.

[0064] The lower electrode 12 is an example of the first electrode. The upper electrode 14 is an example of the second electrode. The lower insulating layer 22 is an example of the first insulating layer. The upper insulating layer 24 is an example of the second insulating layer. The lower barrier conductive layer 26 is an example of the first conductive layer. The upper barrier conductive layer 28 is an example of the second conductive layer. The first sidewall barrier layer 30 is an example of the first layer. The second sidewall barrier layer 32 is an example of the second layer. The lower barrier insulating layer 34 is an example of the third insulating layer. The upper barrier insulating layer 36 is an example of the fourth insulating layer. The first gate insulating film 20a is an example of the first film. The second gate insulating film 20b is an example of the second film.

[0065] The lower electrode 12 is disposed below the oxide semiconductor layer 16. The lower electrode 12 is electrically connected to the oxide semiconductor layer 16. For example, the lower electrode 12 is connected to the oxide semiconductor layer 16. The lower electrode 12 functions as the source electrode or drain electrode of the transistor 100.

[0066] The lower electrode 12 is a conductor. The lower electrode 12 comprises a conductive metal oxide. The lower electrode 12, for example, comprises indium (In), tin (Sn), and oxygen (O). The lower electrode 12, for example, comprises indium tin oxide. The lower electrode 12 is, for example, an indium tin oxide layer.

[0067] An upper electrode 14 is disposed on the oxide semiconductor layer 16. The upper electrode 14 is electrically connected to the oxide semiconductor layer 16. For example, the upper electrode 14 is connected to the oxide semiconductor layer 16. The upper electrode 14 functions as the source electrode or drain electrode of the transistor 100.

[0068] The upper electrode 14 is a conductor. The upper electrode 14 contains a conductive metal oxide. The upper electrode 14 contains, for example, indium (In), tin (Sn), and oxygen (O). The upper electrode 14 contains, for example, indium tin oxide. The upper electrode 14 is, for example, an indium tin oxide layer.

[0069] The lower electrode 12 and the upper electrode 14 may contain the same material, for example. The metal oxides contained in the lower electrode 12 and the upper electrode 14 may contain, for example, indium (In) and tin (Sn). The lower electrode 12 and the upper electrode 14 may contain, for example, indium tin oxide. The lower electrode 12 and the upper electrode 14 may be, for example, layers of indium tin oxide.

[0070] An oxide semiconductor layer 16 is disposed between the lower electrode 12 and the upper electrode 14. The oxide semiconductor layer 16 is, for example, connected to the lower electrode 12. The oxide semiconductor layer 16 is, for example, connected to the upper electrode 14.

[0071] In the oxide semiconductor layer 16, a channel is formed as a current path when the transistor 100 is turned on.

[0072] The oxide semiconductor layer 16 is an oxide semiconductor. The oxide semiconductor layer 16 may be, for example, amorphous.

[0073] The oxide semiconductor layer 16 may contain, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), zinc (Zn), and oxygen (O). The oxide semiconductor layer 16 may contain, for example, indium gallium zinc oxide. The oxide semiconductor layer 16 may be, for example, an indium gallium zinc oxide layer.

[0074] The oxide semiconductor layer 16 may contain, for example, at least one element selected from the group consisting of titanium (Ti), zinc (Zn), and tungsten (W), and oxygen (O). The oxide semiconductor layer 16 may contain, for example, titanium oxide, zinc oxide, or tungsten oxide. The oxide semiconductor layer 16 may be, for example, a titanium oxide layer, a zinc oxide layer, or a tungsten oxide layer.

[0075] The oxide semiconductor layer 16, for example, has a chemical composition different from that of the lower electrode 12 and the upper electrode 14.

[0076] The oxide semiconductor layer 16 contains oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 16 function as donors.

[0077] The length of the oxide semiconductor layer 16 in the first direction is, for example, 80 nm or more and 200 nm or less. The length of the oxide semiconductor layer 16 in the second direction is, for example, 20 nm or more and 100 nm or less.

[0078] The first direction is from the lower electrode 12 toward the upper electrode 14. The second direction is perpendicular to the first direction.

[0079] The gate electrode 18 faces the oxide semiconductor layer 16. The gate electrode 18 is configured such that its position coordinate in the first direction is the value between the position coordinates in the first direction of the lower electrode 12 and the upper electrode 14, respectively.

[0080] like Figure 2 As shown, the gate electrode 18 surrounds the oxide semiconductor layer 16 in a cross-section perpendicular to the first direction. The gate electrode 18 is disposed around the oxide semiconductor layer 16.

[0081] Gate electrode 18 is a conductor. Gate electrode 18 may be, for example, a metal, a metal compound, or a semiconductor. Gate electrode 18 may contain, for example, tungsten (W). Gate electrode 18 may be, for example, a tungsten layer.

[0082] The length of the gate electrode 18 in the first direction is, for example, 20 nm or more and 100 nm or less.

[0083] A gate insulating layer 20 is disposed between the oxide semiconductor layer 16 and the gate electrode 18. The gate insulating layer 20 surrounds the oxide semiconductor layer 16 in a cross-section perpendicular to the first direction. The gate insulating layer 20 is disposed between the lower electrode 12 and the upper electrode 14. The gate insulating layer 20 is in contact with the lower barrier insulating layer 34 and the upper barrier insulating layer 36. For example, the gate insulating layer 20 is in contact with the lower electrode 12 and the upper electrode 14.

[0084] The gate insulating layer 20 comprises silicon (Si) and nitrogen (N). For example, the gate insulating layer 20 comprises silicon nitride.

[0085] The gate insulating layer 20 includes, for example, a first gate insulating film 20a and a second gate insulating film 20b. The second gate insulating film 20b is disposed between the first gate insulating film 20a and the gate electrode 18.

[0086] The second gate insulating film 20b is, for example, connected to the lower electrode 12 and the upper electrode 14. The second gate insulating film 20b is, for example, connected to the lower barrier insulating layer 34 and the upper barrier insulating layer 36.

[0087] The first gate insulating film 20a is, for example, an oxide. The first gate insulating film 20a includes, for example, silicon (Si) and oxygen (O). The first gate insulating film 20a includes, for example, silicon oxide. The first gate insulating film 20a is, for example, a silicon oxide film.

[0088] The second gate insulating film 20b is, for example, a nitride. The second gate insulating film 20b may contain silicon (Si) and nitrogen (N). The second gate insulating film 20b may contain silicon nitride. The second gate insulating film 20b may be, for example, a silicon nitride film.

[0089] The thickness of the gate insulating layer 20 is, for example, 2 nm or more and 10 nm or less.

[0090] The lower insulating layer 22 is disposed on the lower electrode 12. The lower insulating layer 22 is disposed between the lower electrode 12 and the gate electrode 18.

[0091] The lower insulating layer 22 surrounds the oxide semiconductor layer 16 on a plane perpendicular to the first direction. The lower insulating layer 22 also surrounds the gate insulating layer 20 on a plane perpendicular to the first direction.

[0092] The lower insulating layer 22 is an insulator. The lower insulating layer 22 may be, for example, an oxide, a nitride, or an oxide oxynitride. The lower insulating layer 22 may contain, for example, silicon (Si) and oxygen (O). The lower insulating layer 22 may contain, for example, silicon oxide. The lower insulating layer 22 may be, for example, a silicon oxide layer.

[0093] An upper insulating layer 24 is disposed above the gate electrode 18. For example, the upper insulating layer 24 is disposed between the gate electrode 18 and the upper electrode 14.

[0094] The upper insulating layer 24 surrounds the oxide semiconductor layer 16 on a plane perpendicular to the first direction. The upper insulating layer 24 also surrounds the gate insulating layer 20 on a plane perpendicular to the first direction.

[0095] The upper insulating layer 24 is an insulator. The upper insulating layer 24 may be, for example, an oxide, a nitride, or an oxide oxynitride. The upper insulating layer 24 may contain, for example, silicon (Si) and oxygen (O). The upper insulating layer 24 may contain, for example, silicon oxide. The upper insulating layer 24 may be, for example, a silicon oxide layer.

[0096] The lower barrier conductive layer 26 is disposed below the lower electrode 12. The lower barrier conductive layer 26 is in contact with the side opposite to the oxide semiconductor layer 16 in the lower electrode 12.

[0097] The lower barrier conductive layer 26 has the function of suppressing oxygen from detaching from or entering the lower electrode 12. For example, the lower barrier conductive layer 26 has the function of suppressing the oxidation of a metal layer (not shown) disposed below the lower barrier conductive layer 26.

[0098] The lower barrier conductive layer 26 is a conductor. The lower barrier conductive layer 26 comprises a material different from that of the lower electrode 12. The lower barrier conductive layer 26 is formed of a material different from that of the lower electrode 12. The lower barrier conductive layer 26 comprises at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides.

[0099] The lower barrier conductive layer 26 may contain, for example, a metallic element selected from the group consisting of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), and tantalum (Ta). The lower barrier conductive layer 26 may be, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0100] The lower barrier conductive layer 26 may contain, for example, at least one metallic element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta), and nitrogen (N). The lower barrier conductive layer 26 may contain, for example, titanium nitride, tungsten nitride, molybdenum nitride, or tantalum nitride. The lower barrier conductive layer 26 may be, for example, a titanium nitride layer, a tungsten nitride layer, a molybdenum nitride layer, or a tantalum nitride layer.

[0101] The lower barrier conductive layer 26 may contain, for example, at least one metallic element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta), and carbon (C). The lower barrier conductive layer 26 may contain, for example, titanium carbide, tungsten carbide, molybdenum carbide, or tantalum carbide. The lower barrier conductive layer 26 may be, for example, a titanium carbide layer, a tungsten carbide layer, a molybdenum carbide layer, or a tantalum carbide layer.

[0102] The lower barrier conductive layer 26 is formed, for example, of a material with a lower oxygen permeability than the lower electrode 12. The lower barrier conductive layer 26 is formed, for example, of a material with a lower oxygen permeability than indium tin oxide.

[0103] The lower barrier conductive layer 26 is formed, for example, of a material with lower oxygen permeability than the lower interlayer insulating layer 40. The lower barrier conductive layer 26 is formed, for example, of a material with lower oxygen permeability than silicon oxide.

[0104] An upper barrier conductive layer 28 is disposed on the upper electrode 14. The upper barrier conductive layer 28 is in contact with the side opposite to the oxide semiconductor layer 16 in the upper electrode 14.

[0105] The upper barrier conductive layer 28 has the function of inhibiting oxygen from detaching from or entering the upper electrode 14. For example, the upper barrier conductive layer 28 has the function of inhibiting the oxidation of the metal layer 38 disposed on the upper electrode 14.

[0106] The upper barrier conductive layer 28 is a conductor. The upper barrier conductive layer 28 comprises a material different from that of the upper electrode 14. The upper barrier conductive layer 28 is formed of a material different from that of the upper electrode 14. The upper barrier conductive layer 28 comprises at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides.

[0107] The upper barrier conductive layer 28 may contain, for example, a metallic element selected from the group consisting of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), and tantalum (Ta). The upper barrier conductive layer 28 may be, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0108] The upper barrier conductive layer 28 may contain, for example, at least one metallic element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta), and nitrogen (N). The upper barrier conductive layer 28 may contain, for example, titanium nitride, tungsten nitride, molybdenum nitride, or tantalum nitride. The upper barrier conductive layer 28 may be, for example, a titanium nitride layer, a tungsten nitride layer, a molybdenum nitride layer, or a tantalum nitride layer.

[0109] The upper barrier conductive layer 28 may include, for example, at least one metallic element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta), and carbon (C). The upper barrier conductive layer 28 may include, for example, titanium carbide, tungsten carbide, molybdenum carbide, or tantalum carbide. The upper barrier conductive layer 28 may be, for example, a titanium carbide layer, a tungsten carbide layer, a molybdenum carbide layer, or a tantalum carbide layer.

[0110] The upper barrier conductive layer 28 is formed, for example, of a material with lower oxygen permeability than the upper electrode 14. The upper barrier conductive layer 28 is formed, for example, of a material with lower oxygen permeability than indium tin oxide.

[0111] The upper barrier conductive layer 28 is formed, for example, of a material with lower oxygen permeability than the upper interlayer insulating layer 42. The upper barrier conductive layer 28 is formed, for example, of a material with lower oxygen permeability than silicon oxide.

[0112] The first sidewall barrier layer 30 surrounds the side of the lower electrode 12. For example... Figure 3 As shown, the first sidewall barrier layer 30 surrounds the lower electrode 12 in a first cross-section perpendicular to the first direction. Figure 3 The BB' section shown is an example of the first section.

[0113] The first sidewall barrier layer 30 is connected to the lower barrier conductive layer 26 and the lower barrier insulating layer 34. The first sidewall barrier layer 30 is connected to the lower electrode 12, for example. The first sidewall barrier layer 30 is connected to the side of the lower electrode 12, for example.

[0114] The first sidewall barrier layer 30 has the function of inhibiting oxygen from detaching from the lower electrode 12 or oxygen from entering the lower electrode 12.

[0115] The first sidewall barrier layer 30 is, for example, a conductor. The first sidewall barrier layer 30 contains a material different from the lower electrode 12. The first sidewall barrier layer 30 is formed of a material different from the lower electrode 12.

[0116] The first sidewall barrier layer 30, for example, comprises the same material as the lower barrier conductive layer 26. The first sidewall barrier layer 30, for example, is formed of the same material as the lower barrier conductive layer 26. The first sidewall barrier layer 30, for example, is continuous with the lower barrier conductive layer 26. The first sidewall barrier layer 30, for example, comprises at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides.

[0117] The first sidewall barrier layer 30 may contain, for example, a metallic element selected from the group consisting of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), and tantalum (Ta). The first sidewall barrier layer 30 may be, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0118] The first sidewall barrier layer 30 may contain, for example, at least one metallic element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta), and nitrogen (N). The first sidewall barrier layer 30 may contain, for example, titanium nitride, tungsten nitride, molybdenum nitride, or tantalum nitride. The first sidewall barrier layer 30 may be, for example, a titanium nitride layer, a tungsten nitride layer, a molybdenum nitride layer, or a tantalum nitride layer.

[0119] The first sidewall barrier layer 30 includes, for example, at least one metallic element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta), and carbon (C). The lower barrier conductive layer 26 includes, for example, titanium carbide, tungsten carbide, molybdenum carbide, or tantalum carbide. The first sidewall barrier layer 30 is, for example, a titanium carbide layer, a tungsten carbide layer, a molybdenum carbide layer, or a tantalum carbide layer.

[0120] The first sidewall barrier layer 30 is formed, for example, of a material with a lower oxygen permeability than the lower electrode 12. The first sidewall barrier layer 30 is formed, for example, of a material with a lower oxygen permeability than indium tin oxide.

[0121] The first sidewall barrier layer 30 is formed, for example, of a material with lower oxygen permeability than the lower interlayer insulation layer 40. The first sidewall barrier layer 30 is formed, for example, of a material with lower oxygen permeability than silicon oxide.

[0122] The second sidewall barrier layer 32 surrounds the side of the upper electrode 14. For example... Figure 4 As shown, the second sidewall barrier layer 32 surrounds the upper electrode 14 in a second cross-section perpendicular to the first direction. Figure 4 The CC' section shown is an example of the second section.

[0123] The second sidewall barrier layer 32 is connected to the upper barrier conductive layer 28 and the upper barrier insulating layer 36. The second sidewall barrier layer 32 is connected to the upper electrode 14, for example. The second sidewall barrier layer 32 is connected to the side of the upper electrode 14 and the side of the upper barrier conductive layer 28, for example.

[0124] The second sidewall barrier layer 32 has the function of inhibiting oxygen from detaching from the upper electrode 14 or oxygen from entering the upper electrode 14.

[0125] The second sidewall barrier layer 32 is, for example, an insulator. The second sidewall barrier layer 32 may comprise at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride. The second sidewall barrier layer 32 may be, for example, an aluminum oxide layer, magnesium oxide layer, gallium oxide layer, germanium oxide layer, yttrium oxide layer, zirconium oxide layer, lanthanum oxide layer, hafnium oxide layer, tantalum oxide layer, silicon nitride layer, aluminum nitride layer, silicon oxynitride layer, or aluminum oxynitride layer.

[0126] The second sidewall barrier layer 32 is formed, for example, of a material with a lower oxygen permeability than the upper electrode 14. The second sidewall barrier layer 32 is formed, for example, of a material with a lower oxygen permeability than indium tin oxide.

[0127] The second sidewall barrier layer 32 is formed, for example, of a material with lower oxygen permeability than the upper interlayer insulating layer 42. The second sidewall barrier layer 32 is formed, for example, of a material with lower oxygen permeability than silicon oxide.

[0128] A lower barrier insulating layer 34 is disposed between the lower electrode 12 and the lower insulating layer 22. For example, in a cross-section perpendicular to the first direction, the lower barrier insulating layer 34 surrounds the oxide semiconductor layer 16 and the gate insulating layer 20.

[0129] The lower barrier insulating layer 34 is connected to the gate insulating layer 20 and the first sidewall barrier layer 30. The lower barrier insulating layer 34 is connected to, for example, the second gate insulating film 20b. The lower barrier insulating layer 34 is connected to, for example, the lower electrode 12.

[0130] The lower barrier insulating layer 34 has the function of inhibiting oxygen from detaching from the lower electrode 12 or oxygen from entering the lower electrode 12.

[0131] The lower barrier insulating layer 34 is an insulator. The lower barrier insulating layer 34 contains a material different from the lower insulating layer 22. The lower barrier insulating layer 34 is formed of a material different from the lower insulating layer 22.

[0132] The lower barrier insulating layer 34 may comprise, for example, at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride. The lower barrier insulating layer 34 may be, for example, an aluminum oxide layer, magnesium oxide layer, gallium oxide layer, germanium oxide layer, yttrium oxide layer, zirconium oxide layer, lanthanum oxide layer, hafnium oxide layer, tantalum oxide layer, silicon nitride layer, aluminum nitride layer, silicon oxynitride layer, or aluminum oxynitride layer.

[0133] The lower barrier insulating layer 34 is formed, for example, of a material with lower oxygen permeability than the lower electrode 12. The lower barrier insulating layer 34 is formed, for example, of a material with lower oxygen permeability than indium tin oxide.

[0134] The lower barrier insulating layer 34 is formed, for example, of a material with lower oxygen permeability than the lower insulating layer 22. The lower barrier insulating layer 34 is formed, for example, of a material with lower oxygen permeability than silicon oxide.

[0135] An upper barrier insulating layer 36 is disposed between the upper electrode 14 and the upper insulating layer 24. For example, in a cross-section perpendicular to the first direction, the upper barrier insulating layer 36 surrounds the oxide semiconductor layer 16 and the gate insulating layer 20.

[0136] The upper barrier insulating layer 36 is connected to the gate insulating layer 20 and the second sidewall barrier layer 32. The upper barrier insulating layer 36 is connected to, for example, the second gate insulating film 20b. The upper barrier insulating layer 36 is connected to, for example, the upper electrode 14.

[0137] The upper barrier insulating layer 36 has the function of inhibiting oxygen from detaching from the upper electrode 14 or oxygen from entering the upper electrode 14.

[0138] The upper barrier insulating layer 36 is an insulator. The upper barrier insulating layer 36 contains a material different from that of the upper insulating layer 24. The upper barrier insulating layer 36 is formed of a material different from that of the upper insulating layer 24.

[0139] The upper barrier insulating layer 36 may comprise, for example, at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride. The upper barrier insulating layer 36 may be, for example, an aluminum oxide layer, magnesium oxide layer, gallium oxide layer, germanium oxide layer, yttrium oxide layer, zirconium oxide layer, lanthanum oxide layer, hafnium oxide layer, tantalum oxide layer, silicon nitride layer, aluminum nitride layer, silicon oxynitride layer, or aluminum oxynitride layer.

[0140] The upper barrier insulating layer 36 is formed, for example, of a material with lower oxygen permeability than the upper electrode 14. The upper barrier insulating layer 36 is formed, for example, of a material with lower oxygen permeability than indium tin oxide.

[0141] The upper barrier insulating layer 36 is formed, for example, of a material with lower oxygen permeability than the upper insulating layer 24. The upper barrier insulating layer 36 is formed, for example, of a material with lower oxygen permeability than silicon oxide.

[0142] A metal layer 38 is disposed on top of the upper barrier conductive layer 28. The upper barrier conductive layer 28 is disposed between the metal layer 38 and the upper electrode 14. For example, the metal layer 38 is in contact with the upper barrier conductive layer 28.

[0143] Metal layer 38 is a conductor. Metal layer 38 contains a different material than the upper barrier conductive layer 28. Metal layer 38 is formed of a different material than the upper barrier conductive layer 28. Metal layer 38 contains a metal.

[0144] Metal layer 38 may contain, for example, a metallic element selected from the group consisting of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), and tantalum (Ta). Metal layer 38 may be, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0145] The lower interlayer insulation layer 40 is disposed below the lower barrier insulation layer 34. The lower interlayer insulation layer 40 is disposed to the side of the lower electrode 12.

[0146] The lower interlayer insulating layer 40 surrounds the lower electrode 12 in a cross-section perpendicular to the first direction. The lower interlayer insulating layer 40 also surrounds the first sidewall barrier layer 30 in a cross-section perpendicular to the first direction.

[0147] The lower interlayer insulation layer 40, for example, has the function of electrically insulating the wiring layer (not shown) from the lower electrode 12.

[0148] The lower interlayer insulating layer 40 is an insulator. The lower interlayer insulating layer 40 is, for example, an oxide, a nitride, or an oxide oxynitride. The lower interlayer insulating layer 40 may contain, for example, silicon (Si) and oxygen (O). The lower interlayer insulating layer 40 may contain, for example, silicon oxide. The lower interlayer insulating layer 40 may be, for example, a silicon oxide layer.

[0149] The upper interlayer insulating layer 42 is disposed above the upper barrier insulating layer 36. The upper interlayer insulating layer 42 is disposed on the side of the upper electrode 14.

[0150] The upper interlayer insulating layer 42 surrounds the upper electrode 14 in a cross-section perpendicular to the first direction. The upper interlayer insulating layer 42 also surrounds the second sidewall barrier layer 32 in a cross-section perpendicular to the first direction.

[0151] The upper interlayer insulation layer 42, for example, has the function of electrically insulating the wiring layer (not shown) from the upper electrode 14.

[0152] The upper interlayer insulating layer 42 is an insulator. The upper interlayer insulating layer 42 may be, for example, an oxide, a nitride, or an oxide oxynitride. The upper interlayer insulating layer 42 may contain, for example, silicon (Si) and oxygen (O). The lower interlayer insulating layer 40 may contain, for example, silicon oxide. The upper interlayer insulating layer 42 may be, for example, a silicon oxide layer.

[0153] Next, an example of the manufacturing method of the semiconductor device according to the first embodiment will be described.

[0154] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 5-12 Respectively represent and Figure 1 The corresponding cross-section. Figures 5-12 This is a diagram illustrating an example of a manufacturing method for transistor 100.

[0155] The following description uses the following case as an example: the lower electrode 12 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a stacked structure of silicon oxide film and silicon nitride film, the lower insulating layer 22 is a silicon oxide layer, the upper insulating layer 24 is a silicon oxide layer, the lower barrier conductive layer 26 is a titanium nitride layer, the upper barrier conductive layer 28 is a titanium nitride layer, the first sidewall barrier layer 30 is a titanium nitride layer, the second sidewall barrier layer 32 is a silicon nitride layer, the lower barrier insulating layer 34 is a silicon nitride layer, the upper barrier insulating layer 36 is a silicon nitride layer, the metal layer 38 is a tungsten layer, the lower interlayer insulating layer 40 is a silicon oxide layer, and the upper interlayer insulating layer 42 is a silicon oxide layer.

[0156] First, a first silicon oxide film 51 is formed on a substrate (not shown). The first silicon oxide film 51 is formed, for example, by chemical vapor deposition (CVD).

[0157] Next, an opening (not shown) is formed on the first silicon oxide film 51. The opening on the first silicon oxide film 51 is formed, for example, using photolithography and reactive ion etching (RIE).

[0158] Next, a first titanium nitride film 52 and a first indium tin oxide film 53 are formed in the opening of the first silicon oxide film 51. The first titanium nitride film 52 and the first indium tin oxide film 53 are formed, for example, by CVD.

[0159] Next, the first titanium nitride film 52 and the first indium tin oxide film 53 on the surface of the first silicon oxide film 51 are removed. Figure 5 For example, the first titanium nitride film 52 and the first indium tin oxide film 53 are removed using chemical mechanical polishing (CMP).

[0160] The first silicon oxide film 51 ultimately becomes the lower interlayer insulating layer 40. The first titanium nitride film 52 ultimately becomes the lower barrier conductive layer 26 and the first sidewall barrier layer 30. The first indium tin oxide film 53 ultimately becomes the lower electrode 12.

[0161] Next, on the first indium tin oxide film 53, a first silicon nitride film 54, a second silicon oxide film 55, a first tungsten film 56, a third silicon oxide film 57, and a second silicon nitride film 58 are sequentially deposited along the first direction. Figure 6 The first silicon nitride film 54, the second silicon oxide film 55, the first tungsten film 56, the third silicon oxide film 57, and the second silicon nitride film 58 are formed, for example, by using a CVD method.

[0162] A portion of the first silicon nitride film 54 ultimately becomes the lower barrier insulating layer 34. A portion of the second silicon oxide film 55 ultimately becomes the lower insulating layer 22. A portion of the first tungsten film 56 ultimately becomes the gate electrode 18. A portion of the third silicon oxide film 57 ultimately becomes the upper insulating layer 24. A portion of the second silicon nitride film 58 ultimately becomes the upper barrier insulating layer 36.

[0163] Next, an opening 60 is formed from the surface of the second silicon nitride film 58 through the second silicon nitride film 58, the third silicon oxide film 57, the first tungsten film 56, the second silicon oxide film 55, and the first silicon nitride film 54, reaching the first indium tin oxide film 53. Figure 7 The opening 60 is formed, for example, using photolithography and RIE.

[0164] Next, a third silicon nitride film 61 and a fourth silicon oxide film 62 are formed on the inner side of the opening 60. Figure 8 The third silicon nitride film 61 and the fourth silicon oxide film 62 are formed, for example, by CVD deposition and RIE etching. The third silicon nitride film 61 ultimately becomes the second gate insulating film 20b. In addition, the fourth silicon oxide film 62 ultimately becomes the first gate insulating film 20a.

[0165] Next, an indium gallium zinc oxide film 63 is embedded in the opening 60. Figure 9 The indium gallium zinc oxide film 63 ultimately becomes the oxide semiconductor layer 16. For example, after being deposited by CVD, a portion of the indium gallium zinc oxide film 63 is removed using CMP.

[0166] Next, a second indium tin oxide film 64, a second titanium nitride film 65, and a second tungsten film 66 are sequentially formed on the indium gallium zinc oxide film 63. The second indium tin oxide film 64, the second titanium nitride film 65, and the second tungsten film 66 are formed, for example, using a CVD method.

[0167] Next, the second indium tin oxide film 64, the second titanium nitride film 65, and the second tungsten film 66 are patterned. Figure 10 The patterning of the second indium tin oxide film 64, the second titanium nitride film 65, and the second tungsten film 66 is performed, for example, by photolithography and RIE.

[0168] The second indium tin oxide film 64 ultimately becomes the upper electrode 14. The second titanium nitride film 65 ultimately becomes the upper barrier conductive layer 28. In addition, the second tungsten film 66 ultimately becomes the metal layer 38.

[0169] Next, a heat treatment is performed to adjust the amount of oxygen vacancies in the indium gallium zinc oxide film 63. For example, if it is desired to increase the amount of oxygen vacancies, a heat treatment is performed in a non-oxidizing atmosphere to promote the removal of oxygen from the indium gallium zinc oxide film 63. Alternatively, if it is desired to decrease the amount of oxygen vacancies, a heat treatment is performed in an oxidizing atmosphere to promote the oxygen supply to the indium gallium zinc oxide film 63.

[0170] The second indium tin oxide film 64 serves as a pathway for oxygen to escape from the indium gallium zinc oxide film 63, or a pathway for supplying oxygen to the indium gallium zinc oxide film 63. By adjusting the amount of oxygen vacancies in the indium gallium zinc oxide film 63, for example, the threshold voltage of the transistor can be set to a desired value.

[0171] Next, a fourth silicon nitride film 67 is formed on the sides of the second indium tin oxide film 64, the second titanium nitride film 65, and the second tungsten film 66. Figure 11 The fourth silicon nitride film 67 is formed by deposition using CVD and etching using RIE. The fourth silicon nitride film 67 ultimately becomes the second sidewall barrier layer 32.

[0172] Next, a fifth silicon oxide film 68 is formed on the side of the fourth silicon nitride film 67. Figure 12 The fifth silicon oxide film 68 is formed, for example, by CVD. The fifth silicon oxide film 68 ultimately becomes the upper interlayer insulating layer 42.

[0173] Using the above manufacturing methods, manufacture Figure 1 , Figure 2 , Figure 3 and Figure 4 The transistor 100 shown.

[0174] Next, the function and effects of the semiconductor device of the first embodiment will be explained.

[0175] In oxide semiconductor transistors, there are cases where the transistor characteristics change due to heat treatment after the transistor structure is formed. For example, the threshold voltage of the transistor may change due to oxygen detaching from the oxide semiconductor layer that forms the transistor channel, or due to oxygen being supplied to the oxide semiconductor layer.

[0176] The threshold voltage of a transistor changes due to variations in the amount of oxygen vacancies in the oxide semiconductor layer that can act as donors. For example, changes in the amount of oxygen vacancies lead to changes in the transistor's channel length, which in turn causes a change in the transistor's threshold voltage.

[0177] Figure 13 This is a schematic cross-sectional view of a comparative example semiconductor device. Figure 13 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0178] The comparative example semiconductor device is transistor 900. The comparative example transistor 900 differs from the transistor 100 of the first embodiment in that it does not have a first sidewall barrier layer 30, a second sidewall barrier layer 32, a lower barrier insulating layer 34, and an upper barrier insulating layer 36.

[0179] Figure 14 This is an explanatory diagram of a problem with a comparative example semiconductor device.

[0180] For example, imagine in the formation Figure 14 After constructing the transistor 900 of the comparative example shown, a heat treatment is applied. For example, when heat treatment is performed in a non-oxidizing atmosphere, oxygen is removed from the oxide semiconductor layer 16 through the lower electrode 12 or the upper electrode 14. Alternatively, for example, when heat treatment is performed in an oxidizing atmosphere, oxygen is supplied to the oxide semiconductor layer 16 through the lower electrode 12 or the upper electrode 14.

[0181] In the comparative example transistor 900, due to the existence of, for example, Figure 14 The dashed double arrows indicate the oxygen movement path, making it easy for oxygen to escape from or be supplied to the oxide semiconductor layer 16. Because oxygen can easily escape from or be supplied to the oxide semiconductor layer 16, variations in transistor characteristics are easily generated.

[0182] The transistor 100 of the first embodiment includes a first sidewall barrier layer 30, a second sidewall barrier layer 32, a lower barrier insulating layer 34, and an upper barrier insulating layer 36. In the transistor 100 of the first embodiment, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 are surrounded by a gate insulating layer 20, a lower barrier conductive layer 26, an upper barrier conductive layer 28, a first sidewall barrier layer 30, a second sidewall barrier layer 32, a lower barrier insulating layer 34, and an upper barrier insulating layer 36.

[0183] The gate insulating layer 20, lower barrier conductive layer 26, upper barrier conductive layer 28, first sidewall barrier layer 30, second sidewall barrier layer 32, lower barrier insulating layer 34, and upper barrier insulating layer 36 have high oxygen barrier properties. In other words, the oxygen permeability of the gate insulating layer 20, lower barrier conductive layer 26, upper barrier conductive layer 28, first sidewall barrier layer 30, second sidewall barrier layer 32, lower barrier insulating layer 34, and upper barrier insulating layer 36 is low.

[0184] For example, the oxygen permeability of the gate insulating layer 20, the lower barrier conductive layer 26, the upper barrier conductive layer 28, the first sidewall barrier layer 30, the second sidewall barrier layer 32, the lower barrier insulating layer 34, and the upper barrier insulating layer 36 is lower than that of the lower insulating layer 22, the upper insulating layer 24, the lower interlayer insulating layer 40, and the upper interlayer insulating layer 42. Additionally, for example, the oxygen permeability of the gate insulating layer 20, the lower barrier conductive layer 26, the upper barrier conductive layer 28, the first sidewall barrier layer 30, the second sidewall barrier layer 32, the lower barrier insulating layer 34, and the upper barrier insulating layer 36 is lower than that of the lower electrode 12 or the upper electrode 14.

[0185] For example, the oxygen permeability of the gate insulating layer 20, the lower barrier conductive layer 26, the upper barrier conductive layer 28, the first sidewall barrier layer 30, the second sidewall barrier layer 32, the lower barrier insulating layer 34, and the upper barrier insulating layer 36 is lower than that of silicon oxide. Additionally, for example, the oxygen permeability of the gate insulating layer 20, the lower barrier conductive layer 26, the upper barrier conductive layer 28, the first sidewall barrier layer 30, the second sidewall barrier layer 32, the lower barrier insulating layer 34, and the upper barrier insulating layer 36 is lower than that of indium tin oxide.

[0186] In the transistor 100 of the first embodiment, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 are surrounded by a gate insulating layer 20, a lower barrier conductive layer 26, an upper barrier conductive layer 28, a first sidewall barrier layer 30, a second sidewall barrier layer 32, a lower barrier insulating layer 34, and an upper barrier insulating layer 36. In other words, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 of the transistor 100 of the first embodiment are surrounded by layers that have a barrier effect on oxygen. Therefore, it is possible to suppress the detachment of oxygen from the oxide semiconductor layer 16 or the supply of oxygen to the oxide semiconductor layer 16 during heat treatment after the transistor structure is formed.

[0187] Therefore, changes in transistor characteristics accompanying heat treatment are suppressed. Thus, according to the first embodiment, a transistor 100 with excellent transistor characteristics can be realized.

[0188] From the viewpoint of achieving a high barrier to oxygen, the lower barrier conductive layer 26, the upper barrier conductive layer 28, and the first sidewall barrier layer 30 are preferably metal nitrides. From the viewpoint of achieving a high barrier to oxygen, the lower barrier conductive layer 26, the upper barrier conductive layer 28, and the first sidewall barrier layer 30 are preferably composed of titanium (Ti) and nitrogen (N). From the viewpoint of achieving a high barrier to oxygen, the lower barrier conductive layer 26, the upper barrier conductive layer 28, and the first sidewall barrier layer 30 are preferably composed of titanium nitride.

[0189] From the viewpoint of achieving a high barrier to oxygen, the gate insulating layer 20, the second sidewall barrier layer 32, the lower barrier insulating layer 34, and the upper barrier insulating layer 36 are preferably nitrides or oxides of nitrogen. From the viewpoint of achieving a high barrier to oxygen, the gate insulating layer 20, the second sidewall barrier layer 32, the lower barrier insulating layer 34, and the upper barrier insulating layer 36 are preferably composed of silicon (Si) and nitrogen (N). From the viewpoint of achieving a high barrier to oxygen, the gate insulating layer 20, the second sidewall barrier layer 32, the lower barrier insulating layer 34, and the upper barrier insulating layer 36 are preferably composed of silicon nitride.

[0190] (Example 1 of the variations)

[0191] The semiconductor device of the first variation of the first embodiment differs from the semiconductor device of the first embodiment in that the first sidewall barrier layer 30 is an insulator and the second sidewall barrier layer 32 is a conductor.

[0192] Figure 15 This is a schematic cross-sectional view of a semiconductor device according to a first variation of the first embodiment. The semiconductor device in the first variation of the first embodiment is a transistor 101. Figure 15 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0193] The first sidewall barrier layer 30 is an insulator. The first sidewall barrier layer 30 comprises at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride. The second sidewall barrier layer 32 is, for example, an aluminum oxide layer, magnesium oxide layer, gallium oxide layer, germanium oxide layer, yttrium oxide layer, zirconium oxide layer, lanthanum oxide layer, hafnium oxide layer, tantalum oxide layer, silicon nitride layer, aluminum nitride layer, silicon oxynitride layer, or aluminum oxynitride layer.

[0194] The second sidewall barrier layer 32 is a conductor. The second sidewall barrier layer 32 may include, for example, at least one conductor selected from the group consisting of metals, metal nitrides and metal carbides.

[0195] The second sidewall barrier layer 32 may contain, for example, a metallic element selected from the group consisting of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), and tantalum (Ta). The second sidewall barrier layer 32 may be, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0196] The second sidewall barrier layer 32 may contain, for example, at least one metallic element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta), and nitrogen (N). The second sidewall barrier layer 32 may contain, for example, titanium nitride, tungsten nitride, molybdenum nitride, or tantalum nitride. The second sidewall barrier layer 32 may be, for example, a titanium nitride layer, a tungsten nitride layer, a molybdenum nitride layer, or a tantalum nitride layer.

[0197] The second sidewall barrier layer 32 includes, for example, at least one metallic element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta), and carbon (C). The lower barrier conductive layer 26 includes, for example, titanium carbide, tungsten carbide, molybdenum carbide, or tantalum carbide. The second sidewall barrier layer 32 is, for example, a titanium carbide layer, a tungsten carbide layer, a molybdenum carbide layer, or a tantalum carbide layer.

[0198] In the transistor 101 of the first variation of the first embodiment, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 are surrounded by a layer that has a barrier effect on oxygen. Therefore, similar to the transistor 100 of the first embodiment, changes in transistor characteristics caused by heat treatment are suppressed.

[0199] (Second variation example)

[0200] The semiconductor device of the second variation of the first embodiment differs from the semiconductor device of the first embodiment in that it further includes a core insulating layer surrounded by an oxide semiconductor layer.

[0201] Figure 16 This is a schematic cross-sectional view of a semiconductor device in the second variation of the first embodiment. The semiconductor device in the second variation of the first embodiment is a transistor 102. Figure 16 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0202] Transistor 102 includes a core insulating layer 70. The core insulating layer 70 is disposed between the lower electrode 12 and the upper electrode 14. The core insulating layer 70 is surrounded by an oxide semiconductor layer 16. In a cross-section perpendicular to the first direction, the core insulating layer 70 is surrounded by the oxide semiconductor layer 16.

[0203] In the transistor 102 of the second variation of the first embodiment, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 are surrounded by a layer that has a barrier effect on oxygen. Therefore, similar to the transistor 100 of the first embodiment, changes in transistor characteristics caused by heat treatment are suppressed.

[0204] (Example 3)

[0205] The difference between the semiconductor device of the third variation of the first embodiment and the semiconductor device of the first embodiment is that the oxide semiconductor layer has a cone shape.

[0206] Figure 17 This is a schematic cross-sectional view of a semiconductor device according to the third variation of the first embodiment. The semiconductor device in the third variation of the first embodiment is a transistor 103. Figure 17 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0207] The oxide semiconductor layer 16 of transistor 103 has a conical shape. In a cross-section parallel to the first direction, the oxide semiconductor layer 16 has a positive conical shape. In other words, the width of the oxide semiconductor layer 16 in the second direction narrows from the upper electrode 14 toward the lower electrode 12.

[0208] In the transistor 103 of the third variation of the first embodiment, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 are surrounded by a layer that has a barrier effect on oxygen. Therefore, similar to the transistor 100 of the first embodiment, changes in transistor characteristics caused by heat treatment are suppressed.

[0209] According to the first embodiment and its variations, it is possible to suppress changes in transistor characteristics associated with heat treatment and realize a semiconductor device with excellent transistor characteristics.

[0210] (Second Implementation)

[0211] The semiconductor device according to the second embodiment includes: a first electrode comprising a metal oxide; a second electrode comprising a metal oxide; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode surrounding the oxide semiconductor layer; a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, comprising silicon (Si) and nitrogen (N); a first insulating layer disposed between the first electrode and the gate electrode; a second insulating layer disposed between the gate electrode and the first insulating layer; a first conductive layer contacting the surface of the first electrode opposite to the oxide semiconductor layer, comprising at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; a second conductive layer contacting the surface of the second electrode opposite to the oxide semiconductor layer, surrounded by the first electrode in a first cross-section perpendicular to a first direction from the first electrode toward the second electrode, comprising at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; a metal layer surrounded by the second conductive layer in the first cross-section; and a first layer surrounding the first electrode in a second cross-section perpendicular to the first direction. An electrode, connected to a first conductive layer, comprises at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride, or at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; a third insulating layer, disposed between the first electrode and the first insulating layer, connected to the gate insulating layer and the first layer, comprises at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, and... At least one insulator selected from the group consisting of zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride; and a fourth insulating layer having a second insulating layer disposed between itself and a gate electrode, surrounding a metal layer in a third cross-section perpendicular to a first direction, and being in contact with a second conductive layer and a gate insulating layer, comprising at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride.

[0212] The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the second conductive layer is surrounded by the upper electrode, and the metal layer is surrounded by the second conductive layer. Furthermore, the semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that it does not have a second layer. Hereinafter, some descriptions that are repeated in the first embodiment have been omitted.

[0213] Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 19 yes Figure 18 DD' sectional view. Figure 20 yes Figure 18 EE' sectional view. Figure 21 yes Figure 18 FF' section view. Figure 22 yes Figure 18 GG' sectional view. Figure 18 In this context, the up-down direction is referred to as the first direction. Figure 18 In this context, the left and right directions are referred to as the second direction. The second direction is perpendicular to the first direction.

[0214] Section EE' is an example of section 2. Section FF' is an example of section 1. Section GG' is an example of section 3.

[0215] The semiconductor device in the second embodiment is a transistor 200. The transistor 200 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. In the transistor 200, a gate electrode is disposed surrounding the oxide semiconductor layer forming the channel. The transistor 200 is a so-called SGT (Structured Ground Tunnel). The transistor 200 is a so-called vertical transistor.

[0216] The transistor 200 includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a lower insulating layer 22, an upper insulating layer 24, a lower barrier conductive layer 26, an upper barrier conductive layer 28, a first sidewall barrier layer 30, a lower barrier insulating layer 34, an upper barrier insulating layer 36, a metal layer 38, and a lower interlayer insulating layer 40. The gate insulating layer 20 includes a first gate insulating film 20a and a second gate insulating film 20b.

[0217] The lower electrode 12 is an example of the first electrode. The upper electrode 14 is an example of the second electrode. The lower insulating layer 22 is an example of the first insulating layer. The upper insulating layer 24 is an example of the second insulating layer. The lower barrier conductive layer 26 is an example of the first conductive layer. The upper barrier conductive layer 28 is an example of the second conductive layer. The first sidewall barrier layer 30 is an example of the first layer. The lower barrier insulating layer 34 is an example of the third insulating layer. The upper barrier insulating layer 36 is an example of the fourth insulating layer. The first gate insulating film 20a is an example of the first film. The second gate insulating film 20b is an example of the second film.

[0218] The upper electrode 14 is disposed on the oxide semiconductor layer 16. The upper electrode 14 is electrically connected to the oxide semiconductor layer 16. For example, the upper electrode 14 is connected to the oxide semiconductor layer 16. The upper electrode 14 functions as the source electrode or drain electrode of the transistor 200.

[0219] like Figure 21As shown, the upper electrode 14 is surrounded by an upper insulating layer 24 and a gate insulating layer 20. In a first cross-section perpendicular to the first direction, the upper electrode 14 is surrounded by the upper insulating layer 24 and the gate insulating layer 20. The upper electrode 14 is, for example, connected to the gate insulating layer 20. Figure 21 The FF' section shown is an example of the first section.

[0220] like Figure 19 As shown, the gate electrode 18 surrounds the oxide semiconductor layer 16 in a cross-section perpendicular to the first direction. The gate electrode 18 is disposed around the oxide semiconductor layer 16.

[0221] An upper barrier conductive layer 28 is disposed on the upper electrode 14. The upper barrier conductive layer 28 is in contact with the side opposite to the oxide semiconductor layer 16 in the upper electrode 14.

[0222] like Figure 21 As shown, the upper barrier conductive layer 28 is surrounded by the upper electrode 14. In a first cross-section perpendicular to the first direction, the upper barrier conductive layer 28 is surrounded by the upper electrode 14.

[0223] The first sidewall barrier layer 30 surrounds the side of the lower electrode 12. For example... Figure 20 As shown, the first sidewall barrier layer 30 surrounds the lower electrode 12 in a second cross-section perpendicular to the first direction. Figure 20 The EE' section shown is an example of the second section.

[0224] An upper barrier insulating layer 36 is disposed on top of the upper insulating layer 24. The upper insulating layer 24 is disposed between the gate electrode 18 and the upper barrier insulating layer 36. Figure 22 As shown, the upper barrier insulating layer 36 surrounds the metal layer 38 in a third cross-section perpendicular to the first direction. Figure 22 The GG' section shown is an example of the third section.

[0225] The upper barrier insulating layer 36 is connected to the upper barrier conductive layer 28 and the gate insulating layer 20. The upper barrier insulating layer 36 is connected to, for example, the second gate insulating film 20b. The upper barrier insulating layer 36 is connected to, for example, the upper electrode 14.

[0226] An upper electrode 14 is disposed between the upper barrier insulating layer 36 and the oxide semiconductor layer 16.

[0227] A metal layer 38 is disposed on top of the upper barrier conductive layer 28. The upper barrier conductive layer 28 is disposed between the metal layer 38 and the upper electrode 14. For example, the metal layer 38 is in contact with the upper barrier conductive layer 28.

[0228] like Figure 21As shown, the metal layer 38 is surrounded by the upper barrier conductive layer 28. In a first cross-section perpendicular to the first direction, the metal layer 38 is surrounded by the upper barrier conductive layer 28.

[0229] Next, an example of the manufacturing method of the semiconductor device according to the second embodiment will be described.

[0230] Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 and Figure 33 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. Figures 23-33 Respectively represent and Figure 18 The corresponding cross-section. Figures 23-33 This is a diagram illustrating an example of a manufacturing method for transistor 200.

[0231] The following description will be based on the case where the lower electrode 12 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a stacked structure of silicon oxide film and silicon nitride film, the lower insulating layer 22 is a silicon oxide layer, the upper insulating layer 24 is a silicon oxide layer, the lower barrier conductive layer 26 is a titanium nitride layer, the upper barrier conductive layer 28 is a titanium nitride layer, the first sidewall barrier layer 30 is a titanium nitride layer, the lower barrier insulating layer 34 is a silicon nitride layer, the upper barrier insulating layer 36 is a silicon nitride layer, the metal layer 38 is a tungsten layer, and the lower interlayer insulating layer 40 is a silicon oxide layer.

[0232] First, a first silicon oxide film 51 is formed on a substrate (not shown). The first silicon oxide film 51 is formed, for example, by a CVD method.

[0233] Next, an opening (not shown) is formed on the first silicon oxide film 51. The opening on the first silicon oxide film 51 is formed, for example, using photolithography and RIE.

[0234] Next, a first titanium nitride film 52 and a first indium tin oxide film 53 are formed in the opening of the first silicon oxide film 51. The first titanium nitride film 52 and the first indium tin oxide film 53 are formed, for example, by CVD.

[0235] Next, the first titanium nitride film 52 and the first indium tin oxide film 53 on the surface of the first silicon oxide film 51 are removed. Figure 23 The removal of the first titanium nitride film 52 and the first indium tin oxide film 53 is, for example, achieved using the CMP method.

[0236] The first silicon oxide film 51 ultimately becomes the lower interlayer insulating layer 40. The first titanium nitride film 52 ultimately becomes the lower barrier conductive layer 26 and the first sidewall barrier layer 30. The first indium tin oxide film 53 ultimately becomes the lower electrode 12.

[0237] Next, on the first indium tin oxide film 53, a first silicon nitride film 54, a second silicon oxide film 55, a first tungsten film 56, and a third silicon oxide film 57 are sequentially deposited along the first direction. Figure 24 The first silicon nitride film 54, the second silicon oxide film 55, the first tungsten film 56, and the third silicon oxide film 57 are formed, for example, using a CVD method.

[0238] A portion of the first silicon nitride film 54 ultimately becomes the lower barrier insulating layer 34. A portion of the second silicon oxide film 55 ultimately becomes the lower insulating layer 22. A portion of the first tungsten film 56 ultimately becomes the gate electrode 18. A portion of the third silicon oxide film 57 ultimately becomes the upper insulating layer 24.

[0239] Next, an opening 60 is formed from the surface of the third silicon oxide film 57 through the third silicon oxide film 57, the first tungsten film 56, the second silicon oxide film 55, and the first silicon nitride film 54, reaching the first indium tin oxide film 53. Figure 25 The opening 60 is formed, for example, using photolithography and RIE.

[0240] Next, a second silicon nitride film 58 and a fourth silicon oxide film 62 are formed on the inner side of the opening 60. Figure 26 The second silicon nitride film 58 and the fourth silicon oxide film 62 are formed, for example, by deposition using CVD and etching using RIE. The second silicon nitride film 58 ultimately becomes the second gate insulating film 20b. Furthermore, the fourth silicon oxide film 62 ultimately becomes the first gate insulating film 20a.

[0241] Next, an indium gallium zinc oxide film 63 is embedded in the opening 60. Figure 27 The indium gallium zinc oxide film 63 ultimately becomes the oxide semiconductor layer 16. For example, after being deposited by CVD, a portion of the indium gallium zinc oxide film 63 is removed using CMP.

[0242] Next, a portion of the upper part of the indium gallium zinc oxide film 63 is selectively etched back. Figure 28 The etching back of the indium gallium zinc oxide film 63 is performed, for example, using the RIE method.

[0243] Next, a second indium tin oxide film 64, a second titanium nitride film 65, and a second tungsten film 66 are sequentially formed on the indium gallium zinc oxide film 63. Figure 29 The second indium tin oxide film 64, the second titanium nitride film 65, and the second tungsten film 66 are formed, for example, using a CVD method.

[0244] A portion of the second indium tin oxide film 64 ultimately becomes the upper electrode 14. A portion of the second titanium nitride film 65 ultimately becomes the upper barrier conductive layer 28. Additionally, a portion of the second tungsten film 66 ultimately becomes the metal layer 38.

[0245] Next, the upper parts of the second indium tin oxide film 64, the second titanium nitride film 65, and the second tungsten film 66 are removed to planarize them. Figure 30 The upper portions of the second indium tin oxide film 64, the second titanium nitride film 65, and the second tungsten film 66 are planarized, for example, using the CMP method.

[0246] Next, relative to the second tungsten film 66, the second indium tin oxide film 64, the second titanium nitride film 65, the fourth silicon oxide film 62, the second silicon nitride film 58, and the third silicon oxide film 57 are selectively etched back. Figure 31 The second tungsten film 66 remains in a protruding state. Selective etchback is carried out, for example, by the RIE method.

[0247] Next, a heat treatment is performed to adjust the amount of oxygen vacancies in the indium gallium zinc oxide film 63. For example, if it is desired to increase the amount of oxygen vacancies, a heat treatment is performed in a non-oxidizing atmosphere to promote the removal of oxygen from the indium gallium zinc oxide film 63. Alternatively, if it is desired to decrease the amount of oxygen vacancies, a heat treatment is performed in an oxidizing atmosphere to promote the oxygen supply to the indium gallium zinc oxide film 63.

[0248] The second indium tin oxide film 64 serves as a pathway for oxygen to escape from the indium gallium zinc oxide film 63, or a pathway for supplying oxygen to the indium gallium zinc oxide film 63. By adjusting the amount of oxygen vacancies in the indium gallium zinc oxide film 63, for example, the threshold voltage of the transistor can be set to a desired value.

[0249] Next, a third silicon nitride film 61 is formed on top of the second indium tin oxide film 64, the second titanium nitride film 65, and the second tungsten film 66. Figure 32 The third silicon nitride film 61 is formed, for example, using a CVD method. A portion of the third silicon nitride film 61 eventually becomes the upper barrier insulating layer 36.

[0250] Next, the upper surface of the third silicon nitride film 61 is planarized, exposing the surface of the second tungsten film 66. Figure 33 The planarization of the upper surface of the third silicon nitride film 61 is performed, for example, using the CMP method.

[0251] Using the above manufacturing methods, manufacture Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 The transistor 200 shown.

[0252] Next, the function and effects of the semiconductor device in the second embodiment will be explained.

[0253] In the transistor 200 of the second embodiment, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 are surrounded by a gate insulating layer 20, a lower barrier conductive layer 26, an upper barrier conductive layer 28, a first sidewall barrier layer 30, a lower barrier insulating layer 34, and an upper barrier insulating layer 36. In other words, in the transistor 200 of the second embodiment, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 are surrounded by layers that have a barrier effect on oxygen. Therefore, it suppresses the detachment of oxygen from the oxide semiconductor layer 16 or the supply of oxygen to the oxide semiconductor layer 16 during heat treatment after the transistor structure is formed.

[0254] Therefore, by performing the same function as the semiconductor device of the first embodiment, variations in transistor characteristics caused by heat treatment are suppressed. Thus, according to the second embodiment, a transistor 200 with excellent transistor characteristics can be realized.

[0255] Furthermore, in transistor 200, metal layer 38 can be formed on top of oxide semiconductor layer 16 in a self-aligned manner relative to oxide semiconductor layer 16. Therefore, for example, it is not necessary to ensure alignment margin relative to oxide semiconductor layer 16 when forming metal layer 38. Therefore, for example, when transistor 200 is arranged in an array, the spacing of transistor 200 can be reduced.

[0256] According to the second embodiment, it is possible to suppress changes in transistor characteristics associated with heat treatment and to realize a semiconductor device with excellent transistor characteristics.

[0257] (Third Implementation)

[0258] The semiconductor device according to the third embodiment includes: a first electrode comprising a metal oxide; a second electrode comprising a metal oxide; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode surrounding the oxide semiconductor layer; a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, surrounding the second electrode in a first cross-section perpendicular to a first direction from the first electrode toward the second electrode, and comprising silicon (Si) and nitrogen (N); a first insulating layer disposed between the first electrode and the gate electrode; a second insulating layer disposed between the gate electrode and the first insulating layer; a first conductive layer contacting the surface of the first electrode opposite to the oxide semiconductor layer, and comprising at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; and a second conductive layer contacting the surface of the second electrode opposite to the oxide semiconductor layer, and contacting the gate insulating layer, and in a cross-section perpendicular to the gate electrode. A second insulating layer is disposed between the electrodes, comprising at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; a first layer surrounds the first electrode in a second cross-section perpendicular to the first direction and is connected to the first conductive layer, comprising at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride, or at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; and a third insulating layer is disposed between the first electrode and the first insulating layer and is connected to the gate insulating layer and the first layer, comprising at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride.

[0259] The semiconductor device of the third embodiment differs from that of the semiconductor device of the first embodiment in that the second electrode is surrounded by a gate insulating layer and does not have a second and a fourth insulating layer. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0260] Figure 34 , Figure 35 , Figure 36 and Figure 37 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 35 yes Figure 34 HH' sectional view. Figure 36 yes Figure 34 Sectional view II'. Figure 37 yes Figure 34 A cross-sectional view of JJ'. Figure 34 In this context, the up-down direction is referred to as the first direction. Figure 34 In this context, the left and right directions are referred to as the second direction. The second direction is perpendicular to the first direction.

[0261] Section II' is an example of section 2. Section JJ' is an example of section 1.

[0262] The semiconductor device in the third embodiment is a transistor 300. The transistor 300 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. In the transistor 300, a gate electrode is disposed surrounding the oxide semiconductor layer forming the channel. The transistor 300 is a so-called SGT (Structured Ground Tunnel). The transistor 300 is a so-called vertical transistor.

[0263] The transistor 300 includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a lower insulating layer 22, an upper insulating layer 24, a lower barrier conductive layer 26, an upper barrier conductive layer 28, a first sidewall barrier layer 30, a lower barrier insulating layer 34, a metal layer 38, a lower interlayer insulating layer 40, and an upper interlayer insulating layer 42. The gate insulating layer 20 includes a first gate insulating film 20a and a second gate insulating film 20b.

[0264] The lower electrode 12 is an example of the first electrode. The upper electrode 14 is an example of the second electrode. The lower insulating layer 22 is an example of the first insulating layer. The upper insulating layer 24 is an example of the second insulating layer. The lower barrier conductive layer 26 is an example of the first conductive layer. The upper barrier conductive layer 28 is an example of the second conductive layer. The first sidewall barrier layer 30 is an example of the first layer. The lower barrier insulating layer 34 is an example of the third insulating layer. The first gate insulating film 20a is an example of the first film. The second gate insulating film 20b is an example of the second film.

[0265] The upper electrode 14 is disposed on the oxide semiconductor layer 16. The upper electrode 14 is electrically connected to the oxide semiconductor layer 16. For example, the upper electrode 14 is connected to the oxide semiconductor layer 16. The upper electrode 14 functions as the source electrode or drain electrode of the transistor 300.

[0266] like Figure 37 As shown, the upper electrode 14 is surrounded by an upper insulating layer 24 and a gate insulating layer 20. In a first cross-section perpendicular to the first direction, the upper electrode 14 is surrounded by the upper insulating layer 24 and the gate insulating layer 20. Figure 37 The JJ' section shown is an example of the first section.

[0267] like Figure 35 As shown, the gate electrode 18 surrounds the oxide semiconductor layer 16 in a cross-section perpendicular to the first direction. The gate electrode 18 is disposed around the oxide semiconductor layer 16.

[0268] An upper barrier conductive layer 28 is disposed on the upper electrode 14. The upper barrier conductive layer 28 is in contact with the side opposite to the oxide semiconductor layer 16 in the upper barrier conductive layer 28.

[0269] The upper barrier conductive layer 28 is connected to the gate insulating layer 20. For example, the upper barrier conductive layer 28 is connected to the second gate insulating film 20b.

[0270] An upper insulating layer 24 is disposed between the upper barrier conductive layer 28 and the gate electrode.

[0271] The first sidewall barrier layer 30 surrounds the side of the lower electrode 12. For example... Figure 36 As shown, the first sidewall barrier layer 30 surrounds the lower electrode 12 in a second cross-section perpendicular to the first direction. Figure 36 The section II' shown is an example of the second section.

[0272] A metal layer 38 is disposed on top of the upper barrier conductive layer 28. The upper barrier conductive layer 28 is disposed between the metal layer 38 and the upper electrode 14. For example, the metal layer 38 is in contact with the upper barrier conductive layer 28.

[0273] Next, an example of the manufacturing method of the semiconductor device according to the third embodiment will be described.

[0274] Figure 38 , Figure 39 , Figure 40 , Figure 41 , Figure 42 , Figure 43 , Figure 44 , Figure 45 and Figure 46 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. Figures 38-46 Respectively represent and Figure 34 The corresponding cross-section. Figures 38-46 This is a diagram illustrating an example of a manufacturing method for transistor 300.

[0275] The following description will be based on the following case: the lower electrode 12 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a stacked structure of silicon oxide film and silicon nitride film, the lower insulating layer 22 is a silicon oxide layer, the upper insulating layer 24 is a silicon oxide layer, the lower barrier conductive layer 26 is a titanium nitride layer, the upper barrier conductive layer 28 is a titanium nitride layer, the first sidewall barrier layer 30 is a titanium nitride layer, the lower barrier insulating layer 34 is a silicon nitride layer, the metal layer 38 is a tungsten layer, the lower interlayer insulating layer 40 is a silicon oxide layer, and the upper interlayer insulating layer 42 is a silicon oxide layer.

[0276] First, a first silicon oxide film 51 is formed on a substrate (not shown). The first silicon oxide film 51 is formed, for example, by a CVD method.

[0277] Next, an opening (not shown) is formed on the first silicon oxide film 51. The opening on the first silicon oxide film 51 is formed, for example, using photolithography and RIE.

[0278] Next, a first titanium nitride film 52 and a first indium tin oxide film 53 are formed in the opening of the first silicon oxide film 51. The first titanium nitride film 52 and the first indium tin oxide film 53 are formed, for example, by CVD.

[0279] Next, the first titanium nitride film 52 and the first indium tin oxide film 53 on the surface of the first silicon oxide film 51 are removed. Figure 38 The removal of the first titanium nitride film 52 and the first indium tin oxide film 53 is, for example, achieved using the CMP method.

[0280] The first silicon oxide film 51 ultimately becomes the lower interlayer insulating layer 40. The first titanium nitride film 52 ultimately becomes the lower barrier conductive layer 26 and the first sidewall barrier layer 30. The first indium tin oxide film 53 ultimately becomes the lower electrode 12.

[0281] Next, on the first indium tin oxide film 53, a first silicon nitride film 54, a second silicon oxide film 55, a first tungsten film 56, and a third silicon oxide film 57 are sequentially deposited along the first direction. Figure 39 The first silicon nitride film 54, the second silicon oxide film 55, the first tungsten film 56, and the third silicon oxide film 57 are formed, for example, using a CVD method.

[0282] A portion of the first silicon nitride film 54 ultimately becomes the lower barrier insulating layer 34. A portion of the second silicon oxide film 55 ultimately becomes the lower insulating layer 22. A portion of the first tungsten film 56 ultimately becomes the gate electrode 18. A portion of the third silicon oxide film 57 ultimately becomes the upper insulating layer 24.

[0283] Next, an opening 60 is formed from the surface of the third silicon oxide film 57 through the third silicon oxide film 57, the first tungsten film 56, the second silicon oxide film 55, and the first silicon nitride film 54, reaching the first indium tin oxide film 53. Figure 40 The opening 60 is formed, for example, using photolithography and RIE.

[0284] Next, a second silicon nitride film 58 and a fourth silicon oxide film 62 are formed on the inner side of the opening 60. Figure 41 The second silicon nitride film 58 and the fourth silicon oxide film 62 are formed, for example, by deposition using CVD and etching using RIE. The second silicon nitride film 58 ultimately becomes the second gate insulating film 20b. Furthermore, the fourth silicon oxide film 62 ultimately becomes the first gate insulating film 20a.

[0285] Next, an indium gallium zinc oxide film 63 is embedded in the opening 60. Figure 42A portion of the indium gallium zinc oxide film 63 eventually becomes the oxide semiconductor layer 16. For example, after being deposited by CVD, a portion of the indium gallium zinc oxide film 63 is removed using CMP.

[0286] Next, a portion of the upper part of the indium gallium zinc oxide film 63 is selectively etched back. Figure 43 The etching back of the indium gallium zinc oxide film 63 is performed, for example, using the RIE method.

[0287] Next, a second indium tin oxide film 64 is formed on the indium gallium zinc oxide film 63. Figure 44 The second indium tin oxide film 64 is, for example, partially removed from the surface of the third silicon oxide film 57 using a CMP method after being deposited by CVD. The second indium tin oxide film 64 ultimately becomes the upper electrode 14.

[0288] Next, a heat treatment is performed to adjust the amount of oxygen vacancies in the indium gallium zinc oxide film 63. For example, if it is desired to increase the amount of oxygen vacancies, a heat treatment is performed in a non-oxidizing atmosphere to promote the removal of oxygen from the indium gallium zinc oxide film 63. Alternatively, if it is desired to decrease the amount of oxygen vacancies, a heat treatment is performed in an oxidizing atmosphere to promote the oxygen supply to the indium gallium zinc oxide film 63.

[0289] The second indium tin oxide film 64 serves as a pathway for oxygen to escape from the indium gallium zinc oxide film 63, or a pathway for supplying oxygen to the indium gallium zinc oxide film 63. By adjusting the amount of oxygen vacancies in the indium gallium zinc oxide film 63, for example, the threshold voltage of the transistor can be set to a desired value.

[0290] Next, a second titanium nitride film 65 and a second tungsten film 66 are formed on the second indium tin oxide film 64. The second titanium nitride film 65 and the second tungsten film 66 are formed, for example, using a CVD method.

[0291] Next, the second titanium nitride film 65 and the second tungsten film 66 are patterned. Figure 45 The patterning of the second titanium nitride film 65 and the second tungsten film 66 is performed, for example, by photolithography and RIE.

[0292] The second titanium nitride film 65 ultimately becomes the upper barrier conductive layer 28. Additionally, the second tungsten film 66 ultimately becomes the metal layer 38.

[0293] Next, a fifth silicon oxide film 68 is formed on the side surfaces of the second titanium nitride film 65 and the second tungsten film 66. Figure 46 The fifth silicon oxide film 68 is formed, for example, by CVD. The fifth silicon oxide film 68 ultimately becomes the upper interlayer insulating layer 42.

[0294] Using the above manufacturing methods, manufacture Figure 34 , Figure 35 , Figure 36 and Figure 37 The transistor 300 shown.

[0295] Next, the function and effects of the semiconductor device in the third embodiment will be explained.

[0296] In the transistor 300 of the third embodiment, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 are surrounded by a gate insulating layer 20, a lower barrier conductive layer 26, an upper barrier conductive layer 28, a first sidewall barrier layer 30, and a lower barrier insulating layer 34. In other words, in the transistor 300 of the third embodiment, the lower electrode 12, the oxide semiconductor layer 16, and the upper electrode 14 are surrounded by a layer that has a barrier effect on oxygen. Therefore, oxygen loss from the oxide semiconductor layer 16 or oxygen supply to the oxide semiconductor layer 16 during the accompanying heat treatment after the transistor structure is formed is suppressed.

[0297] Therefore, by performing the same function as the semiconductor device of the first embodiment, variations in transistor characteristics caused by heat treatment are suppressed. Thus, according to the third embodiment, a transistor 300 with excellent transistor characteristics can be realized.

[0298] Furthermore, in transistor 300, the upper electrode 14 is surrounded by the gate insulating layer 20. Therefore, for example, the second sidewall barrier layer 32 and the upper barrier insulating layer 36 provided in transistor 100 of the first embodiment are unnecessary. Therefore, for example, the manufacturing steps can be simplified compared to transistor 100 of the first embodiment.

[0299] According to the third embodiment, it is possible to suppress changes in transistor characteristics associated with heat treatment and realize a semiconductor device with excellent transistor characteristics.

[0300] (Fourth implementation)

[0301] The semiconductor memory device of the fourth embodiment includes the semiconductor device of the first embodiment and a capacitor electrically connected to the first electrode or the second electrode.

[0302] The semiconductor memory device of the fourth embodiment is a semiconductor memory 400. The semiconductor memory device of the fourth embodiment is a DRAM. The semiconductor memory 400 uses the transistor 100 of the first embodiment as a switching transistor for a memory cell of the DRAM.

[0303] Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0304] Figure 47 This is an equivalent circuit diagram of the semiconductor memory device according to the fourth embodiment. Figure 47 This example illustrates the case where there is only one storage unit MC, but multiple storage units MC can also be arranged in an array.

[0305] The semiconductor memory 400 includes a memory cell MC, a word line WL, a bit line BL, and a board line PL. The memory cell MC includes a switching transistor TR and a capacitor CA. Figure 47 In the diagram, the area enclosed by the dashed line is the storage unit MC.

[0306] Word line WL is electrically connected to the gate electrode of switching transistor TR. Bit line BL is electrically connected to one of the source and drain electrodes of switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source and drain electrodes of switching transistor TR. The other electrode of capacitor CA is connected to plate line PL.

[0307] The storage cell MC stores data by storing charge in the capacitor CA. Data is written to and read from the storage cell by turning on the switching transistor TR.

[0308] For example, when the desired voltage is applied to the bit line BL, the switching transistor TR is turned on to write data to the memory cell MC.

[0309] Alternatively, for example, the switching transistor TR is turned on, the voltage change of the bit line BL corresponding to the amount of charge stored in the capacitor is detected, and the data of the storage cell MC is read out.

[0310] Figure 48 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment. Figure 48 This shows a cross-section of the memory cell MC of the semiconductor memory 400.

[0311] The semiconductor memory 400 includes a silicon substrate 10, a switching transistor TR, and a capacitor CA.

[0312] The switching transistor TR has the same construction as the transistor 100 in the first embodiment.

[0313] Capacitor CA is disposed between silicon substrate 10 and switching transistor TR. Capacitor CA is disposed between silicon substrate 10 and lower electrode 12. Capacitor CA is electrically connected to lower electrode 12.

[0314] The capacitor CA includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73. The unit electrode 71 is electrically connected to the lower electrode 12. The unit electrode 71 is, for example, connected to the lower barrier conductive layer 26.

[0315] Unit electrode 71 and plate electrode 72 are, for example, titanium nitride. The capacitor insulating film 73 has, for example, a multilayer structure of zirconium oxide, aluminum oxide, and zirconium oxide.

[0316] Gate electrode 18 is electrically connected, for example, to word line WL (not shown). Upper electrode 14 is electrically connected, for example, to bit line BL (not shown). Plate electrode 72 is connected, for example, to plate line PL (not shown).

[0317] The semiconductor memory 400 uses an oxide semiconductor transistor with extremely low channel leakage current during disconnection to the switching transistor TR. Therefore, it achieves DRAM with excellent charge retention characteristics.

[0318] Furthermore, the switching transistor TR of the semiconductor memory 400 suppresses changes in transistor characteristics associated with heat treatment. Therefore, for example, the operating characteristics of the memory cell MC are stable. Thus, a semiconductor memory 400 with excellent operating characteristics can be realized.

[0319] In the fourth embodiment, a semiconductor memory using the transistor of the first embodiment has been described as an example. However, the semiconductor memory of the embodiments of the present invention may also be a semiconductor memory using a transistor of a variation of the first embodiment, a transistor of the second embodiment, or a transistor of the third embodiment.

[0320] In the fourth embodiment, a semiconductor memory with unit electrodes electrically connected to the lower electrode 12 has been described as an example. However, the semiconductor memory in the embodiments of the present invention may also be a semiconductor memory with unit electrodes electrically connected to the upper electrode 14.

[0321] Alternatively, the capacitor CA can be configured to be disposed on top of the switching transistor TR. It can also be configured to be disposed between the silicon substrate 10 and the capacitor CA.

[0322] The foregoing has described several embodiments of the present invention; however, these embodiments are provided as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified to be the constituent elements of another embodiment. The embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0323] [Symbol Explanation]

[0324] 12 Lower electrode (Electrode 1)

[0325] 14 Upper electrode (second electrode)

[0326] 16 Oxide Semiconductor Layer

[0327] 18 gate electrodes

[0328] 20 gate insulating layers

[0329] 20a First gate insulating film (first film)

[0330] 20b Second gate insulating film (second film)

[0331] 22. Lower insulation layer (first insulation layer)

[0332] 24. Upper insulation layer (second insulation layer)

[0333] 26. Lower barrier conductive layer (first conductive layer)

[0334] 28. Upper barrier conductive layer (second conductive layer)

[0335] 30. First sidewall barrier layer (first layer)

[0336] 32. Second sidewall barrier layer (second layer)

[0337] 34. Lower barrier insulation layer (third insulation layer)

[0338] 36. Upper barrier insulation layer (4th insulation layer)

[0339] 38 metal layers

[0340] 100 transistors (semiconductor devices)

[0341] 200 transistors (semiconductor devices)

[0342] 300 transistors (semiconductor devices)

[0343] 400 Semiconductor Memory (Semiconductor Storage Device)

[0344] CA capacitor.

Claims

1. A semiconductor device comprising: The first electrode contains a metal oxide; The second electrode contains a metal oxide; An oxide semiconductor layer is disposed between the first electrode and the second electrode; The gate electrode surrounds the oxide semiconductor layer; A gate insulating layer, disposed between the gate electrode and the oxide semiconductor layer, comprises silicon (Si) and nitrogen (N); A first insulating layer is disposed between the first electrode and the gate electrode; A second insulating layer is disposed between the second electrode and the gate electrode; The first conductive layer is in contact with the side opposite to the oxide semiconductor layer in the first electrode, and includes at least one conductor selected from the group consisting of metals, metal nitrides and metal carbides; The second conductive layer is in contact with the side of the second electrode opposite to the oxide semiconductor layer, and includes at least one conductor selected from the group consisting of metals, metal nitrides and metal carbides; The first layer surrounds the first electrode in a first cross-section perpendicular to a first direction from the first electrode toward the second electrode and is in contact with the first conductive layer. It comprises at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride, or at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides. The second layer surrounds the second electrode in a second cross-section perpendicular to the first direction and is in contact with the second conductive layer, and includes at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride, or at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides; A third insulating layer, disposed between the first electrode and the first insulating layer, and connected to the gate insulating layer and the first layer, comprises at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride; and The fourth insulating layer is disposed between the second electrode and the second insulating layer, and is in contact with the gate insulating layer and the second layer, and includes at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride.

2. The semiconductor device of claim 1, wherein the metal oxide contained in the first electrode and the metal oxide contained in the second electrode comprise indium (In) and tin (Sn).

3. The semiconductor device of claim 1, wherein the first conductive layer and the second conductive layer comprise titanium (Ti) and nitrogen (N).

4. The semiconductor device of claim 1, wherein the first layer comprises titanium (Ti) and nitrogen (N).

5. The semiconductor device of claim 1, wherein the first layer comprises the same material as the first conductive layer, and the first conductive layer and the first layer comprise titanium (Ti) and nitrogen (N).

6. The semiconductor device of claim 1, wherein the third insulating layer and the fourth insulating layer comprise silicon (Si) and nitrogen (N).

7. The semiconductor device of claim 1, wherein the gate insulating layer comprises: a first film comprising silicon (Si) and oxygen (O); and a second film disposed between the first film and the gate electrode and comprising silicon (Si) and nitrogen (N).

8. The semiconductor device of claim 7, wherein the second film is in contact with the third insulating layer and the fourth insulating layer.

9. The semiconductor device according to claim 1, further comprising: a metal layer in contact with the surface of the second conductive layer opposite to the second electrode.

10. A semiconductor memory device comprising: The semiconductor device according to claim 1; and A capacitor is electrically connected to either the first electrode or the second electrode.

11. A semiconductor device comprising: The first electrode contains a metal oxide; The second electrode contains a metal oxide; An oxide semiconductor layer is disposed between the first electrode and the second electrode; The gate electrode surrounds the oxide semiconductor layer; A gate insulating layer, disposed between the gate electrode and the oxide semiconductor layer, comprises silicon (Si) and nitrogen (N); A first insulating layer is disposed between the first electrode and the gate electrode; The second insulating layer has the gate electrode disposed between it and the first insulating layer; The first conductive layer is in contact with the side of the first electrode opposite to the oxide semiconductor layer, and includes at least one conductor selected from the group consisting of metals, metal nitrides and metal carbides; The second conductive layer is in contact with the side of the second electrode opposite to the oxide semiconductor layer, and is surrounded by the second electrode in a first cross-section perpendicular to a first direction from the first electrode toward the second electrode, and includes at least one conductor selected from the group consisting of metals, metal nitrides and metal carbides. A metal layer, which is surrounded by the second conductive layer in the first cross-section; The first layer surrounds the first electrode in a second cross-section perpendicular to the first direction and is in contact with the first conductive layer. It includes at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride, or at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides. A third insulating layer, disposed between the first electrode and the first insulating layer, and connected to the gate insulating layer and the first layer, comprises at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride; and The fourth insulating layer, which is disposed between the second insulating layer and the gate electrode, surrounds the metal layer in a third cross-section perpendicular to the first direction, and is in contact with the second conductive layer and the gate insulating layer, comprises at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride.

12. The semiconductor device of claim 11, wherein the second electrode is disposed between the fourth insulating layer and the oxide semiconductor layer.

13. The semiconductor device of claim 11, wherein the metal oxide contained in the first electrode and the metal oxide contained in the second electrode comprise indium (In) and tin (Sn).

14. The semiconductor device of claim 11, wherein the first conductive layer and the second conductive layer comprise titanium (Ti) and nitrogen (N).

15. The semiconductor device of claim 11, wherein the first layer comprises titanium (Ti) and nitrogen (N).

16. The semiconductor device of claim 11, wherein the first layer comprises the same material as the first conductive layer, and the first conductive layer and the first layer comprise titanium (Ti) and nitrogen (N).

17. The semiconductor device of claim 11, wherein the third insulating layer and the fourth insulating layer comprise silicon (Si) and nitrogen (N).

18. The semiconductor device of claim 11, wherein the gate insulating layer comprises: a first film comprising silicon (Si) and oxygen (O); and a second film disposed between the first film and the gate electrode and comprising silicon (Si) and nitrogen (N).

19. The semiconductor device of claim 18, wherein the second film is in contact with the third insulating layer and the fourth insulating layer.

20. A semiconductor memory device comprising: The semiconductor device according to claim 11; and A capacitor is electrically connected to either the first electrode or the second electrode.

21. A semiconductor device comprising: The first electrode contains a metal oxide; The second electrode contains a metal oxide; An oxide semiconductor layer is disposed between the first electrode and the second electrode; The gate electrode surrounds the oxide semiconductor layer; A gate insulating layer is disposed between the gate electrode and the oxide semiconductor layer, surrounds the second electrode in a first cross-section perpendicular to a first direction from the first electrode toward the second electrode, and comprises silicon (Si) and nitrogen (N); A first insulating layer is disposed between the first electrode and the gate electrode; The second insulating layer has the gate electrode disposed between it and the first insulating layer; The first conductive layer is in contact with the side opposite to the oxide semiconductor layer in the first electrode, and includes at least one conductor selected from the group consisting of metals, metal nitrides and metal carbides; The second conductive layer is connected to the side opposite to the oxide semiconductor layer of the second electrode and to the gate insulating layer. The second insulating layer is disposed between the second electrode and the gate electrode and includes at least one conductor selected from the group consisting of metals, metal nitrides and metal carbides. The first layer surrounds the first electrode in a second cross-section perpendicular to the first direction and is in contact with the first conductive layer. It includes at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride, or at least one conductor selected from the group consisting of metals, metal nitrides, and metal carbides. and The third insulating layer is disposed between the first electrode and the first insulating layer, and is in contact with the gate insulating layer and the first layer, and includes at least one insulator selected from the group consisting of aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride.

22. The semiconductor device of claim 21, wherein the metal oxide contained in the first electrode and the metal oxide contained in the second electrode comprise indium (In) and tin (Sn).

23. The semiconductor device of claim 21, wherein the first conductive layer and the second conductive layer comprise titanium (Ti) and nitrogen (N).

24. The semiconductor device of claim 21, wherein the first layer comprises titanium (Ti) and nitrogen (N).

25. The semiconductor device of claim 21, wherein the first layer comprises the same material as the first conductive layer, and the first conductive layer and the first layer comprise titanium (Ti) and nitrogen (N).

26. The semiconductor device of claim 21, wherein the third insulating layer comprises silicon (Si) and nitrogen (N).

27. The semiconductor device of claim 21, wherein the gate insulating layer comprises: a first film comprising silicon (Si) and oxygen (O); and a second film disposed between the first film and the gate electrode and comprising silicon (Si) and nitrogen (N).

28. The semiconductor device of claim 27, wherein the second film is in contact with the third insulating layer and the second conductive layer.

29. The semiconductor device according to claim 21, further comprising: being in contact with a surface of the second conductive layer opposite to the second electrode.

30. A semiconductor memory device comprising: The semiconductor device according to claim 21; and A capacitor is electrically connected to either the first electrode or the second electrode.

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