Burst-mode optical receiver circuit with built-in reset signal to reduce settling time

Abstract

This invention discloses a burst-mode optical receiver circuit with a built-in reset signal to reduce settling time. Belonging to the field of analog integrated circuits, it amplifies the current signal generated by a photodiode through a pre-amplifier of a transimpedance amplifier. A variable gain amplifier then provides variable amplification within a certain dynamic range. The variable gain amplifier employs source degradation resistors and capacitors to improve linearity. The output signal of the variable gain amplifier is further amplified to a limited state by a limiting amplifier in the feedback loop and sent to an envelope detector to detect the envelope information of the data stream. This envelope information is compared with the DC voltage at the detection point of the transimpedance amplifier by a comparator. The output signal undergoes pulse width broadening to generate a pulse reset signal, which in turn adjusts the loop parameters of the transimpedance amplifier, achieving rapid circuit stabilization. This invention has a simple structure and can significantly reduce settling time by adjusting the slew rate of the comparator and the pulse width of the pulse width broadening circuit, while also providing stronger anti-interference capabilities.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to a built-in reset signal burst mode optical receiver circuit that reduces settling time. Background Technology

[0002] Optical receivers can be divided into continuous mode optical receivers and burst mode optical receivers. Traditional continuous mode optical receivers are difficult to use in optical fiber communication systems where the amplitude of the input signal changes significantly over time, so burst mode optical receivers are needed.

[0003] The input signal of a burst-mode optical receiver mainly consists of a preamble, data, and a guard band. The preamble ensures that the burst-mode optical receiver adjusts its gain control signal within a specific time period, preparing for subsequent data transmission. The time required for the control signal to stabilize is called the settling time. If data transmission begins before the control signal stabilizes, it may lead to data distortion and affect system performance. For burst-mode optical receivers, settling time is a critical parameter to consider in circuit design. Summary of the Invention

[0004] This invention provides a burst-mode optical receiver circuit with an internally generated reset signal to reduce settling time. The circuit is more independent and does not require an external reset signal port as in traditional circuits.

[0005] This invention provides a built-in reset signal burst mode optical receiver circuit with reduced settling time, comprising: a transimpedance amplifier, a variable gain amplifier, and an internal reset signal generation circuit composed of a limiting amplifier, an envelope detector, a comparator, and a pulse width extension circuit;

[0006] The front stage of the transimpedance amplifier is connected to the current signal of the photodiode, and is used to amplify the current signal according to its own gain.

[0007] The input terminal of the variable gain amplifier is connected to the output terminal of the transimpedance amplifier, and is used to amplify the current signal amplified by the transimpedance amplifier within a preset dynamic range according to its own gain.

[0008] The input terminal of the limiting amplifier is connected to the output terminal of the variable gain amplifier, and is used to amplify the output signal of the variable gain amplifier;

[0009] The input terminal of the envelope detector is connected to the output terminal of the limiting amplifier, and is used to detect the envelope information of the data stream;

[0010] The positive input terminal of the comparator is connected to the output terminal of the envelope detector, and the negative output terminal is connected to the reference voltage. It is used to compare the output signal of the envelope detector with the reference voltage to obtain a comparison signal.

[0011] The input terminal of the pulse width extension circuit is connected to the output terminal of the comparator, and the output terminal is connected to the input terminals of the transimpedance amplifier and the variable gain amplifier, respectively. It is used to adjust the pulse width of the pulse width extension circuit according to the comparison signal, output a reset signal, and send the reset signal to the transimpedance amplifier and the variable gain amplifier to control the gain of the transimpedance amplifier and the variable gain amplifier.

[0012] In one embodiment of the present invention, the variable gain amplifier is a source degradation resistor and source degradation capacitor type variable gain amplifier.

[0013] In one embodiment of the present invention, the variable gain amplifier includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4, a first load resistor R1 and a second load resistor R2, a first peaking inductor L1 and a second peaking inductor L2, a source degradation capacitor C1 and a source degradation resistor R3, and a first variable load capacitor C2 and a second variable load capacitor C3.

[0014] The gate of the first transistor M1 is connected to the output signal INI+ of the transimpedance amplifier. The source of the first transistor M1 is connected to the drain of the third transistor M3, and the source of the third transistor M3 is connected to GND. The drain of the first transistor M1 is connected to the first port of the first peaking inductor L1. The gate of the second transistor M2 is connected to the output signal INI- of the transimpedance amplifier. The source of the second transistor M2 is connected to the drain of the fourth transistor M4, and the source of the fourth transistor M4 is connected to GND. The drain of the second transistor M2 is connected to the first port of the second peaking inductor L2. The gate of the third transistor M3 is connected to the DC bias signal V. bias The drain of the third transistor M3 is connected to the source of the first transistor M1, the source of the third transistor M3 is connected to GND, and the gate of the fourth transistor M4 is connected to the DC bias signal V. biasThe drain of the fourth transistor M4 is connected to the source of the second transistor M2, and the source of the fourth transistor M4 is connected to GND. The first port of the first peaking inductor L1 is connected to the drain of the first transistor M1 and the first port of the first variable load capacitor C2. The second port of the peaking inductor L1 is connected to VDD through the first load resistor R1. The first port of the second peaking inductor L2 is connected to the drain of the second transistor M2 and the first port of the second variable load capacitor C3. The second port of the second peaking inductor L2 is connected to VDD through the second load resistor R2. The first port of the first load resistor R1 is connected to the second port of the first peaking inductor L1, and the second port of the first load resistor R1 is connected to VDD. The second load resistor R2... The first port is connected to the second port of the second peaking inductor L2, the second port of the second load resistor R2 is connected to VDD, the first port of the source degradation resistor R3 is connected to the source of the first transistor M1, the second port of the source degradation resistor R3 is connected to the source of the second transistor M2, the first port of the source degradation capacitor C1 is connected to the source of the first transistor M1, the second port of the source degradation capacitor C1 is connected to the source of the second transistor M2, the first port of the first variable load capacitor C2 is connected to the drain of the first transistor M1, the second port of the first variable load capacitor C2 is connected to GND, the first port of the second variable load capacitor C3 is connected to the drain of the second transistor M2, and the second port of the second variable load capacitor C3 is connected to GND.

[0015] In one embodiment of the present invention, the values ​​of the source degradation capacitor C1, the source degradation resistor R3, the first variable load capacitor C2, and the second variable load capacitor C3 are controlled according to the reset signal, so that the zero and pole positions change synchronously when the circuit gain changes.

[0016] In one embodiment of the present invention, the limiting amplifier is further used to amplify the output signal of the variable gain amplifier to a full swing state.

[0017] The built-in reset signal burst mode optical receiver circuit with reduced settling time according to embodiments of the present invention has the following beneficial effects:

[0018] 1. By employing a variable gain amplifier with source degradation resistors and source degradation capacitors, the dynamic range of the output signal is increased and the linearity of the output signal is improved;

[0019] 2. Reset signal V c The values ​​of the degradation capacitor C1, degradation resistor R3, and variable load capacitors C2 and C3 are synchronously controlled so that the zero and pole positions change synchronously when the circuit gain changes, thus ensuring the flatness of the gain curve under all gain conditions.

[0020] 3. By changing the reset signal V c The value of the degradation resistor R3 can be controlled to adjust the gain of the variable gain amplifier;

[0021] 4. This burst-mode transimpedance amplifier employs an internal reset signal to reduce settling time. It utilizes a limiting amplifier and an envelope detector to extract the envelope information of the variable gain amplifier's output signal, compares it with a comparator, and uses a pulse width expansion circuit to fix the output pulse width. This controls the gain of both the transimpedance amplifier and the variable gain amplifier, achieving automatic gain control and thus a shorter settling time. Process verification has shown that this structure has strong anti-interference capabilities, with a settling time of less than 40 ns.

[0022] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0023] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0024] Figure 1 This is a schematic diagram of a built-in reset signal burst mode optical receiver circuit structure for reducing settling time according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the structure of a variable gain amplifier provided according to an embodiment of the present invention. Detailed Implementation

[0026] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0027] Figure 1 This is a schematic diagram of a built-in reset signal burst mode optical receiver circuit structure for reducing settling time according to an embodiment of the present invention.

[0028] like Figure 1 As shown, the built-in reset signal burst-mode optical receiver circuit with reduced settling time includes the following steps:

[0029] The transimpedance amplifier, the variable gain amplifier, and the internal reset signal generation circuit consisting of a limiting amplifier, an envelope detector, a comparator, and a pulse width extension circuit;

[0030] The preamplifier of the transimpedance amplifier is connected to the current signal of the photodiode, and is used to amplify the current signal according to its own gain;

[0031] The input terminal of the variable gain amplifier is connected to the output terminal of the transimpedance amplifier, and is used to amplify the current signal amplified by the transimpedance amplifier within a preset dynamic range according to its own gain.

[0032] The input terminal of the limiting amplifier is connected to the output terminal of the variable gain amplifier to amplify the output signal of the variable gain amplifier;

[0033] The input of the envelope detector is connected to the output of the limiting amplifier to detect the envelope information of the data stream;

[0034] The comparator's positive input is connected to the output of the envelope detector, and its inverting output is connected to the reference voltage. This is used to compare the output signal of the envelope detector with the reference voltage to obtain a comparison signal.

[0035] The input of the pulse width extension circuit is connected to the output of the comparator, and the output is connected to the input of the transimpedance amplifier and the variable gain amplifier, respectively. It is used to adjust the pulse width of the pulse width extension circuit according to the comparison signal, output a reset signal, and send the reset signal to the transimpedance amplifier and the variable gain amplifier to adjust the gain of the transimpedance amplifier and the variable gain amplifier.

[0036] Specifically, the built-in reset signal V c It is generated by a limiting amplifier, an envelope detector, a comparator, and a pulse width extension circuit. The output of the limiting amplifier is connected to the input of the envelope detector, and the output signal V of the envelope detector is... p With reference voltage V ref The generated signal V after comparison pulse V pulse The pulse width of the pulse width expansion circuit is adjusted via the reset signal V of the pulse width expansion circuit. c Control the gain of the transimpedance amplifier and the variable gain amplifier.

[0037] Using a limiting amplifier to further amplify the signal helps the envelope detector extract the signal's envelope information more quickly. The DC voltage at the detection points of the transimpedance amplifier and the variable gain amplifier is compared by a comparator, and the reset signal V... c The overall gain is altered by changing the transimpedance of the preamplifier and the degradation capacitor and resistor in the variable gain amplifier. This scheme, which generates an internal reset signal using a limiting amplifier, envelope detector, and comparator, saves on external control ports compared to conventional external input reset signal schemes.

[0038] In embodiments of the present invention, such as Figure 2As shown, the variable gain amplifier includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4, a first load resistor R1 and a second load resistor R2, a first peaking inductor L1 and a second peaking inductor L2, a source degradation capacitor C1 and a source degradation resistor R3, a first variable load capacitor C2 and a second variable load capacitor C3.

[0039] The gate of the first transistor M1 is connected to the output signal INI+ of the transimpedance amplifier, the source of the first transistor M1 is connected to the drain of the third transistor M3, the source of the third transistor M3 is connected to GND, and the drain of the first transistor M1 is connected to the first port of the first peaking inductor L1.

[0040] The gate of the second transistor M2 is connected to the output signal INI- of the transimpedance amplifier, the source of the second transistor M2 is connected to the drain of the fourth transistor M4, the source of the fourth transistor M4 is connected to GND, and the drain of the second transistor M2 is connected to the first port of the second peaking inductor L2.

[0041] The gate of the third transistor M3 is connected to a DC bias signal V. bias The drain of the third transistor M3 is connected to the source of the first transistor M1, and the source of the third transistor M3 is connected to GND.

[0042] The gate of the fourth transistor M4 is connected to a DC bias signal V. bias The drain of the fourth transistor M4 is connected to the source of the second transistor M2, and the source of the fourth transistor M4 is connected to GND.

[0043] The first port of the first peaking inductor L1 is connected to the drain of the first transistor M1 and the first port of the first variable load capacitor C2, and the second port of the peaking inductor L1 is connected to VDD through the first load resistor R1.

[0044] The first port of the second peaking inductor L2 is connected to the drain of the second transistor M2 and the first port of the second variable load capacitor C3. The second port of the second peaking inductor L2 is connected to VDD through the second load resistor R2.

[0045] The first port of the first load resistor R1 is connected to the second port of the first peaking inductor L1, and the second port of the first load resistor R1 is connected to VDD.

[0046] The first port of the second load resistor R2 is connected to the second port of the second peaking inductor L2, and the second port of the second load resistor R2 is connected to VDD.

[0047] The first port of the source degradation resistor R3 is connected to the source of the first transistor M1, and the second port of the source degradation resistor R3 is connected to the source of the second transistor M2.

[0048] The first port of the source degradation capacitor C1 is connected to the source of the first transistor M1, and the second port of the source degradation capacitor C1 is connected to the source of the second transistor M2.

[0049] The first port of the first variable load capacitor C2 is connected to the drain of the first transistor M1, and the second port of the first variable load capacitor C2 is connected to GND.

[0050] The first port of the second variable load capacitor C3 is connected to the drain of the second transistor M2, and the second port of the second variable load capacitor C3 is connected to GND.

[0051] Specifically, the gate of differential amplifier transistor M1 is connected to the output signal INI+ of the transimpedance amplifier, its drain is connected to the power supply voltage VDD through inductor L1 and resistor R1, and its source is connected to the drain of current source transistor M3. The gate of differential amplifier transistor M2 is connected to the output signal INI- of the transimpedance amplifier, its drain is connected to the power supply voltage VDD through inductor L2 and resistor R2, and its source is connected to the drain of current source transistor M4. Degradation capacitor C1 and degradation resistor R3 are connected between the sources of amplifier transistors M1 and M2. Variable load capacitors C2 and C3 are connected between the drains of amplifier transistors M1 and M2 and GND, respectively. Output nodes OUT+ and OUT- are the drains of amplifier transistors M1 and M2, respectively.

[0052] In one embodiment of the invention, the source degradation resistance and source degradation capacitance of the variable gain amplifier are variable.

[0053] Inductors L1 and L2 are added to increase the bandwidth of the variable gain amplifier. To avoid inconsistent bandwidth at different gain levels of the variable gain amplifier, control signal V is used. c The values ​​of the degradation capacitor C1, degradation resistor R3, and variable load capacitors C2 and C3 are synchronously controlled so that the zero point position changes synchronously when the circuit gain changes, thus ensuring the maximum flatness of the gain curve under all gain conditions.

[0054] Specifically, the current signal I generated by the photodiode in The voltage signals OUT+ and OUT- are converted by a transimpedance amplifier and a variable gain amplifier, then further amplified by a limiting amplifier, and finally generated as a voltage signal V by an envelope detector. p Voltage signal V p With reference voltage V ref A reset pulse V is generated by the comparator. pulse Because the reset pulse width is greatly affected by the manufacturing process, the reset pulse V... pulse A reset signal V with a fixed pulse width is generated after the pulse width expansion circuit. c Reset signal V cThese are used to control the values ​​of C1, C2, and R3 in the variable gain amplifier. The output signals of the transimpedance amplifier are INI+ and INI-.

[0055] Furthermore, to ensure sufficient bandwidth in the circuit at different speeds and to avoid excessive spikes, a reset signal V is used. c The values ​​of the degradation capacitor C1, degradation resistor R3, and variable load capacitors C2 and C3 are synchronously controlled so that the zero and pole positions change synchronously when the circuit gain changes, thus ensuring the flatness of the gain curve under all gain conditions.

[0056] Furthermore, to avoid damage to the linearity of the output signal waveform, unlike the traditional Gilbert-type variable gain amplifier, a source degradation resistor and source degradation capacitor type variable gain amplifier is used to increase the dynamic range of the output signal and improve the linearity of the output signal.

[0057] Furthermore, the output signal of the variable gain amplifier is first input to the limiting amplifier, which amplifies the output signals OUT+ and OUT- to full swing. Then, the envelope information V is extracted by the envelope detector. p V p With V ref The comparator compares the signals to generate a pulse signal V. pulse V pulse After passing through the pulse width expansion circuit, a built-in reset signal V is generated. c V c Control the gain of the transimpedance amplifier and the variable gain amplifier to achieve rapid circuit stabilization.

[0058] The envelope information of the output signal of the variable gain amplifier is extracted using a limiting amplifier and an envelope detector. This information is compared with a comparator, and the comparison result is used to fix the output pulse width through a pulse width expansion circuit, thereby controlling the gain of the transimpedance amplifier and the variable gain amplifier. Compared with a conventional low-pass filter and comparator scheme, this envelope detector, comparator, and pulse width expansion scheme can significantly reduce the settling time, better cope with the adverse effects of temperature, voltage fluctuations, and process angle changes, and has stronger anti-interference capabilities. Furthermore, the settling time can be shortened by adjusting the slew rate of the comparator and the pulse width of the output of the pulse width expansion circuit.

[0059] The burst-mode optical receiver circuit with built-in reset signal proposed in this embodiment of the invention reduces settling time. The current signal generated by the photodiode is amplified by a pre-amplifier of a transimpedance amplifier, and then a variable gain amplifier achieves variable amplification within a certain dynamic range. The variable gain amplifier uses source degradation resistors and source degradation capacitors to improve linearity. The output signal of the variable gain amplifier is further amplified to a limited state by a limiting amplifier in the feedback loop, and then sent to an envelope detector to detect the envelope information of the data stream. This envelope information is compared with the DC voltage at the detection point of the transimpedance amplifier by a comparator. The output signal undergoes pulse width broadening to generate a pulse reset signal, which in turn adjusts the loop parameters of the transimpedance amplifier, achieving rapid circuit stabilization. This invention has a simple structure and can significantly reduce the settling time by adjusting the slew rate of the comparator and the pulse width of the pulse width broadening circuit, while also exhibiting stronger anti-interference capabilities. Process verification shows that the settling time can be less than 40 ns.

[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0061] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. A burst-mode optical receiver circuit with a built-in reset signal to reduce settling time, characterized in that, include: The transimpedance amplifier, the variable gain amplifier, and the internal reset signal generation circuit consisting of a limiting amplifier, an envelope detector, a comparator, and a pulse width extension circuit; The front stage of the transimpedance amplifier is connected to the current signal of the photodiode; The input terminal of the variable gain amplifier is connected to the output terminal of the transimpedance amplifier; The input terminal of the limiting amplifier is connected to the output terminal of the variable gain amplifier; The variable gain amplifier includes a first transistor, a second transistor, a third transistor and a fourth transistor, a first load resistor and a second load resistor, a first peaking inductor and a second peaking inductor, a source degradation capacitor and a source degradation resistor, a first variable load capacitor and a second variable load capacitor. The gate of the first transistor is connected to the output signal of the transimpedance amplifier. INI +, the source of the first transistor is connected to the drain of the third transistor, and the source of the third transistor is connected to GND The drain of the first transistor is connected to the first port of the first peaking inductor, and the gate of the second transistor is connected to the output signal of the transimpedance amplifier. INI - The source of the second transistor is connected to the drain of the fourth transistor, and the source of the fourth transistor is connected to... GND The drain of the second transistor is connected to the first port of the second peaking inductor, and the gate of the third transistor is connected to a DC bias signal. V bias The drain of the third transistor is connected to the source of the first transistor, and the gate of the fourth transistor is connected to a DC bias signal. V bias The drain of the fourth transistor is connected to the source of the second transistor. The first port of the first peaking inductor is connected to the drain of the first transistor and the first port of the first variable load capacitor. The second port of the first peaking inductor is connected to the first load resistor. VDD The first port of the second peaking inductor is connected to the drain of the second transistor and the first port of the second variable load capacitor, and the second port of the second peaking inductor is connected to the second load resistor. VDD The first port of the first load resistor is connected to the second port of the first peaked inductor, and the second port of the first load resistor is connected to... VDD The first port of the second load resistor is connected to the second port of the second peaking inductor, and the second port of the second load resistor is connected to... VDD The first port of the source degradation resistor is connected to the source of the first transistor, and the second port of the source degradation resistor is connected to the source of the second transistor. The first port of the source degradation capacitor is connected to the source of the first transistor, and the second port of the source degradation capacitor is connected to the source of the second transistor. The first port of the first variable load capacitor is connected to the drain of the first transistor, and the second port of the first variable load capacitor is connected to... GND The first port of the second variable load capacitor is connected to the drain of the second transistor, and the second port of the second variable load capacitor is connected to... GND .

2. The built-in reset signal burst mode optical receiver circuit with reduced settling time according to claim 1, characterized in that, The transimpedance amplifier is used to amplify the current signal according to its own gain; The variable gain amplifier is used to amplify the current signal amplified by the transimpedance amplifier within a preset dynamic range according to its own gain. The limiting amplifier is used to amplify the output signal of the variable gain amplifier; The input terminal of the envelope detector is connected to the output terminal of the limiting amplifier, and is used to detect the envelope information of the data stream; The positive input terminal of the comparator is connected to the output terminal of the envelope detector, and the negative output terminal is connected to the reference voltage. It is used to compare the output signal of the envelope detector with the reference voltage to obtain a comparison signal. The input terminal of the pulse width extension circuit is connected to the output terminal of the comparator, and the output terminal is connected to the input terminals of the transimpedance amplifier and the variable gain amplifier, respectively. It is used to adjust the pulse width of the pulse width extension circuit according to the comparison signal, output a reset signal, and send the reset signal to the transimpedance amplifier and the variable gain amplifier to control the gain of the transimpedance amplifier and the variable gain amplifier.

3. The built-in reset signal burst mode optical receiver circuit for reducing settling time according to claim 1, characterized in that, The source degradation capacitor, the source degradation resistor, the first variable load capacitor, and the second variable load capacitor are controlled according to the reset signal so that the zero and pole positions change synchronously when the circuit gain changes.

4. The built-in reset signal burst mode optical receiver circuit for reducing settling time according to claim 1, characterized in that, The limiting amplifier is used to amplify the output signal of the variable gain amplifier to full swing.

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