Compact silicon qubit cell with embedded readout

Abstract

A quantum device having an LC resonator circuit for performing a qubit measurement or readout is disclosed. The device comprises a silicon layer (601), a dielectric layer (603) disposed on the silicon layer (601) and forming a functional interface with the silicon layer (601), a first metal region (614) disposed on the dielectric layer 603, and a second metal region 624 disposed on the dielectric layer 603 and laterally separated from the first metal region (614). The first and second metal regions (614, 624) are arranged to be electrically connected such that a double quantum dot having a first state and a second state of a qubit can be induced to form at the functional interface under the first and second metal regions (614, 624). The double quantum dot provides a capacitor Cl in the LC resonator circuit, the capacitance of the double quantum dot depending on the state of the qubit. The first metal region (614) provides an inductor LI in the LC resonator circuit, the resonance frequency of the LC resonator circuit depending on the state of the qubit, such that the state of the qubit can be measured or inferred.

Description

TECHNICAL FIELD

[0001] The present invention relates to a quantum device comprising an LC resonator circuit. The device is suitable for performing a qubit measurement or readout. BACKGROUND

[0002] In the recent era of near-term, intermediate-scale quantum computing, or NISQ, a qubit processor can use 50-100 qubits. The qubits are typically arranged in a dense array in order to minimize the necessary processor size.

[0003] Quantum computing using a qubit processor typically involves reading out the state of each qubit after performing a series of operations on the qubits. The readout can be performed by coupling a charge sensor to an LC resonator or by embedding the qubit in an LC resonator circuit. However, the circuitry required to read out the state of a qubit occupies a very large area compared to the area required for the qubit itself. Typically, the area occupied by each qubit can be in the order of 100x100 nm 2 compared to 1x1 pm 2 , where the size depends on the properties of the materials used. In contrast, the area occupied by the LC resonator is typically at least 100x100 pm 2 , which is several orders of magnitude larger than the area occupied by the qubit.

[0004] The relatively large area occupied by the LC resonator circuit presents a significant limitation to the scalability of the technology. It is desirable to reduce the size of the readout circuitry. SUMMARY

[0005] Aspects of the invention provide a quantum device having an LC resonator circuit for performing a qubit measurement or readout. The device comprises a semiconductor layer; a dielectric layer disposed on the semiconductor layer and forming a functional interface with the semiconductor layer; a first metal region disposed on the dielectric layer; and a second metal region disposed on the dielectric layer and laterally separated from the first metal region. The first metal region and the second metal region are arranged to be electrically connected such that a double quantum dot having a first state and a second state can be induced to form at the functional interface under the first metal region and the second metal region. The double quantum dot provides a capacitor in the LC resonator circuit and the capacitance of the double quantum dot depends on the state of the qubit. The first metal region provides an inductor in the LC resonator circuit. The resonant frequency of the LC resonator circuit depends on the state of the qubit such that the state of the qubit can be measured or inferred.

[0006] The first and second metal regions are arranged electrically connected to induce a dual quantum dot at the functional interface below the first and second metal regions. This is achieved by applying a bias potential to the first and second metal regions, which alters the potential landscape near the first and second metal regions to locally confine charge carriers. The interface between the semiconductor layer and the dielectric layer typically comprises functional and non-functional portions. When a bias potential is applied to the first and / or second metal regions, the functional portion typically exhibits a larger field effect relative to the non-functional portion, allowing one or more charge carriers to be confined at the functional interface below the first and / or second metal regions. Depending on the polarity of the bias potential, the charge carriers can be electrons or holes.

[0007] A first metal region is arranged for electrical connection, allowing a first quantum dot to be induced below the functional interface. A second metal region is similarly arranged for electrical connection, allowing a second quantum dot to be induced below the functional interface. The sizes of the first and second metal regions affect the sizes of the first and second quantum dots and consequently their electrical properties, such as their charging energy. The charging energy is inversely proportional to the size of the quantum dot; a smaller metal region can be used to induce a smaller quantum dot with a larger charging energy.

[0008] Optionally, a bias potential can be applied to either the first metal region or the second metal region to induce a single quantum dot. However, preferably, a bias potential is applied to both the first and second metal regions to induce a dual quantum dot. A dual quantum dot comprises a first quantum dot and a second quantum dot. The separation between the first and second metal regions allows the first and second quantum dots to tunnel-couple.

[0009] Two quantum dots form qubits with a first state and a second state. For example, the first state may include electrons with antiparallel spin orientations, and the second state may include electrons with parallel spin orientations. In this example, due to the spin dynamics of the two quantum dots, the capacitance of the first state is higher than that of the second state. If the electron spins are parallel, the tunneling effect between the first and second quantum dots is suppressed, or even zero, due to spin blocking.

[0010] The state of a qubit can be read out using an LC resonator circuit, which includes an inductor and a capacitor. An LC resonator circuit can also be called an LC energy storage circuit, an LC resonator, an energy storage circuit, or a resonant circuit. An LC resonator circuit has a resonant frequency ω0, according to the equation... The resonant frequency ω0 depends on the inductance L and capacitance C. Forward power transfer reaches its maximum at the resonant frequency. In the above device, the two quantum dots provide the capacitor in the LC resonator circuit. The capacitance and the resonant frequency depend on the state of the qubits. Therefore, the state of the qubits can be inferred.

[0011] In the aforementioned quantum device, the first metal region performs a dual function. First, the first metal region is arranged for electrical connection, i.e., inducing quantum dots below the functional interface at the first metal region. Second, the first metal region provides an inductor in the LC resonator circuit. Therefore, no additional inductor is required. Preferably, only the first metal region provides an inductor in the LC resonator circuit. Thus, the device advantageously provides a compact qubit readout mechanism for measuring or inferring the state of qubits.

[0012] The semiconductor layer of the device can be any suitable semiconductor, such as gallium arsenide (GaAs), indium arsenide (InAs), silicon germanium (SiGe), silicon carbide (SiC), carbon, or silicon. Different allotropes of carbon, such as graphene or carbon nanotubes, can be used. Different forms of silicon can be used, such as intrinsic silicon or isotopically pure silicon (Si). 28 The semiconductor layer may be doped with silicon. Optionally, the semiconductor layer forms part of a layered substrate, which further includes an insulating layer beneath the semiconductor layer. The substrate may include an additional layer beneath the insulating layer. In an example, the semiconductor layer is a silicon layer disposed on a buried oxide, which is also disposed on a silicon substrate. Alternatively, an insulating layer may not be present beneath the semiconductor layer, and the semiconductor layer may form part of a bulk semiconductor substrate.

[0013] The dielectric layer disposed on the semiconductor layer and forming a functional interface with the semiconductor layer can be any suitable electrically insulating material, such as silicon dioxide, aluminum oxide, undoped aluminum gallium arsenide (AlGaAs), or a material with a high dielectric constant κ, such as hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide.

[0014] Preferably, the first metal region comprises a conductor with high carrier mobility, such as a superconductor. For example, the first metal region may comprise titanium nitride (TiN), niobium nitride (NbN), or titanium niobium nitride (NbTiN). These materials typically exhibit high kinetic inductance. The inductance of the first metal region providing the inductor in an LC resonator circuit depends on the material properties and geometry of the first metal region. The inductance of the first metal region is typically between 10 and 100 nanohenries, and preferably between 40 and 60 nanohenries. For example, the inductance of the first metal region could be 50 nanohenries. The inductance depends on the geometry of the first metal region. Advantageously, when the first metal region comprises a material with high kinetic inductance, the inductor can be made smaller, resulting in a more compact device.

[0015] The dynamic inductance of the first metal region depends on its geometry. The dynamic inductance is inversely proportional to the thickness and length of the first metal region and directly proportional to its extension. Therefore, any of the following will increase the dynamic inductance of the first metal region: a reduced thickness; a narrower region; or an increased extension.

[0016] Preferably, the thickness of the first metal region is 1 to 10 nanometers. A thinner first metal region will have higher dynamic inductance, which advantageously results in a smaller area occupied by the first metal region, thereby enabling a more compact device.

[0017] Superconducting materials, such as those that can form part of a first metallic region, have a critical temperature below which the resistivity of the material is zero, i.e., the material becomes superconducting. The critical temperature of this superconductor can be below 70 Kelvin, preferably below 20 Kelvin, and more preferably below 10 Kelvin. This has the advantage that superconductors with lower critical temperatures generally have higher dynamic inductance. However, the critical temperature of a superconductor is not a limiting factor.

[0018] Therefore, the first metal region provides an inductor in the LC resonator circuit of the quantum device at low temperatures, and the dual quantum dots provide a capacitor in the LC resonator circuit. To measure or infer the state of the qubits, the device preferably further includes a power supply and a probe. The power supply is typically configured to operate at a frequency corresponding to the resonant frequency of the LC resonator circuit. The power supply may be connected to the first metal region. The probe may be connected to the first metal region and / or the second metal region and is typically configured to measure the power transfer through the LC resonator circuit. The measurement of the power transfer through the LC resonator circuit can be used to infer the state of the qubits.

[0019] The measured power transfer can be, for example, forward power transfer S 21 In this example, the power supply is connected to the first metal area, and the probe is connected to the second metal area. 21 These are S-parameters or scattering parameters used to determine the relationship between the first and second ports. Forward power transfer is high at the resonant frequency of the LC resonator circuit. The resonant frequency of this LC resonator circuit depends on the state of the qubits.

[0020] In another example, the measured power transfer could be the reflected power transfer S. 11 In this example, the power supply and probe are connected to the first metal area. 11 These are additional S-parameters that depend on the resonant frequency of the LC resonator circuit. At the resonant frequency of the LC resonator circuit, the reflected power transmission is low.

[0021] In another example, a power supply is connected to a first metal region, and a probe is connected to both a first metal region and a second metal region. In this example, the forward power transfer S can be measured. 21 and reflected power transmission S 11 Both.

[0022] Optionally, the power supply is configured to operate at the resonant frequency of the LC resonator circuit corresponding to the first state of the qubit. Therefore, if the qubit is in the first state, the forward power transfer S... 21 The forward power transfer will be high if the qubit is in the second state. Alternatively, the power supply can be configured to operate at the resonant frequency of the LC resonator circuit corresponding to the second state of the qubit. In this example, the forward power transfer will be high if the qubit is in the second state and low if the qubit is in the first state.

[0023] Optionally, the power supply is configured to operate at the resonant frequency of the LC resonator circuit corresponding to the first state of the qubit, with reflected power transfer S. 11 The reflected power transfer is used to infer the state of a qubit. If the qubit is in the first state, the reflected power transfer will be low. If the qubit is in the second state, the reflected power transfer will be high. The reflected power transfer spectrum includes a reverse peak at the resonant frequency. In another example, the power supply is configured to operate at the resonant frequency of the LC resonator circuit corresponding to the second state of the qubit, and the reflected power transfer is used to infer the state of the qubit: if the qubit is in the second state, the reflected power transfer will be low, and if the qubit is in the first state, the reflected power transfer will be high.

[0024] Advantageously, this device can be used to sensitively infer the state of qubits based on power transfer measurements. Furthermore, compared to existing technologies, the device provides a significantly more compact qubit readout mechanism. The qubit cell, including a first metal region and a second metal region suitable for supporting the dual-quantum-dot qubit, can be approximately 100 nanometers by 10 micrometers. This is about 10,000 times smaller than existing devices with similar functionality.

[0025] Typically, an LC resonator circuit has two resonant frequencies: a first resonant frequency corresponding to the first state of a qubit and a second resonant frequency corresponding to the second state of a qubit. Preferably, the power supply is configured to operate at the lower of the first and second resonant frequencies. Choosing the lower frequency has the advantage of reducing parasitic losses.

[0026] The resonant frequency of an LC resonator circuit is determined by the inductors and capacitors in the circuit. Optionally, a first metal region provides a first inductor in the LC resonator circuit, and a second metal region provides a second inductor. Preferably, only the first and second metal regions provide inductors in the LC resonator circuit. Using this arrangement, no additional inductor is required to perform qubit readout, thus the device can be advantageously more compact. Since readout can be performed at either the first or second metal region, including both the first and second inductors provided by the first and second metal regions advantageously provides additional flexibility compared to having only the first inductor provided by the first metal region. Furthermore, when both the first and second metal regions provide inductors in the LC resonator circuit and the inductors are connected in series, the total inductance of the circuit can be increased. This has the advantage that the device size can be further reduced for a given inductance.

[0027] If the second metal region provides a second inductor in an LC resonator circuit, then the second metal region preferably has substantially the same characteristics as the first metal region. For example, the second metal region preferably comprises a high carrier mobility conductor with high dynamic inductance, such as titanium nitride, niobium nitride, or titanium niobium nitride. The second metal region preferably has similar dimensions to the first metal region. This has the advantage of making such a device easier to manufacture.

[0028] The first and second metal regions are laterally separated. This lateral separation provides electrical isolation. Optionally, the dielectric layer disposed on the semiconductor layer and forming a functional interface with the semiconductor layer is a first dielectric layer, and the device further includes a second dielectric layer, wherein the second dielectric layer is disposed at least on the first and second metal regions. The second dielectric layer may at least partially cover the edges of the first and second metal regions. The portion of the second dielectric layer covering the first metal region may be laterally separated from the portion of the second dielectric layer covering the second metal region. Alternatively, the portion of the second dielectric layer covering the first metal region may be connected to the portion of the second dielectric layer covering the second metal region, such that the gap between the first and second metal regions is closed. The second dielectric layer may be, for example, silicon nitride (Si3N4), aluminum oxide (Al2O3), or silicon dioxide (SiO2). The use of the second dielectric layer advantageously improves the electrical isolation between the first and second metal regions and also protects the first and second metal regions from damage.

[0029] Optionally, the device further includes a masking layer covering the first metal region. The masking layer may be disposed on the first metal region. Optionally, the masking layer also covers the second metal region. The masking layer may include, for example, polysilicon, aluminum, silicon oxide, silicon nitride, or aluminum oxide. The advantage of including the masking layer is that it protects both the first and second metal regions. When the masking layer is disposed on the first and second metal regions, it can protect both regions from mechanical and electrical damage that may occur during device manufacturing and / or during device operation.

[0030] The device is preferably manufactured using a complementary metal-oxide-semiconductor (CMOS) manufacturing process. This advantageously facilitates device production.

[0031] In this aspect of the invention, the semiconductor layer comprises nanowires. Nanowires can be fabricated by selectively etching a substrate to define them. Alternatively, in some examples, nanowires, such as carbon nanotubes, can be grown. A first metal region and a second metal region can be disposed on opposite sides of the nanowire, such that each of the first and second metal regions partially overlaps with an edge of the nanowire, and corresponding portions of the first and second metal regions extend away from the nanowire. The corresponding portions of the first and second metal regions can extend in a direction substantially perpendicular to the nanowire. This can advantageously facilitate the fabrication process.

[0032] Alternatively, the corresponding portions of the first and second metal regions can extend in a non-linear manner. The dynamic inductance of each metal region is proportional to its extension; therefore, arranging the corresponding portions of the first and second metal regions in a non-linear manner (such as meandering or bending, serpentine) has the advantage of allowing the device to occupy a smaller area. In another example, the extensions of the first and second metal regions are angled relative to the nanowire: the specific arrangement of the extensions does not affect the electrical characteristics of the device. A dielectric layer is disposed on the nanowire, thereby providing electrical separation between the semiconductor layer and the first and second metal regions.

[0033] Preferably, the first and second metal regions are positioned such that first and second quantum dots can be induced at the corners of the nanowire. The dual quantum dots comprise a first quantum dot and a second quantum dot located below the first and second metal regions, respectively. This arrangement (which may be referred to as a split-gate transistor) advantageously results in strong carrier confinement due to its geometry: charge carriers are confined in two dimensions by both sides of the formation corner of the nanowire. The extension lengths of the first and second metal regions are selected according to the desired inductance. This arrangement has the additional advantage of being easily scaled up. Preferably, if the metal regions are arranged such that a one-dimensional array of dual quantum dot qubits can be supported along the nanowire, the extension of the metal regions is non-linear or substantially perpendicular to the nanowire. This has the advantage that adjacent metal regions can remain laterally and electrically separated and do not contact each other at any point. Furthermore, such a construction is advantageously easier to design and manufacture.

[0034] To scale up the device, it may optionally further include a third metal region and a fourth metal region disposed on the dielectric layer. The third and fourth metal regions correspond to the first and second metal regions described above. The third and fourth metal regions may be disposed on opposite sides of the nanowire, such that each of the third and fourth metal regions partially overlaps with an edge of the nanowire and includes a corresponding portion extending away from the nanowire (preferably in a direction perpendicular to the nanowire). The third and fourth metal regions are preferably laterally separated from the first and second metal regions along the longitudinal axis of the nanowire. Typically, the first and second metal regions are arranged electrically connected such that a first dual quantum dot can be induced below the first and second metal regions at the functional interface; the third and fourth metal regions are arranged electrically connected such that a second dual quantum dot can be induced below the third and fourth metal regions at the functional interface.

[0035] In this way, the device can be scaled in one dimension. Additional qubit cells can be spaced along the nanowires, with each qubit cell comprising two metallic regions suitable for supporting dual-quantum-dot qubits. The spacing can be regular or irregular. This scalable architecture is advantageous and aligns with research directions in quantum computing and quantum devices for qubit processing.

[0036] Optionally, the inductance of each of the third and fourth metal regions is greater than the inductance of each of the first and second metal regions. To achieve this, the third and fourth metal regions can extend further and / or be narrower than the first and second metal regions. Alternatively, the third and fourth metal regions can be made thinner than the first and second metal regions, although this may be difficult to achieve in practice. Preferably, the third and fourth metal regions extend further than the first and second metal regions and have the same length. Optionally, the first and second metal regions extend linearly, substantially perpendicular to the nanowire, while the third and fourth metal regions extend non-linearly, such that the third and fourth metal regions do not occupy areas extending beyond the first and second metal regions. In this way, the device can be advantageously made more compact.

[0037] The first dual quantum dot forms the first qubit in a first quantum dot cell that includes the first metal region and the second metal region and forms the first LC resonator circuit. The second dual quantum dot forms the second qubit in a second quantum dot cell that includes the third metal region and the fourth metal region and forms the second resonator circuit. The inductance difference between the first and second metal regions, and between the third and fourth metal regions, results in different resonant frequencies for the first and second LC resonator circuits. This provides the advantage that the states of the first and second qubits can be simultaneously measured or inferred using frequency domain multiplexing.

[0038] Typically, the device further includes a source electrode and a drain electrode. For devices comprising a one-dimensional array of qubit cells, the source electrode and drain electrode are preferably arranged at a first end and a second end of the array, respectively. For example, the one-dimensional array may have n qubit cells arranged sequentially from 1 to n along the longitudinal axis of the nanowire. In this case, the source electrode is preferably arranged closest to the first qubit cell and laterally separated along the longitudinal axis of the nanowire. Similarly, the drain electrode is preferably arranged closest to the nth qubit cell and laterally separated along the longitudinal axis of the nanowire. This may also be the case for devices comprising a single qubit cell (i.e., n=1). Typically, the source electrode and drain electrode are arranged electrically connected so that a bias potential can be applied. Applying a bias potential to the source electrode and / or drain electrode can be used to change the conductivity of the semiconductor layer.

[0039] In another embodiment of this invention, the semiconductor layer includes a nanowire, with a first metal region and a second metal region laterally separated along the longitudinal axis of the nanowire. Each of the first and second metal regions may cover one or both edges of the nanowire. This has the advantage of ease of fabrication.

[0040] The first and second metal regions typically extend substantially perpendicular to the nanowire. Alternatively, the first and / or second metal regions can extend at any angle without affecting the device's functionality. In another example, the first and / or second metal regions can extend in a non-linear manner (e.g., a zigzag pattern). The extensions of the first and second metal regions define their inductance; a specific layout can be chosen according to design requirements without affecting device functionality. For practical reasons, it is advantageous for the first and second metal regions to extend substantially perpendicularly to facilitate their arrangement without overlap.

[0041] Optionally, the main portion of the first metal region extends on the same side of the nanowire as the main portion of the second metal region. Alternatively, the main portions of the first and second metal regions may extend on opposite sides of the nanowire. The device is typically designed to reduce the overall area.

[0042] In this embodiment, the source electrode is preferably arranged closer to the first metal region and laterally separated along the longitudinal axis of the nanowire. The drain electrode is preferably arranged closer to the second metal region and laterally separated along the longitudinal axis of the nanowire.

[0043] In another embodiment of this invention, the dielectric layer includes thin regions and thick regions. The dielectric layer may include one or more thin regions and one or more thick regions. The thin and thick regions may be connected such that the dielectric layer is a continuous layer with non-uniform thickness. The thickness of the dielectric layer in the thin regions is typically at least half the thickness of the dielectric layer in the thick regions. The thin regions may have a thickness between 1 and 10 nanometers. The thick regions of the dielectric layer electrically isolate the first metal region and the second metal region from the semiconductor layer. A functional interface is formed between the semiconductor layer and the thin regions of the dielectric layer. Therefore, when a bias potential is applied to the first metal region and / or the second metal region, a confinement region can be induced below the thin regions of the dielectric layer. This has the advantage that the device can be realized in mass production.

[0044] The first metal region typically covers both the thin and thick regions of the dielectric layer. When a bias voltage is applied to the first metal region, one or more charge carriers can be confined below the thin region of the dielectric layer rather than below the thick region due to the reduced field effect below the thick region. The second metal region also typically covers both the thin and thick regions of the dielectric layer.

[0045] The device may include a generally rectangular thin region of a dielectric layer surrounded by a thick region of the dielectric layer. The thin rectangular region typically includes a first edge and a second edge separated by 30 to 200 nanometers, or preferably 30 to 150 nanometers, and may extend several micrometers. Optionally, a first metal region and a second metal region are respectively disposed on the first and second edges of the thin rectangular region, such that each of the first and second metal regions partially overlaps with an edge of the thin rectangular region and includes a corresponding portion extending away from the thin region covering the thick region. Typically, first and second quantum dots may be induced at the edges of the thin rectangular region of the dielectric layer beneath the first and second metal regions, respectively.

[0046] The layout of the extensions of the first and second metal regions covering the thick area can be linear or non-linear. This layout is typically arranged to reduce the area occupied by the first and second metal regions. Preferably, the layout is arranged to facilitate the manufacturing process.

[0047] The device may optionally further include a third metal region and a fourth metal region disposed on the dielectric layer. The third metal region and the fourth metal region may be disposed on the first edge and the second edge of the thin rectangular region, respectively, such that each of the third metal region and the fourth metal region partially overlaps with an edge of the thin rectangular region and includes a corresponding portion extending away from the thin region. The corresponding portion covers the thick region. The third metal region and the fourth metal region are preferably laterally separated from the first metal region and the second metal region along the longitudinal axis of the thin rectangular region.

[0048] The first and second metal regions are arranged to be electrically connected, such that a first double quantum dot can be induced below the functional interface at the first and second metal regions. The third and fourth metal regions are arranged to be electrically connected, such that a second double quantum dot can be induced below the functional interface at the third and fourth metal regions. The functional interface is typically formed between a thin region of the semiconductor layer and the dielectric layer. Optionally, the inductance of each of the third and fourth metal regions is greater than the inductance of each of the first and second metal regions.

[0049] In another example, the first and second metal regions are laterally separated along the longitudinal axis of a thin rectangular region of the dielectric layer. Typically, the first and second quantum dots can be induced below the first and second metal regions at the interface between the thin dielectric layer and the semiconductor layer: this interface is called the functional interface. In this example, the first and second quantum dots can be formed substantially at the center of the thin rectangular region of the dielectric layer.

[0050] Another aspect of the present invention provides a method for performing qubit measurement or readout using the above-described quantum device. The method includes the following steps: applying a first bias potential and a second bias potential to a first metal region and a second metal region, respectively, to induce a dual quantum dot; forming a qubit having a first state and a second state at a functional interface below the first and second metal regions; applying a signal to the first metal region at a selected frequency; applying a bias voltage difference between the first and second metal regions; and measuring the power transfer at the first or second metal region, wherein the measurement is used to measure or infer the state of the qubit.

[0051] In this method, a first metal region and a second metal region are used to induce dual quantum dots and measure or infer the state of the qubits. The first metal region is preferably the sole inductor in the LC resonator circuit used to perform the qubit measurement or readout. This dual function advantageously reduces the area occupied by the device. In some embodiments, the second metal region provides an additional inductor in the LC resonator circuit.

[0052] Optionally, the first bias potential and the second bias potential can be the same, and the first bias potential and the second bias potential can be applied, for example, using a single source. However, the first metal region and the second metal region are electrically separated regions.

[0053] Two quantum dots form qubits with a first state and a second state. The capacitance of a qubit depends on its state. The qubit forms a capacitor in an LC resonator circuit, and a first metallic region provides an inductor in the LC resonator circuit. The resonant frequency of the LC resonator circuit depends on the state of the qubit. At the resonant frequency of the LC resonator circuit, forward power transfer is at its maximum and reflected power transfer is at its minimum.

[0054] The selected frequency applied to the first metal region preferably corresponds to the resonant frequency of the LC resonator circuit. Typically, the selected frequency is the resonant frequency of the LC resonator circuit when the capacitance of the two quantum dots is at its maximum. This can, for example, correspond to the first state of the qubits. The larger the capacitance, the lower the resonant frequency. Applying a signal with a lower frequency has the advantage of generally resulting in lower parasitic losses.

[0055] The measured power transfer can be forward power transfer S 21 Or reflected power transmission S 11Preferably, if the measured power transfer is forward power transfer, the method includes measuring the forward power transfer at the second metal region. Preferably, if the measured power transfer is reflected power transfer, the method includes measuring the reflected power transfer at the first metal region. In the example, when the qubit is in the first state, the frequency of the signal corresponds to the resonant frequency of the LC resonator circuit. In this example, if the qubit is in the first state, the forward power transfer S 21 It will be high and reflective power transmission S 11 The forward power transfer will be low. Conversely, if the qubit is in the second state, the forward power transfer will be low and the reflected power transfer will be high. In this way, the measurement of power transfer at the first or second metal region can be used to measure or infer the state of the qubit.

[0056] The described method includes the measurement of a single qubit. If the device includes multiple additional qubits, the method may further relate to a multiplexing method to read out the states of multiple qubits. In a device with multiple qubits, the method may include: applying a first bias potential and a second bias potential to a first metal region and a second metal region, respectively, to induce a first dual quantum dot to form a first qubit; and applying a third bias potential and a fourth bias potential to a third metal region and a fourth metal region, respectively, to induce a second dual quantum dot to form a second qubit.

[0057] Optionally, the method includes time-domain multiplexing. At a first time t0, the method may include applying a signal to a first metal region at a first selected frequency. At a second time t1 (t1>t0), which is later than the first time, the method may include applying a signal to a third metal region at a second selected frequency. The second selected frequency may be the same as the first selected frequency. Measurements of power transfer in the second and fourth metal regions are performed sequentially to infer the states of the first and second qubits. The advantage of performing time-domain multiplexing is the scalability of the device and the technique.

[0058] Optionally, as an alternative to or in combination with time-domain multiplexing, the method includes frequency-domain multiplexing. To perform frequency-domain multiplexing, the inductance of the first and / or second metal regions differs from that of the third and / or fourth metal regions. As a result, the resonant frequencies of the corresponding LC resonator circuits are different, and measurements of power transfer across the frequency range can be used to simultaneously measure or infer the states of the first and second qubits. The advantage of performing frequency-domain multiplexing is the increased processing speed due to the simultaneous readout of multiple qubits.

[0059] Preferably, the method is carried out at a temperature below 20 Kelvin, and more preferably at a temperature below 10 Kelvin. Advantageously, at lower temperatures, the effect of thermal excitation on the occupancy of the dual quantum dots is reduced. Furthermore, the first metallic region may be included at the critical temperature T. c The following are examples of superconductors. The critical temperature depends on the material, but is typically low. Therefore, when the temperature of the first metal region is at a low temperature, the first metal region is typically superconducting. Advantageously, the first metal region is thus suitable for use as an inductor at low temperatures.

[0060] Another aspect of the present invention provides a method for assembling the aforementioned quantum device. The method includes the following steps: depositing a dielectric layer on a semiconductor layer to form a functional interface; depositing a first metal region on the dielectric layer; and depositing a second metal region laterally separated from the first metal region on the dielectric layer. The first and second metal regions are configured to be electrically connected, such that a dual quantum dot having qubits in a first state and a second state can be induced to form below the functional interface at the first and second metal regions. The dual quantum dot provides a capacitor in an LC resonator circuit, and the capacitance of the dual quantum dot depends on the state of the qubits. The first metal region provides an inductor in the LC resonator circuit. The resonant frequency of the LC resonator circuit depends on the state of the qubits, allowing the state of the qubits to be measured or inferred.

[0061] Preferably, the first metal region provides the sole inductor in the LC resonator circuit. This method of assembling quantum devices advantageously produces compact devices suitable for qubit readout.

[0062] Alternatively, the processing of the first metal region is performed in a different processing step than the processing of the second metal region. In this way, the first and second metal regions can be formed from different materials, such as titanium nitride and polycrystalline silicon.

[0063] Alternatively, the first and second metal regions can be disposed on the dielectric layer in the same processing step. This has the advantage of simplifying the manufacturing process. In this case, the first and second metal regions are typically made of the same material (such as niobium nitride or another material with high dynamic inductance).

[0064] The method may further include disposing a masking layer on the first metal region. Optionally, the method also includes disposing a masking layer on the second metal region. When the first and second metal regions are covered by the masking layer, the first and second metal regions are advantageously protected from damage. Potential damage may be caused by additional processing steps.

[0065] For example, a device typically includes a source electrode and a drain electrode. Methods of assembling the device may optionally include performing a self-aligned implantation process to define source and drain ohmic contacts. During this process, the first and second metal layers may be damaged unless they are covered.

[0066] Aspects of the invention advantageously provide a compact device layout in which a qubit readout mechanism is embedded within a metallic region of the device. The first metallic region provides a dual function, as it can be used to induce quantum dots and can also serve as an inductor in an LC resonator circuit for inferring the state of the qubits: this advantageously reduces the size of the circuitry required to support and read out the qubits by four orders of magnitude compared to existing devices. The circuitry for supporting and reading out the qubits can occupy an area of ​​approximately 100 nanometers by 10 micrometers. Furthermore, aspects of the invention are suitable for integration into scalable device architectures adapted to handle multiple qubits. Attached Figure Description

[0067] Embodiments of the invention will now be described with reference to the accompanying drawings, in which:

[0068] Figure 1A is a cross-sectional side view of a prior art quantum device;

[0069] Figure 1B is a cross-sectional side view of a prior art quantum device;

[0070] Figure 2A This is a cross-sectional side view of a quantum device;

[0071] Figure 2B This is a cross-sectional side view of a quantum device;

[0072] Figure 3A This is a cross-sectional side view of a quantum device;

[0073] Figure 3B This is a cross-sectional side view of a quantum device;

[0074] Figure 4A This is a planar diagram of a quantum device;

[0075] Figure 4B This is a planar diagram of a quantum device;

[0076] Figure 5 This is a flowchart of a method for assembling quantum devices;

[0077] Figure 6 This is a cross-sectional side view of a quantum device;

[0078] Figure 7 This is a cross-sectional side view of a quantum device;

[0079] Figure 8 It is a method used to perform qubit measurement or readout;

[0080] Figure 9 It is a circuit diagram representing a quantum device;

[0081] Figure 10A It is a graph showing the power transfer as a function of the frequency of the first capacitor;

[0082] Figure 10B This is a graph showing the power transfer as a function of the frequency of the second capacitor;

[0083] Figure 11A It is a planar diagram of a quantum device; and

[0084] Figure 11B This is a planar diagram of a quantum device. Detailed Implementation

[0085] Figures 1A and 1B schematically illustrate cross-sectional side views of prior art quantum devices. The device shown in Figure 1A is an exemplary nanowire transistor. The nanowire transistor includes silicon nanowires 1 disposed on a silicon dioxide layer 2. The silicon dioxide layer 2 forms part of a substrate, which further includes a silicon layer (not shown). A dielectric layer 3 containing silicon dioxide covers the silicon nanowires 1. A titanium nitride layer 4 covers the dielectric layer 3. The thickness of the titanium nitride layer 4 is approximately 5 nanometers. A polycrystalline silicon layer 5 covers the titanium nitride layer 4. The polycrystalline silicon layer 5 is conductive and extends from the silicon nanowires 1 to a gate electrode 6. The gate electrode 6 is connected to a power source (not shown) for applying a bias potential to the conductive polycrystalline silicon layer 5. In this way, one or more charge carriers can be confined within the silicon nanowires 1 to form a quantum dot.

[0086] The device shown in Figure 1B is an exemplary planar transistor. The planar transistor includes a silicon layer 7 and a silicon dioxide layer 8 that partially covers the silicon layer 7. The device includes a dielectric layer 3 deposited on the silicon layer 7 in gaps within the silicon dioxide layer 8. In this example, the dielectric layer 3 is silicon dioxide. In another prior art example, a silicon dioxide layer is deposited on the silicon layer, and the silicon dioxide layer has a different thickness. The device shown in Figure 1B further includes a titanium nitride layer 4 and a polysilicon layer 5 connected to a gate electrode 6, as shown in Figure 1A. The titanium nitride layer 4 covers the dielectric layer 3, and the polysilicon layer 5 covers the titanium layer 4. The polysilicon layer 5 extends from the dielectric layer 3 toward the gate electrode 6. When a bias potential is applied to the conductive polysilicon layer 5, this device can confine one or more charge carriers below the dielectric layer 3 (or below a thin region of a variable-thickness silicon dioxide layer). One or more charge carriers can be confined in a quantum dot.

[0087] In Figures 1A and 1B, the titanium nitride layer 4 can be used for threshold voltage engineering. Threshold voltage engineering is a technique used to offset threshold voltages, allowing the operand values ​​of qubits to be set to appropriate values. In alternative prior art examples, the thickness of the titanium nitride layer can vary, but is typically between 1 and 10 nanometers. Titanium nitride is a material with high dynamic inductance. The inductance of the titanium nitride layer 4 depends on the geometry, but is typically less than 1 nanohenry in existing quantum devices.

[0088] Figure 2A and 2B A cross-sectional side view of a quantum device according to an embodiment of the present invention is shown schematically.

[0089] Figure 2A The device shown illustrates a semiconductor layer 201 disposed on a thick dielectric layer 202. In this example, the semiconductor layer 201 comprises silicon, and the thick dielectric layer 202 comprises silicon dioxide (SiO2). In an alternative example, the semiconductor layer 201 can be any suitable semiconductor, such as gallium arsenide, indium arsenide, silicon germanide, graphene, carbon nanotubes, or silicon carbide; the thick dielectric layer 202 can be any suitable electrically insulating layer, such as silicon oxide, silicon nitride, or aluminum oxide. The thick dielectric layer 202 forms part of a substrate, which includes another support layer (not shown) beneath the thick dielectric layer 202, which in this example is made of silicon. In an alternative example, there is no thick dielectric layer, and the semiconductor layer forms part of the substrate.

[0090] Figure 2A The semiconductor layer 201 includes silicon nanowires that extend into the page, such as... Figure 2A As shown in the diagram, a thin dielectric layer 203 is disposed on the semiconductor layer 201. The thin dielectric layer 203 covers the exposed side of the semiconductor layer 201 and includes thermally grown silicon dioxide (SiO2). A metal region 204 is disposed on the thin dielectric layer 203. The thin dielectric layer 203 provides an electrostatic barrier between the semiconductor layer 201 and the metal region 204.

[0091] Metal region 204 comprises titanium nitride (TiN). In alternative examples, the metal region may comprise niobium nitride or titanium niobium nitride. TiN is a superconducting material with high dynamic inductance. For example, for a 10 nm thick film, the dynamic inductance of a TiN film can exceed 200 picohens / square. The inductance of metal region 204 depends on its size. The inductance is proportional to the elongation of metal region 204 and inversely proportional to the length of metal region 204. Therefore, the dynamic inductance is proportional to the ratio of the elongation to the length of metal region 204. For a TiN film with a fixed thickness of 10 nm, the inductance of a region with equal length and elongation will exceed 200 picohens. The high dynamic inductance of TiN means that the metal region can be relatively small, yet provide an inductor with high inductance. In this example, metal region 204 is 20 nm thick. Inductance is inversely proportional to thickness, so in another example, the inductance can be increased by reducing the thickness of the metal region.

[0092] The length of the metal region 204 is measured along the longitudinal axis of the nanowire and is 22 nanometers in this example, although this is not visible in the cross-sectional view. The metal region 204 is electrically connected such that a quantum dot can be induced below the metal region 204 at the functional interface between the semiconductor layer 201 and the thin dielectric layer 203 within the nanowire. The length of the metal region 204 affects the size of the quantum dot, and thus its properties, such as its charging energy. Inductance is inversely proportional to the length of the metal region 204. In another example, the size of the quantum dot can be increased by increasing the length of the metal region; this will result in a lower charging energy for the quantum dot and a reduced inductance for the metal region.

[0093] Metal region 204 extends in a first direction substantially perpendicular to the nanowire. In an alternative example, the metal region extends from the nanowire to form an acute angle between the metal region and the nanowire. Metal region 204 extends to contact gate electrode 206. The extension of metal region 204 is the distance d between gate electrode 206 and semiconductor layer 201 measured along the first direction. g The inductance is defined by the length of current traveling from the gate electrode 206 to the semiconductor layer 201; the inductance of the metal region 204 is proportional to its extension. Thus, in this example, to achieve an inductance of 50 nanohenries, the metal region 204 extends approximately 10.6 µm. In another example, the extension of the metal region can be increased to increase the inductance.

[0094] The metallic region 204 can alternatively extend in a non-linear manner. For example, the metallic region 204 may meander on the surface of the thick dielectric layer 202. Therefore, in this example, the farthest point of the metallic region 204 is less than d. g Although the extension of the metal region is d g This can be used to design more compact device architectures.

[0095] Figure 2B The device shown has the same Figure 2A The device shown has the same structural features. However, in Figure 2B In this structure, semiconductor layer 201 comprises gallium arsenide (GaAs), and thin dielectric layer 203 comprises thermally grown oxide. Support layer (not shown) comprises gallium arsenide, and thick dielectric layer 202 comprises silicon dioxide, silicon nitride, or aluminum oxide. Furthermore, Figure 2B The device also includes a masking layer 205. The masking layer 205 covers the metal region 204. In this example, the masking layer 205 comprises polysilicon. Alternatively, for example, the masking layer may comprise aluminum. The masking layer 205 serves to prevent damage to the metal region 204. Figure 2B The masking layer 205 shown is located between the metal region 204 and the gate electrode 206. The masking layer 205 is conductive, such that the metal region 204 is electrically connected to the gate electrode 206.

[0096] Figure 3A and 3B A cross-sectional side view of a quantum device according to an embodiment of the present invention is shown schematically. Figure 3A The device substrate includes a semiconductor layer 307 comprising indium arsenide (InAs). In an alternative example, any semiconductor material compatible with complementary metal-oxide-semiconductor (CMOS) fabrication processes can be used. A thick dielectric layer 308 partially covers the semiconductor layer 307. This can be achieved by selectively depositing the thick dielectric layer 308 on the semiconductor layer 307, thus preserving the gaps. Alternatively, in a first processing step, the thick dielectric layer 308 can be deposited to completely cover the semiconductor layer 307, and in a second processing step, a portion of the thick dielectric layer 308 can be removed to form gaps. In this example, the thick dielectric layer 308 comprises aluminum oxide (Al₂O₃). In an alternative example, the thick dielectric layer comprises silicon dioxide or silicon nitride.

[0097] A thin dielectric layer 303 comprising aluminum oxide is disposed on the semiconductor layer 307. In another example, the thin dielectric layer comprises hafnium dioxide or any other material having a high dielectric constant. In this example, the thin dielectric layer 303 and the thick dielectric layer 308 are deposited in separate processing steps. Alternatively, the thin dielectric layer 303 can be formed by selectively removing portions of the thick dielectric layer 308 to form regions of the thin dielectric layer 303 using chemical or physical processes.

[0098] Similar to Figure 2A and 2B Metal region 304 is disposed on thin dielectric layer 303. Figure 3A and 3BIn this embodiment, metal region 304 comprises niobium nitride (NbN). NbN is a material with high dynamic inductance. In an alternative example, metal region 304 may comprise titanium nitride or titanium niobium nitride. Metal region 304 extends along thick dielectric layer 308 to make electrical contact with gate electrode 306. Figure 3A and 3B In this process, applying a bias potential to the gate electrode 306 can induce quantum dots at the functional interface between the semiconductor layer 307 and the thin dielectric layer 303, below the metal region 304.

[0099] Figure 3B The device shown has the same Figure 3A The device shown has the same structural features and further includes a masking layer 305. The masking layer 305 comprises aluminum and is disposed on the metal region 304. In another example, the masking layer comprises any conductive material, such as polysilicon. Figure 3B In this structure, semiconductor layer 307 comprises a bilayer of graphene. A thick dielectric layer 308 comprises aluminum dioxide, which is selectively deposited on semiconductor layer 307. A thin dielectric layer 303 comprises graphene oxide, which is deposited or grown after the deposition of the thick dielectric layer 308. Semiconductor layer 307 is supported on a substrate such as a silicon substrate. In an alternative example, the thin dielectric layer comprises aluminum oxide or silicon oxide, which can be deposited using a suitable technique such as chemical vapor deposition (CVD).

[0100] Figure 4A and 4B A schematic plan view of a quantum device according to an embodiment of the present invention is shown. Each device includes a transistor comprising a source electrode 416 and a drain electrode 426 electrically connected to a nanowire 401. In this example, the nanowire comprises silicon. In alternative examples, the nanowire comprises gallium arsenide, single-walled or multi-walled carbon nanotubes, silicon germanium, indium arsenide, graphene, or silicon carbide. The source electrode 416 and drain electrode 426 are electrically connected to a voltage source. Applying a bias voltage difference between the source electrode 416 and the drain electrode 426 can be used to modify the electrical properties of the silicon nanowire 401. The nanowire 401 includes a highly doped region 404 and an undoped region 405.

[0101] Each device also includes a first metal region 414 and a second metal region 424 laterally separated from the first metal region 414. An undoped region 405 of the nanowire 401 extends below the first metal region 414 and the second metal region 424 to the edge of the nanowire 401. The nanowire 401 is electrically separated from the first metal region 414 and the second metal region 424 by a thin dielectric layer (not shown). The first metal region provides a first inductor in an LC resonator circuit, and the second metal region provides a second inductor in an LC resonator circuit. The first and second metal regions provide only inductors in the LC resonator circuit. There are no additional on-chip or off-chip inductors. The first metal region 414 and the second metal region 424 are electrically separated from the nanowire 401 by a thin dielectric layer (not shown), which is located at least between the first metal region 414 and the second metal region 424 and the nanowire 401. In an alternative example, the thin dielectric layer may cover the main portion of the nanowire, or it may be disposed only below the first and second metal layers. In this example, the thin dielectric layer is a thermally grown natural oxide.

[0102] The first metal region 414 and the second metal region 424 are electrically connected to corresponding gate electrodes (not shown), which are connected to an external voltage source. The voltage source can be used to apply a voltage to the first metal region 414 and the second metal region 424, allowing the induction of dual quantum dots below the first metal region 414 and the second metal region 424 at the functional interface. The functional interface is defined by the device geometry and electrical properties of the layers within the device. In this example, a nanowire covered with a thick dielectric layer is provided, which is supported by another support layer containing silicon. The functional interface lies between the outer surface of the nanowire and the thin dielectric layer covering the nanowire. The thick dielectric layer beneath the nanowire reduces field effects away from the nanowire. The dual quantum dots induced at the functional interface form qubits with two states and have variable capacitance that varies according to the state of the qubits. The dual quantum dots provide a capacitor in the LC resonator circuit of the device, which can be used to measure or infer the state of the qubits.

[0103] exist Figure 4A In the nanowire 401, the first metal region 414 and the second metal region 424 are separated along the longitudinal axis of the nanowire 401. In an alternative example, the nanowire 401 is replaced by carbon nanotubes, which have been grown and selected for their semiconductor properties. The spacing S between the first metal region 414 and the second metal region 424 is... gg Typically between 10 nanometers and 100 nanometers. Spacing S gg The spacing S is configured to be large enough that the first quantum dot and the second quantum dot formed beneath the first metal region 414 and the second metal region 424 can be distinguished when a bias potential is applied. On the other hand, the spacing S... ggIt is configured to be small enough that the first and second quantum dots can be tunnel coupled to form a dual quantum dot qubit.

[0104] Each of the first metal region 414 and the second metal region 424 has a length L g and extension d g Typically, the length and extension of the first metal region are the same as those of the second metal region. However, this is not mandatory; the dimensions of the metal regions can be chosen based on the desired device characteristics. The inductance of the first metal region 414 and the second metal region 424 is proportional to the extension and inversely proportional to the length. The dynamic inductance L per unit length is determined by the following equation. K :

[0105]

[0106] Where µ0 is the permeability of vacuum, λ is the London penetration depth, and L g and t g It refers to the length and thickness of the metallic region. Typically, the length L... g Between 7 nanometers and 100 nanometers, extending d g Between 1 nanometer and 100 nanometers. The thickness t of the first and second metal regions. g Typically, the inductance ranges from 1 to 20 nanometers. Thicker metal regions have lower inductance per square meter and therefore occupy a larger area. However, fabricating thinner metal regions can result in lower yields due to manufacturing difficulties. In this example, the metal region comprises TiN with a length of 40 nanometers and a thickness of 10 nanometers. In this example, the inductance of the metal region extending is 5 nanohenries per micrometer.

[0107] exist Figure 4A In the nanowire 401, a first metal region 414 and a second metal region 424 are positioned to cover the two edges of the nanowire 401. Applying a bias potential to the first metal region 414 and the second metal region 424 induces a first quantum dot and a second quantum dot, respectively, below the first and second metal regions in the nanowire 401. Each of the first and second quantum dots is substantially located at the center of the nanowire, away from the edges. The nanowire 401 has a narrow width w, and the corresponding metal region has a length L. gThe functional interface between the nanowire 401 and the thin dielectric layer (not shown) enables the confinement of charge carriers in each of the first and second quantum dots. The width w of the nanowire 401 is typically between 30 nm and 140 nm. Preferably, w is less than 100 nm. In this example, the width w of the silicon nanowire 401 is approximately 60 nm. The narrower the nanowire, the stronger the confinement. The appropriate width of the nanowire will depend on the characteristics of the semiconductor used in the device, such as the effective mass of charge carriers.

[0108] In an alternative example, the first and second metal regions are positioned to cover only one edge of the nanowire, each covering the same edge of the nanowire. The first and second metal regions are laterally separated along the longitudinal axis of the nanowire. In this alternative example, the angle of the nanowire and the length L of the metal regions are used. g This is to achieve confinement of charge carriers. In this alternative example, the width w of the nanowire is irrelevant and can be several micrometers or larger.

[0109] exist Figure 4B In the nanowire 401, a first metal region 414 and a second metal region 424 are located on opposite sides of the nanowire 401. Each of the first metal region 414 and the second metal region 424 partially overlaps with one edge of the nanowire 401. The first metal region 414 and the second metal region 424 are separated by a spacing S along the width of the nanowire 401. vv Separate. The spacing S vv Typically between 10 and 100 nanometers. Spacing S vv The spacing S is configured to be large enough that the first quantum dot and the second quantum dot formed beneath the first metal region 414 and the second metal region 424 can be distinguished when a bias potential is applied. On the other hand, the spacing S... vv They are configured to be small enough that the first and second quantum dots can tunnel couple to form a dual quantum dot qubit.

[0110] The capacitance of this device depends on its geometry and the state of the qubits. The total capacitance consists of the variable capacitance generated by the two quantum dot qubits, the geometric capacitance, and the parasitic capacitance. The resonant frequency of an LC resonator circuit depends on the capacitance.

[0111] A dual-quantum-dot qubit has a first state with a first capacitance and a second state with a second capacitance. The values ​​of the first and second capacitances are different. In this example, the spin orientations of the electrons are antiparallel in the first state of the qubit and parallel in the second state. In the first state, tunneling is possible between the first and second quantum dots. In the second state, tunneling is suppressed due to spin blocking. Therefore, the first capacitance is much larger than the second capacitance. The first capacitance can be in the femtofarad range and will depend on the properties of the qubit.

[0112] The geometric capacitance can be estimated using the following equation:

[0113]

[0114] Where, ε die L is the dielectric constant of the thin dielectric layer. g and t g These are the length and thickness of the metal region, S. vv It is the spacing between the first and second metal regions perpendicular to the longitudinal axis of the nanowire. Using L... g =50 nanometers, t g =10 nanometers and S vv An exemplary value of 10 nanometers, for a device using a thin dielectric layer of silicon dioxide, results in a geometric capacitance of approximately 2 picofarads. This is much smaller than the first capacitance.

[0115] Parasitic capacitance can occur between any metallic region and the electric ground state. However, parasitic capacitance is typically small, for example, about 0.1–0.2 nanofarads. The value of parasitic capacitance is usually quoted by the manufacturer and can be incorporated into calculations to optimize qubit measurement parameters. Variations in capacitance affect the resonant frequency of LC resonator circuits and should therefore be taken into account during measurements.

[0116] In another example, the device includes an additional dielectric layer that covers both the first and second metal layers and optionally completely or partially occupies the gap between the first and second metal layers. The additional dielectric layer may be made of silicon nitride (Si3N4) and serves to ensure electrical separation between adjacent metal regions and provide protection against electrical and / or physical damage. The additional dielectric layer may also be made of any electrically insulating material.

[0117] In another example, the first metal region 414 contains TiN and the second metal region 424 contains polysilicon. In this example, the first metal region 414 provides an inductor in the LC resonator. However, the second metal region 424 does not contribute to the inductance.

[0118] Figure 5 A method for assembling a quantum device according to an embodiment of the present invention is illustrated. In step 501, a dielectric layer is disposed on a semiconductor layer to form a functional interface. The dielectric layer provides an electrically insulating layer. In one example, the semiconductor layer comprises silicon, and the dielectric layer comprises silicon dioxide or a high-dielectric-constant material such as hafnium dioxide. In another example, the semiconductor layer comprises any one of gallium arsenide, indium arsenide, silicon germanium, graphene, carbon nanotubes, or silicon carbide, and the dielectric layer comprises a thermally grown oxide or a high-k dielectric material deposited using atomic layer deposition. In one example, the semiconductor layer is a nanowire with a width between 30 nm and 140 nm. In another example, the semiconductor layer is a flat plateau region, and the dielectric layer comprises thin and thick regions. The width of the thin region is between 30 and 140 nm.

[0119] In step 502, a first metal region is formed on the dielectric layer. In step 503, a second metal region is formed on the dielectric layer, laterally separated from the first metal region. The lateral spacing is typically between 10 nanometers and 100 nanometers. The first and second metal regions are electrically connected such that a first confinement region and a second confinement region can be induced below the first and second metal regions, respectively, at the functional interface. The first and second confinement regions are coupled to form a qubit having a first state and a second state. The qubit has a variable capacitance and a capacitor is provided in an LC resonator circuit, which can be used to measure or infer the state of the qubit.

[0120] The first and second metal regions comprise materials with high dynamic inductance, such as titanium nitride, niobium nitride, or titanium niobium nitride. The first and second metal regions provide a first inductor and a second inductor in an LC resonator circuit. In an alternative example, only the first metal region provides an inductor in the LC resonator circuit. The LC resonator circuit has a first resonant frequency and a second resonant frequency, which depend on the inductance value of the qubit and the variable capacitance value.

[0121] The dimensions of the first and second metal regions affect their inductance. The lengths of the first and second metal regions are typically between 7 and 100 nanometers. The length influences the dimensions of the first and second confinement regions and the inductance: longer first and second metal regions result in larger first and second confinement regions and lower inductance. Depending on the desired inductance, the first and second metal regions are typically extended 1 to 100 micrometers away from the confinement regions. If a larger inductance is required, the first and second metal regions are designed to extend further.

[0122] Table 1 provides the dynamic inductance per square square for titanium nitride (TiN), niobium nitride (NbN), and titanium niobium nitride (NbTiN). For the thicknesses given in Table 1, the dynamic inductance values ​​have been experimentally determined and normalized to provide a comparison of the dynamic inductance of the materials independent of thickness. The critical temperature T is also given for the three materials. c Experimental values ​​for TiN were published in Applied Physics Letters, Vol. 113, 212601 (2018) by Shearrow et al. Experimental values ​​for NbN were published in Journal of Physics: Conference Series, Vol. 507, 042015 (2014) by Hayashi et al. Experimental values ​​for NbTiN were published in Physical Review Applied, Vol. 5, 044004 (2016) by Samkharadze et al.

[0123]

[0124] Table 1: Material properties of TiN, NbN and NbTiN.

[0125] It should be noted that any material with high dynamic inductance is suitable for use as the first and / or second metal layer of the devices described herein. Some superconductors have high dynamic inductance. Generally, disordered superconductors have higher dynamic inductance per square millimeter. Furthermore, superconductors with lower critical temperatures typically have higher dynamic inductance.

[0126] The influence of the dimensions of the first and second metal regions on the inductance can be seen using the values ​​given in Table 2 below. Table 2 shows the thickness t of each of the first and second metal regions required to achieve a 50 nano-Henry inductor using titanium nitride. g Length L g and extension d g Example values.

[0127]

[0128] Table 2: Exemplary relative dimensions of metal regions including TiN with a 50nH inductance

[0129] After processing the first and second metal regions, another exemplary assembly method further includes the step of setting a masking layer to cover the first and second metal layers. The masking layer comprises a conductive material, such as polysilicon or aluminum. The device fabrication process may involve a self-aligned implantation process to define the source and drain electrodes of the device. In this case, the masking layer protects the underlying metal regions.

[0130] The quantum devices according to embodiments of the present invention can be manufactured using industry-standard complementary metal-oxide-semiconductor manufacturing processes.

[0131] Figure 6 A cross-sectional side view of a quantum device according to an embodiment of the present invention is shown. Figure 6 In this example, the device includes a substrate 600 containing silicon. The device includes silicon fins 601 protruding from the substrate 600 to form a fin field-effect transistor (FinFET). In this example, the silicon substrate 600 has been etched to form the fins 601 protruding from the remainder of the substrate.

[0132] A thin dielectric layer 603 comprising silicon dioxide is disposed on the fin 601. A first metal region 614 and a second metal region 624 are arranged to cover the two edges of the fin 601. The first metal region 614 and the second metal region 624 provide a first inductor and a second inductor in the LC resonator of the device. The first metal region 614 and the second metal region 624 extend toward the first gate electrode 616 and the second gate electrode 626, respectively.

[0133] A functional interface is formed between a thin dielectric layer 603 and a fin 601. The thin dielectric layer 603 covers the substrate 600 and the fin 601, but the geometry of the fin 601 enhances the field effect in the fin 601 when a bias voltage is applied to the first metal region 614 and / or the second metal region 624. Therefore, a first quantum dot 610 can be supported at the functional interface between the silicon fin 601 and the thin dielectric layer 603 and below the first metal region 614, at the corner of the fin 601. Similarly, a second quantum dot 620 can be supported at the functional interface and below the second metal region 624, at the corner of the fin 601. The first quantum dot 610 and the second quantum dot 620 can tunnel coupled to form a dual quantum dot. The dual quantum dot forms a qubit with two quantum states and provides a capacitor in the LC resonator circuit of the device. The first quantum dot 610 and the second quantum dot 620 can be induced by applying bias potentials to the first metal region 614 and the second metal region 624, respectively.

[0134] At low temperatures, each of the first quantum dot 610 and the second quantum dot 620 can be used to confine a single electron when a suitable bias potential is applied to the first metal region 614 and / or the second metal region 624. Under certain conditions, electrons can tunnel back and forth between quantum dots 610 and 620. However, under other conditions, tunneling is suppressed due to spin blocking. Therefore, the dual quantum dots behave as variable capacitors, exhibiting high capacitance if the tunneling effect is not quantum state suppressed. In this example, the maximum capacitance of the dual quantum dots is between 1 and 10 nanofarads. The capacitance of the device depends on the state of the qubits as well as the geometry and material properties of the device. Therefore, the resonant frequency of the LC resonator circuit also depends on the state of the qubits. The relationship between the state of the qubits and the resonant frequency of the LC resonator circuit can be used to infer the state of the qubits by measuring frequency-dependent power transfer.

[0135] Figure 7 A cross-sectional side view of a quantum device according to an embodiment of the present invention is shown. Figure 7 In this device, a silicon-containing substrate 700 is included. A dielectric layer with a non-uniform thickness covers the substrate 700. The dielectric layer includes a thin region 703 and a thick region 702. In this example, the dielectric layer is a continuous region containing silicon dioxide.

[0136] A thin region 703 of the dielectric layer occupies a substantially rectangular area. The rectangular region has a first edge and a second edge. The device includes a first metal region 714 that covers a portion of the thin region 703 of the dielectric layer at the first edge and a portion of the thick region 702 of the dielectric layer. The device includes a second metal region 724 that covers a portion of the thin region 703 of the dielectric layer at the second edge and a portion of the thick region 702 of the dielectric layer. In this example, the first metal region 714 and the second metal region 724 contain NbTiN. In an alternative example, the first metal region and the second metal region contain TiN or NbN. When a bias voltage is applied to the first metal region and / or the second metal region, a stronger field effect is observed in the thinner portion of the dielectric layer. Therefore, a functional interface is formed between the thin region 703 of the dielectric layer beneath the first metal region 714 and the second metal region 724 and the substrate 700. First quantum dots and second quantum dots 710 and 720 can be induced at the functional interface below the first metal region and the second metal regions 714 and 724, respectively.

[0137] In another example, when shown in cross-section, the device includes two thin regions and three thick regions. The thin regions may be connected to each other in different areas of the device, while the thick regions may also be connected to each other elsewhere. In this example, a first metal region covers a first thick region, a first thin region, and optionally a portion of a second thick region. A second metal region covers a second thin region, a third thick region, and optionally a portion of a second thick region. However, the first and second metal regions are electrically and physically separate.

[0138] Figure 7 The device shown illustrates a single qubit comprising two quantum dots. This device can be scaled to support qubit arrays. Additional metallic regions can be configured to cover the dielectric layer, at least in thin regions of the dielectric layer. For example, third and fourth metallic regions can be configured to cover thin regions of the dielectric layer and are laterally separated from the first and second metallic regions.

[0139] In further modifications, the thin regions of the dielectric layer can be of any shape. Typically, each thin region of the dielectric layer comprises two parallel edges. However, the spacing between the edges can vary along the length of the thin region of the dielectric layer. The thin regions can also be nonlinear to support a two-dimensional array of qubits.

[0140] Figure 8 A method for performing a qubit measurement or readout according to an embodiment of the invention is shown. This method can be performed on any device according to an embodiment of the invention described herein. The device is cooled to a low temperature before performing the steps of the method detailed below. In this example, the device is cooled to below 4.2 Kelvin. However, in alternative examples, the operating temperature (i.e., the temperature at which the method can be performed) may be different.

[0141] The operating temperature depends on the material used for the first metal region. In order for the first metal region to exhibit the high dynamic inductance characteristics necessary for providing an inductor in an LC resonator, the first metal region must be cooled below the critical temperature T. c The estimated critical temperature is below 2 Kelvin; the estimated critical temperature of niobium nitride is 13-15 Kelvin; and the estimated critical temperature of niobium titanium nitride is 9 Kelvin.

[0142] The operating temperature also depends on the size of the quantum dot. To confine charge carriers within the quantum dot, the thermal energy must be much less than the quantum dot's charging energy. Larger quantum dots will have smaller charging energies, therefore requiring lower operating temperatures to confine charge carriers.

[0143] In step 801, a first bias potential is applied to the first metal region, and a second bias potential is applied to the second metal region. The first metal region and the second metal region can be arranged in series, for example, as shown below. Figure 4A As shown, or in parallel configuration, for example, Figure 4B As shown. The values ​​of the first and second bias potentials induce a first quantum dot below the first metal region at the functional interface between the semiconductor layer and the thin dielectric layer, and induce a second quantum dot below the second metal region at the functional interface. In this example, the first and second bias potentials are substantially the same, approximately 0.5 volts. Appropriate values ​​for the first and second bias potentials will depend on the geometry of the device.

[0144] At low temperatures, the magnitudes of the first and second bias potentials can be chosen to confine a single electron or several electrons within each of the first and second quantum dots. In this example, a single electron is confined within each quantum dot.

[0145] The first and second quantum dots are tunneled together to form a dual quantum dot. Under certain conditions, a single electron can tunnel from the first quantum dot to the second quantum dot, and from the second quantum dot to the first quantum dot. The capacitance of the dual quantum dot is relatively large when a single electron tunnels between the two quantum dots.

[0146] A dual quantum dot qubit forms a qubit with two quantum states defined by the relative electron spin states in a first quantum dot and a second quantum dot. In this example, the qubit is in the first state when the electron spins are antiparallel, and in the second state when the electron spins are parallel. The capacitance of the first qubit state is greater than that of the second qubit state because the tunneling effect is suppressed in the second state due to spin blocking.

[0147] In step 802, a high-frequency signal is applied to the first metal region using a power supply. The frequency of the high-frequency signal corresponds to the resonant frequency of the LC resonant circuit comprising the two quantum dots and the first and second metal regions. The resonant frequency of the LC resonant circuit depends on the capacitance of the two quantum dots. As described above, the capacitance of the two quantum dots depends on the state of the qubits.

[0148] In this example, when the qubit is in this first state, the frequency of the high-frequency signal corresponds to the resonant frequency of the LC resonator circuit. A larger capacitance corresponds to a lower resonant frequency. Applying a lower frequency signal results in less parasitic loss.

[0149] In step 802, the amplitude of the high-frequency excitation is selected so that it is less than the tunneling coupling voltage V between the quantum dots. in Therefore, there is no electron tunneling between the first and second quantum dots. The tunneling coupling voltage is determined by the following equation:

[0150]

[0151] Where e is the electron charge, α is the gate lever arm, Δ is the tunneling coupling energy, and Q is the quality factor of the LC resonator. The gate lever arm is defined as the difference between the ratio of the gate capacitance of the first metal region to that of the first quantum dot and the second quantum dot, and the total capacitance of each quantum dot. In the example, α = 0.5, Δ = 10µeV, Q = 1000, resulting in a tunneling coupling voltage V. in =10nV.

[0152] In step 803, a bias voltage difference is applied between the first metal region and the second metal region. This bias voltage difference is smaller than the first and second bias voltages applied in step 801. The bias voltage difference is greater than the tunneling coupling voltage. Typically, the bias voltage difference is a few millivolts. The bias voltage difference is chosen such that when the selected bias voltage difference exists between the first and second metal regions and a high-frequency signal is applied to the first metal region, if the qubit is in the first state, electrons will tunnel back and forth between the first and second quantum dots, resulting in a high-capacitance state. Alternatively, if the qubit is in the second state, the tunneling effect will be greatly suppressed, resulting in a low-capacitance state.

[0153] In step 804, a probe connected to either the first or second metal region is used to measure the power transfer through the LC resonator circuit. If the qubit is in the first state, the resonant frequency will match the frequency of the high-frequency signal, and the power transfer will be high. If the qubit is in the second state, the power transfer will be low. The reflected power transfer S can be measured using a probe connected to the first metal region. 11 Alternatively, a probe connected to the second metal region can be used to measure the forward power transfer S. 21 .

[0154] In this example, a vector network analyzer is used to measure power transfer. In an alternative example, a high-frequency voltage source and a power sensor can be used to measure power transfer. For example, the power sensor could be a diode.

[0155] In an alternative example, the high-frequency signal in step 802 corresponds to the resonant frequency of the second state of the qubit. In this example, if the qubit is in the first state, the resonant frequency of the circuit will not match the frequency of the high-frequency signal, and power transfer will be low. If the qubit is in the second state, power transfer will be high.

[0156] Figure 9This is a circuit diagram illustrating a quantum device according to an embodiment of the present invention. The device is represented by the dashed area A. A first metal region provides a first inductor L1 with a first inductance in an LC resonator circuit. A second metal region provides a second inductor L2 with a second inductance in an LC resonator circuit. The first inductor L1 and the second inductor L2 are connected in series with a dual quantum dot, which provides a first capacitor C1 in the LC resonator circuit. Note that the capacitance of the dual quantum dot varies depending on the state of the qubits.

[0157] The circuit diagram also shows off-chip sensing electronics. Additional components can be used to design the circuit to tune its operating frequency. Second capacitor C2 and third capacitor C3 represent the parasitic capacitances of the off-chip sensing electronics. Second capacitor C2 and third capacitor C3 represent the total parasitic capacitance, and in this example, the capacitance of each of second capacitor C2 and third capacitor C3 is approximately 200 nanofarads. In an alternative example, the capacitance of second capacitor C2 may differ from the capacitance of third capacitor C3.

[0158] The fourth capacitor C4 and the fifth capacitor C5 represent decoupling capacitors. In this example, the capacitance of each of the fourth capacitor C4 and the fifth capacitor C5 is approximately 0.25 picofarads. The decoupling capacitors allow for maximum power transfer to the device, which provides maximum sensitivity for the measurement of the qubit state. The fourth capacitor C4 and the fifth capacitor C5 can be used to tune the maximum power transfer through the circuit at resonance.

[0159] The circuit may further include a first bias tee and a second bias tee (not shown), which can be used to cancel the DC bias voltage of the first and second metal regions, thereby placing the device at the qubit operating point. Each of the bias tee may include a large resistor with a resistance greater than 1 megohm and may be located between the decoupling capacitor and the device.

[0160] Figure 9 The resonant frequency of the circuit shown depends on the first and second inductors, as well as the first, second, third, fourth, and fifth capacitors. Maximum power transfer occurs at the circuit's resonant frequency. Figure 10A and 10B The forward power transfer S is shown as a function of the frequency of the two values ​​of the first capacitor. 21 The circuit response has been simulated.

[0161] Figure 10A The forward power transfer at the first capacitor of 10 nanofarads is shown. Using these input values, the resonant frequency of the circuit is expected to be approximately 5.15 GHz. At a second value of 5 nanofarads for the first capacitor, the resonant frequency of the circuit is expected to be approximately 7.20 GHz, as...Figure 10B As shown in the image.

[0162] Figure 11A and 11B A schematic plan view of a quantum device according to an embodiment of the present invention is shown. Each device includes a source electrode 1002 and a drain electrode 1003 electrically connected to an external power source. The device may include a high-frequency multiplexer to reduce the number of high-frequency sources and detectors required to read out the state of multiple qubits.

[0163] The device architecture shown illustrates a nanowire 1001 with multiple qubit unit cells 1021-1024 and 1041-1043. Figure 11A and 11B The highly doped region 1004 and the undoped region 1005 are schematically shown. Figure 11A The four-qubit unit cell 1021-1024 is shown; Figure 11B Three qubit unit cells 1041-1043 are shown. For reference, Figure 4B and Figure 6 A similar device with a single qubit cell is shown.

[0164] exist Figure 11A In this example, the nanowire is a silicon-germanium (SiGe) nanowire. In an alternative example, the nanowire is an indium arsenide (InAs) nanowire. Each qubit cell 1021-1024 includes two metal regions 1011-1018 located on opposite sides of the SiGe nanowire 1001. An undoped region 1005 of the nanowire 1001 extends below the metal regions 1011-1018 to the edge of the nanowire 1001, which are electrically separated from the nanowire 1001 by a thin dielectric layer (not shown). The first qubit cell 1021 includes a first metal region 1011 and a second metal region 1012. The second qubit cell 1022 includes a third metal region 1013 and a fourth metal region 1014. The third qubit cell 1023 includes a fifth metal region 1015 and a sixth metal region 1016. The fourth qubit cell 1024 includes a seventh metal region 1017 and an eighth metal region 1018. In alternative examples, the device includes additional qubit cells, or fewer qubit cells. The spacing between the source electrode 1002 and the drain electrode 1003 can be modified according to the number of qubit unit cells. Each metal region 1011-1018 is electrically connected to the gate electrode (not shown). Metal regions 1011-1018 provide the only inductor in the device. There is no external inductor.

[0165] In this example, each of the qubit cells has substantially the same geometry and therefore similar electronic properties. For example, each of the metallic regions 1011-1018 has substantially the same length and therefore substantially the same inductance. Therefore, the resonant frequencies of each qubit cell 1021-1024 will be similar. The state of each qubit can be measured or inferred by performing sequential measurements on the qubits in the first qubit cell 1021, the second qubit cell 1022, the third qubit cell 1023, and the fourth qubit cell 1024.

[0166] Furthermore, the spacing between each pair of metal regions (i.e., the first metal region 1011 and the second metal region 1012; the third metal region 1013 and the fourth metal region 1014; the fifth metal region 1015 and the sixth metal region 1016; and the seventh metal region 1017 and the eighth metal region 1018) is essentially the same. Therefore, considering the variations caused by device defects, the dual quantum dot qubits induced in each quantum dot cell 1021-1024 will have similar electronic properties. Device defects can arise from, for example, material defects or process irregularities.

[0167] Quantum bit cells 1021-1024 are separated along the longitudinal axis of nanowire 1001. The third and fourth metal regions are laterally separated from the first and second metal regions along the longitudinal axis of the nanowire. This lateral separation between each of the adjacent metal regions ensures no overlap. In this example, the spacing between the qubit cells is substantially the same. For example, the spacing between the first metal region 1011 in the first qubit cell 1021 and the third metal region 1013 in the second qubit cell 1022 is between 10 nanometers and 100 nanometers.

[0168] In alternative examples, the spacing between adjacent qubit cells can be different. For example, the spacing between the first metal region 1011 and the third metal region 1013 can be greater than the spacing between the third metal region 1013 and the fifth metal region 1015. However, the arrangement of the metal regions along the nanowire is substantially symmetrical, so the spacing between the first metal region 1011 and the third metal region 1013 is the same as the spacing between the second metal region 1012 and the fourth metal region 1014, allowing for fabrication tolerances.

[0169] exist Figure 11BIn this design, nanowire 1001 comprises silicon. A first qubit cell 1041 includes a first metal region 1031 and a second metal region 1032; a second qubit cell 1042 includes a third metal region 1033 and a fourth metal region 1034; and a third qubit cell 1043 includes a fifth metal region 1035 and a sixth metal region 1036. In alternative examples, the device includes additional qubit cells or fewer qubit cells. Each metal region 1031-1036 is electrically connected to a gate electrode (not shown). Metal regions 1031-1036 are the only inductors in the device's LC resonator circuit. An undoped region 1005 of nanowire 1001 extends below metal regions 1031-1036 to the edge of nanowire 1001, which are electrically separated from nanowire 1001 by a thin dielectric layer (not shown).

[0170] In this example, the spacing between pairs of metal regions within each qubit cell 1041 to 1043 is substantially the same, and the spacing between adjacent metal regions along the two edges of the nanowire is also substantially the same, as regarding Figure 11A As described. However, in Figure 11B In the device shown, each qubit cell 1041-1043 has a different resonant frequency due to the different extensions of metal regions 1031-1036. In this example, each pair of metal regions extends by approximately the same distance. This facilitates the manufacturing process and simplifies data extraction. In this example, the first metal region 1031 and the second metal region 1032 extend the least. The third metal region 1033 and the fourth metal region 1034 extend slightly more than the first metal region 1031 and the second metal region 1032. The fifth metal region 1035 and the sixth metal region 1036 extend the farthest. Therefore, the inductance of each of the first metal region 1031 and the second metal region 1032 is less than the inductance of each of the third metal region 1033 and the fourth metal region 1034, and the inductance of each of the fifth metal region 1035 and the sixth metal region 1036 is the largest.

[0171] In an alternative example, the second metal region 1032, the fourth metal region 1034, and the sixth metal region 1036 can be extended by substantially the same amount, and only the first metal region 1031, the third metal region 1033, and the fifth metal region 1035 have different extensions. In this arrangement, the total inductance per qubit cell is still modified.

[0172] In another example, only the first metal region 1031, the third metal region 1033, and the fifth metal region 1035 provide a unique inductor in their corresponding qubit cells 1041, 1042, and 1043. The second metal region 1032, the fourth metal region 1034, and the sixth metal region 1036 may comprise polysilicon and are of any size; their size does not affect the inductance of the LC resonator circuit. Similarly, the first metal region 1031, the third metal region 1033, and the fifth metal region 1035 may extend by different distances to achieve inductance variations between LC resonator circuits.

[0173] Due to the different inductances and therefore different resonant frequencies of the first, second, and third qubit cells 1041 to 1043, frequency domain multiplexing can be used to measure or infer the state of each qubit.

[0174] Figure 8 A method for qubit measurement or readout of a device having a single qubit cell is described. For devices having multiple qubit cells, time-domain and / or frequency-domain multiplexing can be used to measure or infer the state of the qubits in each qubit cell.

[0175] For example, time-domain multiplexing methods can be used for measurement. Figure 11A The state of each qubit in the device shown is illustrated. In this example, a high-frequency signal is applied to a first metal region, and the state of the qubit in the first qubit cell is subsequently measured or inferred at a second metal region. Then, a high-frequency signal is applied to a third metal region, and the state of the qubit in the second qubit cell is measured or inferred at a fourth metal region.

[0176] for Figure 11B The device shown can be used to measure the state of each qubit using frequency domain multiplexing. In this example, the state of each qubit can be measured or inferred simultaneously.

[0177] In alternative examples, a combination of time-domain and frequency-domain multiplexing methods can be employed. For instance, the device may include some qubit cells of the same size and some qubit cells of different sizes. The specific implementation of the device and method used will depend on the desired device characteristics and any practical constraints such as geometry. For example, a device with twenty qubit cells may not be suitable for having twenty different extensions because the inductance of the smallest metal region may be lower than desired, and the size of the largest metal region may result in large parasitic capacitances and / or geometric constraints.

[0178] As will be appreciated, a quantum device having an LC resonator circuit for performing qubit measurements or readouts, a method for performing qubit measurements or readouts using the device, and a method for assembling the device are disclosed. The LC resonator circuit in the device includes a capacitor and an inductor. The inductor is provided by a metallic region comprising a material having high dynamic inductance. The metallic region is also suitable for inducing quantum dots that can be used to confine one or more electrons. Two adjacent metallic regions can be used to induce the formation of a dual quantum dot having two states of qubits. The capacitor in the LC resonator circuit is provided by a dual quantum dot qubit whose capacitance varies depending on the state of the qubit. The resonant frequency of the LC resonator circuit depends on the capacitance. Power transfer through the LC resonator circuit is frequency-dependent and is maximum at the resonant frequency of the circuit. The state of the qubit affects the capacitance, which in turn affects the resonant frequency. Therefore, a measurement of power transfer at the resonant frequency of the circuit can be used to infer the state of the qubit. The dual function of the first metal region (i.e., inducing quantum dots and providing an inductor in an LC resonator), together with the use of a material with high dynamic inductance to form the first metal region, produces a compact device with quantum bit readout capability.

Claims

1. A quantum device having an LC resonator circuit for performing qubit measurement or readout, the device comprising: Semiconductor layer; A dielectric layer is disposed on the semiconductor layer and forms a functional interface with the semiconductor layer; A first metallic region is disposed on the dielectric layer; as well as A second metal region is disposed on the dielectric layer and is laterally separated from the first metal region; The first metal region and the second metal region are arranged to be electrically connected, such that a dual quantum dot having a first state and a second state can be induced to form at the functional interface below the first metal region and the second metal region. The dual quantum dots provide a capacitor in the LC resonator circuit, and the capacitance of the dual quantum dots depends on the state of the quantum bits. Wherein, the first metal region provides an inductor in the LC resonator circuit; and The resonant frequency of the LC resonator circuit depends on the state of the qubit, making it possible to measure or infer the state of the qubit.

2. The quantum device according to claim 1, wherein, The first metallic region includes a superconductor.

3. The quantum device according to any one of the preceding claims further comprises: The power supply is configured to supply power at a frequency corresponding to the resonant frequency of the LC resonator circuit. as well as A probe, connected to the first metal region and / or the second metal region, is configured to measure the power transfer through the LC resonator circuit to infer the state of the qubit.

4. The quantum device according to claim 1 or 2, wherein, The first metal region provides a first inductor in the LC resonator circuit, and the second metal region provides a second inductor in the LC resonator circuit.

5. The quantum device according to claim 1 or 2 further includes a masking layer covering the first metal region.

6. The quantum device according to claim 1, wherein, The semiconductor layer includes a nanowire, wherein a first metal region and a second metal region are disposed on opposite sides of the nanowire such that each of the first metal region and the second metal region partially overlaps with an edge of the nanowire and includes a corresponding portion extending away from the nanowire.

7. The quantum device according to claim 6, further comprising: The third and fourth metal regions are disposed on the dielectric layer; The third metal region and the fourth metal region are disposed on opposite sides of the nanowire, such that each of the third metal region and the fourth metal region partially overlaps with an edge of the nanowire and includes a corresponding portion extending away from the nanowire. The third metal region and the fourth metal region are laterally separated from the first metal region and the second metal region along the longitudinal axis of the nanowire; The first metal region and the second metal region are arranged to be electrically connected, such that a first dual quantum dot can be induced at the functional interface below the first metal region and the second metal region; and The third metal region and the fourth metal region are arranged to be electrically connected, such that a second dual quantum dot can be induced at the functional interface below the third metal region and the fourth metal region.

8. The quantum device according to claim 7, wherein, The inductance of each of the third and fourth metal regions is greater than the inductance of each of the first and second metal regions.

9. The quantum device according to claim 1 or 2, wherein, The semiconductor layer includes nanowires, wherein the first metal region and the second metal region are laterally separated along the longitudinal axis of the nanowires.

10. The quantum device according to claim 1 or 2, wherein, The dielectric layer includes a thin region and a thick region, wherein the functional interface is formed between the semiconductor layer and the thin region of the dielectric layer.

11. A method for performing qubit measurement or readout using the device according to any one of claims 1 to 10, comprising: A first bias potential and a second bias potential are applied to a first metal region and a second metal region respectively to induce a dual quantum dot, and a quantum bit with a first state and a second state is formed below the first metal region and the second metal region at the functional interface, wherein the first bias potential and the second bias potential are substantially the same. A signal is applied to the first metal region at a selected frequency; Apply a bias voltage difference between the first metal region and the second metal region; and The power transfer at the first metal region or the second metal region is measured, wherein the measurement is used to measure or infer the state of the qubit.

12. The method according to claim 11, wherein, The selected frequency is the resonant frequency of the circuit when the capacitance of the dual quantum dots is at its maximum.

13. The method according to claim 11, wherein, The method is performed at a temperature below 20 Kelvin.

14. A method for assembling a quantum device according to any one of claims 1-10, comprising: A dielectric layer is disposed on a semiconductor layer to form a functional interface; A first metal region is formed on the dielectric layer; as well as A second metal region is disposed on the dielectric layer, and the second metal region is laterally separated from the first metal region. The first metal region and the second metal region are configured to be electrically connected, such that a dual quantum dot having a first state and a second state can be induced to form at the functional interface below the first metal region and the second metal region. The dual quantum dots provide a capacitor in the LC resonator circuit, and the capacitance of the dual quantum dots depends on the state of the quantum bits. Wherein, the first metal region provides an inductor in the LC resonator circuit; and The resonant frequency of the LC resonator circuit depends on the state of the qubit, making it possible to measure or infer the state of the qubit.

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