Gain adaptive reference voltage generation circuit, method, and image sensor

Abstract

This invention provides a gain-adaptive reference voltage generation circuit, including a gain logic circuit, a current mapping circuit, and a resistor array. The gain logic circuit processes a gain control signal from a signal processing path into a current selection signal. The current mapping circuit is electrically connected to the gain logic circuit. The resistor array is also electrically connected to the current mapping circuit. The current mapping circuit adjusts the magnitude of the current selection signal input to the resistor array using the current selection signal sent by the gain logic circuit. The current selection signal then generates a gain-adaptive reference voltage through the resistor array. The reference voltage generation circuit provided by this invention has a gain-adaptive function and can be applied to diagnostic methods to generate a gain-adaptive given voltage.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and more specifically, to a gain-adaptive reference voltage generation circuit, method, and image sensor. Background Technology

[0002] Generally, to avoid unreasonable risks caused by electrical system malfunctions, automotive electronic products must meet the requirements of the ISO 26262 international standard. For automotive image sensor chips, real-time diagnosis of the signal processing path's operating status is crucial for reducing functional safety risks, as anomalies in the signal processing path almost always lead to image anomalies, creating functional safety risks. According to circuit theory, one diagnostic method for signal processing paths covering the entire circuit chain involves processing a given voltage and comparing the output value with the expected value. However, existing voltage diagnostic methods suffer from the problem that the given voltage cannot be effectively controlled, adjusted, or synchronously switched during signal processing path gain switching. This leads to the failure of electrical signal comparison in the circuit structure, significantly reducing the applicability and versatility of the voltage diagnostic method, and causing poor electrical control functions in electrical products. Summary of the Invention

[0003] In view of the above problems, the present invention provides a gain-adaptive reference voltage generation circuit and an image sensor applied thereto, which can effectively solve the problem of comparison failure caused by the inability to switch voltages synchronously.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] In a first aspect, the present invention provides a gain-adaptive reference voltage generation circuit, the reference voltage generation circuit comprising:

[0006] Gain logic circuit, which is used to process the gain control signal of the signal processing path into a current selection signal;

[0007] A current mapping circuit, which is electrically connected to the gain logic circuit;

[0008] A resistor array is electrically connected to the current mapping circuit. The current mapping circuit receives the current selection signal sent by the gain logic circuit. After adjusting the magnitude of the current selection signal connected to the resistor array, the current selection signal generates a gain-adaptive reference voltage through the resistor array.

[0009] In one embodiment, the gain control signal of the signal processing path is an external circuit gain control signal or a control signal that controls the reference voltage.

[0010] In one embodiment, the gain logic circuit includes a logic gate structure, which obtains an x-bit binary current selection signal corresponding to a predetermined multiple gain and a binary current inversion signal corresponding to a predetermined multiple gain based on the gain control signal of the signal processing path, wherein x≥1.

[0011] In one embodiment, the x-bit binary current selection signal with a predetermined multiple gain and the binary current inverse selection signal with a predetermined multiple gain control the switching on of the current mapping circuit to select the magnitude of the current selection signal connected to the resistor array. The predetermined multiple gain ranges from 1 to 2. n , where n≥1.

[0012] In one embodiment, the resistor array includes a plurality of taps, with a resistor disposed between two adjacent taps. The plurality of taps are used to acquire a control signal for the reference voltage, and the gain-adaptive reference voltage is the voltage value generated by the first tap furthest from the current mapping circuit.

[0013] In one embodiment, the current mapping circuit includes a subset of more than one current source connected at the plurality of tap positions of the resistor array, and has the ability to adjust the absolute voltage at the plurality of tap positions.

[0014] In one embodiment, the current source subset of the current mapping circuit includes a current mirror structure, the input of which comes from a reference voltage generated by the reference voltage generation circuit.

[0015] In one embodiment, the current source subset of the current mapping circuit includes a first current subset source, a second current subset source, a third current subset source, and a fourth current subset source. The first reference voltage to the m-th reference voltage are respectively connected from the first resistor to the m-th resistor at the plurality of tap positions of the resistor array, where m≥1.

[0016] In one embodiment, the first current subset source is controlled by an x-bit binary current selection signal with a predetermined multiple gain, and the first current subset source is connected to the m-th reference resistor of the resistor array to generate the first reference voltage to the m-th reference voltage.

[0017] In one embodiment, the second current subset source is controlled by an inverse selection signal of the predetermined multiple gain. The second current subset source is connected to a first reference resistor of the resistor array to compensate for the current flowing through the first reference resistor at different gains, so that the current flowing through the first reference resistor at different gains is equal and the same first voltage is maintained.

[0018] In one embodiment, both the first current subset source and the second current subset source include a switch and a reference current source controlled by multiple pixel signals. The switch is used to turn on the reference current source and select different current signals to be connected to the resistor array.

[0019] In one embodiment, the third current subset source is controlled by a reset voltage signal, and the third current subset source is connected to the first voltage terminal of the resistor array, adjusting the absolute voltage of the first reference voltage according to the reset voltage signal.

[0020] In one embodiment, the fourth current subset source is controlled by a pixel voltage signal. The fourth current subset source is connected to a first voltage terminal of the resistor array and compensates for the current changes of several reference voltages of adjacent step sizes on the first resistor according to the pixel voltage signal to maintain the same first reference voltage.

[0021] In one embodiment, the resistor array is a series-parallel combination of resistors with the same unit value.

[0022] In one embodiment, the equivalent resistance values ​​of the series-parallel combinations of the same unit resistors are different multiples.

[0023] Secondly, a gain-adaptive reference voltage generation method is provided, wherein the gain-adaptive reference voltage generation method is applied to the aforementioned gain-adaptive reference voltage generation circuit, the method comprising:

[0024] The gain logic circuit processes the gain control signal of each signal processing path into a current selection signal according to the working state of each signal processing path;

[0025] The current mapping circuit receives the current selection signal, adjusts the magnitude of the current selection signal connected to the resistor array, and generates a reference voltage with adaptive gain through the resistor array.

[0026] The generated first reference voltage to the m-th reference voltage are selected and connected to the input terminals of each signal processing path in a preset order, where m≥1;

[0027] The first reference voltage is quantized;

[0028] Quantize the second reference voltage to the m-th reference voltage respectively;

[0029] Each signal processing path outputs the quantized values ​​of the first reference voltage to the m-th reference voltage;

[0030] The quantized value is compared with the preset value to determine the working status of each signal processing path.

[0031] Thirdly, the present invention provides an image sensor, the image sensor including the above-described gain-adaptive reference voltage generation circuit.

[0032] This invention provides a gain-adaptive reference voltage generation circuit, comprising a gain logic circuit, a current mapping circuit, and a resistor array. The gain logic circuit processes a gain control signal from a signal processing path into a current selection signal. The current mapping circuit is electrically connected to the gain logic circuit. The resistor array is electrically connected to the current mapping circuit. The current mapping circuit adjusts the magnitude of the current selection signal input to the resistor array using the current selection signal sent by the gain logic circuit, and the current selection signal then generates a gain-adaptive reference voltage through the resistor array. The reference voltage generation circuit provided by this invention has a gain-adaptive function and can be applied to voltage diagnostic methods to generate a gain-adaptive given voltage, preventing damage to electrical products during power use and increasing safety and sensitivity. Furthermore, this invention proposes a technical solution for applying a gain-adaptive reference voltage generation circuit to image sensors, which can be applied to high-accuracy voltage diagnostic methods to generate a gain-adaptive given voltage. It should be noted that the gain-adaptive reference voltage generation circuit described in this invention is not limited to the above application scenarios or specific electrical products and has strong versatility.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of the present invention.

[0035] Figure 1 This is a block diagram of the gain-adaptive reference voltage generation circuit provided in Embodiment 1 of the present invention;

[0036] Figure 2 This is a schematic circuit diagram of the gain-adaptive reference voltage generation circuit provided in Embodiment 1 of the present invention;

[0037] Figure 3 This is a schematic circuit diagram of the current mapping circuit of the current mirror provided in Embodiment 1 of the present invention;

[0038] Figure 4 This is a flowchart of the gain-adaptive reference voltage generation method provided in Embodiment 1 of the present invention. Detailed Implementation

[0039] The embodiments of the present invention are described in detail below, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0040] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0042] Example 1

[0043] Please also refer to Figure 1 , Figure 2 and Figure 3 , Figure 1 This is a block diagram of the gain-adaptive reference voltage generation circuit (hereinafter referred to as the "reference voltage generation circuit") provided in Embodiment 1 of the present invention. Figure 2 This is a schematic circuit diagram of the gain-adaptive reference voltage generation circuit provided in Embodiment 1 of the present invention. Figure 3 This is a schematic circuit diagram of the current mapping circuit (hereinafter referred to as "current mapping circuit") of the current mirror provided in Embodiment 1 of the present invention. The reference voltage generation circuit 100 includes a gain logic circuit 110, a current mapping circuit 120, a resistor array 130, and a signal processing path 140.

[0044] Furthermore, the gain logic circuit 110 processes the gain control signal sent by the signal processing path 140 into a current selection signal. The current mapping circuit 120 and the gain logic circuit 110 are electrically connected to the resistor array 130, and the gain logic circuit 110 is electrically connected to the signal processing path 140. The current mapping circuit 120 receives the current selection signal sent by the gain logic circuit 110, adjusts and / or controls the magnitude of the current selection signal flowing through the resistor array 130, and the current selection signal generates a gain-adaptive reference voltage through the resistor array 130. The reference voltage generation circuit 100 provided by this invention has a gain-adaptive function and can be applied to the voltage diagnostic function of electrical products to generate a gain-adaptive given voltage to prevent damage to electrical products during power use and increase electrical safety. For example, the gain logic circuit 110 can be a central processing unit (CPU), including multiple pins, each pin used to receive and generate electrical signals. For example, the central controller receives input signals from external circuits, and then filters, amplifies, or compares the input signals to convert them into control signals.

[0045] In one embodiment, the gain control signal of the signal processing path 140 is either an external circuit gain control signal or a control signal generated by a control reference voltage. In other words, the external circuit gain control signal is controlled by the gain control signal of the signal processing path 140, and the gain control signal of the signal processing path 140 can control the reference voltage generated by the reference voltage to achieve gain adaptation. The gain logic circuit 110 includes a logic gate structure, which obtains an x-bit binary current selection signal sel corresponding to a predetermined multiple gain based on the gain control signal of the signal processing path 140. <x:0>and the inverse selection signal selb with the predetermined multiple gain <x:0>The preset multiplier range is 1-2. n Where n≥1. Furthermore, the gain control signal of signal processing path 140 is processed by gain logic circuit 110 to obtain an x-bit binary current selection signal sel corresponding to a predetermined multiple gain. <x:0>The x-bit binary current selection signal sel with a predetermined gain. <x:0>and the binary current inversion signal selb with a predetermined multiple gain <x:0>The switching state of the current mapping circuit 120 is controlled (e.g., for a MOSFET electronic component, a circuit is formed when its Vgs exceeds the on-state voltage) to select the magnitude of the current selection signal connected to the resistor array 130. The current selection signal can generate a gain-adaptive reference voltage through different connection methods of multiple resistors in the resistor array 130. The current mapping circuit 120 includes a current mirror structure 121. The current mapping circuit 120 includes more than one current source subset (e.g., a first current subset source block 1, a second current subset source block 2, a third current subset source block 3, and a fourth current subset source block 4). The resistor array 130 includes multiple taps, with one or more resistors disposed between two adjacent taps. The taps are used to acquire one or more reference voltage signals. The gain-adaptive reference voltage is the voltage value generated by the first tap furthest from the current mapping circuit 120. Connected at multiple tap positions of the resistor array 130, it has the ability to adjust the absolute voltage at multiple tap positions. It is understood that in this embodiment, absolute voltage refers to the absolute value of the voltage, effectively increasing the accuracy of the control electrical data.

[0046] In one embodiment, the resistor array 130 can obtain multiple reference voltage signals (e.g., Vrst, Vsig1, Vsig2…Vsigm) through multiple tap positions. The gain-adaptive reference voltage is the voltage value at the first tap position (e.g., Vrst), and the reference voltage is the voltage difference of more than one resistor between any two tap positions (e.g., Rrst, R1, R2…Rm). The reference voltage generation circuit 100 provided by this invention has a gain-adaptive function and can be applied to circuit system diagnostic methods to generate a gain-adaptive given voltage to prevent damage when the electrical conditions are unstable during power-on, thereby increasing safety and stability. In addition, this invention proposes a gain-adaptive reference voltage generation circuit that can be applied to electrical diagnostic methods to generate a gain-adaptive given voltage and a relatively stable current output. This function is not limited to the above application scenarios and has strong versatility in electronic products.

[0047] Please refer to it again. Figure 1-3 In one embodiment, the gain logic circuit 110, current mapping circuit 120, resistor array 130, and signal processing circuit 140 can be applied to an image sensor (not shown). During a specific time period of quantization by the image sensor, the generated first reference voltage (Vrst) to the m-th reference voltage (Vsigm), where m>=1 (e.g., the overall reference voltages are Vrst, Vsig1, Vsig2…Vsigm), are connected to the input terminals of each signal processing path in a preset order. During the time period of the quantization reset signal of the reference voltage generation circuit 100, the first reference voltage is quantized (Vrst). Furthermore, during the time period of quantizing the pixel signal, the second reference voltage to the m-th reference voltage (e.g., Vsig1…Vsigm) are quantized according to the different connections of each signal processing path. Alternatively, the first reference voltage (Vrst) can be quantized again to increase the accuracy of the detection voltage and enhance the accuracy of the reproducible experimental data. Each signal processing path 140 outputs quantized values ​​from the first reference voltage to the m-th reference voltage. The quantized values ​​are compared with preset values ​​to determine the operating state of each signal processing path. The gain logic circuit 110 processes the gain control signals of each signal processing path 140 into adjustable current selection signals according to the operating state of each signal processing path 140, thereby increasing applicability.

[0048] In one embodiment, the gain logic circuit 110 obtains an x-bit binary current selection signal sel corresponding to a predetermined multiple gain based on the gain control signals of each signal processing path 140. <x:0>and the inverse selection signal selb with the predetermined multiple gain <x:0>For example, the current mapping circuit 120 includes a first current subset source block 1, a second current subset source block 2, a third current subset source block 3, and a fourth current subset source block 4, wherein the first reference voltage (Vrst) to the m-th reference voltage (Vsigm) are respectively connected from the first resistor (Rrst) to the m-th resistor (Rm) (m>=3) at multiple tap positions of the resistor array 130 (e.g., connected from intermediate nodes). The first current subset source block 1, the second current subset source block 2, the third current subset source block 3, and the fourth current subset source block 4 include a current mirror structure 121, the input of which comes from a gain-adaptive reference voltage generated by the reference voltage generation circuit 100.

[0049] In one embodiment, the first current subset source block1 is subject to an x-bit binary current selection signal sel with a predetermined multiple gain. <x:0>Controlled, the first current subset source block1 is connected to the m-th reference resistor (m>=1) of the resistor array 130 to generate the first reference voltage (Vrst) to the m-th reference voltage (Vsigm) (m>=1). The second current subset source block2 is controlled by the inverse selection signal selb with a predetermined multiple gain. <x:0>The control is that the second current subset source block2 is connected to the first reference resistor (Rrst) of the resistor array 130 to compensate for the current flowing through the first reference resistor (Rrst) at different gains, so that the current flowing through the first reference resistor (Rrst) at each gain is equal and the same first reference voltage (Vrst) is maintained.

[0050] In one embodiment, the first current subset source block1 and the second current subset source block2 include multiple pixel voltage signals sig <s:0>The control switch (s>=0) is used to turn on the reference current source of the current mirror and select different current signals to be connected to the resistor array 130. The first current subset source block1 and the second current subset source block2 have the same number of switches. The first current subset source block1 is subjected to an x-bit binary current selection signal sel. <x:0>Controlled, the second current subset source block2 is subjected to the binary current inversion signal selb. <x:0>Control. The third current subset source, block3, is controlled by the reset voltage signal rst. <x:0>Control: The third current subset source block3 is connected to the first voltage terminal (Vrst) of the resistor array 130, according to the reset voltage signal rst. <x:0>The absolute voltage of the first reference voltage (Vrst) is adjusted. The third current subset source block3 receives the reset voltage signal rst. <x:0>Control, number of switches and reset signal rst <x:0>It depends on the number of bits, for example, the reset voltage signal rst <x:0>If the number of bits is N bits, then there are N switches in block 3, and so on. It can be understood that in this embodiment, the absolute voltage of the first reference voltage (Vrst) refers to the absolute value of the first reference voltage (Vrst).

[0051] In one embodiment, the fourth current subset source block4 is affected by the pixel voltage signal sig. <s:0>Control, the fourth current subset source block4 is connected to the first reference voltage (Vrst) of the resistor array 130, according to the pixel voltage signal sig <s:0>The current variation across the first resistor (Rrst) is compensated to maintain the same first reference voltage (Vrst). The fourth current subset source, block4, is fed by the pixel voltage signal sig. <s:0>Control, number of switches and pixel voltage signal sig <s:0>It is related to the number of bits, for example, the pixel voltage signal sig. <s:0>If the number of bits is N bits, then the fourth current subset source block4 has N switches, and so on. The first resistor (Rrst) to the m-th resistor (Rsigm) of the resistor array 130 are series-parallel combinations of resistors with the same unit resistance (for example, series connection increases the total resistance, while parallel connection decreases the total resistance). The equivalent resistance values ​​of the series-parallel combinations of resistors with the same unit resistance are different multiples. The first resistor (Rrst) to the m-th resistor (Rsigm) of the resistor array 130 have the same unit resistance. The reference current generation circuit generates the current from the bandgap reference voltage applied to the resistor. The unit resistance of the reference current generation circuit from the bandgap reference voltage applied to the resistor is consistent with the unit voltage of the resistor array 130, which has the ability to resist PVT (process voltage temperature) fluctuations. The present invention also provides an image sensor, which includes the above-described gain-adaptive reference voltage generation circuit 100. The self-diagnostic function of an image sensor for multiple signal processing paths aims to detect when a signal from a particular path exceeds the expected range, indicating an abnormality in its operation. This function reports the issue to an external chip via changes to the pull-up or pull-down state of a specific external chip pin (e.g., voltage adjustment). The image sensor can be configured to perform self-diagnostics on multiple signal processing paths every frame or at startup, effectively increasing electrical safety.

[0052] Please also refer to Figures 1-4 , Figure 4 This is a flowchart of the gain-adaptive reference voltage generation method provided in Embodiment 1 of the present invention.

[0053] A gain-adaptive reference voltage generation method, wherein the gain-adaptive reference voltage generation method is applied to the aforementioned gain-adaptive reference voltage generation circuit, the method comprising:

[0054] S410, The gain logic circuit processes the gain control signal of each signal processing path into a current selection signal according to the working state of each signal processing path;

[0055] S420, The current mapping circuit receives the current selection signal, adjusts the magnitude of the current selection signal connected to the resistor array, and generates a reference voltage with adaptive gain through the resistor array;

[0056] S430. Select the generated first reference voltage to the m-th reference voltage and connect them to the input terminals of each signal processing path in a preset order, where m≥1;

[0057] S440. Quantize the first reference voltage;

[0058] S450, quantize the second reference voltage to the m-th reference voltage respectively;

[0059] S460, Each signal processing path outputs the quantized values ​​of the first reference voltage to the m-th reference voltage respectively;

[0060] S470. Compare the quantized value with the preset value to determine the working status of each signal processing path.

[0061] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention have been clearly and completely described above with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0062] Therefore, the above detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

Claims

1. A gain-adaptive reference voltage generation circuit, characterized in that, The reference voltage generation circuit includes: Gain logic circuit, which is used to process the gain control signal of the signal processing path into a current selection signal; A current mapping circuit, which is electrically connected to the gain logic circuit; A resistor array is electrically connected to the current mapping circuit. The current mapping circuit receives the current selection signal sent by the gain logic circuit. After adjusting the magnitude of the current selection signal connected to the resistor array, the current selection signal generates a gain-adaptive reference voltage through the resistor array. The current selection signal includes an x-bit binary current selection signal with a predetermined multiple gain, and the gain logic circuit also outputs a binary current inverse selection signal with a predetermined multiple gain according to the gain control signal of the signal processing path. The current mapping circuit includes a subset of current sources with more than one current source, and the subset of current sources includes a first current source and a second current source. The first current subset source is controlled by the x-bit binary current selection signal with the predetermined multiple gain. The first current subset source is connected to the m-th reference resistor of the resistor array to generate the first reference voltage to the m-th reference voltage, where m≥1. The second current subset source is controlled by the binary current inversion signal of the predetermined multiple gain. The second current subset source is connected to the first reference resistor of the resistor array to compensate for the current flowing through the first reference resistor at different gains, so that the current flowing through the first reference resistor at different gains is equal and the same first reference voltage is maintained.

2. The voltage generating circuit according to claim 1, characterized in that, The gain control signal of the signal processing path is either an external circuit gain control signal or a control signal generated by controlling the reference voltage.

3. The voltage generating circuit according to claim 1, characterized in that, The gain logic circuit includes a logic gate structure, and the x-bit binary current selection signal with a predetermined multiple gain and the binary current inversion signal with the predetermined multiple gain are output by the logic gate structure, wherein x≥1.

4. The voltage generating circuit according to claim 3, characterized in that, The x-bit binary current selection signal with a predetermined gain and the binary current inversion signal with a predetermined gain control the switching on of the current mapping circuit to select the magnitude of the current selection signal connected to the resistor array. The predetermined gain ranges from 1 to 2. n , where n≥1.

5. The voltage generating circuit according to claim 3, characterized in that, The resistor array includes multiple taps, with a resistor disposed between two adjacent taps. The multiple taps are used to obtain a control signal for the reference voltage. The gain-adaptive reference voltage is the voltage value generated by the first tap furthest from the current mapping circuit.

6. The voltage generating circuit according to claim 5, characterized in that, The current source subset of the current mapping circuit is connected at the plurality of tap positions of the resistor array, and has the ability to adjust the absolute voltage at the plurality of tap positions.

7. The voltage generating circuit according to claim 6, characterized in that, The current source subset of the current mapping circuit includes a current mirror structure, the input of which comes from the reference voltage generated by the reference voltage generation circuit.

8. The voltage generating circuit according to claim 6, characterized in that, The current source subset of the current mapping circuit further includes a third current subset source and a fourth current subset source, wherein the first reference voltage to the m-th reference voltage are respectively connected from the first resistor to the m-th resistor at the plurality of tap positions of the resistor array.

9. The voltage generating circuit according to claim 8, characterized in that, Both the first current subset source and the second current subset source include a switch and a reference current source controlled by multiple pixel signals. The switch is used to turn on the reference current source and select different current selection signals to be connected to the resistor array.

10. The voltage generating circuit according to claim 8, characterized in that, The third current subset source is controlled by a reset voltage signal. The third current subset source is connected to the first voltage terminal of the resistor array and adjusts the absolute voltage of the first reference voltage according to the reset voltage signal.

11. The voltage generating circuit according to claim 8, characterized in that, The fourth current subset source is controlled by the pixel voltage signal. The fourth current subset source is connected to the first voltage terminal of the resistor array. It compensates for the current changes of several reference voltages of adjacent step sizes on the first resistor according to the pixel voltage signal to maintain the same first reference voltage.

12. The voltage generating circuit according to claim 1, characterized in that, The resistor array is a series-parallel combination of resistors with the same unit value.

13. The voltage generating circuit according to claim 12, characterized in that, The equivalent resistance values ​​of the series and parallel combinations of the same unit resistors are different multiples.

14. A gain-adaptive reference voltage generation method, characterized in that, The gain-adaptive reference voltage generation method is applied to the gain-adaptive reference voltage generation circuit as described in any one of claims 1-13, the method comprising: The gain logic circuit processes the gain control signal of each signal processing path into a current selection signal according to the working state of each signal processing path; The current mapping circuit receives the current selection signal, adjusts the magnitude of the current selection signal connected to the resistor array, and generates a reference voltage with adaptive gain through the resistor array. The generated first reference voltage to the m-th reference voltage are selected and connected to the input terminals of each signal processing path in a preset order, where m≥1; The first reference voltage is quantized; Quantize the second reference voltage to the m-th reference voltage respectively; Each signal processing path outputs the quantized values ​​of the first reference voltage to the m-th reference voltage; The quantized value is compared with the preset value to determine the working status of each signal processing path.

15. An image sensor, characterized in that, The image sensor includes a gain-adaptive reference voltage generation circuit as described in any one of claims 1-13.

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