Data processing method and encoding circuit

Abstract

The disclosure provides a data processing method and an encoding circuit, which can be applied to the technical field of time measurement, the technical field of computers and other technical fields. The method comprises the following steps: grouping a plurality of data in an original data sequence to obtain a plurality of target subsequences; inputting each target subsequence into a lookup table array set corresponding to the target subsequence respectively to obtain a target value corresponding to each target subsequence, wherein the target value represents the sum of position information of data with adjacent positions and different data values in the target subsequence; and determining a target value of the original data sequence based on the target values corresponding to the plurality of target subsequences respectively.

Description

Technical Field

[0001] The present disclosure relates to the fields of time measurement technology, computer technology, and other technical fields, and in particular to a data processing method and a coding circuit. Background Art

[0002] A time-to-digital converter (TDC) can convert time interval information into a high-resolution digital signal. The tapped delay chain interpolation type TDC is the mainstream type of TDC, offering significant advantages in measurement accuracy and other aspects. In a TDC, the signal to be measured passes through a tapped delay chain, and then, based on a D-type flip-flop sequence, each tap of the tapped delay chain is latched in the system clock cycle. This yields a tapped delay chain data sequence, and the time interval information of the signal to be measured can be determined by the edge position information of the tapped delay chain data sequence.

[0003] In the process of realizing the concept disclosed in the present invention, the inventors found that there are at least the following problems in the related technology: in the scheme for determining the edge change position information of the tap delay chain data sequence, there is a problem that it is difficult to determine the actual edge change position due to "bubbles"; there are high conditional restrictions on the length, pulse width, etc. of the tap delay chain data sequence; and a large number of hardware resources are used, resulting in a long development cycle, increased power consumption and cost. Summary of the Invention

[0004] In view of the above problems, the present disclosure provides a data processing method, apparatus, device, medium program product, and encoding circuit.

[0005] According to one aspect of the present disclosure, a data processing method is provided, comprising: grouping multiple data in an original data sequence to obtain multiple target subsequences; inputting each of the above target subsequences into a lookup table array set corresponding to the above target subsequence to obtain target values ​​corresponding to each of the multiple target subsequences, wherein the above target value represents the sum of position information of data with adjacent positions and different data values ​​in the above target subsequences; and determining the target value of the above original data sequence based on the target values ​​corresponding to each of the multiple target subsequences.

[0006] According to an embodiment of the present disclosure, the grouping of multiple data in the original data sequence to obtain multiple target subsequences includes: determining the number of groups of the original data sequence based on the multiple data in the original data sequence; and grouping the multiple data to obtain multiple target subsequences based on the number of groups and the position identifiers of each of the multiple data in the original data sequence.

[0007] According to an embodiment of the present disclosure, the determining the grouping number of the original data sequence based on the plurality of data in the original data sequence comprises: determining at least one target data group from the plurality of data in the original data sequence, wherein the target data group comprises a plurality of target data which are positionally continuous and have the same data value; determining a target adjacent variable distance based on the target data group, wherein the target adjacent variable distance is a data amount of a target data group comprising the smallest data amount in the at least one target data group; determining a plurality of region information of the variable distance from the plurality of data in the original data sequence; determining a plurality of target regions based on the plurality of region information; determining a target region length based on the region length of each of the plurality of target regions, wherein the target region length represents the maximum region length in the region length of each of the plurality of target regions; and determining the grouping number of the original data sequence based on the target adjacent variable distance and the target region length, wherein the grouping number is less than or equal to the target adjacent variable distance and greater than or equal to the target region length.

[0008] According to an embodiment of the present disclosure, the plurality of lookup table arrays in the lookup table array set comprise a plurality of lookup tables; and the inputting each of the target sub-sequences into the lookup table array set corresponding to the target sub-sequence to obtain the target value corresponding to each of the plurality of target sub-sequences comprises: for each of the target sub-sequences, determining a plurality of sub-sequence fragments from the target sub-sequence based on the number of input ends of the lookup tables in the lookup table array; inputting the plurality of sub-sequence fragments into the corresponding lookup table array to obtain the target value corresponding to each of the plurality of sub-sequence fragments; and obtaining the target value of the target sub-sequence based on the target value corresponding to each of the plurality of sub-sequence fragments.

[0009] According to an embodiment of the present disclosure, in a case where the number of data bits included in the sub-sequence fragment is less than the number of input ends of the lookup table, the target input data of the input end without input data is set as predetermined data.

[0010] According to an embodiment of the present disclosure, the maximum target value of each of the plurality of sub-sequence fragments is determined based on the plurality of sub-sequence fragments of the target sub-sequence; and the number of lookup tables included in the lookup table array corresponding to each of the sub-sequence fragments is determined based on the maximum target value of each of the plurality of sub-sequence fragments.

[0011] According to an embodiment of the present disclosure, the determining the target value of the original data sequence based on the target value corresponding to each of the plurality of target sub-sequences comprises: inputting the target value corresponding to each of the plurality of target sub-sequences into an adder to obtain the target value of the original data sequence.

[0012] According to an embodiment of the present disclosure, the original data sequence comprises a tapped-delay chain data sequence.

[0013] Another aspect of the present disclosure provides an encoding circuit, comprising: a plurality of special logic circuits, configured to convert a target sub-sequence corresponding to each of the special logic circuits into a target value, wherein the target sub-sequence is obtained based on grouping of an original data sequence; and a first adder, connected to the plurality of special logic circuits respectively, configured to add the target values to obtain a target value of the original data sequence.

[0014] According to an embodiment of the present disclosure, the special logic circuit comprises: a lookup table array set, configured to convert a sub-sequence slice corresponding to each of the lookup table arrays in the lookup table array set into a sub-target value, wherein the sub-sequence slice is obtained based on grouping of the target sub-sequence, and the sub-target value is a target value of the sub-sequence slice; and a second adder, connected to the plurality of lookup table arrays respectively, configured to add the sub-target values to obtain a target value of the target sub-sequence.

[0015] Another aspect of the present disclosure provides a data processing apparatus, comprising: a target sub-sequence determination module, configured to group a plurality of data in an original data sequence to obtain a plurality of target sub-sequences; a first target value determination module, configured to input each of the target sub-sequences into a lookup table array set corresponding to the target sub-sequence to obtain a target value corresponding to each of the target sub-sequences, wherein the target value represents a sum of position information of data having adjacent positions and different data values in the target sub-sequence; and a second target value determination module, configured to determine a target value of the original data sequence based on the target values corresponding to the target sub-sequences.

[0016] According to the data processing method provided in the present disclosure, by grouping the plurality of data in the original data sequence, a plurality of target sub-sequences can be obtained, and by inputting the plurality of target sub-sequences into the lookup table array set corresponding to the target sub-sequences respectively, a target value corresponding to each target sub-sequence can be obtained, and based on the target values of the plurality of target sub-sequences, a target value of the tapped delay chain data can be obtained. Since the plurality of data in the original data sequence is grouped to obtain the plurality of target sub-sequences, at most one bubble error is contained in the sub-sequences, and since some sub-sequences do not contain bubble errors, the problem of being difficult to determine the true run position is at least partially solved, and the technical effect of improving the accuracy of determining the run position is achieved. Since each target sub-sequence is input into the lookup table array set corresponding to the target sub-sequence respectively, the plurality of target sub-sequences are processed in parallel, the target value corresponding to each target sub-sequence is quickly obtained, and based on the target values of the plurality of target sub-sequences, the target value of the original data sequence is determined, the problem of high condition limit and more hardware resources used in the related art is at least partially solved, and the technical effects of saving hardware resources, high universality, less condition limit, short encoding time for the original data sequence, and high accuracy of the target value of the original data sequence are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A flowchart of a data processing method according to an embodiment of the present disclosure is schematically shown;

[0019] Figure 2 A schematic diagram of obtaining an original data sequence according to an embodiment of the present disclosure is schematically shown;

[0020] Figure 3 A flowchart of determining a target sub-sequence target value according to an embodiment of the present disclosure is schematically shown;

[0021] Figure 4 A schematic diagram of a lookup table array according to an embodiment of the present disclosure is schematically shown;

[0022] Figure 5 A schematic diagram of a data processing method according to another embodiment of the present disclosure is schematically shown;

[0023] Figure 6 A schematic diagram of an encoding circuit according to an embodiment of the present disclosure is schematically shown;

[0024] Figure 7 A schematic diagram of a special-purpose logic circuit according to an embodiment of the present disclosure is schematically shown;

[0025] Figure 8 A timing diagram according to an embodiment of the present disclosure is schematically shown; and

[0026] Figure 9 A structural block diagram of a data processing apparatus according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely for illustration, and is not intended to limit the scope of the present disclosure. In the following detailed description of embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. However, it would be apparent to those skilled in the art that the embodiments, or portions thereof, can be practiced without such specific details. In other instances, well-known structures and features have been omitted in order to avoid obscuring the concepts of the present disclosure.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "includes" and tautological expressions thereof, such as "including," "includes," "include," "contains," "containing," and so on, mean the stated features, steps, operations and / or components are present, but do not preclude the presence or addition of one or more other features, steps, operations, components, and / or groups thereof.

[0029] All terms used herein (including technical and scientific terms) have the meanings commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings that are consistent with the context of the specification, and should not be interpreted in an idealized or overly formal manner.

[0030] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should be generally interpreted as including one or more of the items enumerated in the list (e.g., "a system having at least one of A, B, and C" should include, but not be limited to, a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc.).

[0031] In the technical solutions of the present disclosure, the collection, storage, use, processing, transmission, provision, disclosure, and application of data (such as including but not limited to user personal information) involved in the technical solutions comply with the relevant legal regulations, necessary security measures are taken, and do not violate public order and good customs.

[0032] During the research, it is found that time-to-digital converter can convert time interval information into high-resolution digital signal, which is widely used in positron emission tomography (PET), light detection and ranging (LiDAR), autonomous driving, time-of-flight imaging, frontier particle physics experiment and space experiment, and has wide application prospects in aerospace, deep space exploration, geological mapping, medical imaging, radar scanning and other fields.

[0033] The tap delay chain interpolation type time-to-digital converter is the mainstream type of time-to-digital converter at present, which adopts the method of combining coarse time and fine time, and has significant advantages in measurement accuracy, measurement dead time and measurement dynamic range. The accuracy of ordinary tap delay chain interpolation type time-to-digital converter is limited by the delay size of the interpolation unit. In order to further improve the accuracy and break through the delay time limit of the single delay unit, some improved delay chain interpolation type time-to-digital converters apply the "Wave Union A" technology, that is, one to-be-measured signal generates or releases one or more periodic narrow pulse sequences in the trigger circuit, and the measurement results obtained by measuring the multiple edges of the narrow pulse sequence are calculated to obtain a measurement accuracy higher than the delay unit.

[0034] In the ordinary delay chain interpolation type time-to-digital converter, the delay chain has only one edge change, and the tap delay chain data sequence latched by the D flip-flop array has a form similar to …11111111100000…, which is a typical thermometer code. The number of "1"s in the thermometer code can be directly added to efficiently convert the thermometer code into binary code, and the "bubble" error in the form of …11111100100000… caused by different clock synchronization of the D flip-flop array can be eliminated.

[0035] However, when there are multiple edge changes in the carry chain, the tap delay chain data sequence has a form similar to …000001111110000000111111110000…, and in actual cases, each edge change also contains "bubble" errors, so that the tap delay chain data sequence becomes similar to …0000010111110100000000000000001011111111110011000000…, wherein the "bubble" error can represent that there is a "1" in multiple "0"s and a "0" in multiple "1"s. The "bubble" error will make the edge information blurred and difficult to extract. Moreover, since "Wave Union A" is used, the method of adding "1" cannot be used to obtain the edge change position.

[0036] In addition, related technologies have proposed a method for finding edge changes by using slice-wise XOR to address this issue. Based on the logic elements in a field programmable gate array (FPGA), the edge change positions are searched one by one in the data segments of the tap delay chain data sequence.

[0037] While this approach solves the basic edge-varying position encoding problem, the sliced ​​XOR structure imposes strict upper and lower limits on pulse width, requiring extensive preliminary testing and being unsuitable for a wide range of FPGA devices. Its logic is complex, consuming significant logic resources, and reducing system integration, increasing power consumption, and increasing costs.

[0038] Based on the above, it can be seen that in the scheme of determining the edge change position information of the tap delay chain data sequence in the related technology, there is a problem that it is difficult to determine the actual edge change position due to "bubbles"; there are high conditional restrictions on the length of the tap delay chain data sequence, pulse width, etc.; and a large number of hardware resources are used, resulting in a long development cycle, increased power consumption and cost. As a result, the delay chain interpolation time-to-digital converter has low universality, and obtaining multiple edge change positions requires consuming a large amount of logic resources and has a complex structure, resulting in a long system development cycle, increased power consumption and cost.

[0039] In view of this, an embodiment of the present disclosure provides a data processing method, including: grouping multiple data in an original data sequence to obtain multiple target subsequences; inputting each target subsequence into a lookup table array set corresponding to the target subsequence to obtain target values ​​corresponding to each of the multiple target subsequences, wherein the target value represents the sum of position information of data at adjacent positions in the target subsequence and with different data values; and determining the target value of the original data sequence based on the target values ​​corresponding to each of the multiple target subsequences.

[0040] Figure 1 The flowchart of the data processing method according to the embodiment of the present disclosure is schematically shown.

[0041] like Figure 1 As shown, the data processing method of the embodiment of the present disclosure includes operations S110 to S130.

[0042] In operation S110 , a plurality of data in an original data sequence is grouped to obtain a plurality of target subsequences.

[0043] According to an embodiment of the present disclosure, the plurality of data included in the original data sequence can be positionally marked, for example, the original delay chain data with a length of m bits can be sequentially marked as the 0th bit, the 1st bit, …, the (m-1)th bit, and then grouped, for example, the original data sequence with a length of m bits is divided into n groups, i.e., the 0th group, the 1st group, …, the (n-1)th group, and each group has a length of m / n bits, counted as l bits.

[0044] According to an embodiment of the present disclosure, when the original data sequence is grouped, the (kn+i)th bit of data can be grouped into the kth bit of the ith group of tap data subsequences, where n is the number of groups, for example, the original data sequence is 0001110010, if the original data sequence is divided into two groups, the first target subsequence is 00101, and the second target subsequence is 01100, the 1st, 3rd, 5th, 7th, and 9th bits of the original data sequence are the first target subsequence, and the 2nd, 4th, 6th, 8th, and 10th bits are the second target subsequence.

[0045] According to an embodiment of the present disclosure, the type of data of the original data sequence is not limited, for example, it can be a tap delay chain data sequence, wherein the tap delay chain data sequence can be obtained through a delay chain composed of a plurality of delay units; the type of delay unit is also not limited, and a suitable delay unit can be selected according to actual needs, for example, CARRY4.

[0046] Figure 2 An illustrative diagram of a delay chain interpolation type time-to-digital converter related to obtaining an original data sequence is shown.

[0047] According to an embodiment of the present disclosure, when the original data sequence is a tap delay chain data sequence, the original data sequence can be obtained in the following manner: a periodic narrow pulse sequence is generated by a trigger circuit from a time signal to be measured, the periodic narrow pulse sequence passes through a tap delay chain composed of a plurality of delay units, and a D flip-flop sequence adopts a system clock period to sample and latch the results of each tap of the tap delay chain, thereby obtaining the original data sequence.

[0048] According to an embodiment of the present disclosure, the tap delay chain data sequence can obtain edge variable position information through an encoding circuit, and the edge variable position information can also be referred to as edge variable edge position information, which is the position information of the rising edge or falling edge in the tap delay chain data sequence or the position information of two adjacent data with different values. According to an embodiment of the present disclosure, by grouping and rearranging the original data sequence, the elimination of “bubble” errors in the tap data subsequences can be achieved, so that the edge variable edge position in each tap data subsequence in the target subsequence is clear and accurate.

[0049] In operation S120, each target sub-sequence is respectively input into a look-up table array set corresponding to the target sub-sequence, to obtain a target value corresponding to each target sub-sequence, wherein the target value represents a sum of position information of data with adjacent positions and different data values in the target sub-sequence.

[0050] According to an embodiment of the present disclosure, each target sub-sequence has a corresponding look-up table (LUT) array set, the LUT array set includes a plurality of LUT arrays, and each LUT array includes a plurality of LUTs.

[0051] According to an embodiment of the present disclosure, the number of input ends of the look-up table is not limited, and different numbers of input ends of the look-up table can be used according to actual conditions.

[0052] According to an embodiment of the present disclosure, positions with adjacent positions and different data values can be referred to as along-along positions, and the target value can represent a sum of along-along position information, that is, a sum of along-along position information, which is obtained from the along-along position information, for example, the along-along position information is 7 and 9, and the sum of along-along position information is 16.

[0053] According to an embodiment of the present disclosure, the number of data bits required to be input for each LUT can be input according to actual conditions, and the data with along-along can be input, for example, for a 6-input LUT array, the number of data bits input each time is 6, but the input data of each LUT in the LUT array is not necessarily 6 bits, which can be optimized and adjusted according to the input and output conditions to reduce resource consumption.

[0054] According to an embodiment of the present disclosure, the number of data bits of the input data of each LUT in the LUT array is not limited, and can be the same or different.

[0055] According to an embodiment of the present disclosure, the number of input ends of each LUT in the LUT array is not limited, and can be the same LUT with the same number of input ends, or different LUT arrays with different numbers of input ends, and the same LUT array can also include LUTs with the same number of input ends and LUTs with different numbers of input ends.

[0056] According to an embodiment of the present disclosure, the data included in the target sub-sequence is respectively input into the input end of the look-up table array, and the target value of the target sub-sequence can be obtained.

[0057] According to an embodiment of the present disclosure, each group of l-bit target subsequence contains l-1 possible run-along positions. The possible run-along position 0 is between the 0th bit and the 1st bit of the target subsequence data, the possible run-along position 1 is between the 1st bit and the 2nd bit of the target subsequence data, and the possible run-along position l-2 is between the l-2th bit and the l-1th bit of the target subsequence data. Specifically, for example, if the xth bit and the x+1th bit of the subsequence are not equal, i.e., the xth bit is 0, the x+1th bit is 1, or the xth bit is 1, the x+1th bit is 0, then a run-along position occurs, and the xth bit is the run-along position. If the xth bit and the x+1th bit of the subsequence are equal, i.e., the xth bit = 0, the x+1th bit = 0, or the xth bit = 1, the x+1th bit = 1, then no run-along position occurs.

[0058] According to an embodiment of the present disclosure, for calculating the target value of each target subsequence, a parallel calculation mode can be used, i.e., each target subsequence is input into the corresponding lookup table array in parallel. Similarly, a serial processing mode can also be used, i.e., after a target subsequence is input into the lookup table array to obtain the target value of the target subsequence, the next target subsequence is input to obtain the target value of the target subsequence, and so on, until the target values of the multiple target subsequences are obtained.

[0059] According to an embodiment of the present disclosure, by inputting the target subsequence into the corresponding lookup table array set of the target subsequence, the target value corresponding to each target subsequence can be obtained, thereby achieving the advantages of less hardware resources used in the process of obtaining the target value, i.e., the sum of the run-along position information, short encoding time, and high positioning accuracy. Moreover, the parallel or serial mode can be used to obtain the target value of each target subsequence according to the requirement, and the selection is more. In the case of using the parallel mode to obtain each target subsequence, the processing speed is fast, the structure is simple, and the dead time is small. In the case of using the serial mode to obtain the target value of each target subsequence, the logic structure is used, the clock frequency is high, the dead time is small, and the throughput is high.

[0060] In operation S130, based on the target values corresponding to the multiple target subsequences, the target value of the original data sequence is determined.

[0061] According to an embodiment of the present disclosure, by performing the first calculation processing on the target values corresponding to the multiple target subsequences, the target value of the original data sequence can be obtained, wherein the first calculation processing can be addition calculation and the like.

[0062] According to the embodiment of the present disclosure, by the positive correlation between the size of the target value of the original data sequence and the size of the delay value, the target value can be converted into a delay time value, i.e., fine time data, by a first calculation method, such as a code density statistical method, and combined with coarse time data obtained by a second calculation method, such as a high-speed clock counting method, to obtain the measurement size of the time interval value of the time signal to be measured, and the measured time interval value has the technical effect of higher measurement accuracy.

[0063] According to the data processing method provided by the present disclosure, by grouping the multiple data in the original data sequence, multiple target sub-sequences can be obtained, and the multiple target sub-sequences are respectively input into the lookup table array set corresponding to the target sub-sequences, so that the target value corresponding to each target sub-sequence can be obtained, and based on the target values of the multiple target sub-sequences, the target value of the tap delay chain data can be obtained. Since the multiple data in the original data sequence are grouped to obtain the multiple target sub-sequences, at most one bubble error exists in the sub-sequences, because the two data of the "bubble" error do not exist in the same target sub-sequence, so the problem of difficult to determine the real transition position is at least partially solved, and the technical effect of determining the accuracy of the transition position is realized. Since each target sub-sequence is respectively input into the lookup table array set corresponding to the target sub-sequence, the multiple target sub-sequences are processed in parallel, the target value corresponding to each target sub-sequence is quickly obtained, and based on the target values of the multiple target sub-sequences, the target value of the original data sequence is determined, the problem of high condition limit and more hardware resources used in related technologies is at least partially solved, and the technical effects of saving hardware resources, high universality, less condition limit, short encoding time for the original data sequence, and high accuracy of the target value of the original data sequence are realized.

[0064] Figure 3 A flowchart for determining multiple target sub-sequences according to an embodiment of the present disclosure is schematically shown.

[0065] As shown in Figure 3 Determining the target values of the multiple target sub-sequences includes operation S111 to operation S112.

[0066] In operation S111, the grouping number of the original data sequence is determined based on the multiple data in the original data sequence.

[0067] In operation S112, the multiple data are grouped to obtain the multiple target sub-sequences based on the grouping number and the position identifiers of the multiple data in the original data sequence.

[0068] According to the embodiment of the present disclosure, the target adjacent edge transition distance in the narrow pulse sequence based on the to-be-tested time signal can be determined based on the plurality of data in the original data sequence, that is, the target pulse width of at least one narrow pulse included in the narrow pulse sequence is determined, wherein the target data group including a plurality of continuous and same-value target data in the plurality of data in the original data sequence can be determined, and the ambiguous region of the original data sequence can be determined, which is caused by the "bubble" error, the region length can be determined based on the ambiguous region, and the grouping number of the original data sequence can be determined by using the region length and the target adjacent edge transition distance.

[0069] According to the embodiment of the present disclosure, the plurality of data can be grouped based on the grouping number and the respective position identifiers of the plurality of data in the original data sequence, so as to obtain a plurality of target sub-sequences, wherein the grouping manner is not limited, and any grouping manner in which the same target sub-sequence does not include any two data of the same edge transition "bubble" error can be used.

[0070] According to the embodiment of the present disclosure, the grouping manner can be a manner of grouping the kn+i th data in the original data sequence into the k th data in the i th target sub-sequence, that is, each data in the original data sequence is sequentially and respectively grouped into each target sub-sequence, for example, the original data sequence includes 111000111000 and the grouping number is 4, the first data in the first target sub-sequence is 1, the first data in the second target sub-sequence is 1, the first data in the third target sub-sequence is 1, and the first data in the fourth target sub-sequence is 0, similarly, the second data in the first target sub-sequence is 0, the second data in the second target sub-sequence is 0, the second data in the third target sub-sequence is 1, and the second data in the fourth target sub-sequence is 1, and the third data in the first target sub-sequence is 1, the third data in the second target sub-sequence is 0, the third data in the third target sub-sequence is 0, and the third data in the fourth target sub-sequence is 0, finally, the first target sub-sequence is 101, the second target sub-sequence is 100, the third target sub-sequence is 011, and the fourth target sub-sequence is 010.

[0071] According to the embodiment of the present disclosure, the target adjacent edge transition distance and the region length can be determined based on the plurality of data in the original data sequence, the grouping number of the original data sequence can be determined by using the region length and the target adjacent edge transition distance, and the original data sequence can be grouped, so as to quickly eliminate the "bubble" error, and meanwhile, the pulse number, the pulse width change, the delay unit delay value change, and the tap delay chain length are not sensitive during the determination of the edge transition position of the original data sequence, that is, the encoding, and the embodiment has strong universality, expansibility, and portability.

[0072] According to an embodiment of the present disclosure, the grouping number of the original data sequence is determined based on the plurality of data in the original data sequence, including the following operations.

[0073] At least one target data group is determined from the plurality of data in the original data sequence, wherein the target data group includes a plurality of target data that are continuous in position and have the same data value; a target adjacent run distance is determined based on the target data group, wherein the target adjacent run distance is the data amount of the target data group that includes the smallest data amount in the at least one target data group; a plurality of region information of the run is determined from the plurality of data in the original data sequence; a plurality of target regions is determined based on the plurality of region information; a target region length is determined based on the region length of each of the plurality of target regions, wherein the target region length represents the maximum region length in the region length of each of the plurality of target regions; and the grouping number of the original data sequence is determined based on the target adjacent run distance and the target region length, wherein the grouping number is less than or equal to the target adjacent run distance and greater than or equal to the target region length.

[0074] According to an embodiment of the present disclosure, the original data sequence can include a plurality of target data groups that have the same data value and are continuous, and the target data group includes a plurality of target data. The target data is not limited, for example, the target data can be data with a data value of 1.

[0075] According to an embodiment of the present disclosure, the target data group can be a narrow pulse sequence, and the distance between adjacent run-to-run can be determined based on the data amount of the target data included in the target data group, i.e., the pulse width. The target data group can be multiple or one, and the data amount of the target data group with the smallest data amount in the plurality of target data groups can be the target adjacent run distance. In the case of one target data group, the data amount of the target data group is the target adjacent run distance.

[0076] According to an embodiment of the present disclosure, in the case of a narrow pulse sequence, the process of determining the target adjacent run distance based on the data amount of the target data can be, for example, the original data sequence is 01111111111110110000000000000110111111110100, the delay unit can determine two target data groups, i.e., two pulse sequences, from the original data sequence, which are 111111111111 and 11111111, respectively, and the data amount of the two target data groups is determined to be 12 and 8, respectively. The distance between adjacent run-to-run in the data sequence, i.e., the pulse width, is 12 and 8, respectively. The data amount of the target data group with the smallest data amount is the target adjacent run distance, so the target adjacent run distance is 8. The calculation method of the data amount is not limited, which can be determined based on the number of data bits included in the data group.

[0077] According to an embodiment of the present disclosure, the region information can be region information with adjacent data value changes, for example, 01 and 10 are adjacent data value changes.

[0078] According to an embodiment of the present disclosure, based on the plurality of region information, the target region can be determined, for example, in the case of the original data sequence being 00010011111111111101100000000000001101111111101000, based on the adjacent data value changes, the plurality of region information can be …00100…, …0011…, …10110…, …00110…, …110100…, and …110… The target region can be a fuzzy region, which can be a region with 0 mixed in a plurality of 1 or 1 mixed in a plurality of 0. For a normal adjacent data value change region in which a plurality of 0 changes to a plurality of 1 or a plurality of 1 changes to a plurality of 0, it is not considered as a target region, for example, based on the above target region, it can be …100…, …011…, …110…, and …01…

[0079] According to an embodiment of the present disclosure, the length of the target region can be the number of data bits of the data included in the region, which can also be referred to as bubble depth, for example, in the above target region, it can be determined that the region lengths are 3, 3, 3, and 2 respectively, and the target region length is the maximum region length, which can be 3.

[0080] According to an embodiment of the present disclosure, based on the target region length and the target adjacent data value change distance, the grouping number can be determined, that is, the grouping number is less than or equal to the target adjacent data value change distance and the grouping number is greater than or equal to the target region length, for example, in the case of the target adjacent data value change distance being 8 and the target region length being 3 based on the above example, the grouping number can be any integer value between 3 and 8, such as 3, 4, 5, 6, 7, and 8.

[0081] According to an embodiment of the present disclosure, based on the grouping number determined based on the target adjacent data value change distance and the target region length, each pulse of the narrow pulse sequence can be sampled in all target subsequences, and the bubble error of the same adjacent data value change does not appear in the same target subsequence, so that the adjacent data value change position information in the target subsequence is clear and accurate, and there is no bubble error. At the same time, when determining the adjacent data value change position information of the target subsequence, the pulse number, pulse width change, delay unit delay value change, and tap delay chain length are not sensitive, and in the case of ensuring that the grouping number is less than or equal to the target adjacent data value change distance and the grouping number is greater than or equal to the target region length, any pulse number, pulse width change, delay unit delay value change, and tap delay chain length can use the data processing method of the present disclosure, therefore, it has strong universality and expansibility, and the increase and decrease of the module can be conveniently realized according to the requirements when used.

[0082] According to an embodiment of the present disclosure, the lookup table array set includes multiple lookup table arrays, and the lookup table array includes multiple lookup tables; each target subsequence is input into the lookup table array set corresponding to the target subsequence, and obtaining the target values ​​corresponding to each of the multiple target subsequences includes the following operations.

[0083] For each target subsequence, a plurality of subsequence slices are determined from the target subsequence based on the number of input terminals of the lookup table in the lookup table array; the plurality of subsequence slices are respectively input into the corresponding lookup table array to obtain target values ​​corresponding to the plurality of subsequence slices; and a target value of the target subsequence is obtained based on the target values ​​corresponding to the plurality of subsequence slices.

[0084] According to embodiments of the present disclosure, multiple subsequence slices can be determined from a target subsequence based on the number of inputs to the lookup tables in a lookup table array. For example, for a 6-input lookup table, data bits 0 to 5 of the target subsequence can be connected to the first set of configured LUT arrays, data bits 5 to 10 can be connected to the second set of configured LUT arrays, data bits 10 to 15 can be connected to the third set of configured LUT arrays, and bits 1-6 to 1-1 of the subsequence can be connected to LUT array 1 / 5, where 1 represents the number of data bits in the target subsequence. The number of LUTs in each set of configured LUT arrays can be selected based on specific circumstances. For example, if the target subsequence is 000111000011110, the subsequences can be 000111, 100001, and 11110, respectively.

[0085] According to an embodiment of the present disclosure, each subsequence slice includes a corresponding lookup table array. The number of lookup tables included in the lookup table array corresponding to each subsequence slice is not limited and can be determined individually for each subsequence slice.

[0086] According to an embodiment of the present disclosure, the output of each LUT may be a one-bit binary code representing 0 or 1. Since the LUT array corresponding to each subsequence slice may contain multiple LUTs, the target value of the subsequence slice included in the target subsequence can be obtained through the multi-bit binary code output by a LUT array. For example, if the output of a LUT array is 0010000, its target value is 0010000. Similarly, the target value can also be converted into decimal data, that is, 16.

[0087] According to an embodiment of the present disclosure, the target value of the target subsequence is obtained by adding the target values ​​corresponding to the multiple subsequence fragments through adders.

[0088] According to the embodiment of the present disclosure, the target sub-sequence is divided into a plurality of sub-sequence segments, the target value of each sub-sequence segment is calculated respectively, and finally the target value of the target sub-sequence is obtained. This can only generate the intermediate data of the target value of the sub-sequence segment in the process of determining the target value of the target sub-sequence, and the target value of the target sub-sequence can be obtained by adding the target values of the plurality of sub-sequence segments. The calculation method is relatively simple, which makes the determination of the target value of the target sub-sequence efficient, and can achieve the same accuracy as the determination of the position information along the variable position. At the same time, the determination of the target value of the target sub-sequence can be realized by using a small amount of hardware resources, which realizes the saving of resources to a certain extent, and the input end of the lookup table is not limited. In the case of less input data bits, a lookup table with less input end can be used to save resources.

[0089] According to the embodiment of the present disclosure, the sub-sequence segments can be input into the lookup table array in parallel to obtain the target value, so as to accelerate the calculation rate and reduce the dead time. The sub-sequence segments can also be input into the corresponding lookup table array in series or one by one, so as to make the decoding logic run at a very high clock frequency, the overall dead time is small, and the throughput is high.

[0090] Figure 4 The schematic diagram of the lookup table array according to the embodiment of the present disclosure is shown schematically.

[0091] As shown in Figure 4 The LUT array includes a plurality of LUTs. Taking a LUT with 6 inputs as an example, each LUT has 6 inputs, and each LUT outputs one binary code. By inputting the sub-sequence segments into the LUT array multiple times, a plurality of binary codes can be obtained at the same time. By sorting the plurality of binary codes in order, the target value of the sub-sequence segment can be obtained. For example, any data of the binary code can be specified as the most significant bit (MSB) and any data of the binary code can be specified as the least significant bit (LSB) according to the requirement.

[0092] According to the embodiment of the present disclosure, in the case that the number of data bits included in the sub-sequence segment is less than the number of inputs of the lookup table, the target input data of the input end without input data is set to the predetermined data.

[0093] According to the embodiment of the present disclosure, the number of input bits of the input data of the LUT is not limited, which can be determined according to the number of inputs of the LUT, so that each input end has its own input data. According to the requirement, the data with adjacent position and different data value can be input into the LUT.

[0094] According to an embodiment of the present disclosure, based on the target subsequence, in the case that the number of data bits of the subsequence slice present data does not satisfy the number of input bits of the LUT, i.e. in the case that the number of input data bits is less than the number of inputs of the lookup table, the input data of the remaining inputs can be set as predetermined data, which can be 0 or 1, and the specific value can be determined according to the actual situation, for example: if the output data of the tap delay chain without input is all 0, the predetermined data can be set as 0, and if the data of the tap delay chain without input is all 1, the predetermined data can be set as 1.

[0095] According to an embodiment of the present disclosure, in the case that the number of input data bits is less than the number of inputs of the current lookup table, the lookup table can also be updated to a lookup table with the number of inputs of mod(l, 5) + 1.

[0096] According to an embodiment of the present disclosure, the case that the number of data bits of the subsequence slice present data does not satisfy the number of input bits of the LUT can include the case that the number of data bits of the target subsequence cannot be divided by the number of inputs of the LUT.

[0097] According to an embodiment of the present disclosure, based on the plurality of subsequence slices of the target subsequence, the maximum target value of each of the plurality of subsequence slices is determined; and based on the maximum target value of each of the plurality of subsequence slices, the number of lookup tables included in the lookup table array corresponding to each of the plurality of subsequence slices is determined.

[0098] According to an embodiment of the present disclosure, based on the plurality of subsequence slices of the target subsequence, the maximum target value of each of the plurality of subsequence slices can be determined, wherein the maximum target value can be the maximum target value calculated according to the possible occurrence of the edge along of the subsequence slice, i.e. the sum of the maximum edge along position information, for example: for the zeroth subsequence slice of the target subsequence, there can be a sequence including the maximum target value 010101, and since there are 5 edge along positions 1, 2, 3, 4 and 5, the maximum target value of the zeroth subsequence slice is 15, and similarly, for the first subsequence slice, there can be a sequence including the maximum target value 010101, and since there are 5 edge along positions 6, 7, 8, 9 and 10, the maximum target value of the first subsequence slice is 40.

[0099] According to an embodiment of the present disclosure, based on the maximum target value of the subsequence slice, the number of lookup table arrays corresponding to the subsequence slice can be determined, and the determination method is not limited, for example, the number of lookup tables contained in the lookup table array can be determined by using the maximum target value less than or equal to 2 r -1 and greater than or equal to 2 r-1 , and r represents the number of lookup tables contained in the lookup table array. For example: for the subsequence slice with the maximum target value of 40, the 2 6-1 <=40<=2 6-1, the number of look-up tables of the look-up table array corresponding to the sub-sequence slice is 6.

[0100] According to an embodiment of the present disclosure, the LUT array contains at most r LUTs with s inputs. In most cases, the task of slicing can be completed using r LUTs with less than or equal to s inputs.

[0101] According to an embodiment of the present disclosure, the target value of the original data sequence is determined based on the target values corresponding to the plurality of target sub-sequences, including: inputting the target values corresponding to the plurality of target sub-sequences into an adder to obtain the target value of the original data sequence.

[0102] According to an embodiment of the present disclosure, the target values corresponding to the plurality of target sub-sequences are inputted into the adder at the same time, and the target value of the original data sequence is obtained, for example, the target values of the plurality of target sub-sequences are 33, 34, 31, and 33 respectively, and the target value of the original data sequence is 32+34+31+33=130.

[0103] According to an embodiment of the present disclosure, by dividing the original data sequence into a plurality of target sub-sequences, the target values are determined by dividing the target sub-sequences into a plurality of sub-sequence slices, and the target values are added respectively to obtain the target value of the original data sequence. Based on the above, the same accuracy as the fixed positioning can be achieved, and the number of pulses, the pulse width, the delay unit delay value, and the tap delay chain length are not sensitive. In the case of ensuring that the number of groups is less than or equal to the target adjacent edge distance and the number of groups is greater than or equal to the target region length, any number of pulses, pulse width, delay unit delay value, and tap delay chain length will not be affected. Therefore, it has strong universality and expansibility, and the increase and decrease of the module can be conveniently realized according to the demand in use.

[0104] Figure 5 A schematic diagram of a data processing method according to another embodiment of the present disclosure is schematically shown.

[0105] As shown in Figure 5 For a tap delay chain composed of 60 delay units, the output original data sequence of the tap delay chain is a tap delay chain data sequence with 60 bits. In the part of the delay chain where there is no pulse input, the pulse has not arrived, and the pulse has passed, the delay chain output data is 0.

[0106] According to the embodiment of the present disclosure, when the once-to-be-detected signal generates a narrow pulse sequence into the delay chain after passing through the flip-flop, a valid tapped delay chain data sequence is output. For example, the output 60-bit tapped delay chain data sequence is 000000000100111111111111011000000000000011011111111010000000. The data output by the delay unit where the pulse is located is 1, and the example data contains two narrow pulses.

[0107] According to the embodiment of the present disclosure, the target region exists at the pulse edge change positions …100…, …011…, …110…, and …01…, and the target region is caused by the "bubble" error. The length of the target region is defined as the number of bits where 0 and 1 exist simultaneously, that is, the bubble depth. The bubble depths at the above four edge change positions are 3, 3, 3, and 2, respectively, and the maximum bubble depth is 3.

[0108] According to the embodiment of the present disclosure, the two narrow pulse sequences included in the tapped delay chain data sequence correspond to the target data groups 111111111111 and 11111111, respectively, the data amount or pulse width is 12 and 8, respectively, the target pulse width or target adjacent edge distance is 8, the data corresponding to the narrow pulse sequence in the target data group can be determined by determining the distance between adjacent edge changes, and the distance between the two edge changes is determined by the data amount in each target data group.

[0109] According to the embodiment of the present disclosure, according to the grouping number requirement, it is ensured that each pulse of the narrow pulse sequence is sampled in all tapped data subsequences, and "bubble" errors of the same edge change do not appear in the same tapped data subsequence; that is, the minimum pulse width is greater than the requirement that the grouping number is greater than the maximum bubble depth, the grouping number needs to be greater than or equal to 3 and less than or equal to 8. For example, the grouping number is 4, and the minimum pulse width is the target adjacent edge distance.

[0110] According to the embodiment of the present disclosure, for the example output 60-bit tapped delay chain data sequence "000000000100111111111111011000000000000011011111111010000000", the original code kn+i bit of the tapped delay chain data is grouped into the kth bit of the ith group of tapped data subsequences, for example, when n=4, the original sequence is divided into 4 groups of 15-bit tapped data subsequences. They are respectively recorded as the 0th target subsequence, the 1st target subsequence, the 2nd target subsequence, and the 3rd target subsequence. The 15-bit data in each target subsequence is sequentially recorded as the 0th bit, the 1st bit, …, and the 14th bit.

[0111] According to an embodiment of the present disclosure, for example, the 11th bit of the tap delay chain data sequence, i.e., the (2*4+3)th bit is grouped into the 2nd bit of the 3rd target subsequence. According to the grouping scheme, the following is obtained:

[0112] The 0th target subsequence is 000111000011110, the 1st target subsequence is 001111100011100, the 2nd target subsequence is 000111100001100, and the 3rd target subsequence is 000111000011000.

[0113] According to an embodiment of the present disclosure, as shown in Figure 5 Wave Union A type TDC coding special logic circuit 0~Wave Union A type TDC coding special logic circuit 4 correspond to each target subsequence group respectively.

[0114] According to an embodiment of the present disclosure, each Wave Union A type TDC coding special logic circuit includes a respective LUT array, for example, Wave Union A type TDC coding special logic circuit 0 includes LUT array 0~LUT array 2.

[0115] According to an embodiment of the present disclosure, the LUT array corresponds to each subsequence slice.

[0116] According to an embodiment of the present disclosure, taking the 0th target subsequence and the 6-input LUT array as an example, the subsequence slicing operation is performed, then the 0th subsequence slice is the 0th~5th bit of the target subsequence: 000111, the 1st subsequence slice is the 5th~10th bit of the target subsequence: 100001, and the 2nd subsequence slice is the 10th~14th bit of the target subsequence: 11110.

[0117] According to an embodiment of the present disclosure, taking the 1st subsequence slice 100001 of the 0th target subsequence as an example, it is connected to the configured LUT array 1; since the 1st subsequence slice 100001 of the 0th target subsequence corresponds to two edge change positions, which are 6 and 10 respectively; then the output data 16(O) of the configured LUT array 1, i.e., 0010000(B), is the edge change position and data of all subsequence slices. Similarly, the edge change position and data of the 0th subsequence slice are 3(O), and the edge change position and data of the 2nd subsequence slice are 14(O), wherein O represents decimal, and B represents binary.

[0118] According to the embodiment of the present disclosure, the above steps are executed in parallel in hardware, and the sum of the target sub-sequence group is obtained by directly adding the data along the variable position in the obtained sub-sequence fragment. The sum of the variable position of the 0th tap data sub-sequence is 33, and the sum of the variable position information of the 1st-3rd tap data sub-sequences is 34, 31, and 32, respectively.

[0119] According to the embodiment of the present disclosure, the sum of the variable position information of each target sub-sequence group is added, and the target value of the original data sequence is obtained as 32+34+31+33=130.

[0120] According to the embodiment of the present disclosure, the sum of the variable position information of all the variable positions in the tap delay chain of the narrow pulse sequence is directly related to the fine time of the arrival time of the signal to be measured, and the measured time interval can be obtained by combining the coarse time information.

[0121] Figure 6 The schematic diagram of the encoding circuit according to the embodiment of the present disclosure is shown schematically.

[0122] As shown in Figure 6 , the encoding circuit includes a plurality of special logic circuits 610 and a first adder 620.

[0123] The plurality of special logic circuits 610 are used to convert the target sub-sequence corresponding to each special logic circuit into a target value, wherein the target sub-sequence is obtained by grouping the original data sequence.

[0124] The first adder 620 is connected to the plurality of special logic circuits respectively, and is used to add the plurality of target values to obtain the target value of the original data sequence.

[0125] According to the embodiment of the present disclosure, the encoding circuit includes a plurality of special logic circuits 610 and a first adder 620, and based on the plurality of special logic circuits 610, the plurality of target sub-sequences obtained by grouping the original data sequence can be converted into the target values of the target sub-sequences, wherein different target sub-sequences can correspond to the same or similar special logic circuits.

[0126] According to the embodiment of the present disclosure, the first adder 620 is connected to the plurality of special logic circuits respectively, and can add the output values of each special logic circuit, i.e., the target values of the target sub-sequences, to obtain the target value of the original data sequence.

[0127] According to the embodiment of the present disclosure, the special logic circuit can be multiple or one. If the special logic circuit is multiple, the target sub-sequences can be processed in parallel, and if the special logic circuit is one, the target sub-sequences can be processed one by one through the pipeline processing mode.

[0128] According to an embodiment of the present disclosure, the original data sequence comprises a tap delay chain data sequence.

[0129] According to an embodiment of the present disclosure, the encoding circuit realizes the determination of the target value of the original data sequence, i.e., the edge position information and the sum of the original data sequence, by the plurality of special logic circuits and the first adder, effectively saving hardware resources and greatly shortening the encoding time, and achieving the same accuracy as the fixed positioning.

[0130] According to an embodiment of the present disclosure, based on the parallel processing of the target subsequence by the special logic circuit, a simple structure and a small dead time can be achieved. Based on the pipeline processing by the special logic circuit, the entire encoding logic can run at a high clock frequency, and the overall dead time is small and the throughput is high.

[0131] According to an embodiment of the present disclosure, to verify the feasibility, the following experiment is performed. After the data processing method is instantiated on an FPGA, a behavior level simulation is performed. The simulation is run on a Vivado software platform. The Vivado software platform includes a highly integrated design environment and a new generation of system-to-IC-level tools, which are all based on a shared scalable data model and a common debugging environment. The input data is a 352-bit original data sequence. The 11-bit binary data representing the sum of all edge positions in the original data sequence can be encoded as required, and the enable signal is accurate. Finally, the time-to-digital converter tap delay chain encoding method disclosed in the present application is used in an XC7K410T-2FFG900I type FPGA of Xilinx. The encoding circuit can stably run at a clock of 400 MHz.

[0132] The special logic circuit comprises: a lookup table array set 611, configured to convert a subsequence segment corresponding to each lookup table array in the lookup table array set into a target value of the subsequence segment, wherein the subsequence segment is obtained based on grouping of the target subsequence, and the target value of the subsequence segment is the target value of the subsequence segment; and a second adder 612, connected to the plurality of lookup table arrays respectively, configured to add the target values of the subsequence segments to obtain the target value of the target subsequence.

[0133] According to an embodiment of the present disclosure, the special logic circuit comprises the lookup table array set and the second adder. By inputting the subsequence segments into the corresponding lookup table arrays respectively, the target value of each subsequence segment can be obtained. The target value can be binary data, for example, the first output can be the most significant bit, and the last output can be the least significant bit. By using the second adder, the target values of the target subsequence segments can be added.

[0134] Figure 7A schematic diagram of a special-purpose logic circuit according to an embodiment of the present disclosure is shown.

[0135] As shown in Figure 7 , taking a lookup table with six inputs as an example, the special-purpose logic circuit includes a lookup table array and an adder, the lookup table array includes a plurality of lookup tables, each lookup table can output a binary code, and the plurality of lookup tables can output target values of subsequence fragments. The target values of each subsequence are added by the second adder to obtain a target value of a target subsequence, i.e., a sum of the variable position information.

[0136] According to an embodiment of the present disclosure, the number of inputs of the lookup table is only illustrative, and a lookup table with a different number of inputs can be used according to actual conditions.

[0137] Figure 8 A timing diagram according to an embodiment of the present disclosure is shown.

[0138] As shown in Figure 8 , for the data valid in the clock period, the data is marked in the original data sequence, so that valid data 0 and valid data 1 can be obtained. Since the process of determining the target subsequence from the original data sequence is mainly to group the data included in the original data sequence to obtain the target subsequence, the clock period of the valid data 0 and the valid data 1 in the target subsequence is the same. In the process of determining the variable position information sum based on the target subsequence, the LUT array set and the adder are used for calculation, so that the valid data 0 and the valid data 1 in the timing diagram of the variable position data of the target subsequence are delayed by one clock period. The variable position information sum of the original data sequence is obtained. Similarly, the variable position information sum of the original data sequence is obtained by adding the respective variable position information sum of the target subsequence, so that the variable position data of the original data sequence is delayed by one clock period. Finally, the data storage control signal can be recorded by using a data storage tool, such as a first input first output (FIFO), to control data storage.

[0139] The above-described specific embodiments further illustrate the purpose, technical solutions, and beneficial effects of the present application. It should be understood that the above-described specific embodiments are only examples of the present application and are not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

[0140] Based on the above-described data processing method, the present disclosure further provides a data processing device. The device will be described in detail below. Figure 9 .

[0141] Figure 9 A structural block diagram of a data processing apparatus according to an embodiment of the present disclosure is shown schematically.

[0142] As shown in Figure 9 The data processing apparatus 900 of this embodiment includes a target subsequence determining module 910, a first target value determining module 920, and a second target value determining module 930.

[0143] The target subsequence determining module 910 is configured to group the plurality of data in the original data sequence to obtain a plurality of target subsequences. In an embodiment, the target subsequence determining module 910 can be configured to perform the operation S110 described above, and thus no further elaboration is made herein.

[0144] The first target value determining module 920 is configured to input each target subsequence into a lookup table array set corresponding to the target subsequence, to obtain a target value corresponding to each target subsequence, wherein the target value represents a sum of position information of data with adjacent positions and different data values in the target subsequence. In an embodiment, the first target value determining module 920 can be configured to perform the operation S120 described above, and thus no further elaboration is made herein.

[0145] The second target value determining module 930 is configured to determine a target value of the original data sequence based on the target values corresponding to the plurality of target subsequences. In an embodiment, the second target value determining module 930 can be configured to perform the operation S130 described above, and thus no further elaboration is made herein.

[0146] According to an embodiment of the present disclosure, the target subsequence determining module 910 can include a grouping number determining sub-module and a target subsequence determining sub-module.

[0147] The grouping number determining sub-module is configured to determine a grouping number of the original data sequence based on the plurality of data in the original data sequence.

[0148] The target subsequence determining sub-module is configured to group the plurality of data based on the grouping number and respective position identifiers of the plurality of data in the original data sequence, to obtain the plurality of target subsequences.

[0149] According to an embodiment of the present disclosure, the grouping number determining sub-module can include a target data group determining unit, a target adjacent distance determining unit, a region information determining unit, a target region determining unit, a target region length determining unit, and a grouping number determining unit.

[0150] The target data group determining unit is configured to determine at least one target data group from the plurality of data in the original data sequence, wherein the target data group includes a plurality of target data with consecutive positions and same data values.

[0151] A target adjacent run distance determination unit is configured to determine a target adjacent run distance based on the target data set, wherein the target adjacent run distance is a data amount of a target data set including a minimum data amount in the at least one target data set.

[0152] A region information determination unit is configured to determine a plurality of region information of the run from the plurality of data in the original data sequence.

[0153] A target region determination unit is configured to determine a plurality of target regions based on region lengths of the plurality of region information.

[0154] A target region length determination unit is configured to determine a target region length based on region lengths of the plurality of target regions, wherein the target region length represents a maximum region length in the region lengths of the plurality of target regions.

[0155] A group number determination unit is configured to determine a group number of the original data sequence based on the target adjacent run distance and the target region length, wherein the group number is less than or equal to the target adjacent run distance and greater than or equal to the target region length.

[0156] According to an embodiment of the present disclosure, the lookup table array set includes a plurality of lookup table arrays, and each lookup table array includes a plurality of lookup tables; the first target value determination module includes a sub-sequence slice determination sub-module, a sub-sequence slice target value determination sub-module, and a first target value determination sub-module.

[0157] The sub-sequence slice determination sub-module is configured to determine a plurality of sub-sequence slices from each target sub-sequence based on the number of inputs of the lookup tables in the lookup table array.

[0158] The sub-sequence slice target value determination sub-module is configured to input the plurality of sub-sequence slices into the corresponding lookup table array respectively to obtain a plurality of target values corresponding to the plurality of sub-sequence slices respectively.

[0159] The first target value determination sub-module is configured to obtain a target value of the target sub-sequence based on the target values corresponding to the plurality of sub-sequence slices respectively.

[0160] According to an embodiment of the present disclosure, the data processing apparatus 900 further includes an input processing module.

[0161] The input processing module is configured to set a target input data of an input end without input data as a predetermined data in a case where the number of data bits included in the sub-sequence slice is less than the number of inputs of the lookup table.

[0162] According to an embodiment of the present disclosure, the data processing apparatus 900 further includes a maximum target value determination module and a lookup table number determination module.

[0163] a maximum target value determination module configured to determine a maximum target value of each of the plurality of sub-sequence fragments based on the plurality of sub-sequence fragments of the target sub-sequence.

[0164] a lookup table number determination module configured to determine a number of lookup tables included in a lookup table array corresponding to each of the plurality of sub-sequence fragments based on the maximum target value of each of the plurality of sub-sequence fragments.

[0165] According to an embodiment of the present disclosure, the second target value determination module includes a target value input sub-module.

[0166] The target value input sub-module is configured to input the target value corresponding to each of the plurality of target sub-sequences into the adder to obtain the target value of the original data sequence.

[0167] According to an embodiment of the present disclosure, any one or more of the target sub-sequence determination module 910, the first target value determination module 920 and the second target value determination module 930 can be combined in one module, or any one of them can be split into multiple modules. Alternatively, at least part of the function of one or more of these modules can be combined with at least part of the function of other modules, and implemented in one module. According to an embodiment of the present disclosure, at least one of the target sub-sequence determination module 910, the first target value determination module 920 and the second target value determination module 930 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or any other reasonable way of integrating or packaging a circuit, etc. hardware or firmware, or any one of the three implementation ways of software, hardware and firmware or any appropriate combination of any of them. Alternatively, at least one of the target sub-sequence determination module 910, the first target value determination module 920 and the second target value determination module 930 can be at least partially implemented as a computer program module which can perform the corresponding functions when the computer program module is run.

[0168] The computer program product of the first aspect can include one or more non-transitory computer-readable media storing instructions that, when executed, cause one or more processors to perform the operations of the first aspect. The one or more non-transitory computer-readable media can include, for example, magnetic media such as one or more magnetic disks, magnetic tapes or cassettes; optical media such as one or more compact discs (CD), optical discs or discs (for example, DVD, Blu-ray Disc®, digital video disc, ultra density disc, ultra-compact disc, any optical media, etc.); semiconductor media such as solid state hard drives (for example, flash memory, solid state USB drives, etc.); any other suitable medium; or any suitable combination of media.

[0169] Those skilled in the art will understand that features of the various embodiments and / or claims of the present disclosure can be combined or / and integrated with one another, even though such a combination or integration is not expressly disclosed in the present disclosure. In particular, the features of the various embodiments and / or claims of the present disclosure can be combined and / or integrated with one another in any number of ways, without departing from the spirit and scope of the present disclosure. All such combinations and / or integrations are within the scope of the present disclosure.

[0170] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although the above describes each embodiment separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A data processing method, comprising: grouping a plurality of data in an original data sequence to obtain a plurality of target subsequences, the original data sequence comprising a tapped-delay-line data sequence; inputting each of the target subsequences into a corresponding set of lookup table arrays to obtain a corresponding target value for each of the target subsequences, wherein the target value represents a sum of position information of data having adjacent positions and different data values in the target subsequence; determining a target value of the original data sequence based on the target values corresponding to the target subsequences; and the grouping the plurality of data in the original data sequence to obtain the plurality of target subsequences, comprising: determining a grouping number of the original data sequence based on the plurality of data in the original data sequence; grouping the plurality of data in the original data sequence to obtain the plurality of target subsequences based on the grouping number and position identifiers of the plurality of data in the original data sequence; the determining the grouping number of the original data sequence based on the plurality of data in the original data sequence, comprising: determining at least one target data group from the plurality of data in the original data sequence, wherein the target data group comprises a plurality of target data having consecutive positions and same data values; determining a target adjacent run distance based on the target data group, wherein the target adjacent run distance is a data amount of a target data group having a minimum data amount among the at least one target data group; determining a plurality of region information of run-to-run distances from the plurality of data in the original data sequence; determining a plurality of target regions based on the plurality of region information; determining a target region length based on region lengths of the plurality of target regions, wherein the target region length represents a maximum region length among the region lengths of the plurality of target regions; determining the grouping number of the original data sequence based on the target adjacent run distance and the target region length, wherein the grouping number is less than or equal to the target adjacent run distance and greater than or equal to the target region length; and the determining the target value of the original data sequence based on the target values corresponding to the target subsequences, comprising: inputting the target values corresponding to the target subsequences into an adder to obtain the target value of the original data sequence.

2. The method of claim 1, wherein, the set of lookup table arrays comprises a plurality of lookup table arrays, and each of the lookup table arrays comprises a plurality of lookup tables; the inputting each of the target subsequences into the corresponding set of lookup table arrays to obtain the target values corresponding to the target subsequences, comprising: for each of the target subsequences, determining a plurality of subsequence fragments from the target subsequence based on an input number of the lookup tables in the set of lookup table arrays; inputting the plurality of subsequence fragments into the corresponding lookup table arrays to obtain target values corresponding to the plurality of subsequence fragments; and obtaining the target value of the target subsequence based on the target values corresponding to the plurality of subsequence fragments.

3. The method of claim 2, further comprising: In a case where the number of data bits included in the sub-sequence slice is less than the number of inputs of the lookup table, target input data of the input not having input data is set to predetermined data.

4. The method of claim 1, further comprising: determining a maximum target value of each of a plurality of sub-sequence slices of the target sub-sequence based on the plurality of sub-sequence slices; determining a number of lookup tables included in a lookup table array corresponding to each of the plurality of sub-sequence slices based on the maximum target value of each of the plurality of sub-sequence slices.

5. An encoding circuit, comprising: a plurality of special-purpose logic circuits configured to convert a target sub-sequence corresponding to each of the special-purpose logic circuits into a target value, wherein the target sub-sequence is obtained based on grouping of an original data sequence; obtaining the target sub-sequence based on the original data sequence includes: determining a number of groupings of the original data sequence based on a plurality of data in the original data sequence; grouping the plurality of data based on the number of groupings and a position identifier of each of the plurality of data in the original data sequence to obtain a plurality of target sub-sequences; the determining the number of groupings of the original data sequence based on the plurality of data in the original data sequence includes: determining at least one target data group from the plurality of data in the original data sequence, wherein the target data group includes a plurality of target data that are positionally continuous and have the same data value; determining a target adjacent run distance based on the target data group, wherein the target adjacent run distance is a data amount of a target data group having a smallest data amount among the at least one target data group; determining a plurality of region information of a run-to-run distance from the plurality of data in the original data sequence; determining a plurality of target regions based on the plurality of region information; determining a target region length based on a region length of each of the plurality of target regions, wherein the target region length represents a maximum region length among the region lengths of the plurality of target regions; determining the number of groupings of the original data sequence based on the target adjacent run distance and the target region length, wherein the number of groupings is less than or equal to the target adjacent run distance and greater than or equal to the target region length; a first adder connected to the plurality of special-purpose logic circuits, respectively, configured to add the plurality of target values to obtain a target value of the original data sequence; wherein the special-purpose logic circuit includes: a lookup table array set configured to convert a sub-sequence slice corresponding to each of the lookup table arrays in the lookup table array set into a sub-target value, wherein the sub-sequence slice is obtained based on grouping of the target sub-sequence, the sub-target value is a target value of the sub-sequence slice, and the lookup table array set includes a plurality of lookup table arrays; a second adder connected to the plurality of lookup table arrays, respectively, configured to add the sub-target values to obtain a target value of the target sub-sequence.

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