Processor, operation method and storage device for implementing vector stride memory access

Abstract

A processor, an operation method and a storage device are provided. The processor is adapted to access a memory. The processor includes a vector register file and the storage device. The storage device is coupled to the vector register file. The storage device performs a striding operation on the memory. In a current iteration of the striding operation, the storage device reads a plurality of first data elements at a plurality of non-contiguous addresses in the memory and writes the first data elements into the vector register file, or the storage device reads a plurality of second data elements from the vector register file and writes the second data elements into the memory at the plurality of non-contiguous addresses in the current iteration of the striding operation.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more particularly to a processor, operating method, and storage device for implementing vector step memory access. Background Technology

[0002] Vector non-unit (constant) strided operations access data elements discretely located at different memory addresses. In the first iteration of a strided operation, the base effective address is used as the first access address, and the first data element at that address is accessed. In the second iteration, the base effective address is added to a byte offset (or stride) to generate a second access address, and the second data element at that address is accessed. In the third iteration, the base effective address is added to a two-byte offset to generate a third access address, and the third data element at that address is accessed. This process continues, allowing vector strided operations to access multiple data elements discretely located at different memory addresses. In each iteration of a strided operation, current techniques generate only one access address at a time. Therefore, if there are n target data (data elements) scattered across n addresses in memory, existing technologies will access these n target data in memory in n iterations. Summary of the Invention

[0003] The present invention provides a processor, an operation method, and a storage device to accelerate strided operations.

[0004] In an embodiment of the invention, the processor described above is adapted to access memory. The processor includes a vector register file (VRF) and a load store device. The load store device is coupled to the vector register file. The load store device performs a step operation on the memory. In the current iteration of the step operation, the load store device reads a plurality of first data elements at a plurality of non-contiguous addresses in memory and writes these first data elements into the vector register file, or the load store device reads a plurality of second data elements from the vector register file and writes these second data elements respectively at a plurality of non-contiguous addresses in memory in the current iteration of the step operation.

[0005] In an embodiment of the present invention, the above-described operation method includes: performing a step operation on the memory by a storage device; and having the storage device read a plurality of first data elements at a plurality of non-contiguous addresses in the memory and write these first data elements into a vector register file in the current iteration of the step operation, or having the storage device read a plurality of second data elements from the vector register file and write these second data elements respectively at a plurality of non-contiguous addresses in the memory in the current iteration of the step operation.

[0006] In an embodiment of the present invention, the above-described storage device includes a step address generator and a storage circuit. The step address generator generates a plurality of step addresses based on a current base address and a step size. The storage circuit is coupled to the step address generator to receive the step addresses. The storage circuit reads a plurality of first data elements from memory based on the current base address and these step addresses, and writes these first data elements into a vector register file; or the storage circuit reads a plurality of second data elements from the vector register file and writes these second data elements into memory based on the current base address and these step addresses.

[0007] Based on the above, the memory loading device described in the embodiments of the present invention can perform step operations on memory. Within the same iteration of the step operation, the memory loading device can access multiple non-contiguous addresses in memory to accelerate the step operation. When the memory loading device reads multiple first data elements from multiple non-contiguous addresses in memory, it can write these first data elements into a vector register file for use by the processor's vector function unit (VFU). After the vector function unit writes the processing result (second data elements) back to the vector register file, the memory loading device can read these second data elements from the vector register file and write these second data elements to multiple non-contiguous addresses in memory within one iteration of the step operation. Attached Figure Description

[0008] Figure 1A This is a schematic diagram of a circuit block of a processor according to an embodiment of the present invention;

[0009] Figure 1B This is a circuit block diagram of a processor according to another embodiment of the present invention;

[0010] Figure 2 This is a flowchart illustrating a processor operation method according to an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram illustrating a specific example of a stepping operation according to an embodiment of the present invention;

[0012] Figure 4 This is a circuit block diagram of a storage device according to an embodiment of the present invention;

[0013] Figure 5 This is a circuit block diagram of a storage circuit according to an embodiment of the present invention;

[0014] Figure 6 This is a circuit block diagram of a storage circuit according to another embodiment of the present invention;

[0015] Figure 7 This is a circuit block diagram of a storage circuit according to another embodiment of the present invention;

[0016] Figure 8 This is a circuit block diagram of a storage circuit according to another embodiment of the present invention;

[0017] Figure 9 This is a circuit block diagram of a storage circuit according to a further embodiment of the present invention.

[0018] Explanation of reference numerals in the attached figures

[0019] 10: Memory

[0020] 100: Processor

[0021] 105: Instruction Read / Decode / Publish Unit

[0022] 110: Functional Unit

[0023] 120: Vector Functional Unit

[0024] 130: Storage device

[0025] 131: Step Address Generator

[0026] 132: Storage circuit

[0027] 132a: Control circuit

[0028] 132b, 132d, 132g, 132i, 132n, 132q: Line buffers

[0029] 132c: Carrier Circuit

[0030] 132e, 132j: Boundary Buffer

[0031] 132f, 132k, mux1, mux2, mux3, mux4, mux5, mux6, mux7, mux8, mux81: Multitasking

[0032] 132h: Storage circuit

[0033] 132m, 132r: Routing circuit

[0034] 132p: Data processing circuit

[0035] 140: Register File

[0036] 150: Vector Register File

[0037] 160: Main Memory

[0038] 170: DMA controller

[0039] 180: Memory access

[0040] A, B, C, D, E0, E1, E2, E3: Data elements

[0041] Ab: Current base address

[0042] byte_off_1, byte_off_8, byte_off_n: Shift values

[0043] byte_we1, byte_we2: Byte write enable signals

[0044] Cn: Carry part

[0045] mux_sel_1, mux_sel_8, mux_sel_n: Multitasking selection signals

[0046] OFFn: Offset part

[0047] PLM: Configuration Circuit

[0048] rd_ptr: Read pointer

[0049] S210~S260: Steps

[0050] ST: stride

[0051] wr_ptr: Write pointer

[0052] x: Non-target data Detailed Implementation

[0053] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0054] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0055] Figure 1A This is a circuit block diagram of a processor 100 according to an embodiment of the present invention. The processor 100 can be a general-purpose processor or a special-purpose processor. The general-purpose processor may include a central processing unit or other general-purpose processors. The special-purpose processor may include a network processor, a communication processor, a digital signal processor (DSP), an embedded processor, or other special-purpose processors. The processor may have any of the following instruction set architectures: Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), Very Long Instruction Word (VLIW), or a hybrid instruction set architecture, or other types of instruction set architectures. Depending on the actual design, the processor 100 may be a Single Instruction Multiple Data (SIMD) processor, a vector processor, or other processors.

[0056] Processor 100 can access memory 10. For example, processor 100 can read programming codes from memory 10 and execute them. During the execution of programming codes, processor 100 can read data elements from memory 10 and / or write data elements back to memory 10. Figure 1AThe processor 100 shown includes a vector register file (VRF) 150 and a load store device 130. Depending on the actual design, the processor 100 may also include an instruction fetching / decoding / issuing unit 105, a function unit (FU) 110, a vector function unit (vectorFU) 120, and a register file (RF) 140. Function unit 110 and / or vector function unit 120 may include integer function units, floating-point function units, and / or other function units. The instruction fetching / decoding / issuing unit 105 can fetch instructions from memory 10 via an instruction cache (not shown). The instruction fetching / decoding / issuing unit 105 can decode the fetched instructions and then control function unit 110, vector function unit 120, and load store device 130 according to the decoding result. Based on the decoding results, functional unit 110 and / or vector functional unit 120 can perform the relevant functional operations of the read instructions.

[0057] According to the actual design, register file 140 includes an integer register file, a floating-point register file, and / or other register files. The data width of register file 140 may be 32 bits, 64 bits, or other widths. When an instruction needs to read a data element from memory 10, based on the control of instruction read / decode / issue unit 105, storage device 130 can read the data element from memory 10 and then store the data element in register file 140. Based on the instruction operation, functional unit 110 and vector functional unit 120 can retrieve data elements from register file 140. After the instruction is executed, functional unit 110 and vector functional unit 120 can write the processing result back to register file 140. Either functional unit 110 or vector functional unit 120 can access one data element in register file 140 in one cycle.

[0058] According to the actual design, the vector register file 150 includes an integer register file, a floating-point register file, and / or other register files. The data width of each vector register file 150 can be greater than the data width of the register file 140. For example, the data width of the vector register file 150 can be 256 bits, 512 bits, or other widths. When an instruction needs to read multiple data elements in memory 10, based on the control of the instruction read / decode / issue unit 105, the storage device 130 can read these data elements from memory 10 and then store them in the vector register file 150. Based on the operation of the vector processing instruction, the vector function unit 120 can also retrieve data elements (first data elements) from the vector register file 150. After the vector processing instruction is executed, the vector function unit 120 can write the processing result (second data element) back to the vector register file 150.

[0059] Based on the control of the instruction read / decode / issue unit 105, the storage device 130 can access memory 10 through a data cache (not shown). The storage device 130 is coupled to the vector register file 150. In some operating scenarios, the storage device 130 can read data elements in memory 10 through the data cache and load these data elements into the register file 140 or the vector register file 150. In other operating scenarios, the storage device 130 can read data elements from the register file 140 or the vector register file 150 and store these data elements in memory 10 through the data cache.

[0060] Based on the control of the instruction read / decode / issue unit 105, the storage device 130 can also perform strided operations on the memory 10. A strided operation involves accessing data elements located at different addresses within the memory 10. In some operational scenarios, the storage device 130 can read multiple first data elements from multiple non-contiguous addresses within the memory 10 within the same iteration (current iteration) of a strided operation, and write these first data elements into the vector register file 150. In other operational scenarios, the storage device 130 can read multiple second data elements from the vector register file 150, and write these second data elements to multiple non-contiguous addresses within the memory 10 within the same iteration (current iteration) of a strided operation.

[0061] According to the actual design, Figure 1A The processor 100 shown can be packaged as a single integrated circuit; however, the implementation of this invention should not be limited to this. Figure 1AThe illustrated embodiment. In other embodiments, the memory carrier 130 and the vector register file 150 may be packaged as different integrated circuits. For example, the memory carrier 130 may be used in a Direct Memory Access (DMA) controller or other memory access circuitry. Figure 1B This is a circuit block diagram of a processor according to another embodiment of the present invention. Figure 1B The electronic device shown includes main memory 160, DMA controller 170, and secondary memory 180. Figure 1B The main memory of 160 shown can be used as a reference. Figure 1A The relevant explanations for memory 10 shown can be extrapolated from this. Figure 1B The DMA controller 170 shown can be referenced. Figure 1A The description of the storage device 130 shown is used by analogy, and Figure 1B The memory level shown is 180, which can be used as a reference. Figure 1A The relevant descriptions of the vector register file 150 shown are analogous, so they will not be repeated here.

[0062] Figure 2 This is a flowchart illustrating a processor operation method according to an embodiment of the present invention. Please refer to... Figure 1A and Figure 2 In step S210, the storage device 130 can perform a stepping operation on the memory 10. When the storage device 130 wants to load the first data element of the memory 10 into the vector register file 150 (the determination result of step S220 is "load data"), the stepping operation includes steps S230 and S240. When the storage device 130 wants to store the second data element of the vector register file 150 into the memory 10 (the determination result of step S220 is "store data"), the stepping operation includes steps S250 and S260.

[0063] Figure 3 This is a schematic diagram illustrating a specific example of a stepping operation according to an embodiment of the present invention. Please refer to... Figure 1A , Figure 2 and Figure 3 Suppose that the loading device 130 wants to load the first data element of memory 10 into vector register file 150. In the current iteration of the strafing operation, the loading device 130 can read multiple first data elements at multiple non-contiguous addresses within memory 10 (step S230) and write these first data elements into vector register file 150 (step S240). For example, in the same iteration of the strafing operation, the loading device 130 uses the current base address Ab and the stride (or offset) ST to generate multiple strafing addresses for the current iteration. Figure 3Taking the scenario shown as an example, the memory storage device 130 can generate the first step address (i.e., Ab) and the second step address (i.e., Ab + ST) of the current iteration. 1) The third step address (i.e., Ab + ST) 2) With the fourth step address (i.e., Ab + ST) 3). Then, the storage device 130 can transfer multiple non-contiguous addresses (i.e., "Ab", "Ab + ST") within memory 10 in the same iteration of the step operation. 1”, “Ab + ST” 2” and “Ab + ST” Data elements E0, E1, E2, and E3 at address 3) are loaded into vector register file 150. At the end of an iteration, the current base address Ab is updated to point to the data element to be processed in the next iteration. Similarly, the vector step operation can load other data elements discrete at different addresses within memory 10 into vector register file 150 in the next iteration.

[0064] Suppose that storage device 130 wants to store the second data element of vector register file 150 into memory 10. Storage device 130 can read multiple second data elements from vector register file 150 (step S250), and write these second data elements to multiple non-contiguous addresses in memory 10 during the current iteration of the straddle operation (step S260). For example, storage device 130 can read data elements E0, E1, E2, and E3 from vector register file 150. Storage device 130 will use the current base address Ab and straddle ST to generate multiple straddle addresses for the current iteration, namely straddle addresses "Ab", "Ab + ST", etc. 1”, Ab +ST 2” and “Ab + ST” 3". In the same iteration of the step operation, the storage device 130 can write these data elements E0, E1, E2 and E3 to multiple non-contiguous addresses in memory 10 (i.e. "Ab", "Ab + ST"). 1”, “Ab + ST” 2” and “Ab + ST” 3”). At the end of an iteration, the current base address Ab is updated to point to the address of the data element to be written in the next iteration. In this way, the vector step operation can store the data elements of the vector register file 150 into multiple non-contiguous addresses in memory 10 in the next iteration.

[0065] In summary, the storage device 130 can perform step operations on the memory 10. Within the same iteration of the step operation, the storage device 130 can access multiple non-contiguous addresses within the memory 10 to accelerate the step operation. When the storage device 130 reads multiple first data elements from multiple non-contiguous addresses within the memory 10, it can write these first data elements into the vector register file 150 for use by functional units of the processor 100 (e.g., vector functional unit 120). After the vector functional unit 120 writes the processing result (second data elements) back to the vector register file 150, the storage device 130 can read these second data elements from the vector register file 150 and write these second data elements to multiple non-contiguous addresses within the memory 10 within one iteration of the step operation.

[0066] Figure 4 This is a circuit block diagram of a storage device 130 according to an embodiment of the present invention. Figure 4 The memory 10, storage device 130, and vector register file 150 shown can be referenced. Figure 1A The descriptions of memory 10, storage device 130, and vector register file 150 shown are analogous and will not be repeated here. Figure 4 The storage device 130 shown can be used as Figure 1A One of the many embodiments of the storage device 130 shown.

[0067] exist Figure 4 In the illustrated embodiment, the load store device 130 includes a strided address generator 131 and a load store circuit 132. The strided address generator 131 can generate multiple strided addresses based on the current base address Ab and the stride ST. For example (but not limited to), the strided address generator 131 can calculate {Cn, OFFn} = LSB1 + LSB2. (n-1) is used to generate the N stride addresses for the current iteration, where n is an integer greater than 0 and less than or equal to N, and N is an integer determined according to the actual design. In some embodiments, the integer N can be 8 or other integers. LSB2 is the least significant bit part of the stride ST, LSB1 is the least significant bit part of the current base address Ab, {Cn,OFFn} is the nth stride address among these stride addresses, OFFn is the offset of the nth stride address {Cn,OFFn}, and Cn is the carry part of the nth stride address {Cn,OFFn}. The number of bits (width) of the least significant bit parts LSB1 and LSB2 can be determined according to the actual design. For example, the width (address space) of the least significant bit parts LSB1 and / or LSB2 can be adapted to the width of the line buffer of the storage circuit 132. In some embodiments, the width of the least significant bit portion LSB1 and / or LSB2 can be 5 bits or any other number of bits.

[0068] The loading circuit 132 is coupled to the step address generator 131 to receive multiple step addresses. When the loading device 130 wants to load multiple first data elements from memory 10 into vector register file 150, the loading circuit 132 can read these first data elements from memory 10 based on the current base address Ab and these step addresses, and write these first data elements into vector register file 150. Alternatively, when the loading device 130 wants to store multiple second data elements from vector register file 150 into memory 10, the loading circuit 132 can read these second data elements from vector register file 150, and write these second data elements into multiple non-contiguous addresses in memory 10 based on the current base address Ab and these step addresses. The width of the first data element and / or the second data element, i.e., the data element length ELEN, can be determined according to the actual application. For example, in some application scenarios, the data element length ELEN can be 1 byte, 2 bytes, 4 bytes, 8 bytes, or other widths.

[0069] At the end of an iteration, the step address generator 131 can update the current base address Ab according to the usage of the step address {Cn,OFFn}, so that the current base address Ab points to the data element to be processed in the next iteration. For example, assuming that the 1st to the (n-1st)th step address among N step addresses ({C1,OFF1}~{CN,OFFN}) in an iteration is used / processed by the storage circuit 132, the step address generator 131 can calculate Ab2 = {MSB1+Cn,OFFn} to update the current base address Ab, where MSB1 is the most significant bit part of the current base address Ab, and Ab2 is the new base address Ab for the next iteration.

[0070] Figure 5 This is a circuit block diagram of a storage circuit 132 according to an embodiment of the present invention. Figure 5 The memory 10 and vector register file 150 shown can be referenced. Figure 1A The related descriptions of memory 10 and vector register file 150 shown can be extrapolated from this. Figure 5 The storage circuit 132 shown can be referred to Figure 4 The relevant descriptions of the storage circuit 132 shown are analogous and will not be repeated here. Figure 5 The storage circuit 132 shown can be used as Figure 4 This is one of many embodiments of the storage circuit 132 shown.

[0071] exist Figure 5 In the illustrated embodiment, the storage circuit 132 includes a control circuit 132a, a line buffer 132b, a storage circuit 132c, and a line buffer 132d. The line buffer 132b can read multiple bytes from multiple consecutive addresses in the current iteration based on the most significant bit (MSB1) of the current base address Ab, where these bytes include the multiple first data elements. The width of the line buffer 132b can be determined according to the actual design. For example, in some application scenarios, the width of the line buffer 132b can be 32 bytes (256 bits) or other widths. Assuming the width of the line buffer 132b is 32 bytes, the width of the least significant bit (LSB1) of the current base address Ab and / or the width of the least significant bit (LSB2) of the stride ST can be 5 bits to fit the width of the line buffer 132b. Assuming the current base address Ab is {MSB1, LSB1}, then the line buffer 132b can read multiple bytes from memory 10 at multiple consecutive addresses {MSB1, 0b00000} to {MSB1, 0b11111} in the current iteration.

[0072] Control circuit 132a can be coupled to step address generator 131 to receive N step addresses (i.e., {Cn, OFFn}, where n is an integer greater than 0 and less than or equal to N). Control circuit 132a can select one or more of the offset portions OFFn of these step addresses according to the data element length ELEN to generate N offset values, i.e., offn. For example, suppose the number of step addresses {Cn, OFFn} (i.e., N) is 8. For an application scenario where the data element length ELEN is 1 byte, control circuit 132a can select offset portions OFF1 to OFF8 as offset values ​​off1 to off8. For an application scenario where the data element length ELEN is 2 bytes, control circuit 132a can select offset portions OFF1 to OFF4 to generate offset values ​​off1 to off8. For example, offset values ​​off1 to off8 are "OFF1", "OFF1 + 1", "OFF2", "OFF2 + 1", "OFF3", "OFF3 + 1", "OFF4", and "OFF4 + 1", respectively. For applications where the data element length ELEN is 4 bytes, the control circuit 132a can select offset units OFF1 to OFF2 to generate offset values ​​off1 to off8. For example, offset values ​​off1 to off8 are "OFF1", "OFF1 + 1", "OFF1 + 2", "OFF1 + 3", "OFF2", "OFF2 + 1", "OFF2 + 2", and "OFF2 + 3", respectively. For applications where the data element length ELEN is 8 bytes, the control circuit 132a can select offset unit OFF1 to generate offset values ​​off1 to off8. For example, offset values ​​off1 to off8 are "OFF1", "OFF1 + 1", "OFF1 + 2", "OFF1 + 3", "OFF1 + 4", "OFF1 + 5", "OFF1 + 6", and "OFF1 + 7", respectively.

[0073] Control circuit 132a can use a write pointer wr_ptr to point to the current vector register load position in the inline buffer 132d. Control circuit 132a can generate N multiplexer selection signals mux_sel_n by rotating these offset values ​​offn according to the write pointer wr_ptr. For example, assuming N is 8, control circuit 132a can use Table 1 below to generate 8 multiplexer selection signals mux_sel_1 to mux_sel_8. Although Table 1 only lists the range of the write pointer wr_ptr as 0 to 7, other ranges of the write pointer wr_ptr can be deduced from Table 1. In other embodiments, the method of generating the multiplexer selection signal mux_sel_n is not limited to Table 1.

[0074] Table 1: Examples of write pointer wr_ptr rotation offset values ​​offn

[0075]

[0076] Carrier circuit 132c is coupled to control circuit 132a to receive these multiplexer selection signals mux_sel_n. Carrier circuit 132c can collect the plurality of first data elements from multiple bytes of line buffer 132b according to these multiplexer selection signals mux_sel_n. Second line buffer 132d is coupled to carrier circuit 132c to receive these first data elements.

[0077] The control circuit 132a can also calculate OVRn = Cn | (MSB2 ≠ 0) to generate the overflow value of the current iteration, where OVRn represents the nth bit in the overflow value, Cn is the carry of the nth step address {Cn, OFFn} provided by the step address generator 131, the | operator is an OR operation, and MSB2 is the most significant bit part of the step size ST. The overflow value has N bits. The control circuit 132a can select at least one bit in the overflow value according to the data element length ELEN to generate N overflow bits "ovrrn". For example, assuming N is 8, the lowest overflow bit ovr1 is always "0". For applications where the data element length ELEN is 1 byte, the control circuit 132a can select bits OVR2 to OVR8 in the overflow value as overflow bits ovr2 to ovr8. For applications where the data element length ELEN is 2 bytes, the control circuit 132a can select bits OVR2 to OVR4 from the overflow value to generate overflow bits ovr1 to ovr8. For example, overflow bits ovr1 to ovr8 are "0", "0", "OVR2", "OVR2", "OVR3", "OVR3", "OVR4", and "OVR4", respectively. For applications where the data element length ELEN is 4 bytes, the control circuit 132a can select bit OVR2 from the overflow value to generate overflow bits ovr1 to ovr8. For example, overflow bits ovr1 to ovr8 are "0", "0", "0", "0", "OVR2", "OVR2", "OVR2", and "OVR2", respectively. For applications where the data element length ELEN is 8 bytes, the control circuit 132a can set all overflow bits ovr1 to ovr8 to "0".

[0078] Control circuit 132a can invert these overflow bits ovrn to generate N inverted overflow bits "ovrbn". Control circuit 132a can shift these inverted overflow bits ovrbn according to the write pointer wr_ptr to generate a byte write enable signal byte_we1. The byte write enable signal byte_we1 has M+N-1 bits, where M is an integer determined according to the actual design. Line buffer 132d can determine which byte positions of the multiple first data elements provided by carrier circuit 132c should be written to line buffer 132d according to the byte write enable signal byte_we1.

[0079] For example, suppose M is 32 and N is 8, the overflow bits ovr1 to ovr8 are "00000000", and the write pointer wr_ptr is 4. Control circuit 132a can invert these overflow bits ovr1 to ovr8, making the inverted overflow bits ovrb1 to ovrb8 "11111111". Control circuit 132a can then shift these inverted overflow bits ovrb1 to ovrb8 four bits to the left (towards the higher-order bits) based on the write pointer wr_ptr, making the byte write enable signal byte_we1 "00…00 11111111 0000". Each bit of the byte write enable signal byte_we1 corresponds to a byte position in the line buffer 132d. A bit of the byte write enable signal byte_we1 being "0" indicates that the corresponding byte position in the line buffer 132d is refused writing by the carrying circuit 132c. Conversely, if a bit of the byte write enable signal byte_we1 is "1", it means that a corresponding byte position in the line buffer 132d can be written by the carrier circuit 132c. Therefore, the line buffer 132d can determine which byte positions of the 8 bytes (multiple first data elements) provided by the carrier circuit 132c to write to the line buffer 132d based on the byte write enable signal byte_we1.

[0080] Figure 6 This is a circuit block diagram of a storage circuit 132 according to another embodiment of the present invention. Figure 6 In the embodiment shown, the storage circuit 132 includes a line buffer 132b, a storage circuit 132c, a line buffer 132d, a boundary buffer 132e, and a multiplexer 132f. Figure 6 The vector register file 150 shown can be referenced. Figure 1A The relevant descriptions of the vector register file 150 shown can be extrapolated from this. Figure 6 The line buffer 132b, the carrier circuit 132c, and the line buffer 132d shown can be referenced. Figure 5The descriptions of line buffer 132b, carrier circuit 132c, and line buffer 132d shown are analogous and will not be repeated here. Figure 6 The shown circuit 132c can be used as Figure 5 This is one of many embodiments of the carrier circuit 132c shown.

[0081] exist Figure 6 In the illustrated embodiment, the carrier circuit 132c includes N multiplexers, for example... Figure 6 The multiplexers shown are mux1, mux2, mux3, mux4, mux5, mux6, mux7, and mux8. The control terminal of each of these multiplexers is coupled to the control circuit 132a to receive one of the N multiplexer selection signals mux_sel_n. For example, multitasker mux1 is controlled by multitasker selection signal mux_sel_1, multitasker mux2 is controlled by multitasker selection signal mux_sel_2, multitasker mux3 is controlled by multitasker selection signal mux_sel_3, multitasker mux4 is controlled by multitasker selection signal mux_sel_4, multitasker mux5 is controlled by multitasker selection signal mux_sel_5, multitasker mux6 is controlled by multitasker selection signal mux_sel_6, multitasker mux7 is controlled by multitasker selection signal mux_sel_7, and multitasker mux8 is controlled by multitasker selection signal mux_sel_8.

[0082] Each of the multiplexers mux1 to mux8 has M select terminals (which serve as inputs, for example) and a common terminal (which serves as an output, for example). The data width of these select terminals and the common terminal is one byte, and M is an integer determined according to the actual design and is the number of bytes in the line buffer 132b. The select terminals of each of the multiplexers mux1 to mux8 are coupled to the line buffer 132b to receive byte data at different positions. The control circuit 132a can generate multiplexer selection signals mux_sel_1 to mux_sel_8 by rotating these offset values ​​offn according to the write pointer wr_ptr (as shown in Table 1 above, for example). The multiplexers mux1 to mux8 collect the corresponding data element (first data element) from the line buffer 132b according to the multiplexer selection signals mux_sel_1 to mux_sel_8.

[0083] For example, suppose the length M of the line buffer 132b (or 132d) is 32 bytes and N is 8 bytes, the data element length ELEN is 2 bytes, the stride ST is "0b0…000100" (binary), and the current base address Ab is "0b…110100" (binary). Therefore, the most significant bit MSB1 and the least significant bit LSB1 of the current base address Ab are "0b…1" and "0b10100" (i.e., decimal 20), respectively, while the most significant bit MSB2 and the least significant bit LSB2 of the stride ST are "0b0" and "0b00100" (i.e., decimal 4), respectively. Based on the calculation of the control circuit 132a, the offset values ​​off1 to off8 are decimal "20", "21", "24", "25", "28", "29", "0", and "1". Further assume the write pointer wr_ptr is 28. Based on the write pointer wr_ptr, the control circuit 132a can cycle through these offset values ​​off1 to off8, so that the multiplexer selection signals mux_sel_1 to mux_sel_8 are respectively decimal "28", "29", "0", "1", "20", "21", "24", and "25". Figure 6 In the operational scenario shown, a data element is assumed to be 2 bytes; however, in other operational scenarios, a data element may have a different width. Figure 6 In the data buffer, the data element located at offsets "28" and "29" is labeled "C", the data element located at offsets "0" and "1" is labeled "x", the data element located at offsets "20" and "21" is labeled "A", and the data element located at offsets "24" and "25" is labeled "B". Figure 6 In this context, "x" represents non-target data. Therefore, according to the multiplexer selection signals mux_sel_1 to mux_sel_8, the first data elements collected by multiplexers mux1 to mux8 from line buffer 132b are "C", "x", "A", and "B" in sequence. Line buffer 132d includes multiple segments, each with a data width of N bytes. The output of the common terminal of multiplexers mux1 to mux8 is copied to each segment.

[0084] exist Figure 6In the illustrated embodiment, the load circuit 132 further includes a boundary buffer 132e and a multiplexer 132f. The boundary buffer 132e is coupled to the load circuit 132c. When a data element from a previous iteration (the third data element) is written near the high boundary of the line buffer 132d, causing a remainder of the third data element to extend beyond the high boundary, the boundary buffer 132e can store the remainder of the previous iteration. The byte width of the boundary buffer 132e can be determined according to the actual design. For example, assuming the number N of straddle addresses {Cn, OFFn} is 8, the byte width of the boundary buffer 132e can be 7 bytes to store the remainder of the previous iteration.

[0085] The first input of multiplexer 132f is coupled to carrier circuit 132c to receive a portion of the first data element in the current iteration. The second input of multiplexer 132f is coupled to boundary buffer 132e to receive the remainder from previous iterations. The output of multiplexer 132f is coupled to line buffer 132d. When boundary buffer 132e has a remainder, multiplexer 132f selects the remainder from the previous iteration to the lower boundary of line buffer 132d. When boundary buffer 132e has no remainder, multiplexer 132f selects a portion of the first data element to the lower boundary of line buffer 132d.

[0086] by Figure 6 In the illustrated scenario, data elements "C", "B", and "A" are written near the high boundary of line buffer 132d, while the remaining portion "C" exceeds the high boundary. Therefore, the remaining portion "C" is stored in boundary buffer 132e. Upon entering the next iteration, the remaining portion "C" of boundary buffer 132e can be written to the low boundary of line buffer 132d via multiplexer 132f. Line buffer 132d can determine whether to refuse to write data elements provided by carrier circuit 132c to line buffer 132d based on the byte write enable signal byte_we1. For example, suppose the overflow bits ovr8~ovr1 are "11000000", the number of step addresses {Cn,OFFn} N is 8, the byte size M of line buffer 132b (or 132d) is 32, the byte width of boundary buffer 132e is 7 bytes, and the write pointer wr_ptr is 28. Therefore, the byte write enable signal byte_we1 has 39 bits, with 32 bits used for line buffer 132d and the remaining 7 bits used for boundary buffer 132e. Based on the calculations of control circuit 132a, the byte write enable signal byte_we1 is "0000011_11110…0". Therefore, data elements "B" and "A" can be written near the high boundary of line buffer 132d, while data element "C" can be written to boundary buffer 132e.

[0087] Upon completion of the current iteration, the write pointer wr_ptr is updated to point to the new location in the line buffer 132d. For example, control circuit 132a can calculate wr_ptr2 = wr_ptr1 + Σovrbn to update the write pointer wr_ptr, where wr_ptr1 represents the current write pointer wr_ptr, and wr_ptr2 represents the new write pointer wr_ptr. Figure 6 Taking the illustrated scenario as an example, the byte_we1[33:32] (i.e., "1" and "1") of the byte write enable signal byte_we1 will be passed to the next iteration to move the data element "C" in the boundary buffer 132e. Based on the byte_we1[38:32] of the byte write enable signal byte_we1 from the previous iteration, in the next iteration, the first and second bytes of the line buffer 132d will be written to the remaining data element "C" from the previous iteration. The write pointer wr_ptr will be updated to "2" ((28+6)%32=2, i.e., pointing to the third byte position of the line buffer 132d), ready for use in the next iteration. After the line buffer 132d is full, the contents of the line buffer 132d can be dumped to the vector register file 150.

[0088] Figure 7 This is a circuit block diagram of a storage circuit 132 according to another embodiment of the present invention. Figure 7 The memory 10 and vector register file 150 shown can be referenced. Figure 1A The related descriptions of memory 10 and vector register file 150 shown can be extrapolated from this. Figure 7 The storage circuit 132 shown can be referred to Figure 4 The relevant descriptions of the storage circuit 132 shown are analogous and will not be repeated here. Figure 7 The storage circuit 132 shown can be used as Figure 4 This is one of many embodiments of the storage circuit 132 shown.

[0089] exist Figure 7 In the illustrated embodiment, the storage circuit 132 includes a control circuit 132a, a line buffer 132g, a storage circuit 132h, and a line buffer 132i. The line buffer 132g can read multiple elements from the current vector register in the vector register file 150, where these elements include the multiple second data elements. The width of the line buffer 132g can be determined according to the actual design. For example, in some application scenarios, the width of the line buffer 132g can be 32 bytes (256 bits) or other widths. Assuming the width of the line buffer 132g is 32 bytes, the width of the least significant bit LSB1 of the current base address Ab and / or the width of the least significant bit LSB2 of the step ST can be 5 bits to fit the width of the line buffer 132g.

[0090] Control circuit 132a can be coupled to step address generator 131 to receive N step addresses (i.e., {Cn, OFFn}, where n is an integer greater than 0 and less than or equal to N). Control circuit 132a can calculate OVRn = Cn | (MSB2 ≠ 0) to generate N overflow values ​​for the current iteration (this overflow value has N bits, i.e., OVRn, where n is an integer greater than 0 and less than or equal to N). Control circuit 132a can select at least one bit from the overflow values ​​according to the data element length ELEN to generate N overflow bits "ovrn". Control circuit 132a can invert these overflow bits ovrn to generate N inverted overflow bits "ovrbn". Details of control circuit 132a's calculation of the overflow values, overflow bits ovrn, and inverted overflow bits ovrbn can be found in [reference needed]. Figure 5 The relevant descriptions of the control circuit 132a are omitted here. Control circuit 132a can accumulate these inverted overflows ovrbn to generate an accumulated value. Control circuit 132a can update the read pointer rd_ptr based on the accumulated value. For example, control circuit 132a can calculate rd_ptr2 = rd_ptr1 + Σovrbn to update the read pointer rd_ptr, where rd_ptr1 represents the current read pointer, and rd_ptr2 represents the new read pointer.

[0091] Storage circuit 132h is coupled to control circuit 132a to receive a read pointer rd_ptr and N shift values ​​byte_off_n (n is an integer greater than 0 and less than or equal to N). Storage circuit 132h can read the plurality of second data elements from the plurality of elements of line buffer 132g according to the read pointer rd_ptr. Control circuit 132a can combine the nth overflow ovrn and the nth offset value offn to generate the nth shift value byte_off_n (i.e., {ovrn,offn}). For example, control circuit 132a can combine the first overflow ovr1 and the first offset value off1 such that the first shift value byte_off_1 is {ovr1,off1}. Similarly, control circuit 132a can combine the eighth overflow ovr8 and the eighth offset value off8 such that the eighth shift value byte_off_8 is {ovr8,off8}. The storage circuit 132h has M output ports, each with a width of 1 byte. Based on these shift values ​​byte_off_n, the storage circuit 132h can determine which output port to place a corresponding data element from the plurality of second data elements.

[0092] Line buffer 132i is coupled to memory circuit 132h to receive the plurality of second data elements. Based on the nth offset value offn among these offset values, control circuit 132a can shift the nth inverted overflow bit ovrbn (e.g., shift it to the left) to generate a corresponding bit in byte write enable signal byte_we2. For example, assuming the overflow bit ovrn is "0" (i.e., the inverted ovrn is "1") and the offset value offn is 28, then the 29th bit in byte write enable signal byte_we2 (i.e., byte_we2

[28] ) is "1". Line buffer 132i writes these second data elements of line buffer 132i into memory 10 based on byte write enable signal byte_we2 and the most significant bit MSB1 of the current base address Ab.

[0093] Figure 8 This is a circuit block diagram of a storage circuit 132 according to another embodiment of the present invention. Figure 8 In the embodiment shown, the storage circuit 132 includes a line buffer 132g, a storage circuit 132h, a line buffer 132i, a boundary buffer 132j, and a multiplexer 132k. Figure 8 The memory 10 shown can be referenced. Figure 1A The relevant explanations for memory 10 shown can be extrapolated from this. Figure 8 The line buffer 132g, storage circuit 132h, and line buffer 132i shown can be referenced. Figure 7 The descriptions of the line buffer 132g, storage circuit 132h, and line buffer 132i shown are analogous and will not be repeated here. Figure 8 The storage circuit 132h shown can be used as Figure 7 This is one of many embodiments of the storage circuit 132h shown.

[0094] Boundary buffer 132j ​​is coupled to line buffer 132g. Boundary buffer 132j ​​corresponds to the high boundary section of line buffer 132g, such as... Figure 8 As shown. When the read pointer rd_ptr does not point to the high boundary segment, the contents of the high boundary segment are loaded into the boundary buffer 132j. Figure 8 In the operational scenario shown, a data element is assumed to be 2 bytes; however, in other operational scenarios, a data element may have a different width. Figure 8 In the diagram, data elements are labeled as “A”, “B”, “C”, and “D”. Figure 8 In the text, "x" represents non-target data. Figure 8Taking the illustrated operating scenario as an example, data elements "A" and "B" stored in the high boundary section of the line buffer 132g in a previous iteration are copied / backed up to the boundary buffer 132j ​​for use in the current iteration. The first input of the multiplexer 132k is coupled to the high boundary section of the line buffer 132g. The second input of the multiplexer 132k is coupled to the boundary buffer 132j. The output of the multiplexer 132k is coupled to the storage circuit 132h. When the read pointer rd_ptr points to the high boundary section (e.g.) Figure 8 As shown), the multitasking unit 132k can optionally provide the contents of the boundary buffer 132j ​​to the storage circuit 132h.

[0095] exist Figure 8 In the illustrated embodiment, storage circuit 132h includes a multiplexer mux81 and a placement circuit (PLM). The control terminal of the multiplexer mux81 is coupled to control circuit 132a to receive a read pointer rd_ptr. The multiplexer mux81 has M select terminals and one common terminal, where M is an integer and the number of bytes in the line buffer 132g. The data width of the select terminals is one byte, and the data width of the common terminal is N bytes. These select terminals of the multiplexer mux81 are coupled to the line buffer 132g and the multiplexer 132k. For example, assuming N is 8 and M is 32, the bit width of the line buffer 132g is 32. 8 = 256 bits, and the common terminal of the multitasking mux81 has a bit width of 8. 8 = 64 bits. The common bit width of the mux81 multitasker is 8 bytes, and the byte width of the boundary buffer 132j ​​can be 7 bytes. Therefore, the high-order 7 select terminals of the mux81 multitasker are coupled to the output of the multitasker 132k, while the other 25 lower select terminals of the mux81 multitasker are coupled to the low-order 25 bytes of the line buffer 132g.

[0096] The multitasking unit mux81 can select N consecutive bytes from the line buffer 132g and / or boundary buffer 132j, starting from the position pointed to by the read pointer rd_ptr, as the output of the multitasking unit mux81. Figure 8 Taking the illustrated operation scenario as an example, assuming N is 8, M is 32, the data element length ELEN is 2 bytes, and the read pointer rd_ptr is 28, the multitasking mux81 can select eight consecutive selectors (i.e., the 29th, 30th, 31st, 32nd, 1st, 2nd, 3rd, and 4th selectors) from the 32 selectors of the multitasking mux81, starting from the 29th selector corresponding to the read pointer rd_ptr. Therefore, the multitasking mux81 can... Figure 8The data elements “A”, “B”, “C” and “D” of the line buffer 132g and boundary buffer 132j ​​shown are output to the configuration circuit PLM.

[0097] The configuration circuit PLM is coupled to the multiplexer mux81 to receive the output of the multiplexer mux81. The configuration circuit PLM is also coupled to the control circuit 132a to receive multiple shift values, such as... Figure 8 The shift values ​​shown are byte_off_1 to byte_off_8. Based on the nth shift value byte_off_n among these shift values ​​byte_off_1 to byte_off_8, the configuration circuit PLM can select a target byte position from multiple bytes of the line buffer 132i. The configuration circuit PLM can transfer the nth output byte corresponding to the nth shift value byte_off_n in the output of the multiplexer mux81 to the target byte position of the line buffer 132i.

[0098] For example, suppose N is 8, M is 32, the data element length ELEN is 2 bytes, the read pointer rd_ptr is 28, the stride ST is "0b0…000100" (binary), and the current base address Ab is "0b0…0110100" (binary). Therefore, the most significant bit MSB1 and the least significant bit LSB1 of the current base address Ab are "0b0…01" and "0b10100" respectively, while the most significant bit MSB2 and the least significant bit LSB2 of the stride ST are "0b0" and "0b00100" respectively. Based on the calculations of control circuit 132a, the eight overflow bits ovr1 to ovr8 are "0", "0", "0", "0", "0", "0", "1" and "1", and the eight offset values ​​off1 to off8 are "0b10100", "0b10101", "0b11000", "0b11001", "0b11100", "0b11101", "0b00000", and "0b00001" (i.e., decimal "20", "21", "24", "25", "28"). The shift values ​​byte_off_1 to byte_off_8 are “0b0_10100”, “0b0_10101”, “0b0_11000”, “0b0_11001”, “0b0_11100”, “0b0_11101”, “0b1_00000”, and “0b1_00001” (i.e., decimal “20”, “21”, “24”, “25”, “28”, “29”, “32”, and “33”). Based on the shift values ​​byte_off_1 and byte_off_2, the configuration circuit PLM can transfer the data element “A” (the first and second output bytes in the output of the multiplexer mux81) to the 21st and 22nd bytes of the line buffer 132i. Based on shift values ​​byte_off_3 and byte_off_4, the configuration circuit PLM can transfer data element "B" (the 3rd and 4th output bytes of the multiplexer mux81) to the 25th and 26th bytes of the line buffer 132i. Based on shift values ​​byte_off_5 and byte_off_6, the configuration circuit PLM can transfer data element "C" (the 5th and 6th output bytes of the multiplexer mux81) to the 29th and 30th bytes of the line buffer 132i. Because shift values ​​byte_off_7 and byte_off_8 are outside the addressing range of the line buffer 132i, the configuration circuit PLM can discard data element "D" (the 7th and 8th output bytes of the multiplexer mux81).

[0099] The line buffer 132i can write these second data elements of the line buffer 132i into memory 10 based on the byte write enable signal byte_we2 and the most significant bit MSB1 of the current base address Ab. For example, suppose N is 8, M is 32, the data element length ELEN is 2 bytes, the read pointer rd_ptr is 28, the stride ST is "0b0…000100" (binary), and the current base address Ab is "0b0…0110100" (binary). Based on the calculations of control circuit 132a, the eight overflow bits ovr1 to ovr8 are “0”, “0”, “0”, “0”, “0”, “1” and “1”, the eight offset values ​​off1 to off8 are “20”, “21”, “24”, “25”, “28”, “29”, “0” and “1” (decimal), and the byte write enable signal byte_we2 is “0b0011 0011 0011 0000 00000000 0000 0000 (binary, where bit “1” indicates write enable and “0” indicates write disable). Based on the most significant bit MSB1 of the current base address Ab and the byte write enable signal byte_we2, the line buffer 132i can write data elements “A”, “B” and “C” (second data elements) to the addresses {MSB1,20}, {MSB1,21}, {MSB1,24}, {MSB1,25}, {MSB1,28} and {MSB1,29} (decimal) of memory 10.

[0100] Figure 9 This is a circuit block diagram of a storage circuit 132 according to a further embodiment of the present invention. Figure 9 The memory 10 and vector register file 150 shown can be referenced. Figure 1A The related descriptions of memory 10 and vector register file 150 shown can be extrapolated from this. Figure 9 The storage circuit 132 shown can be referred to Figure 4 The relevant descriptions of the storage circuit 132 shown are analogous and will not be repeated here. Figure 9 The storage circuit 132 shown can be used as Figure 4 This is one of many embodiments of the storage circuit 132 shown.

[0101] exist Figure 9In the illustrated embodiment, the memory loading circuit 132 includes a control circuit 132a, a routing circuit 132m, a line buffer 132n, a data processing circuit 132p, a line buffer 132q, and a routing circuit 132r. The routing circuit 132m is coupled to the line buffer 132n. The second routing circuit 132r is coupled to the line buffer 132q. When the memory loading device 130 reads multiple first data elements at multiple non-contiguous addresses in memory 10 (i.e., the memory loading device 130 operates in load mode), the routing circuit 132m couples memory 10 to the line buffer 132n in load mode, and the routing circuit 132r couples the vector register file 150 to the line buffer 132q in load mode. When the memory loading device 130 operates in load mode... Figure 9 The operation of the control circuit 132a shown can be referred to Figure 5 and Figure 6 The description of the control circuit 132a shown is analogous and will not be repeated here. When the storage device 130 writes multiple second data elements to multiple non-contiguous addresses in the memory 10 (i.e., the storage device 130 operates in memory mode), the routing circuit 132m couples the vector register file 150 to the line buffer 132n in memory mode, and the routing circuit 132r couples the memory 10 to the line buffer 132q in memory mode. When the storage device 130 operates in memory mode, Figure 9 The operation of the control circuit 132a shown can be referred to Figure 7 and Figure 8 The relevant descriptions of the control circuit 132a shown are analogous, so they will not be repeated here.

[0102] When memory 10 is coupled to line buffer 132n (load mode), line buffer 132n can read multiple bytes from multiple consecutive addresses in the current iteration based on the most significant bit MSB1 of the current base address Ab. At this time, Figure 9 The operation of the line buffer 132n shown can be referred to Figure 5 The relevant description of the line buffer 132b shown can be used as a reference, or refer to... Figure 6 The description of the line buffer 132b shown is analogous and will not be repeated here. The data processing circuit 132p is coupled to the control circuit 132a to receive N multiplexer selection signals mux_sel_n, N shift values ​​byte_off_n, and a read pointer rd_ptr. In load mode, the data processing circuit 132p can collect the plurality of first data elements from the multiple bytes of the line buffer 132n according to these multiplexer selection signals mux_sel_n. At this time, Figure 9 The operation of the data processing circuit 132p shown can be referred to Figure 5 or Figure 6 The relevant descriptions of the carrier circuit 132c shown are analogous, so they will not be repeated here.

[0103] Line buffer 132q is coupled to data processing circuit 132p to receive the plurality of first data elements in load mode. In load mode, line buffer 132q determines which byte positions of the plurality of first data elements to write to line buffer 132q based on the byte write enable signal byte_we1. At this time, Figure 9 The operation of the line buffer 132q shown can be referred to Figure 5 The relevant description of the line buffer 132d shown can be used as a reference, or refer to... Figure 6 The descriptions of the line buffer 132d, boundary buffer 132e, and multiplexer 132f shown are analogous and will not be repeated here.

[0104] When vector register file 120 is coupled to line buffer 132n (store mode), line buffer 132n reads multiple elements from the current vector register in vector register file 150. At this time, Figure 9 The operation of the line buffer 132n shown can be referred to Figure 7 The relevant specifications for the line buffer 132g shown can be deduced by analogy, or refer to... Figure 8 The descriptions of the line buffer 132g, boundary buffer 132j, and multiplexer 132k shown are analogous and will not be repeated here. In storage mode, the data processing circuit 132p can read the plurality of second data elements from the line buffer 132n according to the read pointer rd_ptr. At this time, Figure 9 The operation of the data processing circuit 132p shown can be referred to Figure 7 or Figure 8 The relevant explanations for the storage circuit 132h shown can be deduced by analogy, so they will not be repeated here.

[0105] Line buffer 132q is coupled to data processing circuit 132p to receive the plurality of second data elements in memory mode. In memory mode, line buffer 132q determines which byte positions of the plurality of second data elements to write to line buffer 132q based on the byte write enable signal byte_we2. At this time, Figure 9 The operation of the line buffer 132q shown can be referred to Figure 7 or Figure 8 The relevant descriptions of the line buffer 132i shown are analogous, so they will not be repeated here.

[0106] Depending on different design requirements, the aforementioned storage device 130, step address generator 131, storage circuit 132, control circuit 132a, storage circuit 132c, storage circuit 132h, and / or data processing circuit 132p can be implemented in hardware, firmware, or a combination of the above. In hardware form, the aforementioned storage device 130, step address generator 131, storage circuit 132, control circuit 132a, storage circuit 132c, storage circuit 132h, and / or data processing circuit 132p can be implemented as logic circuits on an integrated circuit. The functions of the aforementioned storage device 130, step address generator 131, storage circuit 132, control circuit 132a, storage circuit 132c, storage circuit 132h, and / or data processing circuit 132p can be implemented as hardware using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages. For example, the functions of the aforementioned storage device 130, step address generator 131, storage circuit 132, control circuit 132a, storage circuit 132c, storage circuit 132h, and / or data processing circuit 132p can be implemented in various logic blocks, modules, and circuits within one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), and / or other processing units.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A processor adapted to access memory, characterized in that, The processor includes: Vector register file; and A storage device, coupled to the vector register file, is used to perform a stepping operation on the memory, wherein the storage device reads multiple first data elements from multiple non-contiguous addresses in the memory and writes the multiple first data elements into the vector register file in the current iteration of the stepping operation, or the storage device reads multiple second data elements from the vector register file and writes the multiple second data elements respectively to multiple non-contiguous addresses in the memory in the current iteration of the stepping operation. The storage device includes: A step address generator generates multiple step addresses based on the current base address and step size; and A memory loading circuit, coupled to the step address generator, receives the plurality of step addresses, wherein the memory loading circuit reads the plurality of first data elements from the memory and writes the plurality of first data elements into the vector register file based on the current base address and the plurality of step addresses, or the memory loading circuit reads the plurality of second data elements from the vector register file and writes the plurality of second data elements into the memory respectively based on the current base address and the plurality of step addresses. The step address generator calculates... This generates N of the plurality of stride addresses for the current iteration, where N is an integer, n is an integer greater than 0 and less than or equal to N, LSB2 is the least significant bit of the stride, and LSB1 is the least significant bit of the current base address. Let OFFn be the nth step address among the plurality of step addresses, OFFn be the offset part of the nth step address, and Cn be the carry part of the nth step address.

2. The processor according to claim 1, characterized in that, The storage circuit includes: A first line buffer is configured to read multiple bytes from multiple consecutive addresses in the memory based on the most significant bit of the current base address in the current iteration, wherein the multiple bytes include the multiple first data elements; A control circuit, coupled to the step address generator, receives the plurality of step addresses, wherein the control circuit selects at least one of the offset portions of the plurality of step addresses based on the data element length to generate N offset values, and the control circuit generates N multiplexer select signals by rotating these offset values ​​according to a write pointer; and The carrier circuit is coupled to the control circuit to receive these multiplexer selection signals for collecting the plurality of first data elements from the plurality of bytes of the first line buffer based on these multiplexer selection signals.

3. The processor according to claim 2, characterized in that, The storage circuit also includes: A second-line buffer is coupled to the carrier circuit to receive the plurality of first data elements; The control circuit calculates OVRn = Cn | (MSB2 ≠ 0) to generate the overflow value of the current iteration, the overflow value having N bits, MSB2 being the most significant bit of the step size, the | operator being an OR operation, and OVRn being the nth bit in the overflow value. The control circuit selects at least one bit in the overflow value according to the data element length to generate N overflow bits. The control circuit inverts these overflow bits to generate N inverted overflow bits. The control circuit generates a byte write enable signal based on the write pointer shifting these inverted overflow bits. The second line buffer determines which byte positions of the plurality of first data elements to write to the second line buffer based on the byte write enable signal.

4. The processor according to claim 3, characterized in that, The carrier circuit includes: N multiplexers, wherein the control terminal of each of these multiplexers is coupled to the control circuit to receive the corresponding of the multiplexer selection signals, each of these multiplexers has M selection terminals and a common terminal, the data width of any one of these selection terminals and the common terminal is one byte, M is an integer and is the number of bytes in the first line buffer, the selection terminals of each of these multiplexers are coupled to the first line buffer to receive the bytes, the second line buffer includes a plurality of segments, each of the plurality of segments has a data width of N bytes, and the output of the common terminal of these multiplexers is copied to each of the plurality of segments.

5. The processor according to claim 3, characterized in that, The storage circuit also includes: A boundary buffer, coupled to the carrier circuit, is used to store the remaining portions of the previous iteration when a plurality of third data elements from a previous iteration preceding the current iteration are written near the high boundary of the second line buffer, causing the remainders of the plurality of third data elements to extend beyond the high boundary; and A multiplexer has a first input coupled to the carrier circuit to receive a portion of the plurality of first data elements in the current iteration, wherein a second input of the multiplexer is coupled to the boundary buffer to receive the remaining portion of the previous iteration, and an output of the multiplexer is coupled to a second line buffer. When the boundary buffer has the remaining portion, the multiplexer writes the remaining portion of the previous iteration to the low boundary of the second line buffer, and when the boundary buffer does not have the remaining portion, the multiplexer writes the portion of the plurality of first data elements to the low boundary of the second line buffer.

6. The processor according to claim 1, characterized in that, The storage circuit includes: A first line buffer is used to read multiple elements from the current vector register in the vector register stack, wherein the multiple elements include the multiple second data elements; A control circuit, coupled to the step address generator to receive the plurality of step addresses, wherein the control circuit calculates OVRn = Cn | (MSB2 ≠ 0) to generate the overflow value of the current iteration, the overflow value having N bits, MSB2 being the most significant bit of the step size, the | operator being an OR operation, OVRn being the nth bit in the overflow value, the control circuit selecting at least one bit in the overflow value according to the data element length to generate N overflow bits, the control circuit inverting these overflow bits to generate N inverted overflow bits, and the control circuit accumulating these inverted overflow bits to generate an accumulated value; and A storage circuit, coupled to the control circuit, receives a read pointer to read the plurality of second data elements from the plurality of elements of the first line buffer according to the read pointer. The control circuit updates the read pointer based on the accumulated value.

7. The processor according to claim 6, characterized in that, The storage circuit also includes: A boundary buffer, coupled to the first line buffer, wherein the boundary buffer corresponds to a high boundary segment of the first line buffer, and the contents of the high boundary segment are loaded into the boundary buffer when the read pointer is not pointing to the high boundary segment; and A multiplexer has a first input coupled to the high boundary section of the first line buffer, wherein a second input of the multiplexer is coupled to the boundary buffer, an output of the multiplexer is coupled to the storage circuit, and the multiplexer provides the contents of the boundary buffer to the storage circuit when the read pointer points to the high boundary section.

8. The processor according to claim 6, characterized in that, The storage circuit also includes: A second-line buffer is coupled to the storage circuit to receive the plurality of second data elements; The control circuit selects at least one of the offset portions of the plurality of step addresses according to the data element length to generate N offset values, and the control circuit shifts the nth inverted overflow bit among the nth offset value offn to generate the corresponding bit in the byte write enable signal, and the second line buffer writes the plurality of second data elements of the second line buffer into the memory according to the byte write enable signal and the most significant bit portion of the current base address.

9. The processor according to claim 8, characterized in that, The storage circuit includes: A multiplexer, wherein the control terminal of the multiplexer is coupled to the control circuit to receive the read pointer, the multiplexer has M select terminals and a common terminal, where M is an integer and is the number of bytes in the first line buffer, the data width of any one of these select terminals is one byte, the data width of the common terminal is N bytes, the select terminals of the multiplexer are coupled to the first line buffer, and the multiplexer selects N consecutive bytes of the first line buffer as its output, starting from the position pointed to by the read pointer; and A configuration circuit is coupled to the multiplexer to receive the output of the multiplexer, and coupled to the control circuit to receive a plurality of shift values, wherein the configuration circuit selects a target byte position from a plurality of bytes in the second line buffer based on the nth shift value among the plurality of shift values, and the configuration circuit transmits the nth output byte corresponding to the nth shift value in the output of the multiplexer to the target byte position.

10. The processor according to claim 9, characterized in that, The control circuit selects at least one of the offset portions of the plurality of step addresses based on the data element length to generate N offset values, and the control circuit combines the nth overflow ovrn of the plurality of overflows with the nth offset value offn of these offset values ​​to generate the nth shift value of these shift values.

11. The processor according to claim 1, characterized in that, The storage circuit includes: First-line buffer; A first routing circuit is coupled to a first line buffer, wherein the first routing circuit couples the memory to the first line buffer in a load mode, and in the load mode, the first line buffer reads multiple bytes at multiple consecutive addresses in the memory pointed to by the most significant bit of the current base address in the current iteration; the first routing circuit couples the vector register file to the first line buffer in a store mode, and in the store mode, the first line buffer reads multiple elements from the current vector register in the vector register file; A control circuit, coupled to the step address generator to receive the plurality of step addresses, wherein the control circuit selects at least one of the offset portions of the plurality of step addresses according to the data element length to generate N offset values, and the control circuit generates N multiplexer selection signals by rotating the plurality of offset values ​​according to a write pointer, the control circuit calculates OVRn = Cn | (MSB2≠0) to generate the overflow value of the current iteration, the overflow value having N bits, MSB2 being the most significant bit of the step size, the | operator being an OR operation, OVRn being the nth bit in the overflow value, the control circuit selects at least one bit in the overflow value according to the data element length to generate N overflow bits, the control circuit inverts these overflow bits to generate N inverted overflow bits, and the control circuit accumulates these inverted overflow bits to generate an accumulated value; A data processing circuit, coupled to the control circuit, receives these multiplexer selection signals and a read pointer, wherein in the load mode, the data processing circuit collects the plurality of first data elements from the first line buffer according to the multiplexer selection signals, and in the store mode, the data processing circuit reads the plurality of second data elements from the first line buffer according to the read pointer; A second line buffer, coupled to the data processing circuit to receive the plurality of first data elements or the plurality of second data elements, wherein the control circuit generates a first byte write enable signal in the load mode based on shifting these inverted overflow bits by the write pointer; the second line buffer, in the load mode, determines which byte positions of the plurality of first data elements to write to the second line buffer based on the first byte write enable signal; the control circuit, in the memory mode, generates a corresponding bit in the second byte write enable signal by shifting the nth inverted overflow bit by the nth offset value offn; and the second line buffer, in the memory mode, writes the plurality of second data elements of the second line buffer to the memory based on the second byte write enable signal and the most significant bit of the current base address; and A second routing circuit is coupled to the second line buffer, wherein the second routing circuit couples the vector register file to the second line buffer in the load mode, and the second routing circuit couples the memory to the second line buffer in the store mode. The control circuit updates the read pointer based on the accumulated value.

12. A method of operating a processor, characterized in that, The operation method includes: The memory is stepped by the storage device; The storage device reads multiple first data elements from multiple non-contiguous addresses in memory during the current iteration of the stepping operation and writes the multiple first data elements into the vector register file; or the storage device reads multiple second data elements from the vector register file and writes the multiple second data elements into multiple non-contiguous addresses in memory during the current iteration of the stepping operation. The step address generator of the storage device generates multiple step addresses based on the current base address and step size; and The storage circuit of the storage device reads the plurality of first data elements from the memory according to the current base address and the plurality of step addresses and writes the plurality of first data elements into the vector register file; or the storage circuit reads the plurality of second data elements from the vector register file and writes the plurality of second data elements into the memory according to the current base address and the plurality of step addresses; and Calculated by the step address generator The N step addresses of the current iteration are generated, where N is an integer, n is an integer greater than 0 and less than or equal to N, LSB2 is the least significant bit of the step size, LSB1 is the least significant bit of the current base address, {Cn,OFFn} is the nth step address among these step addresses, OFFn is the offset of the nth step address, and Cn is the carry of the nth step address.

13. The operating method according to claim 12, characterized in that, The operation method further includes: The first line buffer of the memory carrying circuit reads multiple bytes from multiple consecutive addresses in the current iteration based on the most significant bit of the current base address, wherein the multiple bytes include the multiple first data elements; The control circuit of the storage circuit selects at least one of the offset portions of the plurality of step addresses according to the data element length to generate N offset values; The control circuit generates N multiplexer selection signals based on the write pointer rotating these offset values; and The carrier circuit of the storage circuit collects the plurality of first data elements from the first line buffer according to these multiplexer selection signals.

14. The operating method according to claim 13, characterized in that, The operation method further includes: The control circuit calculates OVRn = Cn | (MSB2≠0) to generate the overflow of the current iteration, wherein the overflow has N bits, MSB2 is the most significant bit of the step size, the operator | is an OR operation, and OVRn is the nth bit in the overflow. The control circuit selects at least one bit from the overflow value based on the length of the data element to generate N overflow bits; The control circuit inverts these overflows to generate N inverted overflows; The control circuit generates a byte write enable signal based on the inverted overflow bits shifted by the write pointer; The second line buffer of the storage circuit determines which byte positions of the plurality of first data elements to write to the second line buffer based on the byte write enable signal.

15. The operating method according to claim 12, characterized in that, The operation method further includes: The first line buffer of the storage circuit reads multiple elements from the current vector register in the vector register file, wherein the multiple elements include the multiple second data elements; The control circuit of the storage circuit calculates OVRn = Cn | (MSB2≠0) to generate the overflow of the current iteration, wherein the overflow has N bits, MSB2 is the most significant bit of the step size, and the operator | is an OR operation, and OVRn is the nth bit in the overflow. The control circuit selects at least one bit from the overflow value based on the data element length to generate N overflow bits; The control circuit inverts these overflows to generate N inverted overflows, and the control circuit accumulates these inverted overflows to generate an accumulated value. The storage circuit of the storage circuit reads the plurality of second data elements from the plurality of elements of the first line buffer according to the read pointer; and The control circuit updates the read pointer based on the accumulated value.

16. The operating method according to claim 15, characterized in that, The operation method further includes: The control circuit of the storage circuit selects at least one of the offset portions of the plurality of step addresses according to the data element length to generate N offset values; The control circuit shifts the nth inverted overflow bit among these inverted overflow bits according to the nth offset value offn, thereby generating a byte to be written to the corresponding bit in the enable signal; and The second line buffer of the memory-carrying circuit writes the plurality of second data elements of the second line buffer into the memory according to the byte write enable signal and the most significant bit of the current base address.

17. The operating method according to claim 12, characterized in that, The operation method further includes: In load mode, the memory is coupled to the first line buffer of the memory carrying circuit by the first routing circuit of the memory carrying circuit. When the memory is coupled to the first line buffer, the first line buffer reads multiple bytes from multiple consecutive addresses in the memory based on the most significant bit of the current base address in the current iteration; The first routing circuit couples the vector register stack to the first line buffer in storage mode; When the vector register file is coupled to the first line buffer, the first line buffer reads multiple elements from the current vector register in the vector register file; The control circuit of the storage circuit selects at least one of the offset portions of the plurality of step addresses according to the data element length to generate N offset values; The control circuit generates N multiplexer selection signals based on the write pointer rotating these offset values; The control circuit calculates OVRn = Cn | (MSB2≠0) to generate the overflow of the current iteration, wherein the overflow has N bits, MSB2 is the most significant bit of the step size, the operator | is an OR operation, and OVRn is the nth bit in the overflow. The control circuit selects at least one bit from the overflow value based on the length of the data element to generate N overflow bits; The control circuit inverts these overflows to generate N inverted overflows; The control circuit accumulates these inverted overflows to generate an accumulated value. The control circuit generates a first byte write enable signal in the load mode based on the write pointer shifting these inverted overflows; The control circuit, in the storage mode, shifts the nth inverted overflow bit among these offset values ​​(offn) to generate the corresponding bit in the second byte write enable signal. The data processing circuit of the carrying circuit collects the plurality of first data elements from the plurality of bytes of the first line buffer in the carrying mode according to these multiplexer selection signals; The data processing circuit reads the plurality of second data elements from the plurality of elements of the first line buffer according to a read pointer in the storage mode; The second line buffer of the storage circuit determines, in the load mode, which byte positions of the plurality of first data elements will be written to the second line buffer based on the first byte write enable signal; The second line buffer writes the plurality of second data elements of the second line buffer into the memory in the memory mode according to the second byte write enable signal and the most significant bit of the current base address; The second routing circuit of the load circuit couples the vector register stack to the second line buffer in the load mode; The second routing circuit couples the memory to the second line buffer in the storage mode; and The control circuit updates the read pointer based on the accumulated value.

18. A storage device, characterized in that, The storage device includes: A step address generator generates multiple step addresses based on the current base address and step size; and A memory loading circuit, coupled to the step address generator, receives the plurality of step addresses, wherein the memory loading circuit reads a plurality of first data elements from memory based on the current base address and the plurality of step addresses and writes the plurality of first data elements into a vector register file, or the memory loading circuit reads a plurality of second data elements from the vector register file and writes the plurality of second data elements into memory respectively based on the current base address and the plurality of step addresses. The step address generator calculates... The current iteration contains N stride addresses that generate the stride operation, where N is an integer, n is an integer greater than 0 and less than or equal to N, LSB2 is the least significant bit of the stride, LSB1 is the least significant bit of the current base address, {Cn,OFFn} is the nth stride address among the multiple stride addresses, OFFn is the offset of the nth stride address, and Cn is the carry of the nth stride address.

19. The storage device according to claim 18, characterized in that, The storage circuit includes: A first line buffer is configured to read multiple bytes from multiple consecutive addresses in the memory based on the most significant bit of the current base address in the current iteration, wherein the multiple bytes include the multiple first data elements; A control circuit, coupled to the step address generator, receives the plurality of step addresses, wherein the control circuit selects at least one of the offset portions of the plurality of step addresses according to the data element length to generate N offset values, and the control circuit generates N multiplexer selection signals by rotating these offset values ​​according to a write pointer; and The carrier circuit is coupled to the control circuit to receive these multiplexer selection signals for collecting the plurality of first data elements from the bytes of the first line buffer based on these multiplexer selection signals.

20. The storage device according to claim 19, characterized in that, The storage circuit also includes: A second-line buffer is coupled to the carrier circuit to receive the plurality of first data elements; The control circuit calculates OVRn = Cn | (MSB2 ≠ 0) to generate the overflow value of the current iteration, the overflow value having N bits, MSB2 being the most significant bit of the step size, the | operator being an OR operation, and OVRn being the nth bit in the overflow value. The control circuit selects at least one bit in the overflow value according to the data element length to generate N overflow bits. The control circuit inverts these overflow bits to generate N inverted overflow bits. The control circuit generates a byte write enable signal based on the write pointer shifting these inverted overflow bits. The second line buffer determines which byte positions of the plurality of first data elements to write to the second line buffer based on the byte write enable signal.

21. The storage device according to claim 20, characterized in that, The carrier circuit includes: N multiplexers, wherein the control terminal of each of these multiplexers is coupled to the control circuit to receive the corresponding of the multiplexer selection signals, each of these multiplexers has M selection terminals and a common terminal, any one of these selection terminals and the common terminal has a data width of one byte, M is an integer and is the number of bytes in the first line buffer, the selection terminals of each of these multiplexers are coupled to the first line buffer to receive these bytes, the second line buffer includes multiple segments, each of these segments has a data width of N bytes, and the output of the common terminal of these multiplexers is copied to each of these segments.

22. The storage device according to claim 20, characterized in that, The storage circuit also includes: A boundary buffer, coupled to the carrier circuit, is used to store the remaining portions of the previous iteration when a plurality of third data elements from a previous iteration preceding the current iteration are written near the high boundary of the second line buffer, causing the remainders of the plurality of third data elements to extend beyond the high boundary; and A multiplexer has a first input coupled to the carrier circuit to receive a portion of the plurality of first data elements in the current iteration, wherein a second input of the multiplexer is coupled to the boundary buffer to receive the remaining portion of the previous iteration, and an output of the multiplexer is coupled to a second line buffer. When the boundary buffer has the remaining portion, the multiplexer writes the remaining portion of the previous iteration to the low boundary of the second line buffer, and when the boundary buffer does not have the remaining portion, the multiplexer writes the portion of the plurality of first data elements to the low boundary of the second line buffer.

23. The storage device according to claim 18, characterized in that, The storage circuit includes: A first line buffer is used to read multiple elements from the current vector register in the vector register stack, wherein the multiple elements include the multiple second data elements; A control circuit, coupled to the step address generator to receive the plurality of step addresses, wherein the control circuit calculates OVRn = Cn | (MSB2 ≠ 0) to generate the overflow value of the current iteration, the overflow value having N bits, MSB2 being the most significant bit of the step size, the | operator being an OR operation, OVRn being the nth bit in the overflow value, the control circuit selecting at least one bit in the overflow value according to the data element length to generate N overflow bits, the control circuit inverting these overflow bits to generate N inverted overflow bits, and the control circuit accumulating these inverted overflow bits to generate an accumulated value; and A storage circuit, coupled to the control circuit, receives a read pointer for reading the plurality of second data elements from the plurality of elements of the first line buffer according to the read pointer. The control circuit updates the read pointer based on the accumulated value.

24. The storage device according to claim 23, characterized in that, The storage circuit also includes: A boundary buffer, coupled to the first line buffer, wherein the boundary buffer corresponds to a high boundary segment of the first line buffer, and the contents of the high boundary segment are loaded into the boundary buffer when the read pointer is not pointing to the high boundary segment; and A multiplexer has a first input coupled to the high boundary section of the first line buffer, wherein a second input of the multiplexer is coupled to the boundary buffer, an output of the multiplexer is coupled to the storage circuit, and the multiplexer provides the contents of the boundary buffer to the storage circuit when the read pointer points to the high boundary section.

25. The storage device according to claim 23, characterized in that, The storage circuit also includes: A second-line buffer is coupled to the storage circuit to receive the plurality of second data elements; The control circuit selects at least one of the offset portions of the plurality of step addresses according to the data element length to generate N offset values, and the control circuit shifts the nth inverted overflow bit among the nth inverted overflow bit according to the nth offset value offn among these offset values ​​to generate the corresponding bit in the byte write enable signal, and the second line buffer writes the plurality of second data elements of the second line buffer into the memory according to the byte write enable signal and the most significant bit portion of the current base address.

26. The storage device according to claim 25, characterized in that, The storage circuit includes: A multiplexer, wherein the control terminal of the multiplexer is coupled to the control circuit to receive the read pointer, the multiplexer has M select terminals and a common terminal, M being an integer and the number of bytes in the first line buffer, the data width of any one of the multiple select terminals is one byte, the data width of the common terminal is N bytes, the multiple select terminals of the multiplexer are coupled to the first line buffer, and the multiplexer selects N consecutive bytes of the first line buffer as its output, starting from the position pointed to by the read pointer; and A configuration circuit is coupled to the multiplexer to receive the output of the multiplexer, and coupled to the control circuit to receive a plurality of shift values, wherein the configuration circuit selects a target byte position from a plurality of bytes in the second line buffer based on the nth shift value among the plurality of shift values, and the configuration circuit transmits the nth output byte corresponding to the nth shift value in the output of the multiplexer to the target byte position.

27. The storage device according to claim 26, characterized in that, The control circuit selects at least one of the offset portions of the plurality of step addresses based on the data element length to generate N offset values, and the control circuit combines the nth overflow ovrn of these overflows with the nth offset value offn of these offset values ​​to generate the nth shift value of these shift values.

28. The storage device according to claim 18, characterized in that, The storage circuit includes: First-line buffer; A first routing circuit is coupled to a first line buffer, wherein the first routing circuit couples the memory to the first line buffer in a load mode, and in the load mode, the first line buffer reads multiple bytes from multiple consecutive addresses in the memory based on the most significant bit of the current base address in the current iteration; the first routing circuit couples the vector register file to the first line buffer in a store mode, and in the store mode, the first line buffer reads multiple elements from the current vector register in the vector register file; A control circuit, coupled to the step address generator to receive these step addresses, wherein the control circuit selects at least one of the offset portions of these step addresses according to the data element length to generate N offset values, and the control circuit generates N multiplexer selection signals by rotating these offset values ​​according to the write pointer, the control circuit calculates OVRn = Cn | (MSB2 ≠ 0) to generate the overflow value of the current iteration, the overflow value having N bits, MSB2 being the most significant bit of the step size, the operator | being an OR operation, OVRn being the nth bit in the overflow value, the control circuit selects at least one bit in the overflow value according to the data element length to generate N overflow bits, the control circuit inverts these overflow bits to generate N inverted overflow bits, and the control circuit accumulates these inverted overflow bits to generate an accumulated value; A data processing circuit, coupled to the control circuit, receives these multiplexer selection signals and a read pointer, wherein in the load mode, the data processing circuit collects the plurality of first data elements from the bytes of the first line buffer according to the multiplexer selection signals, and in the store mode, the data processing circuit reads the plurality of second data elements from the plurality of elements of the first line buffer according to the read pointer. A second line buffer, coupled to the data processing circuit to receive the plurality of first data elements or the plurality of second data elements, wherein the control circuit generates a first byte write enable signal in the load mode based on the write pointer shifting the plurality of inverted overflow bits; the second line buffer, in the load mode, determines which byte positions of the plurality of first data elements to write to the second line buffer based on the first byte write enable signal; the control circuit, in the store mode, generates a corresponding bit in the second byte write enable signal by shifting the nth inverted overflow bit of the plurality of inverted overflow bits based on the nth offset value offn of the plurality of offset values; and the second line buffer, in the store mode, writes the plurality of second data elements of the second line buffer into the memory based on the second byte write enable signal and the most significant bit of the current base address; and A second routing circuit is coupled to the second line buffer, wherein the second routing circuit couples the vector register file to the second line buffer in the load mode, and the second routing circuit couples the memory to the second line buffer in the store mode. The control circuit updates the read pointer based on the accumulated value.

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