Heterojunction battery and preparation method thereof

Abstract

The present invention discloses a heterojunction battery and a method for manufacturing the same. The method comprises the following steps: forming intrinsic amorphous silicon layers on the front and back sides of an N-type silicon substrate; forming an N-type doped layer on the front intrinsic amorphous silicon layer; forming a P-type doped layer on the back intrinsic amorphous silicon layer; forming a metal aluminum thin film seed layer, an indium-free transparent conductive thin film layer, and a metal aluminum thin film intermediate layer on the P-type doped layer and the N-type doped layer, respectively; forming an indium-based transparent conductive oxide thin film layer or an indium-free transparent conductive oxide thin film layer on each metal aluminum thin film intermediate layer; forming metal electrodes on the indium-based transparent conductive oxide thin film layer; or forming a protective layer on the indium-free transparent conductive oxide thin film layer, and forming metal electrodes on the protective layer; the metal electrodes extending to the corresponding metal aluminum thin film intermediate layer. The present invention significantly reduces manufacturing and processing costs and meets reliability requirements.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a heterojunction battery and a preparation method thereof. Background Art

[0002] Silicon heterojunction (SHJ) technology achieved a record-breaking efficiency of 26.81%, also a record for crystalline silicon cell efficiency. SHJ cells are N-type bifacial cells characterized by a simple process, high efficiency, low temperature coefficient, low temperature operation throughout, and energy savings. They are also free of LID and LeTID degradation issues. SHJ cells also offer numerous advantages, including suitability for thin-film production and excellent low-light response. Silicon heterojunction solar cells use crystalline silicon as the absorption layer. Photons are absorbed to generate electron-hole pairs. Holes travel through the intrinsic passivation layer and p-type doped layer to the metal electrode for hole collection. Electrons travel through the intrinsic passivation layer and n-type doped layer to the metal electrode for electron collection, generating a photocurrent.

[0003] Traditional heterojunction cell structures utilize intrinsic amorphous silicon passivation on both sides, with doped amorphous silicon or microcrystalline silicon serving as the emitter and back field electrode. Double-sided ITO serves as an anti-reflection and conductive film, and metal electrodes are formed by screen printing or copper electroplating. While indium oxide (In2O3)-based transparent conductive oxides (TCOs), commonly used in existing heterojunction (HJT) cells, exhibit excellent optoelectronic properties and can be used to fabricate high-efficiency HJT cells, indium is a rare metal with limited reserves and high price. The cost of indium-based TCOs accounts for approximately 10-15% of the non-silicon cost of HJT cells, second only to low-temperature silver paste. Existing indium-free materials studied and reported primarily include ZnO, AZO, GZO, GAZO, and SnO2. However, these indium-free materials, compared to indium-based transparent conductive materials, suffer from inferior optical transmittance, electrical conductivity, or both optical and electrical performance. Furthermore, they also face challenges with weather resistance, which is a major obstacle to their application in HJT cells. Summary of the Invention

[0004] Based on this, it is necessary to provide a method for preparing a heterojunction battery. The method of preparing a heterojunction battery of the present invention can promote the crystallization of the indium-free TCO material after film formation, reduce its resistivity, improve its transmittance, and thus significantly improve the photoelectric conversion efficiency of the indium-free heterojunction battery. At the same time, the indium-free TCO material is superimposed with an anti-reflection protective layer, which can not only further increase the utilization rate of incident light, but also solve the reliability problem.

[0005] An embodiment of the present application provides a method for preparing a heterojunction battery.

[0006] A method for preparing a heterojunction battery comprises the following steps:

[0007] Providing an N-type silicon substrate;

[0008] preparing intrinsic amorphous silicon layers on the front and back sides of the N-type silicon substrate respectively;

[0009] preparing an N-type doped layer on the front intrinsic amorphous silicon layer;

[0010] preparing a P-type doped layer on the intrinsic amorphous silicon layer on the back side;

[0011] Sequentially preparing a metal aluminum thin film seed layer, an indium-free transparent conductive thin film layer, and a metal aluminum thin film intermediate layer on the P-type doped layer;

[0012] Sequentially preparing a metal aluminum thin film seed layer, an indium-free transparent conductive thin film layer, and a metal aluminum thin film intermediate layer on the N-type doped layer;

[0013] preparing an indium-based transparent conductive oxide thin film layer or an indium-free transparent conductive oxide thin film layer on each of the metal aluminum thin film intermediate layers;

[0014] Metal electrodes are respectively prepared on the indium-based transparent conductive oxide film layer; or a protective layer is respectively prepared on the indium-free transparent conductive oxide film layer, and a metal electrode is prepared on the protective layer; the metal electrode extends to the corresponding metal aluminum film intermediate layer.

[0015] In some embodiments, providing an N-type silicon substrate specifically includes the following steps:

[0016] Providing an N-type single crystal silicon wafer, and performing a gettering process on the N-type single crystal silicon wafer using a high-temperature furnace tube or a chain-type gettering device, wherein the sheet resistance of the N-type single crystal silicon wafer after gettering is 20Ω / □ to 40Ω / □;

[0017] The PSG layer on the surface of the N-type single crystal silicon wafer is removed using a wet acid solution, and the N-type single crystal silicon wafer is polished and textured using an alkaline solution to form the N-type silicon substrate with a pyramid-shaped surface light trapping structure.

[0018] In some embodiments, the thickness of the N-type single crystal silicon wafer is 60 μm to 180 μm;

[0019] And / or, the resistivity of the N-type single crystal silicon wafer is 0.2Ω.cm to 3Ω.cm.

[0020] In some embodiments, when the intrinsic amorphous silicon layer is respectively prepared on the front side and the back side of the N-type silicon substrate, the following steps are specifically included:

[0021] The intrinsic amorphous silicon layer is deposited by a radio frequency plasma enhanced chemical vapor deposition (RF-PECVD) system, and the required process gases include one or more of SiH4, H2, CO2, CH4 and N2O. The deposition temperature is 160°C to 210°C, and the deposition pressure is 0.2mbar to 2mbar.

[0022] In some embodiments, the thickness of the intrinsic amorphous silicon layer is 2 nm to 10 nm.

[0023] In some embodiments, when forming an N-type doped layer on the front intrinsic amorphous silicon layer, the following steps are specifically included:

[0024] The N-type doped layer is deposited on the intrinsic amorphous silicon layer by very high frequency plasma enhanced chemical vapor deposition (VHF-PECVD) equipment. The required process gases include one or more of SiH4, H2, CO2, CH4, N2O and PH3. The deposition temperature is 160°C to 210°C and the deposition pressure is 0.5mbar to 5mbar.

[0025] In some embodiments, the thickness of the N-type doped layer is 5 nm to 20 nm.

[0026] In some embodiments, when preparing a P-type doped layer on the back intrinsic amorphous silicon layer, the following steps are specifically included:

[0027] The P-type doping layer is deposited on the N-type doping layer by a very high frequency plasma enhanced chemical vapor deposition (VHF-PECVD) device; the required process gases include one or more of SiH4, H2, CO2, CH4, N2O, B2H6 and TMB, the deposition temperature is 160°C to 210°C, and the deposition pressure is 0.5mbar to 5mbar.

[0028] In some embodiments, the thickness of the P-type doped layer is 5 nm to 30 nm.

[0029] In some embodiments, when a metal aluminum thin film seed layer, an indium-free transparent conductive thin film layer, and a metal aluminum thin film intermediate layer are sequentially prepared on the P-type doped layer, the steps specifically include:

[0030] Depositing a metal aluminum thin film seed layer on the P-type doped layer; the thickness of the metal aluminum thin film seed layer is 1nm to 10nm, the deposition temperature is 0 to 200°C, and the power is 1KW to 10KW;

[0031] Depositing an indium-free transparent conductive film layer on the metal aluminum film seed layer; the indium-free transparent conductive film layer has a thickness of 20 nm to 50 nm, a deposition temperature of 0 to 200° C., and a power of 1 kW to 8 kW;

[0032] A metal aluminum film intermediate layer is deposited on the indium-free transparent conductive film layer; the thickness of the metal aluminum film intermediate layer is 1nm to 10nm, the deposition temperature is 0 to 200°C, and the power is 1KW to 10KW.

[0033] In some embodiments, when a metal aluminum thin film seed layer, an indium-free transparent conductive thin film layer, and a metal aluminum thin film intermediate layer are sequentially prepared on the N-type doped layer, the steps specifically include:

[0034] Depositing a metal aluminum thin film seed layer on the N-type doped layer; the thickness of the metal aluminum thin film seed layer is 1nm to 10nm, the deposition temperature is 0 to 200°C, and the power is 1KW to 10KW;

[0035] Depositing an indium-free transparent conductive film layer on the metal aluminum film seed layer; the indium-free transparent conductive film layer has a thickness of 20 nm to 50 nm, a deposition temperature of 0 to 200° C., and a power of 1 kW to 8 kW;

[0036] A metal aluminum film intermediate layer is deposited on the indium-free transparent conductive film layer; the thickness of the metal aluminum film intermediate layer is 1nm to 10nm, the deposition temperature is 0 to 200°C, and the power is 1KW to 10KW.

[0037] In some embodiments, the indium-free transparent conductive film layer is ZnO-based doped with one or more of Ga, Al, and B elements, or SnO2 doped with one or more of F and Hf elements.

[0038] In some embodiments, the indium-based transparent conductive oxide thin film layer is In2O3 doped with one or more of Ga, Ti, Ce, W, Mo, Ca, and Zr, and the proportion of the doping elements is 0-10%.

[0039] In some embodiments, when an indium-based transparent conductive oxide thin film layer is prepared on each of the metal aluminum thin film intermediate layers, the deposition temperature is 0 to 200° C., the power is 1 KW to 10 KW, and the thickness of the indium-based transparent conductive oxide thin film layer is 20 nm to 50 nm;

[0040] And / or, when preparing indium-free transparent conductive oxide thin film layers on each of the metal aluminum thin film intermediate layers, the deposition temperature is 0-200° C., the power is 1KW-8KW, and the thickness of the indium-free transparent conductive oxide thin film layer is 20nm-50nm.

[0041] In some embodiments, when a protective layer is separately prepared on the indium-free transparent conductive oxide thin film layer, the following steps are specifically included:

[0042] Using a low-temperature CVD device at a deposition temperature of ≤200° C., the protective layer is respectively prepared on each of the indium-free transparent conductive oxide thin film layers;

[0043] And / or, the thickness of the protective layer is 5 nm to 30 nm.

[0044] In some embodiments, the protective layer is one or more of silicon nitride, silicon oxynitride, and silicon oxide films.

[0045] In some embodiments, when metal electrodes are prepared on the indium-based transparent conductive oxide thin film layer, the following steps are specifically included:

[0046] The metal electrode is prepared by screen printing, laser transfer of low-temperature silver paste, low-temperature copper paste or silver-coated copper paste;

[0047] Alternatively, the metal electrode is prepared by electroplating one or more alloys of Al, Ti, Ni, Co, Ag, Cu and Sn.

[0048] In some embodiments, when preparing a metal electrode on the protective layer, the following steps are specifically included:

[0049] Using an acid-resistant mask combined with an exposure technique to form patterned masks on the front and back surfaces, respectively, using a 3%-10% HF solution to remove the protective layer in the unmasked area, and then using an alkaline solution to remove the patterned mask;

[0050] The metal electrode is prepared by screen printing, laser transfer of low-temperature silver paste, low-temperature copper paste or silver-coated copper paste; or, the metal electrode is prepared by electroplating one or more alloys of Al, Ti, Ni, Co, Ag, Cu and Sn.

[0051] In some embodiments, the N-type doped layer is N-type doped amorphous silicon or microcrystalline silicon, and the P-type doped layer is P-type doped amorphous silicon or microcrystalline silicon.

[0052] An embodiment of the present application also provides a heterojunction battery.

[0053] A heterojunction battery is prepared using the preparation method.

[0054] The above-mentioned heterojunction battery preparation method is optimized through the combination of equipment and process. Based on the existing mature industrial-grade PVD physical vapor deposition equipment, a metal aluminum coating cavity is rationally designed to be added. The metal aluminum film is used as a seed layer and intermediate layer, thereby promoting the crystallization of the subsequent indium-free TCO thin film material after deposition, reducing two types of carrier scattering, grain boundary scattering and phonon scattering, thereby improving the thin film carrier mobility, and then improving the carrier mobility of the indium-free TCO. According to the formula ρ = 1 / eN*μ, the increase in mobility can significantly reduce the film resistivity and improve the battery fill factor FF. At the same time, the high degree of crystallization of the TCO film can also improve the optical transmittance. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0056] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings. In the following description, the same reference numerals represent the same parts.

[0057] Figure 1 Schematic diagram of a method for preparing a heterojunction battery according to an embodiment of the present invention;

[0058] Figure 2 This is a schematic diagram of the heterojunction battery structure according to Example 1 of the present invention;

[0059] Figure 3 This is a schematic diagram of the heterojunction battery structure described in Example 2 of the present invention.

[0060] Description of Reference Numerals

[0061] 10. Heterojunction cell structure; 100. N-type silicon substrate; 200. Intrinsic amorphous silicon layer; 300. N-type doped layer; 400. P-type doped layer; 500. Metal aluminum film seed layer; 600. Indium-free transparent conductive film layer; 700. Metal aluminum film intermediate layer; 800. Indium-based transparent conductive oxide film layer; 900. Indium-free transparent conductive oxide film layer; 1000. Protective layer; 1100. Metal electrode. DETAILED DESCRIPTION

[0062] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth numerous specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0063] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0064] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0065] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0066] In the description of the present invention, "several" means more than one, "plurality" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0068] The present invention provides a method for preparing a heterojunction battery to address the problem that conventional indium-free materials, such as ZnO, AZO, GZO, GAZO, and SnO2, have limited optical transmittance, electrical conductivity, and weather resistance, limiting their application in heterojunction batteries. The following describes the method for preparing a heterojunction battery with reference to the accompanying figures.

[0069] The preparation method of the heterojunction battery provided in the embodiment of the present application is exemplary, please refer to Figure 1 As shown, Figure 1 A schematic diagram of the structure of the method for preparing a heterojunction battery provided in an embodiment of the present application. In order to more clearly illustrate the structure of the method for preparing a heterojunction battery, the method for preparing a heterojunction battery will be introduced below in conjunction with the accompanying drawings.

[0070] For example, see Figure 1 As shown, a method for preparing a heterojunction battery includes the following steps:

[0071] Providing an N-type silicon substrate 100;

[0072] Intrinsic amorphous silicon layers 200 are formed on the front and back surfaces of the N-type silicon substrate 100;

[0073] An N-type doped layer 300 is formed on the front intrinsic amorphous silicon layer 200 ;

[0074] A P-type doped layer 400 is formed on the intrinsic amorphous silicon layer 200 at the back side;

[0075] A metal aluminum thin film seed layer 500, an indium-free transparent conductive thin film layer 600, and a metal aluminum thin film intermediate layer 700 are sequentially formed on the P-type doped layer 400;

[0076] A metal aluminum thin film seed layer 500, an indium-free transparent conductive thin film layer 600, and a metal aluminum thin film intermediate layer 700 are sequentially formed on the N-type doped layer 300;

[0077] An indium-based transparent conductive oxide thin film layer 800 or an indium-free transparent conductive oxide thin film layer 900 is respectively formed on each metal aluminum thin film intermediate layer 700;

[0078] Metal electrodes 1100 are respectively prepared on the indium-based transparent conductive oxide film layer 800; or a protective layer 1000 is respectively prepared on the indium-free transparent conductive oxide film layer 900, and a metal electrode 1100 is prepared on the protective layer 1000; the metal electrode 1100 extends to the corresponding metal aluminum film intermediate layer 700.

[0079] The above-mentioned preparation method of heterojunction battery is optimized by combining equipment and process. On the basis of existing mature industrial-grade PVD physical vapor deposition equipment, a metal aluminum coating cavity is rationally designed and added. The metal aluminum film is used as a seed layer and an intermediate layer to promote the crystallization of the subsequent indium-free TCO thin film material after deposition, reduce the two types of carrier scattering, grain boundary scattering and phonon scattering, thereby improving the carrier mobility of the thin film, and then improving the carrier mobility of the indium-free TCO. According to the formula ρ = 1 / eN*μ, the improvement of mobility can significantly reduce the resistivity of the film and improve the battery fill factor FF. At the same time, the high degree of crystallization of the TCO film can also improve the optical transmittance. On the other hand, the insertion of the metal aluminum film also greatly reduces the resistivity of the entire film. Finally, two heterojunction battery structures with low indium and indium-free are formed10:

[0080] Low indium heterojunction battery: low indium heterojunction battery with Al+TCO1 (indium-free TCO) + Al+TCO2 (indium-based TCO) composite film structure.

[0081] Indium-free heterojunction battery: Al+TCO1 (indium-free TCO) + Al+TCO2 (indium-free TCO) + SiN / SiO / SiON composite film structure protective layer.

[0082] In some embodiments, providing the N-type silicon substrate 100 specifically includes the following steps:

[0083] Provide N-type single crystal silicon wafers, and use high-temperature furnace tubes or chain-type impurity gettering equipment to getter the N-type single crystal silicon wafers. After gettering, the sheet resistance of the N-type single crystal silicon wafers is 20Ω / □~40Ω / □;

[0084] The PSG layer on the surface of the N-type single crystal silicon wafer is removed using a wet acid solution, and the N-type single crystal silicon wafer is polished and textured using an alkaline solution to form an N-type silicon substrate 100 with a pyramid-shaped surface light trapping structure.

[0085] In some embodiments, the thickness of the N-type single crystal silicon wafer is 60 μm to 180 μm;

[0086] And / or, the resistivity of the N-type single crystal silicon wafer is 0.2Ω.cm to 3Ω.cm.

[0087] In some embodiments, when the intrinsic amorphous silicon layer 200 is formed on the front and back sides of the N-type silicon substrate 100, the following steps are specifically included:

[0088] The intrinsic amorphous silicon layer 200 is deposited by a radio frequency plasma enhanced chemical vapor deposition (RF-PECVD) system, and the required process gases include one or more of SiH4, H2, CO2, CH4 and N2O. The deposition temperature is 160°C to 210°C, and the deposition pressure is 0.2mbar to 2mbar.

[0089] In some embodiments, the thickness of the intrinsic amorphous silicon layer 200 is 2 nm to 10 nm.

[0090] In some embodiments, the N-type doped layer 300 is formed on the front intrinsic amorphous silicon layer 200 , specifically including the following steps:

[0091] An N-type doped layer 300 is deposited on the intrinsic amorphous silicon layer 200 by Very High Frequency Plasma Enhanced Chemical Vapor Deposition (VHF-PECVD). The required process gases include one or more of SiH4, H2, CO2, CH4, N2O and PH3. The deposition temperature is 160°C to 210°C and the deposition pressure is 0.5mbar to 5mbar.

[0092] In some embodiments, the thickness of the N-type doped layer 300 is 5 nm to 20 nm.

[0093] In some embodiments, the preparation of the P-type doped layer 400 on the back intrinsic amorphous silicon layer 200 specifically includes the following steps:

[0094] A P-type doped layer 400 is deposited on the N-type doped layer 300 by a very high frequency plasma enhanced chemical vapor deposition (VHF-PECVD) device; the required process gases include one or more of SiH4, H2, CO2, CH4, N2O, B2H6 and TMB, the deposition temperature is 160°C to 210°C, and the deposition pressure is 0.5mbar to 5mbar.

[0095] In some embodiments, the thickness of the P-type doped layer 400 is 5 nm to 30 nm.

[0096] In some embodiments, the following steps are specifically included when sequentially forming the metal aluminum thin film seed layer 500, the indium-free transparent conductive thin film layer 600, and the metal aluminum thin film intermediate layer 700 on the P-type doped layer 400:

[0097] Depositing a metal aluminum thin film seed layer 500 on the P-type doped layer 400; the thickness of the metal aluminum thin film seed layer 500 is 1 nm to 10 nm, the deposition temperature is 0 to 200° C., and the power is 1 KW to 10 KW;

[0098] Depositing an indium-free transparent conductive film layer 600 on the metal aluminum film seed layer 500; the thickness of the indium-free transparent conductive film layer 600 is 20 nm to 50 nm, the deposition temperature is 0 to 200° C., and the power is 1 KW to 8 KW;

[0099] A metal aluminum thin film intermediate layer 700 is deposited on the indium-free transparent conductive thin film layer 600; the thickness of the metal aluminum thin film intermediate layer 700 is 1 nm to 10 nm, the deposition temperature is 0 to 200° C., and the power is 1 KW to 10 KW.

[0100] In some embodiments, the following steps are specifically included when sequentially forming the metal aluminum thin film seed layer 500, the indium-free transparent conductive thin film layer 600, and the metal aluminum thin film intermediate layer 700 on the N-type doped layer 300:

[0101] Depositing a metal aluminum thin film seed layer 500 on the N-type doped layer 300; the thickness of the metal aluminum thin film seed layer 500 is 1 nm to 10 nm, the deposition temperature is 0 to 200° C., and the power is 1 KW to 10 KW;

[0102] Depositing an indium-free transparent conductive film layer 600 on the metal aluminum film seed layer 500; the thickness of the indium-free transparent conductive film layer 600 is 20 nm to 50 nm, the deposition temperature is 0 to 200° C., and the power is 1 KW to 8 KW;

[0103] A metal aluminum thin film intermediate layer 700 is deposited on the indium-free transparent conductive thin film layer 600; the thickness of the metal aluminum thin film intermediate layer 700 is 1 nm to 10 nm, the deposition temperature is 0 to 200° C., and the power is 1 KW to 10 KW.

[0104] In some embodiments, the indium-free transparent conductive film layer 600 is a ZnO-based film doped with one or more of Ga, Al, and B elements, or SnO2 doped with one or more of F and Hf elements. Preferably, the indium-free transparent conductive film layer 600 is a Ga and Al co-doped GAZO film, because Ga 3+ With Zn 2+ With similar ionic radius, gallium doping can reduce lattice distortion, and Ga is less active than Al. When exposed to a humid atmosphere, Ga-doped ZnO has better electrical stability than AZO.

[0105] In some embodiments, the indium-based transparent conductive oxide thin film layer 800 is mainly composed of In2O3, and In2O3 is doped with one or more elements such as Ga, Ti, Ce, W, Mo, Ca, and Zr, and the proportion of the doped elements is 0-10%.

[0106] In some embodiments, when an indium-based transparent conductive oxide thin film layer 800 is formed on each metal aluminum thin film intermediate layer 700, the deposition temperature is 0 to 200°C, the power is 1 KW to 10 KW, and the thickness of the indium-based transparent conductive oxide thin film layer 800 is 20 nm to 50 nm.

[0107] And / or, when preparing the indium-free transparent conductive oxide thin film layer 900 on each metal aluminum thin film intermediate layer 700, the deposition temperature is 0-200°C, the power is 1KW-8KW, and the thickness of the indium-free transparent conductive oxide thin film layer 900 is 20nm-50nm.

[0108] In some embodiments, the protective layer 1000 is prepared on the indium-free transparent conductive oxide thin film layer 900, and the steps include:

[0109] A protective layer 1000 is formed on each of the indium-free transparent conductive oxide thin film layers 900 using a low-temperature CVD device at a deposition temperature of ≤200° C.;

[0110] And / or, the thickness of the protective layer 1000 is 5 nm to 30 nm.

[0111] In some embodiments, the protective layer 1000 is one or more of silicon nitride, silicon oxynitride, and silicon oxide films.

[0112] In some embodiments, the steps of preparing the metal electrodes 1100 on the indium-based transparent conductive oxide thin film layer 800 include:

[0113] The metal electrode 1100 is prepared by screen printing, laser transfer of low-temperature silver paste, low-temperature copper paste or silver-coated copper paste;

[0114] Alternatively, the metal electrode 1100 is prepared by electroplating one or more alloys of Al, Ti, Ni, Co, Ag, Cu and Sn.

[0115] In some embodiments, the process of preparing the metal electrode 1100 on the protective layer 1000 specifically includes the following steps:

[0116] A patterned mask is formed on the front and back surfaces respectively using an acid-resistant mask combined with an exposure technique, and the protective layer 1000 in the unmasked area is removed using a 3%-10% HF solution, and then the patterned mask is removed using an alkaline solution;

[0117] The metal electrode 1100 is prepared by screen printing, laser transfer of low-temperature silver paste, low-temperature copper paste or silver-coated copper paste; or, the metal electrode 1100 is prepared by electroplating one or more alloys of Al, Ti, Ni, Co, Ag, Cu and Sn.

[0118] In some embodiments, the N-type doped layer 300 is N-type doped amorphous silicon or microcrystalline silicon, and the P-type doped layer 400 is P-type doped amorphous silicon or microcrystalline silicon.

[0119] An embodiment of the present application also provides a heterojunction battery.

[0120] A heterojunction battery is prepared using a preparation method.

[0121] Example 1

[0122] This embodiment provides a heterojunction battery, which is prepared by the following preparation method.

[0123] A method for preparing a heterojunction battery comprises the following steps:

[0124] (1) Providing an N-type silicon substrate 100; specifically comprising the following steps: providing an N-type single crystal silicon wafer, the N-type single crystal silicon wafer having a thickness of 60 μm; the N-type single crystal silicon wafer having a resistivity of 0.2 Ω.cm to 3 Ω.cm. Using a high-temperature furnace tube or chain-type impurity gettering equipment to perform impurity gettering on the N-type single crystal silicon wafer, the sheet resistance of the N-type single crystal silicon wafer after impurity gettering being 20 Ω / □;

[0125] The PSG layer on the surface of the N-type single crystal silicon wafer is removed using a wet acid solution, and the N-type single crystal silicon wafer is polished and textured using an alkaline solution to form an N-type silicon substrate 100 with a pyramid-shaped surface light trapping structure.

[0126] (2) Intrinsic amorphous silicon layers 200 are formed on the front and back surfaces of the N-type silicon substrate 100. Specifically, the following steps are included: The intrinsic amorphous silicon layer 200 is deposited by an RF-PECVD process using SiH4 as the process gas, at a deposition temperature of 160°C and a deposition pressure of 0.2 mbar. The thickness of the intrinsic amorphous silicon layer 200 is 2 nm.

[0127] (3) Preparing an N-type doped layer 300 on the front intrinsic amorphous silicon layer 200. The N-type doped layer 300 is N-type doped amorphous silicon or microcrystalline silicon. Specifically, the N-type doped layer 300 is deposited on the intrinsic amorphous silicon layer 200 by a VHF-PECVD process. The process gas required for the VHF-PECVD process includes SiH4, the deposition temperature is 160°C, and the deposition pressure is 0.5 mbar. The thickness of the N-type doped layer 300 is 5 nm.

[0128] (4) Preparing a P-type doped layer 400 on the back intrinsic amorphous silicon layer 200. The P-type doped layer 400 is P-type doped amorphous silicon or microcrystalline silicon. The process comprises the following steps: depositing the P-type doped layer 400 on the N-type doped layer 300 by a VHF-PECVD process; the process gas required for the VHF-PECVD process includes SiH4, the deposition temperature is 160°C, and the deposition pressure is 0.5 mbar. The thickness of the P-type doped layer 400 is 5 nm.

[0129] (5) A metal aluminum film seed layer 500, an indium-free transparent conductive film layer 600, and a metal aluminum film intermediate layer 700 are sequentially prepared on the P-type doped layer 400; specifically, the following steps are included: depositing a metal aluminum film seed layer 500 on the P-type doped layer 400; the thickness of the metal aluminum film seed layer 500 is 1 nm, the deposition temperature is 50°C, and the power is 1 KW; depositing an indium-free transparent conductive film layer 600 on the metal aluminum film seed layer 500; the thickness of the indium-free transparent conductive film layer 600 is 20 nm, the deposition temperature is 50°C, and the power is 1 KW; depositing a metal aluminum film intermediate layer 700 on the indium-free transparent conductive film layer 600; the thickness of the metal aluminum film intermediate layer 700 is 1 nm, the deposition temperature is 50°C, and the power is 1 KW.

[0130] (6) A metal aluminum film seed layer 500, an indium-free transparent conductive film layer 600, and a metal aluminum film intermediate layer 700 are sequentially prepared on the N-type doped layer 300; specifically, the following steps are included: depositing a metal aluminum film seed layer 500 on the N-type doped layer 300; the thickness of the metal aluminum film seed layer 500 is 1 nm, the deposition temperature is 50°C, and the power is 1 KW; depositing an indium-free transparent conductive film layer 600 on the metal aluminum film seed layer 500; the thickness of the indium-free transparent conductive film layer 600 is 20 nm, the deposition temperature is 50°C, and the power is 1 KW; depositing a metal aluminum film intermediate layer 700 on the indium-free transparent conductive film layer 600; the thickness of the metal aluminum film intermediate layer 700 is 1 nm, the deposition temperature is 50°C, and the power is 1 KW.

[0131] (7) An indium-based transparent conductive oxide thin film layer 800 is prepared on each metal aluminum thin film intermediate layer 700, with a deposition temperature of 50°C and a power of 1 kW. The thickness of the indium-based transparent conductive oxide thin film layer 800 is 20 nm. The indium-based transparent conductive oxide thin film layer 800 is a Ga-doped In2O3 thin film.

[0132] (8) Metal electrodes 1100 are prepared on the indium-based transparent conductive oxide thin film layer 800. The process specifically includes the following steps: preparing the metal electrodes 1100 by screen printing low-temperature silver paste.

[0133] Example 2

[0134] This embodiment provides a heterojunction battery, which is prepared by the following preparation method.

[0135] A method for preparing a heterojunction battery comprises the following steps:

[0136] A method for preparing a heterojunction battery comprises the following steps:

[0137] (1) Providing an N-type silicon substrate 100; specifically comprising the following steps: providing an N-type single crystal silicon wafer, the N-type single crystal silicon wafer having a thickness of 180 μm; the N-type single crystal silicon wafer having a resistivity of 0.2 Ω.cm to 3 Ω.cm. Using a high-temperature furnace tube or chain-type gettering equipment to perform gettering on the N-type single crystal silicon wafer, the sheet resistance of the N-type single crystal silicon wafer after gettering is 40 Ω / □;

[0138] The PSG layer on the surface of the N-type single crystal silicon wafer is removed using a wet acid solution, and the N-type single crystal silicon wafer is polished and textured using an alkaline solution to form an N-type silicon substrate 100 with a pyramid-shaped surface light trapping structure.

[0139] (2) Intrinsic amorphous silicon layers 200 were formed on the front and back surfaces of the N-type silicon substrate 100. Specifically, the following steps were performed: The intrinsic amorphous silicon layer 200 was deposited by RF-PECVD using process gases containing SiH₄ and N₂O at a deposition temperature of 210°C and a deposition pressure of 2 mbar. The thickness of the intrinsic amorphous silicon layer 200 was 10 nm.

[0140] (3) Preparing an N-type doped layer 300 on the front intrinsic amorphous silicon layer 200. The N-type doped layer 300 is N-type doped amorphous silicon or microcrystalline silicon. Specifically, the N-type doped layer 300 is deposited on the intrinsic amorphous silicon layer 200 by a VHF-PECVD process. The process gases required for the VHF-PECVD process include SiH4 and PH3. The deposition temperature is 210°C and the deposition pressure is 5 mbar. The thickness of the N-type doped layer 300 is 20 nm.

[0141] (4) Preparing a P-type doped layer 400 on the back intrinsic amorphous silicon layer 200. The P-type doped layer 400 is P-type doped amorphous silicon or microcrystalline silicon. The process comprises the following steps: depositing the P-type doped layer 400 on the N-type doped layer 300 by a VHF-PECVD process; the process gases required for the VHF-PECVD process include SiH4 and TMB, the deposition temperature is 210°C, and the deposition pressure is 5 mbar. The thickness of the P-type doped layer 400 is 30 nm.

[0142] (5) A metal aluminum film seed layer 500, an indium-free transparent conductive film layer 600, and a metal aluminum film intermediate layer 700 are sequentially prepared on the P-type doped layer 400; specifically, the following steps are included: depositing a metal aluminum film seed layer 500 on the P-type doped layer 400; the thickness of the metal aluminum film seed layer 500 is 10 nm, the deposition temperature is 200°C, and the power is 10 kW; depositing an indium-free transparent conductive film layer 600 on the metal aluminum film seed layer 500; the thickness of the indium-free transparent conductive film layer 600 is 50 nm, the deposition temperature is 200°C, and the power is 8 kW; depositing a metal aluminum film intermediate layer 700 on the indium-free transparent conductive film layer 600; the thickness of the metal aluminum film intermediate layer 700 is 10 nm, the deposition temperature is 200°C, and the power is 10 kW.

[0143] (6) A metal aluminum film seed layer 500, an indium-free transparent conductive film layer 600, and a metal aluminum film intermediate layer 700 are sequentially prepared on the N-type doped layer 300; specifically, the following steps are included: depositing a metal aluminum film seed layer 500 on the N-type doped layer 300; the thickness of the metal aluminum film seed layer 500 is 10 nm, the deposition temperature is 200° C., and the power is 10 KW; depositing an indium-free transparent conductive film layer 600 on the metal aluminum film seed layer 500; the thickness of the indium-free transparent conductive film layer 600 is 50 nm, the deposition temperature is 200° C., and the power is 8 KW; depositing a metal aluminum film intermediate layer 700 on the indium-free transparent conductive film layer 600; the thickness of the metal aluminum film intermediate layer 700 is 10 nm, the deposition temperature is 200° C., and the power is 10 KW.

[0144] (7) An indium-free transparent conductive oxide thin film layer 900 is prepared on each metal aluminum thin film intermediate layer 700, with a deposition temperature of 200°C and a power of 8KW. The thickness of the indium-free transparent conductive oxide thin film layer 900 is 50nm; the indium-free transparent conductive thin film layer 600 is a Ga and Al co-doped GAZO thin film.

[0145] (8) Protective layers 1000 are formed on the indium-free transparent conductive oxide thin film layers 900. Specifically, the protective layers 1000 are formed on each indium-free transparent conductive oxide thin film layer 900 using a low-temperature CVD device at a deposition temperature of ≤200°C. The protective layers 1000 have a thickness of 30 nm. The protective layers 1000 are one or more of silicon nitride, silicon oxynitride, and silicon oxide thin films.

[0146] (9) A metal electrode 1100 is formed on the protective layer 1000; the metal electrode 1100 extends to the corresponding metal aluminum thin film intermediate layer 700. Specifically, the steps include: forming a patterned mask on the front and back surfaces using an acid-resistant mask combined with an exposure technique, removing the protective layer 1000 from the unmasked area using a 10% HF solution, and then removing the patterned mask using an alkaline solution; and forming the metal electrode 1100 by electroplating Al.

[0147] In summary, the above-mentioned indium-free heterojunction battery solves the problems of low crystallization rate and poor photoelectric properties of indium-free TCO materials after film formation by magnetron sputtering, rapid increase in square resistance due to the influence of oxygen during annealing in air, and poor weather resistance. The above-mentioned indium-free heterojunction battery significantly reduces manufacturing and processing costs and meets reliability requirements while ensuring the efficiency of HJT batteries. The preparation method of the above-mentioned indium-free heterojunction battery can promote the crystallization of indium-free TCO materials after film formation, reduce their resistivity, improve transmittance, and significantly improve the photoelectric conversion efficiency of indium-free heterojunction batteries. At the same time, the indium-free TCO material is superimposed with an anti-reflection protective layer 1000, which can not only further increase the utilization rate of incident light, but also solve the reliability problem, which is of great significance to the cost reduction and industrial development of HJT batteries.

[0148] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0149] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0150] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for preparing a heterojunction battery, characterized in that: The steps include: Providing an N-type silicon substrate; preparing intrinsic amorphous silicon layers on the front and back sides of the N-type silicon substrate respectively; preparing an N-type doped layer on the front intrinsic amorphous silicon layer; preparing a P-type doped layer on the intrinsic amorphous silicon layer on the back side; Sequentially preparing a metal aluminum thin film seed layer, an indium-free transparent conductive thin film layer, and a metal aluminum thin film intermediate layer on the P-type doped layer; Sequentially preparing a metal aluminum thin film seed layer, an indium-free transparent conductive thin film layer, and a metal aluminum thin film intermediate layer on the N-type doped layer; preparing an indium-free transparent conductive oxide thin film layer on each of the metal aluminum thin film intermediate layers; A protective layer is prepared on each of the indium-free transparent conductive oxide thin film layers, and a metal electrode is prepared on the protective layer; the metal electrode extends to the corresponding metal aluminum thin film intermediate layer.

2. The method for preparing a heterojunction battery according to claim 1, wherein: When providing an N-type silicon substrate, the following steps are specifically included: Providing an N-type single crystal silicon wafer, and performing a gettering process on the N-type single crystal silicon wafer using a high-temperature furnace tube or a chain-type gettering device, wherein the sheet resistance of the N-type single crystal silicon wafer after gettering is 20Ω / □ to 40Ω / □; The PSG layer on the surface of the N-type single crystal silicon wafer is removed using a wet acid solution, and the N-type single crystal silicon wafer is polished and textured using an alkaline solution to form the N-type silicon substrate with a pyramid-shaped surface light trapping structure.

3. The method for preparing a heterojunction battery according to claim 2, wherein: The thickness of the N-type single crystal silicon wafer is 60 μm to 180 μm; And / or, the resistivity of the N-type single crystal silicon wafer is 0.2Ω·cm to 3Ω·cm.

4. The method for preparing a heterojunction battery according to claim 1, wherein: When the intrinsic amorphous silicon layer is prepared on the front side and the back side of the N-type silicon substrate respectively, the following steps are specifically included: The intrinsic amorphous silicon layer is deposited by a radio frequency plasma enhanced chemical vapor deposition system, the required process gases include one or more of SiH4, H2, CO2, CH4 and N2O, the deposition temperature is 160°C to 210°C, and the deposition pressure is 0.2mbar to 2mbar.

5. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: The thickness of the intrinsic amorphous silicon layer is 2nm-10nm.

6. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: When preparing an N-type doped layer on the front intrinsic amorphous silicon layer, the following steps are specifically included: The N-type doped layer is deposited on the intrinsic amorphous silicon layer by very high frequency plasma enhanced chemical vapor deposition equipment. The required process gas includes one or more of SiH4, H2, CO2, CH4, N2O and PH3. The deposition temperature is 160℃~210℃ and the deposition pressure is 0.5mbar~5mbar.

7. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: The thickness of the N-type doping layer is 5 nm to 20 nm.

8. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: When preparing a P-type doped layer on the intrinsic amorphous silicon layer on the back side, the following steps are specifically included: The P-type doped layer is deposited on the N-type doped layer by very high frequency plasma enhanced chemical vapor deposition equipment; the required process gas includes one or more of SiH4, H2, CO2, CH4, N2O, B2H6 and TMB, the deposition temperature is 160℃~210℃, and the deposition pressure is 0.5mbar~5mbar.

9. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: The thickness of the P-type doping layer is 5nm to 30nm.

10. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: When a metal aluminum thin film seed layer, an indium-free transparent conductive thin film layer, and a metal aluminum thin film intermediate layer are sequentially prepared on the P-type doped layer, the steps specifically include: Depositing a metal aluminum thin film seed layer on the P-type doped layer; the thickness of the metal aluminum thin film seed layer is 1nm to 10nm, the deposition temperature is 0 to 200°C, and the power is 1KW to 10KW; Depositing an indium-free transparent conductive film layer on the metal aluminum film seed layer; the indium-free transparent conductive film layer has a thickness of 20 nm to 50 nm, a deposition temperature of 0 to 200° C., and a power of 1 kW to 8 kW; A metal aluminum film intermediate layer is deposited on the indium-free transparent conductive film layer; the thickness of the metal aluminum film intermediate layer is 1nm to 10nm, the deposition temperature is 0 to 200°C, and the power is 1KW to 10KW.

11. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: When a metal aluminum thin film seed layer, an indium-free transparent conductive thin film layer, and a metal aluminum thin film intermediate layer are sequentially prepared on the N-type doped layer, the steps specifically include: Depositing a metal aluminum thin film seed layer on the N-type doped layer; the thickness of the metal aluminum thin film seed layer is 1nm to 10nm, the deposition temperature is 0 to 200°C, and the power is 1KW to 10KW; Depositing an indium-free transparent conductive film layer on the metal aluminum film seed layer; the indium-free transparent conductive film layer has a thickness of 20 nm to 50 nm, a deposition temperature of 0 to 200° C., and a power of 1 kW to 8 kW; A metal aluminum film intermediate layer is deposited on the indium-free transparent conductive film layer; the thickness of the metal aluminum film intermediate layer is 1nm to 10nm, the deposition temperature is 0 to 200°C, and the power is 1KW to 10KW.

12. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: The indium-free transparent conductive film layer is ZnO-based doped with one or more of Ga, Al, and B elements, or SnO2 doped with one or more of F and Hf elements.

13. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: When preparing indium-free transparent conductive oxide thin film layers on each of the metal aluminum thin film intermediate layers, the deposition temperature is 0-200° C., the power is 1KW-8KW, and the thickness of the indium-free transparent conductive oxide thin film layer is 20nm-50nm.

14. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: When preparing a protective layer on the indium-free transparent conductive oxide thin film layer, the steps include: The protective layer is prepared on each of the indium-free transparent conductive oxide thin film layers using a low-temperature CVD device at a deposition temperature of ≤200°C.

15. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: The thickness of the protective layer is 5nm to 30nm.

16. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: The protective layer is one or more of silicon nitride, silicon oxynitride, and silicon oxide thin film.

17. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: When preparing a metal electrode on the protective layer, the following steps are specifically included: Using an acid-resistant mask combined with an exposure technique to form patterned masks on the front and back surfaces, respectively, using a 3%-10% HF solution to remove the protective layer in the unmasked area, and then using an alkaline solution to remove the patterned mask; The metal electrode is prepared by screen printing, laser transfer of low-temperature silver paste, low-temperature copper paste or silver-coated copper paste; or, the metal electrode is prepared by electroplating one or more alloys of Al, Ti, Ni, Co, Ag, Cu and Sn.

18. The method for preparing a heterojunction battery according to any one of claims 1 to 4, characterized in that: The N-type doping layer is N-type doped amorphous silicon or microcrystalline silicon, and the P-type doping layer is P-type doped amorphous silicon or microcrystalline silicon.

19. A heterojunction battery, characterized in that: The preparation method is described in any one of claims 1 to 18.

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