A comparator circuit for facilitating a DCDC boost device with an ultra-low input voltage

Abstract

A comparator circuit for a DCDC boost device conducive to ultra-low input voltage, comprising a reference comparison module, a boost system switch drive control module, a P-type transistor Q1 and an N-type transistor Q2; the reference comparison module includes a PFM comparator unit PFMCMP, a bandgap reference unit BANDGAP and a bias current unit IBIAS; the PFM comparator unit PFMCMP of the PFM comparator module includes an N-type transistor MN0, an N-type transistor MN1, an N-type transistor MN2, an N-type transistor MN3, an N-type transistor MN4, an N-type transistor MN5, a P-type transistor MP0, a P-type transistor MP1, a P-type transistor MP2 and a logic Schmitt trigger SMIT. Therefore, the present invention is used to compare a substitute signal VREF0 generating a comparator reference voltage with a voltage division VFB of an output voltage at a lower input voltage, and normally output a PFM high-level signal, that is, it can solve the limitation of the start-up voltage of the boost system under ultra-low input voltage and ensure that the boost system can work normally.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit (IC) automatic test equipment (Automatic Test Equipment, abbreviated as ATE), and relates to a comparator circuit for facilitating a DCDC boost device with an ultra-low input voltage. Background Art

[0002] The DCDC boost device is commonly used in power supply application scenarios such as alkaline batteries, nickel-metal hydride rechargeable batteries, lithium-manganese batteries, or lithium-ion rechargeable batteries. Please refer to Figure 1 , Figure 1 shown is a schematic diagram of the comparator circuit structure of a DCDC boost device using the prior art. As Figure 1 shown, the circuit mainly includes a reference comparison module, a boost system switch drive control module, an inductor L0, a feedback resistor R1, a feedback resistor R2, a sampling resistor R3, a capacitor CIN, a capacitor COUT, a transistor Q1, and a transistor Q2 and other components. The reference comparison module includes a PFM comparator unit PFMCMP, a bandgap reference unit BANDGAP, and a bias current unit BIAS; the boost system switch drive control module includes a zero-crossing detection comparator unit ZCDCMP, a current limit detection comparator unit OCLCMP, a drive unit DRIVER, a current limit detection logic control unit OCLCTRL, and an oscillator unit OSC.

[0003] Please refer to Figure 1 in combination with Figure 2 , Figure 2 for Figure 1 shown is a schematic diagram of the PFM comparator unit PFMCMP in the boost device system. As Figure 2 shown, the PFM comparator unit PFMCMP includes an N-type transistor MN0, an N-type transistor MN1, an N-type transistor MN2, an N-type transistor MN3, an N-type transistor MN4, a P-type transistor MP0, a P-type transistor MP1, a P-type transistor MP2, and a logic Schmitt trigger SMIT.

[0004] When the circuit starts up, the external input VIN is powered on. The current from VIN charges the capacitor COUT through the inductor L0 and the transistor Q1, and the output voltage VOUT rises to a voltage value close to the external input VIN. The power supplies of the internal modules are all provided by the external input VIN. When the external input VIN meets the voltage at which the system can operate, first, the bias current unit IBIAS starts up, providing the bias current IB for the PFM comparator unit PFMCMP, the zero-crossing detection comparator unit ZCDCMP, and the overcurrent limit detection comparator unit OCLCMP. At the same time, the bandgap reference unit BANDGAP starts up, outputting VREF to provide the reference voltage for the PFM comparator unit PFMCMP. The output voltage VOUT is divided by the resistors R1 and R2 to obtain VFB, which is compared with the reference voltage VREF by the PFM comparator unit PFMCMP. When the PFM comparator unit PFMCMP detects that VREF > VFB, the PFM comparator unit PFMCMP outputs an enable control signal with PFM being at a logic high level. At this time, the oscillator unit OSC starts to oscillate and outputs a clock signal CLK with a fixed period. On the premise that the enable signals of PZCD and NOCL are invalid, the driver unit DRIVER receives the CLK signal and outputs VPG and VNG to connect to the gates of the transistors Q1 and Q2, realizing the turn-on or turn-off of the transistors Q1 and Q2.

[0005] When the transistor Q1 is turned off and the transistor Q2 is turned on, the external input VIN, the inductor L0, and the N-type transistor Q2 form a charging loop, and the inductor L0 starts to store energy. When the transistor Q1 is turned on and the transistor Q2 is turned off, the current at both ends of L0 does not change immediately, and a discharging loop is formed between VIN and VOUT. The energy of the inductor L0 is slowly released, and the inductor energy is transmitted to the VOUT terminal through the transistor Q1, thereby increasing the VOUT voltage.

[0006] When VFB > VREF, it means that VOUT is greater than the target voltage. At this time, the PFM comparator unit PFMCMP outputs a logic low-level signal to control the oscillator unit OSC to stop working. At this time, the clock signal CLK is always at a low level. Through the driver unit DRIVER, the VNG signal continuously outputs a low level, and the transistor Q2 cannot be turned on. During the energy release process of the inductor L0, the zero-crossing detection comparator unit ZCDCMP compares the magnitudes of SW and VOUT voltages. When VOUT > SW, it means that the current of the inductor L0 is released to be close to 0, and ZCD outputs a logic low-level signal. The ZCD signal passes through the zero-crossing detection logic control unit ZCDCTRL to output PZCD and transmit it to the switch driver logic control unit DRIVER, and the VPG signal is output to turn off the transistor Q1 to prevent the current of the inductor L0 from flowing back to the input terminal.

[0007] When VFB < VREF, it indicates that VOUT is less than the target voltage. At this time, PFMCMP outputs a logic high-level signal to control the operation of the oscillator unit OSC and continuously outputs a clock signal CLK with a fixed period. The driver unit DRIVER receives the CLK signal and outputs VPG and VNG to control the turning on or off of transistor Q1 and transistor Q2. During the continuous increase of the current in inductor L0, the overcurrent detection comparator unit OCLCMP compares the magnitudes of VB and VS. When VS > VB, it indicates that the current in inductor L0 exceeds the set overcurrent limit value, and OCL outputs a logic low level. The OCL signal is transmitted to the switch driver logic control unit DRIVER through the overcurrent detection logic control unit OCLCTRL as NOCL, and the VNG signal is output to turn off transistor Q2. Transistor Q2 will not be turned on again until the start of the next CLK cycle, thus limiting the peak value of the inductor current.

[0008] In the prior art, the power supply of the internal module, that is, VOUT, must reach a relatively high voltage value for the internal module to work properly and the boost device system to start normally. The prerequisite for the normal start of the boost device is that VREF must be greater than VFB for the oscillator module to output the CLK clock signal, so as to drive and realize the alternating on or off of transistor Q1 and transistor Q2 through the switch driver logic control unit DRIVER.

[0009] For example, the bandgap reference unit BANDGAP with a traditional BJT architecture needs at least 1.5V of power supply voltage to work properly and generate VREF. Therefore, the input voltage VIN must be at least higher than 1.5V for the system to start normally, which limits the application range of lower input voltages.

[0010] Currently, electronic devices on the market are generally small, light, and portable. There are many applications that use a single dry battery to supply power to the boost device. However, too low an input voltage greatly limits the system boost. Using a higher voltage battery or multiple batteries to supply power, although the device can work properly, there will be many problems such as large volume and inconvenient carrying.

[0011] Of course, if a BANDAGAP module with other special device architectures is used, although it can normally output VREF at a lower input power supply voltage and enable the system to work properly and start the boost device system at a lower input voltage, special devices have high requirements for the process selection, which will additionally increase the production cost and is not conducive to the economy of the product. Summary of the Invention

[0012] To solve the above technical problems, the present invention proposes a comparator circuit for a DCDC boost device conducive to ultra-low input voltages. By improving the voltage comparator circuit in the reference module, the boost device can be started and operate normally at ultra-low input voltages.

[0013] To achieve the above object, the technical solution of the present invention is as follows:

[0014] A comparator circuit for a DCDC boost converter conducive to ultra-low input voltage, which includes a reference comparison module, a boost system switch drive control module, a P-type transistor Q1, and an N-type transistor Q2; the reference comparison module includes a PFM comparator unit PFMCMP, a bandgap reference unit BANDGAP, and a bias current unit IBIAS; the boost system switch drive control module includes a zero-crossing detection comparator unit ZCDCMP, a zero-crossing detection logic control unit ZCDCTRL, an overcurrent limit detection comparator unit OCLCMP, a switch drive logic control unit DRIVER, an overcurrent limit detection logic control unit OCLCTRL, and an oscillator unit OSC; wherein, the bias current unit IBIAS provides a bias current IB for the PFM comparator unit PFMCMP, the zero-crossing detection comparator unit ZCDCMP, and the overcurrent limit detection comparator unit OCLCMP; the bandgap reference unit BANDGAP provides a reference voltage for the PFM comparator unit PFMCMP and the overcurrent limit detection comparator unit OCLCMP; the PFM comparator unit PFMCMP compares the reference voltage VREF with the divided voltage VFB of the output terminal VOUT, and outputs an enable control signal PFM; the oscillator unit OSC outputs a clock signal with a fixed period to supply the subsequent switch drive logic control unit DRIVER; the zero-crossing detection comparator unit ZCDCMP compares the SW signal with the voltage of the output terminal VOUT, and outputs a ZCD signal; the zero-crossing detection logic control unit ZCDCTRL receives the ZCD signal and outputs a PZCD signal; the overcurrent limit detection comparator unit OCLCMP compares the VS signal with the voltage of the output terminal VB, and outputs an OCL signal; the overcurrent limit detection logic control unit OCLCTRL receives the OCL signal and outputs a NOCL signal; the switch drive logic control unit DRIVER receives the clock signal, the PZCD signal, and the NOCL signal to control the gates of the P-type transistor Q1 and the N-type transistor Q2;

[0015] The PFM comparator unit PFMCMP of the PFM comparator module includes an N-type transistor MN0, an N-type transistor MN1, an N-type transistor MN2, an N-type transistor MN3, an N-type transistor MN4, an N-type transistor MN5, a P-type transistor MP0, a P-type transistor MP1, a P-type transistor MP2, and a logic Schmitt trigger SMIT;

[0016] Among them, the logic Schmitt trigger SMIT is connected between the output terminal VOUT and the ground terminal GND, its output terminal is PFM, and its input terminal is connected to the drains of the P-type transistor MP2 and the N-type transistor MN4; the gates of the P-type transistor MP2, the drain of the P-type transistor MP1 and the drain of the N-type transistor MN1 are connected, the sources of the P-type transistor MP0, the P-type transistor MP1, the P-type transistor MP2 and the P-type transistor MP3 are connected to the output terminal VOUT; the gates of the N-type transistor MN4, the gates and drains of the N-type transistor MN2, the gate of the N-type transistor MN5, and the gate of the N-type transistor MN3 are connected to the voltage terminal IB; the sources of the N-type transistor MN2, the N-type transistor MN3 and the N-type transistor MN4 are connected to the ground terminal GND, the drain of the N-type transistor MN3 is connected to the sources of the N-type transistor MN5, the N-type transistor MN0 and the N-type transistor MN1; the gate of the N-type transistor MN1 is connected to VFB, and the gate of the N-type transistor MN0 is connected to VREF; the drain of the N-type transistor MN5, the gate and drain of the P-type transistor MP0, the drain of the N-type transistor MN0 and the gate of the P-type transistor MP1 are connected.

[0017] Further, the comparator circuit of the DCDC boost device beneficial to ultra-low input voltage further includes a feedback resistor R1 and a feedback resistor R2, which are connected in series between the output terminal VOUT and the ground terminal GND for generating the divided voltage VFB.

[0018] Further, the comparator circuit of the DCDC boost device beneficial to ultra-low input voltage further includes an inductor L0, a capacitor COUT and a capacitor CIN. One end of the capacitor CIN is connected to the external input voltage VIN and one end of the inductor L0, and the other end is connected to the ground terminal GND. The other end of the inductor L0 is connected to the connection point of the SW signal terminal, the drain of the P-type transistor Q1 and the drain of the N-type transistor Q2.

[0019] It can be seen from the above technical solutions that the comparator circuit of the DCDC boost device beneficial to ultra-low input voltage of the present invention improves the input circuit of the PFM comparator unit PFMCMP of the PFM comparator module. When the bandgap reference unit BANDGAP cannot work properly at a lower voltage, VREF0 with a higher voltage is preferentially selected to replace VREF. When VREF0 is greater than VFB, a PFM logic high-level signal can be output, enabling the boost system switch drive control module to work properly to drive the transistors Q1 and Q2 to alternately turn on and transmit energy to the output terminal VOUT, thereby realizing the startup of the boost system at ultra-low input voltage. Description of the Drawings

[0020] Figure 1 The figure shows a schematic structural diagram of a boost device system using the prior art

[0021] Figure 2 is Figure 1 a schematic diagram of the PFM comparator unit PFMCMP in the boost device system shown

[0022] Figure 3 The figure shows a schematic diagram of a preferred embodiment of a comparator circuit for a DCDC boost device facilitating ultra-low input voltage in an embodiment of the present invention

[0023] Figure 4 is Figure 3 a schematic diagram of the PFM comparator unit PFMCMP in the boost device system shown

[0024] Figure 5 The figure shows a schematic diagram of voltage comparison during the boost process between the boost device system in an embodiment of the present invention and the boost device system of the prior art Specific embodiments

[0025] The following will further elaborate on the specific embodiments of the present invention in conjunction with the attached Figures 3 - 5 drawings

[0026] Please refer to Figure 3 , Figure 3 The figure shows a schematic diagram of a preferred embodiment of a comparator circuit for a DCDC boost device facilitating ultra-low input voltage in an embodiment of the present invention. As Figure 3 shown, the improved boost system mainly includes a reference comparison module, a boost system switch drive control module, a P-type transistor Q1, an N-type transistor Q2, resistors, capacitors, inductors, and transistor devices, etc

[0027] The reference comparison module includes a PFM comparator unit PFMCMP, a bandgap reference unit BANDGAP, and a bias current unit IBIAS; the boost system switch drive control module includes a zero-crossing detection comparator unit ZCDCMP, a zero-crossing detection logic control unit ZCDCTRL, an overcurrent limit detection comparator unit OCLCMP, a switch drive logic control unit DRIVER, an overcurrent limit detection logic control unit OCLCTRL, and an oscillator unit OSC

[0028] Among them, the bias current unit IBIAS provides bias current for the PFM comparator unit PFMCMP, the zero-crossing detection comparator unit ZCDCMP, and the over-current limit detection comparator unit OCLCMP; the bandgap reference unit BANDGAP provides a reference voltage for the PFM comparator unit PFMCMP and the over-current limit detection comparator unit OCLCMP; the PFM comparator unit PFMCMP compares the reference voltage VREF with the divided voltage VFB of the output terminal VOUT and outputs an enable control signal PFM; the oscillator unit OSC outputs a clock signal with a fixed period to supply the subsequent switch drive logic control unit DRIVER; the zero-crossing detection comparator unit ZCDCMP compares the magnitude of the SW signal with the voltage of the output terminal VOUT and outputs a ZCD signal; the zero-crossing detection logic control unit ZCDCTRL receives the ZCD signal and outputs a PZCD signal; the over-current limit detection comparator unit OCLCMP compares the magnitude of the VS signal with the voltage of the output terminal VB and outputs an OCL signal; the over-current limit detection logic control unit OCLCTRL receives the OCL signal and outputs a NOCL signal; the switch drive logic control unit DRIVER receives the clock signal, the PZCD signal, and the NOCL signal to control the gates of the transistor Q1 and the transistor Q2.

[0029] In addition, the comparator circuit further includes a feedback resistor R1 and a feedback resistor R2, which are connected in series between the output terminal VOUT and the ground terminal GND for generating the divided voltage VFB.

[0030] The comparator circuit further includes an inductor L0 and a capacitor CIN. One end of the capacitor CIN is connected to the input voltage VIN and one end of the inductor L0, and the other end is connected to the ground terminal GND. The other end of the inductor L0 is connected to the connection point of the SW signal terminal, the drain of the P-type transistor Q1, and the drain of the N-type transistor Q2.

[0031] Please refer to Figure 4 , Figure 4 For Figure 3 the schematic diagram of the PFM comparator unit PFMCMP in the boost device system shown. As Figure 4 shown, the PFM comparator module PFM comparator unit PFMCMP includes an N-type transistor MN0, an N-type transistor MN1, an N-type transistor MN2, an N-type transistor MN3, an N-type transistor MN4, an N-type transistor MN5, a P-type transistor MP0, a P-type transistor MP1, a P-type transistor MP2, and a logic Schmitt trigger SMIT.

[0032] In an embodiment of the present invention, the PFM comparator module's PFM comparator unit PFMCMP is used to generate a comparison between a substitution signal VREF0 of the comparator reference voltage and a voltage division VFB of the voltage at the output terminal VOUT when the input voltage is low, and normally outputs a PFM high-level signal.

[0033] Among them, the logic Schmitt trigger SMIT is connected between the output terminal VOUT and the ground terminal GND, its output terminal is PFM, and its input terminal is connected to the drains of the P-type transistor MP2 and the N-type transistor MN4; the gates of the P-type transistor MP2, the drain of the P-type transistor MP1, and the drain of the N-type transistor MN1 are connected, the source of the P-type transistor MP0, the source of the P-type transistor MP1, and the source of the P-type transistor MP2 are connected to the output terminal VOUT; the gates of the N-type transistor MN4, the gates and drains of the N-type transistor MN2, the gate of the N-type transistor MN5, and the gate of the N-type transistor MN3 are connected to the voltage terminal IB; the sources of the N-type transistor MN2, the N-type transistor MN3, and the N-type transistor MN4 are connected to the ground terminal GND, the drain of the N-type transistor MN3 is connected to the sources of the N-type transistor MN5, the N-type transistor MN0, and the N-type transistor MN1; the gate of the N-type transistor MN1 is connected to VFB, and the gate of the N-type transistor MN0 is connected to VREF; the drain of the N-type transistor MN5, the gate and drain of the P-type transistor MP0, the drain of the N-type transistor MN0, and the gate of the P-type transistor MP1 are connected.

[0034] Please combine Figure 3 and 4 refer to Figure 5 , Figure 5 The following shows a voltage comparison schematic diagram of the boost device system in the embodiment of the present invention and the boost device system in the prior art during the boost process. As Figure 5 shown,

[0035] When starting with an ultra-low input voltage, the external input voltage VIN powers on, and the current from the external input voltage VIN charges the capacitor COUT through the inductor L0 and the P-type transistor Q1, and the voltage at the output terminal VOUT rises to a voltage value close to the external input voltage VIN.

[0036] The internal module power supply is all provided by the voltage at the output terminal VOUT. Since the external input voltage VIN is low, the voltage at the output terminal VOUT is also correspondingly low and not sufficient to ensure that all internal modules can work properly. At this time, the bias current unit IBIAS starts first, and the bias current unit IBIAS provides a bias current IB for the PFM comparator unit PFMCMP, the zero-crossing detection comparator unit ZCDCMP, and the overcurrent limiting detection comparator unit OCLCMP.

[0037] However, the bandgap reference cell BANDGAP still cannot work properly to output the correct reference voltage VREF. Therefore, the PFM comparator unit PFMCMP uses the bias current provided by the bias current IB to generate a relatively high voltage reference voltage VREF0 through the N-type transistor MN2.

[0038] At this time, the PFM comparator unit PFMCMP will select the relatively high reference voltage VREF0 to compare with the divided voltage VFB of VOUT. When it is detected that the reference voltage VREF0 > the reference voltage VFB, the PFM comparator unit PFMCMP outputs an enable control signal with PFM being at a logic high level; at the same time, the oscillator unit OSC starts to oscillate and outputs a clock signal CLK with a fixed period. On the premise that the enable signals of PZCD and NOCL are invalid, the switch drive logic control unit DRIVER receives the CLK signal and outputs VPG and VNG to connect to the gates of the P-type transistor Q1 and the N-type transistor Q2, realizing the turn-on or turn-off of the P-type transistor Q1 and the N-type transistor Q2.

[0039] When the P-type transistor Q1 is turned off and Q2 is turned on, the external input VIN, the inductor L0, and the N-type transistor Q2 form a charging loop, and the inductor L0 starts to store energy; when the P-type transistor Q1 is turned on and Q2 is turned off, the current at both ends of L0 will not change immediately, and a discharge loop is formed between VIN and VOUT. The energy of the inductor L0 is slowly released, and the inductor energy is transmitted to the VOUT terminal through the P-type transistor Q1, thereby increasing the VOUT voltage.

[0040] As the voltage at the output terminal VOUT continues to rise, if it rises to a level where the bandgap reference cell BANDGAP can work properly and generate a reference voltage VREF greater than VREF0, the input terminal of the PFM comparator unit PFMCMP will switch to comparing VREF with VFB, and the boost system starts up to the preset output voltage value.

[0041] When VFB > VREF, it means that VOUT is greater than the target voltage. At this time, the PFM comparator unit PFMCMP outputs a logic low-level signal to control the oscillator unit OSC to stop working. At this time, the clock signal CLK is always at a low level. Through the switch drive logic control unit DRIVER, the VNG signal continues to output at a low level, and the N-type transistor Q2 cannot be turned on. During the energy release process of the inductor L0, the zero-crossing detection comparator unit ZCDCMP compares the magnitudes of SW and VOUT voltages.

[0042] When the voltage VOUT at the output terminal VOUT > SW, it indicates that the current of the inductor L0 is released to nearly 0, the output ZCD is a logic low-level signal, and the ZCD signal passes through the zero-crossing detection logic control unit ZCDCTRL to output PZCD and transmit it to the switch drive logic control unit DRIVER, and the output VPG signal turns off the P-type transistor Q1 to prevent the current of the inductor L0 from flowing back to the input terminal.

[0043] When VFB < VREF, it indicates that the voltage at the output terminal VOUT is less than the target voltage. At this time, the PFM comparator unit PFMCMP outputs a logic high-level signal to control the oscillator unit OSC to work and continuously output a clock signal CLK with a fixed period. The switch drive logic control unit DRIVER receives the CLK signal and outputs VPG and VNG to control the on or off of the P-type transistor Q1 and the N-type transistor Q2. During the continuous rise of the current of the inductor L0, the current-limiting detection comparator unit OCLCMP compares the magnitudes of VB and VS; when VS > VB, it indicates that the current of the inductor L0 exceeds the set current-limiting value, and the output OCL is a logic low level. The OCL signal passes through the current-limiting detection logic control unit OCLCTRL to output NOCL and transmit it to the switch drive logic control unit DRIVER, and the output VNG signal turns off the N-type transistor Q2 until the start of the next CLK cycle, and the N-type transistor Q2 will be turned on again, thereby limiting the peak value of the inductor current.

[0044] The above are only the preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, all equivalent structural changes made by using the description and drawings of the present invention should, by the same token, be included in the protection scope of the present invention.

Claims

1. A comparator circuit for an ultra-low input voltage DCDC boost device, characterized in that, It includes a reference comparison module, a boost system switch drive control module, a P-type transistor Q1 and an N-type transistor Q2; the reference comparison module includes a PFM comparator unit PFMCMP, a bandgap reference unit BANDGAP and a bias current unit IBIAS; the boost system switch drive control module includes a zero-crossing detection comparator unit ZCDCMP, a zero-crossing detection logic control unit ZCDCTRL, an overcurrent limit detection comparator unit OCLCMP, a switch drive logic control unit DRIVER, an overcurrent limit detection logic control unit OCLCTRL and an oscillator unit OSC; wherein, the bias current unit IBIAS provides a bias current IB for the PFM comparator unit PFMCMP, the zero-crossing detection comparator unit ZCDCMP and the overcurrent limit detection comparator unit OCLCMP; the bandgap reference unit BANDGAP provides a reference voltage for the PFM comparator unit PFMCMP and the overcurrent limit detection comparator unit OCLCMP; the PFM comparator unit PFMCMP compares the reference voltage VREF with the divided voltage VFB of the voltage at the output terminal VOUT and outputs an enable control signal PFM; the oscillator unit OSC outputs a clock signal with a fixed period to supply the switch drive logic control unit DRIVER at the subsequent stage; the zero-crossing detection comparator unit ZCDCMP compares the SW signal with the voltage at the output terminal VOUT and outputs a ZCD signal; the zero-crossing detection logic control unit ZCDCTRL receives the ZCD signal and outputs a PZCD signal; the overcurrent limit detection comparator unit OCLCMP compares the VS signal with the voltage at the output terminal VB and outputs an OCL signal; the overcurrent limit detection logic control unit OCLCTRL receives the OCL signal and outputs a NOCL signal; the switch drive logic control unit DRIVER receives the clock signal, the PZCD signal and the NOCL signal to control the gates of the P-type transistor Q1 and the N-type transistor Q2; The PFM comparator unit PFMCMP of the PFM comparator module includes an N-type transistor MN0, an N-type transistor MN1, an N-type transistor MN2, an N-type transistor MN3, an N-type transistor MN4, an N-type transistor MN5, a P-type transistor MP0, a P-type transistor MP1, a P-type transistor MP2 and a logic Schmitt trigger SMIT; Among them, the logic Schmitt trigger SMIT is connected between the output terminal VOUT and the ground terminal GND, its output terminal is PFM, and its input terminal is connected to the drains of the P-type transistor MP2 and the N-type transistor MN4; the gates of the P-type transistor MP2, the drains of the P-type transistor MP1 and the N-type transistor MN1 are connected, the sources of the P-type transistor MP0, the sources of the P-type transistor MP1 and the sources of the P-type transistor MP2 are connected to the output terminal VOUT; the gates of the N-type transistor MN4, the gates and drains of the N-type transistor MN2, the gates of the N-type transistor MN5, the gates of the N-type transistor MN3 are connected to the voltage terminal IB; the sources of the N-type transistor MN2, the sources of the N-type transistor MN3 and the sources of the N-type transistor MN4 are connected to the ground terminal GND, the drain of the N-type transistor MN3 is connected to the sources of the N-type transistor MN5, the N-type transistor MN0 and the N-type transistor MN1; the gate of the N-type transistor MN1 is connected to VFB, and the gate of the N-type transistor MN0 is connected to VREF; the drain of the N-type transistor MN5, the gates and drains of the P-type transistor MP0, the drain of the N-type transistor MN0 and the gate of the P-type transistor MP1 are connected; the drain of the P-type transistor MP1, the gate of the N-type transistor MN2 and the drain of the N-type transistor MN1 are connected.

2. The comparator circuit for facilitating the ultra-low input voltage DCDC boost device according to claim 1, wherein It further includes a feedback resistor R1 and a feedback resistor R2, which are connected in series between the output terminal VOUT and the ground terminal GND and are used to generate the divided voltage VFB.

3. The comparator circuit for facilitating the ultra-low input voltage DCDC boost device according to claim 1, characterized in that, It further includes an inductor L0, a capacitor COUT and a capacitor CIN. One end of the capacitor CIN is connected to the external input voltage VIN and one end of the inductor L0, and the other end is connected to the ground terminal GND. The other end of the inductor L0 is connected to the connection point of the SW signal terminal, the drains of the P-type transistor Q1 and the N-type transistor Q2.

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