Analog-to-digital converter control system, chip and device

Abstract

The application discloses an analog-digital converter control system, a chip and equipment, and the analog-digital converter control system comprises a plurality of host data processing units, a plurality of host units, a plurality of slave arbitration units, a plurality of slave units, a plurality of cross clock domain bridges and a plurality of analog-digital conversion control units; each host data processing unit is connected with a corresponding host unit, each host unit is connected with a plurality of slave arbitration units respectively, each slave arbitration unit is connected with a corresponding slave unit, each slave unit is connected with a corresponding cross clock domain bridge, and each cross clock domain bridge is connected with a corresponding analog-digital conversion control unit. The application solves the problems that the prior art is high in circuit complexity, difficult to realize, difficult to maintain and difficult to solve the timing problem caused by the multiple ADC staggered sampling conversion.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, specifically to an analog-to-digital converter control system, chip, and device. Background Technology

[0002] The effective sampling rate / sampling conversion rate of an analog-to-analog converter (analog unit) is a metric for measuring its conversion performance. In other words, the higher the effective sampling rate, the more results the analog-to-analog converter can produce per unit time. Figures 1-2 As shown, Figure 2 Midpoints a1, a2, and a3 represent the conversion of a single analog-to-analog converter a (analog unit). Figure 1 The conversion results of the analog signal under test in the figure are limited by the effective sampling rate of the analog converter. The horizontal interval between points a1, a2, and a3 in Figure 2 is relatively long, which causes the analog converter a to be unable to capture some details of voltage changes in Figure 1.

[0003] However, due to limitations in existing analog technology, it is difficult to increase the effective sampling rate / sampling conversion rate of an analog converter. Therefore, in order to increase the effective sampling rate of the analog signal under test, existing technologies typically use multiple analog converters to perform interleaved conversion on an analog signal. This is the interleaved sampling conversion technique.

[0004] Existing interleaved sampling conversion techniques typically employ multiple analog converters to convert the same analog signal under test at different time intervals to obtain details of voltage changes in the signal. However, when using multiple analog converters to convert the same signal, it is necessary to control these converters to work together on a single conversion task. In practical applications, if multiple analog signals need to be processed simultaneously, the number of analog converters required increases exponentially, undoubtedly leading to high circuit complexity, implementation difficulty, and maintenance challenges.

[0005] Therefore, a new technological solution is needed. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide an analog-to-digital converter control system, chip, and device to at least solve the problems of high circuit complexity, high implementation difficulty, difficult maintenance, and difficult timing issues caused by using multiple ADCs for interleaved sampling conversion in the prior art.

[0007] The embodiments of the present invention provide the following technical solutions:

[0008] This invention provides an analog-to-digital converter control system, including multiple master data processing units, multiple master units, multiple slave arbitration units, multiple slave units, multiple cross-clock domain bridges, and multiple analog-to-digital conversion control units;

[0009] Each of the host data processing units is connected to a corresponding host unit, each of the host units is connected to the plurality of slave arbitration units, each of the slave arbitration units is connected to a corresponding slave unit, each slave unit is connected to a corresponding cross-clock domain bridge, and each cross-clock domain bridge is connected to a corresponding analog-to-digital conversion control unit.

[0010] The host unit is used to send a priority value to the plurality of slave arbitration units, and the slave arbitration units connect the host unit to the corresponding slave unit according to the priority value.

[0011] Furthermore, the slave arbitration unit is equipped with a digital comparator, which is connected to the slave arbitration unit and is used to compare multiple priority values ​​sent by the multiple master units.

[0012] Furthermore, the clock domains of the multiple analog-to-digital conversion control units are independent of each other.

[0013] Furthermore, the multiple host data processing units, multiple host units, multiple slave arbitration units, and multiple slave units all operate under the same master clock domain.

[0014] Furthermore, the analog-to-digital converter control system also includes:

[0015] A first processing unit is connected to a corresponding slave unit;

[0016] The slave decoder unit is connected to the first arithmetic processing unit.

[0017] Furthermore, the analog-to-digital converter control system also includes:

[0018] Slave decoder unit, which is connected to the plurality of slave units.

[0019] Furthermore, the analog-to-digital converter control system also includes:

[0020] The second processing unit is connected to the slave decoder unit.

[0021] Furthermore, the slave arbitration unit is connected to the two master units respectively, wherein the two master units are configured as a regular sequence master unit and an injected sequence master unit, and the priority value of the regular sequence master unit is greater than the priority value of the injected sequence master unit.

[0022] This invention also provides an analog-to-digital converter (ADC) control chip, including any of the ADC control systems described above.

[0023] This invention also provides an analog-to-digital converter control device, including any of the analog-to-digital conversion control systems described above.

[0024] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of the present invention can achieve include at least:

[0025] The present invention provides an analog-to-digital converter control system that configures multiple host units to perform multiple conversion tasks simultaneously. It can assign a conversion task to two or more host units to perform interleaved sampling conversion as in the prior art, which has the advantages of high effective sampling rate, high ADC resource utilization, and multiple parallel execution tasks. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the analog signal to be tested.

[0028] Figure 2 A schematic diagram of the results of continuous conversion by a single analog-to-digital converter;

[0029] Figure 3 A schematic diagram of the data resulting from continuous interleaved sampling and conversion by four analog-to-digital converters;

[0030] Figure 4 This is a schematic diagram of the structure of an analog-to-digital converter control system according to an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the analog-to-digital converter control system in an on-chip system according to an embodiment of the present invention;

[0032] Figure 6 This is a simplified analog-to-digital conversion control system that controls only one analog-to-digital converter in this embodiment of the invention;

[0033] The reference numerals in the drawings of this invention are as follows:

[0034] 10. Master data processing unit; 20. Master unit; 30. Slave arbitration unit; 40. Slave unit; 50. Cross-clock domain bridge; 60. Analog-to-digital conversion control unit; 70. First arithmetic processing unit; 80. Slave decoder unit; 90. Second arithmetic processing unit. Detailed Implementation

[0035] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0036] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0038] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0040] The effective sampling rate / sampling conversion rate of an analog-to-analog converter (analog unit) is a metric for measuring its conversion performance. A higher effective sampling rate means the analog-to-analog converter (analog unit) can convert more results per unit time, and the horizontal interval between the converted results is shorter. Figure 2 As shown, points a1, a2, and a3 represent the analog converter a (analog unit) converting... Figure 1 The conversion result of the analog signal under test shown is in Figure 2 Because the horizontal spacing between a1, a2, and a3 is too long, it cannot be captured. Figure 1 Details of voltage changes.

[0041] Limited by existing analog technology, it is very difficult to increase the effective sampling rate / sampling conversion rate of an analog converter (analog unit). Therefore, in existing technologies, using multiple analog converters (analog units) to perform interleaved conversion on an analog signal can increase the effective sampling rate of the analog signal under test, thereby achieving interleaved sampling conversion.

[0042] like Figure 3 As shown, four independent analog converters a, b, c, and d employ interleaved sampling conversion technology to... Figure 1 The simulated signal under test is converted as shown. The conversion results of analog converter a are represented by points a1, a2, and a3. Analog converter b starts its conversion after a short delay (the horizontal interval between points a1 and b1) when analog converter a (the analog unit) begins its first conversion, and its conversion results are shown as points b1, b2, and b3. Similarly, analog converter c starts its conversion after a short delay when analog converter b begins its first conversion, and its conversion results are shown as points c1, c2, and c3; analog converter d also starts its conversion after a short delay when analog converter c begins its first conversion, and its conversion results are shown as points d1, d2, and d3. Figure 3 As shown, Figure 3 The image shows the superimposed conversion results of analog converters a, b, c, and d, that is, points a1, b1, c1, ..., d3 compared to... Figure 2 It can better express Figure 1 Details of voltage changes.

[0043] like Figure 3 As shown, more independent analog converters are involved. Figure 1In the conversion of a single analog signal under test, the closer the conversion result is to the original waveform of the analog signal under test, the more accurate the conversion result needs to be. Therefore, to obtain an accurate conversion result, it is necessary to control multiple analog converters to jointly perform a conversion task. In practical applications, it is often necessary to process multiple analog signals under test simultaneously, that is, to perform multiple conversion tasks in parallel. If the above-mentioned multiple parallel conversion tasks all adopt interleaved conversion technology, the number of analog converters (analog units) that need to be controlled at the same time will increase exponentially.

[0044] Addressing the lack of a digital circuit or solution in existing products and technologies that can automatically control multiple (e.g., 32) independent analog-to-digital converters (analog units), and the problem that traditional products and technologies require frequent software intervention and processing, which greatly affects the performance of chips or electronic devices, this application provides an analog-to-digital converter control system. This system performs interleaved sampling conversion in the prior art by assigning a conversion task to two or more host units, thereby solving the shortcomings and deficiencies of interleaved sampling conversion in the prior art. It has the advantages of high effective sampling rate, high ADC resource utilization, and multiple parallel execution tasks.

[0045] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0046] Example 1

[0047] like Figure 4 As shown, this embodiment of the invention provides an analog-to-digital converter control system, including multiple host data processing units 10, multiple host units 20, multiple slave arbitration units 30, multiple slave units 40, multiple cross-clock domain bridges 50, and multiple analog-to-digital conversion control units 60;

[0048] Each host data processing unit 10 is connected to a corresponding host unit 20, each host unit 20 is connected to multiple slave arbitration units 30, each slave arbitration unit 30 is connected to a corresponding slave unit 40, each slave unit 40 is connected to a corresponding cross-clock domain bridge 50, and each cross-clock domain bridge 50 is connected to a corresponding analog-to-digital conversion control unit 60.

[0049] Among them, the host data processing unit 10, host unit 20, slave arbitration unit 30, slave unit 40, cross-clock domain bridge 50 and analog-to-digital conversion control unit 60 are all physical structures, and are composed of various digital logic gate components, flip-flops and connecting lines in digital circuits. They are part of the internal hardware circuit of the chip or electronic device.

[0050] The judgment, calculation, and transmission modules of each unit described in this application can all be completed by a combination of digital logic gates (AND gates, OR gates, NOT gates, etc.). This application does not limit the connection method between the host data processing unit 10, host unit 20, slave arbitration unit 30, slave unit 40, cross-clock domain bridge 50, and analog-to-digital conversion control unit 60. It can be any connection method in the prior art. The protection point of this application is the system composed of multiple host data processing units 10, multiple host units 20, multiple slave arbitration units 30, multiple slave units 40, multiple cross-clock domain bridges 50, and multiple analog-to-digital conversion control units 60, rather than the connection method between adjacent units.

[0051] The host unit 20 is used to send priority values ​​to multiple slave arbitration units 30, and the slave arbitration units 30 connect the host unit 20 to the corresponding slave unit 40 according to the priority values.

[0052] Specifically, after receiving the trigger signal sent by the host data processing unit 10, the host unit 20 sends the priority value, the slave unit control request signal, and the control data (the control data is all the data required for a conversion task) to multiple slave arbitration units 30. The slave arbitration units 30 connect the host unit 20 to the corresponding slave unit 40 according to the priority value, so that the slave unit 40 sends the control data to the corresponding cross-clock domain bridge 50.

[0053] The host data processing unit 10 is a component in the ADC system responsible for receiving and processing digitized data from the ADC, and for further processing, analysis and application of the sampled data, such as data parsing and correction.

[0054] Specifically, the host data processing unit 10 is used to receive external input signals (user register data, external trigger signals, etc.) and perform analysis and processing. The host data processing unit 10 is also used to determine when and in what mode the host unit 20 under its control should work based on the analysis results, such as controlling the host unit 20 to work in single-channel mode or multi-channel mode.

[0055] The number of host data processing units 10 is the same as the number of host units 20.

[0056] The host unit 20 in the ADC system is responsible for communicating with external devices or systems and controlling and managing the ADC's workflow, such as data transmission, control, and configuration.

[0057] Specifically, after receiving the trigger signal from the host data processing unit 10, the host unit 20 outputs the priority value, the slave unit control request signal, and all the data necessary to control one analog-to-digital conversion task to all slave arbitration units 30. One host unit 20 can establish control relationships with multiple slave units 40 at the same time to synchronously control the analog-to-digital converter to complete tasks that require the participation of multiple analog-to-digital converters, such as interleaved sampling conversion.

[0058] The host unit 20 is connected to the host data processing unit 10 and the slave arbitration unit 30 respectively. There can be one or more host units 20, and each host unit 20 is connected to one host data processing unit 10 and all slave arbitration units 30 respectively.

[0059] Among them, the slave arbitration unit 30 is a component used in analog-to-digital conversion to coordinate communication between multiple slave devices and the master device, and is used to manage and control access conflicts between slave devices to ensure smooth data transmission.

[0060] Specifically, the slave arbitration unit 30 determines which master unit 20 gains control of the slave unit 40 connected to the slave arbitration unit 30 based on the priority value output by the master unit 20. After establishing the control relationship between the master unit 20 and the slave unit 40, the slave arbitration unit 30 sends data from the master unit 20 to the slave unit 40 and feeds back the connection status and working status of the slave unit 40 to the corresponding master unit 20.

[0061] Specifically, the priority of the master unit 20 is determined by the priority value (priority signal) output by the master unit 20 to the slave arbitration unit. For example, if the priority value sent by the master unit 20 is 3, then the priority of the master unit 20 is 3. The source of the priority value is the data stored in the user register, and this data is written in advance.

[0062] The slave arbitration unit 30 is connected to all the master units 20 and one slave unit 40 respectively, and the number of slave arbitration units 30 is the same as the number of analog-to-digital conversion control units 60.

[0063] Specifically, the slave arbitration unit 30 includes a digital comparator, and the digital comparator is connected to the slave arbitration unit, that is, the digital comparator is integrated into the slave arbitration unit 30.

[0064] The digital comparator is used to compare the priority values ​​of each host unit 20. The smaller the priority value of the host unit 20, the higher the priority of the corresponding host unit 20.

[0065] In some embodiments, when the priority values ​​of the host units 20 are equal, the smaller the number of the host unit 20, the higher the priority.

[0066] The digital comparator is also used to compare the serial number of the host unit 20.

[0067] The following is a specific embodiment of determining the priority of host unit 20 using a digital comparator:

[0068] When both master unit 1 and master unit 2 request control of slave unit simultaneously, if the priority value of master unit 1 is 4 and the priority value of master unit 2 is 3, then slave arbitration unit 30 will determine through a digital comparator that the priority of master unit 2 is higher than that of master unit 1 (the smaller the priority value of master unit 20, the higher the priority). Slave arbitration unit 30 will then connect master unit 2 to its connected slave unit 40, and master unit 1 will wait for master unit 2 to release control before acquiring control of the slave unit.

[0069] When the priority values ​​of master unit 1 and master unit 2 are the same, slave arbitration unit 30 uses a digital comparator to determine the sequence number of master unit 1 and master unit 2. Since the sequence number of master unit 1 is less than the sequence number of master unit 2, the priority of master unit 1 is greater than that of master unit 2. At this time, master unit 1 is connected to slave unit 40 connected to slave arbitration unit 30.

[0070] In the above embodiments, priority determination is automatically completed by digital circuits, and the priority value and sequence number of host unit 1 are pre-set, so the determination process does not require software participation.

[0071] In some of these embodiments, at any given time, a slave unit 40 can only establish a control relationship with at most one master unit 20 during the same time period.

[0072] The slave unit 40 is an auxiliary component that communicates with the master unit 20. It coordinates the communication between the master unit 20 and the ADC and provides necessary interfaces and functions, such as data transmission functions.

[0073] Specifically, after receiving control data from the master unit 20, the slave unit 40 sends the data to the cross-clock domain bridge 50. Then, the control data passes through the cross-clock domain bridge 50 and reaches the analog-to-digital conversion control unit 60. Finally, the slave unit 40 waits for and receives the analog-to-digital conversion result sent by the analog-to-digital conversion control unit 60, and outputs the conversion result to the arithmetic processing unit.

[0074] The number of slave units 40 is equal to the number of analog-to-digital conversion control units 60, and each slave unit 40 is connected to a slave arbitration unit 30 and a cross-clock domain bridge 50.

[0075] The cross-clock domain bridge 50 is used to perform cross-clock synchronization processing on signals from different clock domains. In this application, all other components except the cross-clock domain bridge 50 and the analog-to-digital conversion control unit 60 operate under the same master clock domain. That is, multiple master data processing units 10, multiple master units 20, multiple slave arbitration units 30, and multiple slave units 40 all operate under the same master clock domain.

[0076] The number of cross-clock domain bridge 50 units is the same as the number of analog-to-digital conversion control units 60, and the cross-clock domain bridge 50 is connected to a slave unit 40 and an analog-to-digital conversion control unit 60 respectively.

[0077] In some embodiments, the analog-to-digital conversion control unit 60 can operate in the main clock domain or in a separate clock domain to perform analog-to-digital conversion tasks with different requirements.

[0078] In some embodiments, the clock domains in which each analog-to-digital conversion control unit 60 operates can be independent of each other, such as Figure 4 As shown, the present invention can have up to m+1 independent clock signals.

[0079] In some embodiments, the analog-to-digital converter control system further includes a first processing unit 70 and a slave decoder unit 80. The first processing unit 70 is connected to a corresponding slave unit 40; the slave decoder unit 80 is connected to the first processing unit 70.

[0080] The first arithmetic processing unit 70 is used to process the conversion results sent by the slave unit 40, such as performing mathematical operations like sampling accumulation and simulated watchdog detection, and then send the processing results to the slave decoder unit 80.

[0081] In some embodiments, the analog-to-digital converter control system further includes a slave decoder unit 80, which is connected to a plurality of slave units 40.

[0082] In cases where it is not necessary to process the conversion results sent by slave unit 40, slave decoder unit 80 can be directly connected to slave unit 40 to obtain the conversion results.

[0083] like Figure 5 As shown, the destination of the output signal of this application is a storage unit such as a user register. After receiving the conversion result, the slave decoder unit can save the conversion result to the specified storage unit address.

[0084] In some embodiments, the analog-to-digital converter control system further includes a second arithmetic processing unit 90, which is connected to the slave decoder unit 80.

[0085] In some of these embodiments, each analog-to-digital conversion control unit 60 is connected to an analog unit, and the digital signal interface and timing of the analog-to-digital conversion control unit 60 are matched with those of the analog unit.

[0086] The analog unit is an analog-to-digital converter.

[0087] Each analog-to-digital conversion control unit 60 synchronously controls one analog-to-digital converter (analog unit) to complete one analog-to-digital conversion.

[0088] In some of these embodiments, the digital signal interface of the analog-to-digital conversion control unit 60 is matched with the analog unit.

[0089] In some of these embodiments, the functional specifications of each simulation unit may be different.

[0090] This invention coordinates the collaborative work of analog units of different specifications through a control relationship chain of host unit-slave unit-analog-digital conversion control unit-analog unit, so as to solve the shortcomings of the complex circuit of interleaved sampling conversion of multiple ADC systems in the prior art.

[0091] In some embodiments, the slave arbitration unit 30 is connected to two master units 20 respectively, and the two master units 20 are configured as a regular sequence master unit and an injected sequence master unit respectively. The priority value of the regular sequence master unit is greater than the priority value of the injected sequence master unit, that is, the priority of the injected sequence master unit is higher than the priority of the regular sequence master unit.

[0092] For example, such as Figure 6 As shown, the regular sequence is configured in host unit 1, and the injected sequence is configured in host unit 2, with host unit 2 having a higher priority than host unit 1. When host unit 1 controls slave unit 40, if host unit 2 initiates a control request, slave unit 40 will disconnect from host unit 1 and establish a control relationship with host unit 2. After host unit 2 completes its task and disconnects from slave unit 40, host unit 1 re-establishes a control relationship with slave unit 40, thus realizing the traditional analog-to-digital converter control technology.

[0093] This embodiment can realize the interconnection and control of one or more analog-to-digital conversion units; each analog-to-digital conversion unit can operate at different clock frequencies; each analog-to-digital conversion unit can work independently or collaboratively; it can handle multiple analog-to-digital conversion tasks, and each task can be assigned to multiple analog-to-digital conversion units.

[0094] This invention can automatically complete various conversion tasks without software intervention, and obtain data stored in the user register. It can automatically complete various pre-arranged conversion tasks, such as determining the priority of the host unit based on the priority value of the host unit in the user register, and can process multiple conversion tasks continuously and in parallel until the conversion tasks are stopped or updated.

[0095] Example 2

[0096] This embodiment provides an analog-to-digital converter (ADC) control chip, including the ADC control system as described in any of Embodiment 1.

[0097] Example 3

[0098] This embodiment provides an analog-to-digital converter (ADC) control device, including an ADC control system as described in any of Embodiment 1 or an ADC control chip as described in Embodiment 2.

[0099] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.

[0100] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An analog-to-digital converter control system, characterized by, The analog-to-digital converter control system comprises a plurality of host data processing units, a plurality of host units, a plurality of slave arbitration units, a plurality of slave units, a plurality of cross-clock domain bridges, and a plurality of analog-to-digital conversion control units. Each of the host data processing units is connected with a corresponding host unit, each of the host units is connected with the plurality of slave arbitration units, each of the slave arbitration units is connected with a corresponding slave unit, each of the slave units is connected with a corresponding cross-clock domain bridge, and each of the cross-clock domain bridges is connected with a corresponding analog-to-digital conversion control unit. The slave arbitration unit is provided with a digital comparator connected with the slave arbitration unit and used for comparing a plurality of priority values sent by the plurality of host units. Each of the slave arbitration units is connected with two host units, wherein the two host units are configured as a regular sequence host unit and an injected sequence host unit, and the priority value of the regular sequence host unit is greater than the priority value of the injected sequence host unit. The host unit is configured to send a priority value to the plurality of slave arbitration units, and the slave arbitration unit is configured to connect the host unit with a corresponding slave unit according to the priority value.

2. The analog-to-digital converter control system of claim 1, wherein, The clock domains of the plurality of analog-to-digital conversion control units are independent of each other.

3. The analog-to-digital converter control system of claim 1, wherein, The plurality of host data processing units, the plurality of host units, the plurality of slave arbitration units, and the plurality of slave units operate under the same master clock domain.

4. The analog-to-digital converter control system of claim 1, wherein, The analog-to-digital converter control system further comprises: a first operation processing unit connected with a corresponding slave unit; a slave decoder unit connected with the first operation processing unit.

5. The analog-to-digital converter control system of claim 1, wherein, The analog-to-digital converter control system further comprises: a slave decoder unit connected with the plurality of slave units.

6. The analog-to-digital converter control system of any of claims 4-5, wherein, The analog-to-digital converter control system further comprises: a second operation processing unit connected with the slave decoder unit.

7. An analog-to-digital converter control chip, characterized by The analog-to-digital converter control system comprises the analog-to-digital converter control system according to any one of claims 1 to 6.

8. An analog-to-digital converter control device, characterized by The analog-to-digital converter control system comprises the analog-to-digital converter control system according to any one of claims 1 to 6.

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