A novel structure of thermal tuning laser chip and a manufacturing method thereof

Abstract

This invention relates to the field of semiconductor laser chip technology, and provides a novel thermally tunable laser chip and its fabrication method. The chip includes a substrate and multiple functional layers sequentially grown on the substrate. Specifically, thermally insulating grooves connecting to the substrate are etched into channels on both sides of a ridge waveguide. At least one functional layer below the ridge waveguide is hollowed out to form a hollow thermally insulating region, with the two sides of the hollow thermally insulating region adjacent to the thermally insulating grooves. This invention avoids heat loss within the chip, improves the chip's thermal insulation effect, and thus improves the chip's thermal tuning efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser chip technology, and in particular to a novel thermally tunable laser chip and its fabrication method. Background Technology

[0002] Tunable semiconductor lasers, as lasers whose output wavelength can be continuously changed within a certain range, are key components of dense wavelength division multiplexing systems and future all-optical networks. Their advantages will become increasingly prominent as the demand for transmission speed and capacity in network systems continues to rise. The unique advantages of tunable lasers in terms of tuning range and narrow linewidth have attracted numerous researchers to study their structure, aiming to adjust parameters such as temperature and current within the laser cavity to emit different wavelengths.

[0003] In tunable semiconductor lasers, the temperature inside the optical cavity is mainly adjusted by resistors. However, in the existing technology, the temperature insulation effect of semiconductor lasers is poor, and the heat generated by the resistors is easily spread to the outside, resulting in low utilization of the heat of the resistors. The temperature inside the optical cavity cannot reach the expected temperature, thus affecting the thermal tuning efficiency of the chip.

[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem to be solved by this invention is that the tunable semiconductor laser chip has poor temperature insulation and low thermal tuning efficiency.

[0006] The present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a novel thermally tunable laser chip, comprising a substrate 1 and a plurality of functional layers 2 sequentially grown on the substrate 1, specifically:

[0008] Thermal insulation grooves 3 that connect to the substrate 1 are etched on both sides of the ridge waveguide. At least one functional layer 2 below the ridge waveguide is hollowed out to form a hollow thermal insulation region 4. The two sides of the hollow thermal insulation region 4 are adjacent to the thermal insulation grooves 3.

[0009] Preferably, the inner wall of the heat insulation groove 3 is provided with a support and corrosion-resistant structure 5. The support and corrosion-resistant structure 5 is composed of a first support and corrosion-resistant part 51 and a second support and corrosion-resistant part 52 spaced apart. In the first support and corrosion-resistant part 51, the heat insulation groove 3 and the hollow heat insulation area 4 are separated by the first support and corrosion-resistant part 51. In the second support and corrosion-resistant part 52, the heat insulation groove 3 and the hollow heat insulation area 4 are connected.

[0010] Preferably, the second support corrosion inhibitor portion 52 is sputtered metal Ti and Pt. The second support corrosion inhibitor portion 52 consists of a first layer of sputtered metal Ti and Pt, which is the outermost layer adjacent to the heat insulation groove 3, and the second layer is an oxide film deposited by CVD.

[0011] Preferably, the plurality of functional layers 2 sequentially grown on the substrate 1 include at least one of the following: lower etch stop layer 21, lower sacrificial layer 22, upper etch stop layer 23, upper sacrificial layer 24, active layer 25, and contact layer 26.

[0012] Preferably, it also includes two parts: resistor 6 and electrode 7. Each resistor 6 is sputtered on the ridge waveguide of the laser above the dielectric layer, and each resistor 6 is connected to a set of electrodes 7.

[0013] Secondly, this invention provides a novel method for fabricating a thermally tunable laser chip, wherein multiple functional layers 2 are sequentially grown on a substrate 1 in advance, the method comprising:

[0014] A ridge waveguide structure is etched on the plurality of functional layers 2, wherein the channel of the ridge waveguide structure is etched to the active layer 25;

[0015] The location of the heat insulation groove 3 is drawn by photolithography, and the first groove is obtained by etching and / or wet etching. The first groove is hollowed out to the upper corrosion stop layer 23; a second support corrosion inhibitor 52 is grown on the inner wall of the first groove.

[0016] The upper corrosion stop layer 23, the lower sacrificial layer 22 and the lower corrosion stop layer 21 below the first groove are hollowed out by etching and / or wet etching to form a heat insulation groove 3 that is connected to the substrate 1; a first support corrosion inhibitor portion 51 is grown at intervals on the inner wall of the heat insulation groove 3.

[0017] Corrosion liquid is injected into the second support corrosion-resistant part 52, and the lower corrosion stop layer 21 below the ridge waveguide structure is hollowed out by wet corrosion to obtain the hollow heat insulation area 4.

[0018] Preferably, the laser chip is fabricated on the laser wafer 8, and the method further includes:

[0019] Multiple laser chips are disposed on the laser wafer 8. An ultrasonic detector 9 is disposed at the contact position between the laser wafer 8 and the laser chips. The ultrasonic detector 9 includes a probe 91 and a processor 92. The probe 91 of the ultrasonic detector 9 is in seamless contact with the laser chip substrate 1 to detect the completion of the hollow heat insulation region 4 in the laser chip.

[0020] When the ultrasonic detector 9 detects that the hollow heat insulation area 4 of the corresponding laser chip is fully formed, and the inner walls on both sides of the laser chip still retain part of the structure of the lower corrosion stop layer 21, the laser chip is manufactured and qualified.

[0021] Preferably, the step of detecting the completeness of the hollow heat insulation region 4 in the laser chip specifically includes:

[0022] The probe 91 emits a wave towards the substrate 1. When the emitted wave enters the etching solution from the substrate 1, it is reflected once and the probe 91 receives the first echo. When the emitted wave enters the corresponding upper functional layer 2 from the etching solution, it is reflected twice and the probe 91 receives the second echo.

[0023] The completion degree of the cavity insulation region 4 is determined based on the time difference between the first and second echoes received by the probe 91.

[0024] Preferably, obtaining the ridge waveguide structure through etching specifically includes:

[0025] The corresponding ridge waveguide pattern is defined on the surface of the functional layer 2 grown sequentially on the substrate 1 by photolithography. Based on the defined ridge waveguide pattern, etching is performed on the semiconductor chip, and the etching depth exceeds the contact layer 26.

[0026] An acidic etching solution is used to etch the chip waveguide layer, thereby forming grooves on the left and right sides of the semiconductor chip waveguide that extend along the direction close to the substrate 1.

[0027] Preferably, the step of hollowing out the upper etch stop layer 23, lower sacrificial layer 22, and lower etch stop layer 21 below the first groove by etching and / or wet etching to form a heat-insulating groove 3 that is conductive to the substrate 1 specifically includes:

[0028] The lower sacrificial layer 22 of the InP material is etched using a hydrochloric acid solution, and the lower etching stop layer 21 of the InGaAsP material is etched using an H2SO4 acid solution to form a heat-insulating groove 3 that is connected to the substrate 1.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention prevents heat from being transferred from the bottom to the substrate by setting a hollow heat insulation area under the ridge waveguide, and sets heat insulation grooves on both sides of the ridge waveguide to prevent heat from being transferred to the edge of the chip, thereby preventing heat from being transferred from the edge of the chip to the substrate and leaking out from the substrate, avoiding heat loss inside the chip, improving the temperature insulation effect of the chip, and thus improving the thermal tuning efficiency of the chip. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a cross-sectional view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0032] Figure 2 This is a cross-sectional view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0033] Figure 3 This is a cross-sectional view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0034] Figure 4 This is a cross-sectional view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0035] Figure 5 This is a cross-sectional view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0036] Figure 6 This is a cross-sectional view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0037] Figure 7 This is a top view schematic diagram of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0038] Figure 8 This is a flowchart illustrating a novel thermally tunable laser chip fabrication method provided in an embodiment of the present invention.

[0039] Figure 9 This is a flowchart illustrating a novel thermally tunable laser chip fabrication method provided in an embodiment of the present invention.

[0040] Figure 10 This is a schematic diagram of the structure of the laser wafer used in a novel thermally tunable laser chip fabrication method provided in an embodiment of the present invention.

[0041] Figure 11 This is a schematic diagram of the structure of the ultrasonic detector in the laser wafer used in a novel thermally tunable laser chip fabrication method provided in an embodiment of the present invention.

[0042] Figure 12This is a partially enlarged schematic diagram of the wafer and laser chip during the fabrication process of a novel thermally tunable laser chip according to an embodiment of the present invention.

[0043] Figure 13 This is a partially enlarged schematic diagram of the wafer and laser chip during the fabrication process of a novel thermally tunable laser chip according to an embodiment of the present invention.

[0044] Figure 14 This is a schematic diagram showing the position of the ultrasonic detector in the laser wafer used in a novel thermally tunable laser chip fabrication method provided in this embodiment of the invention.

[0045] Figure 15 This is a flowchart of a method for fabricating a novel thermally tunable laser chip according to an embodiment of the present invention.

[0046] In all the accompanying drawings, the reference numerals are as follows, wherein:

[0047] 1. Substrate; 2. Functional layer; 21. Lower etch stop layer; 22. Lower sacrificial layer; 23. Upper etch stop layer; 24. Upper sacrificial layer; 25. Active layer; 26. Contact layer; 3. Thermal insulation groove; 4. Void thermal insulation area; 5. Support corrosion inhibition structure; 51. First support corrosion inhibition part; 52. Second support corrosion inhibition part; 6. Resistor; 7. Electrode; 8. Laser wafer; 9. Ultrasonic detector; 91. Probe; 92. Processor. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0049] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0050] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0051] Example 1:

[0052] Embodiment 1 of the present invention provides a novel thermally tunable laser chip, comprising a substrate 1 and multiple functional layers 2 sequentially grown on the substrate 1, such as... Figure 1 As shown, specifically:

[0053] Thermal insulation grooves 3 that connect to the substrate 1 are etched on both sides of the ridge waveguide. At least one functional layer 2 below the ridge waveguide is hollowed out to form a hollow thermal insulation region 4. The two sides of the hollow thermal insulation region 4 are adjacent to the thermal insulation grooves 3.

[0054] Each functional layer 2 is tightly connected and fixed to the inner wall of the chip. The inner wall of the chip can be the inner wall around the chip or the upper inner wall of the chip, specifically the inner wall of the chip that is bonded or fixed to the retained functional layer 2. This allows the ridge waveguide to be suspended and supported by the retained functional layer 2 when the area below the ridge waveguide is hollowed out.

[0055] The connection to the substrate 1 can be to the upper surface of the substrate 1, or the substrate 1 can be partially hollowed out to form a larger heat insulation groove 3 volume and optimize the heat insulation effect.

[0056] Ideally, the corresponding functional layer 2 should not have any structural losses other than forming the hollow heat insulation region 4 and the heat insulation groove 3. However, due to the process limitations in the mass production of laser chips, while forming the hollow heat insulation region 4, the functional layer 2 used to generate the hollow heat insulation region 4 may also form corresponding small cavities on both sides of the heat insulation groove 3, such as... Figure 1 As shown, in this case, a preferred implementation is that the functional layer 2, which is used to form the hollow heat insulation region 4, retains a partial structure on both sides of the heat insulation groove 3 to provide support for the laser chip.

[0057] Research and testing revealed that the heat generated by the chip during normal operation is mainly exchanged with the outside air through the substrate 1 material. In this embodiment, a hollow heat insulation area 4 is set below the ridge waveguide to prevent heat from being transferred from below to the substrate 1. Heat insulation grooves 3 are set on both sides of the ridge waveguide to prevent heat from being transferred to the edge of the chip. This prevents heat from being transferred from the edge of the chip to the substrate 1 and then leaking out from the substrate 1, thus avoiding heat loss inside the chip, improving the chip's heat insulation effect, and thereby improving the chip's thermal tuning efficiency.

[0058] To further reduce heat diffusion from below to the substrate 11, in conjunction with the above embodiments, the following preferred implementations also exist, such as... Figure 2 and Figure 3 As shown, it specifically includes:

[0059] The inner wall of the heat insulation groove 3 is provided with a support and corrosion-resistant structure 5. The support and corrosion-resistant structure 5 is composed of a first support and corrosion-resistant part 51 and a second support and corrosion-resistant part 52 spaced apart. In the first support and corrosion-resistant part 51, the heat insulation groove 3 and the hollow heat insulation area 4 are separated by the first support and corrosion-resistant part 51. In the second support and corrosion-resistant part 52, the heat insulation groove 3 and the hollow heat insulation area 4 are connected.

[0060] To illustrate the specific distribution of the first corrosion-resistant support portion 51 and the second corrosion-resistant support portion 52 in the laser chip, this embodiment also provides... Figure 4 and Figure 5 The diagram shown is a top-view cross-sectional view of the laser chip structure, with the plane containing the hollow heat insulation region 4 as the focal point. Figure 4 The first support corrosion-resistant portion 51 and the second support corrosion-resistant portion 52 are marked. It can be seen that at the location of the second support corrosion-resistant portion 52, the hollow heat-insulating area 4 is connected to the heat-insulating groove 3; at the location of the first support corrosion-resistant structure 51, the hollow heat-insulating area 4 is separated from the heat-insulating groove 3. And... Figure 5 In the diagram, dashed line 1b represents the location of the second support corrosion-resistant part 52, and dashed line 2b represents the location of the first support corrosion-resistant part 51. Figure 2 and Figure 3 These are schematic diagrams of the laser chip obtained by longitudinally slicing it from positions 2b and 1b (dashed lines).

[0061] The corrosion-resistant support structure 5 can be composed of one or more layers, or it can be a single dielectric layer. In this embodiment of the invention, a preferred implementation is provided, which specifically includes: the second corrosion-resistant support portion 52 is sputtered metal Ti and Pt, and the second corrosion-resistant support portion 52 consists of a first layer of sputtered metal Ti and Pt, which is the outermost layer adjacent to the heat insulation groove 3, and the second layer is an oxide film deposited by CVD.

[0062] The distribution characteristics of the first support corrosion-resistant portion 51 and the second support corrosion-resistant portion 52 need to be determined by comprehensively considering multiple factors such as the support of the laser chip and the fabrication of the hollow heat insulation area 4.

[0063] This preferred embodiment, by providing a supporting corrosion-resistant structure 5 on the inner wall of the heat insulation groove 3, not only enhances heat insulation and prevents the corresponding functional layers 2 from being corroded in subsequent processes, thus improving the thermal tuning efficiency of the chip, but also provides corresponding support to the ridge waveguide through the multiple functional layers 2 connected to the outer wall of the supporting corrosion-resistant structure 5. This achieves double support for the ridge waveguide, enhancing the stability of the ridge waveguide structure and preventing the chip structure from collapsing due to external forces. Furthermore, by integrating heat insulation and support, this embodiment reduces the chip space required when separately setting up the heat insulation structure and support frame. By placing the supporting corrosion-resistant structure 5 on the inner wall of the heat insulation groove 3, it reduces the difficulty of the manufacturing process and makes reasonable use of existing space, eliminating the need for additional space and reducing the chip's space occupation, thus providing a basis for the miniaturization of the chip.

[0064] Meanwhile, the second support and corrosion-resistant part 52 of the support and corrosion-resistant structure 5 also connects the heat insulation groove 3 to the hollow heat insulation area 4, so that the heat insulation grooves 3 on both sides can exchange heat through the hollow heat insulation area 4, thereby forming a complete heat insulation cavity that is connected and avoids heat loss.

[0065] like Figure 6 As shown, the plurality of functional layers 2 sequentially grown on the substrate 1 include at least one of the following: lower etch stop layer 21, lower sacrificial layer 22, upper etch stop layer 23, upper sacrificial layer 24, active layer 25, and contact layer 26.

[0066] The specific structure of the aforementioned functional layer 2 depends on the actual scenario and can be one or more of the following: a laser layer structure, a detector layer structure, a modulator layer structure, or a passive waveguide layer structure. In actual implementation, these various functional layers 2 are usually designed in combination to address different thermally tunable laser chip requirements. The laser layer structure and the modulator layer structure are typically the most practically significant in terms of performance. Other functional layers 2 are designed based on the support requirements, thermal insulation requirements, and fabrication process of the ridge waveguide. The designed parameters include, but are not limited to, the material, thickness, and arrangement of the functional layers 2.

[0067] In this embodiment of the invention, a more practical complex structure diagram is also provided, such as... Figure 7 As shown, it also includes two parts: resistor 6 and electrode 7. Each resistor 6 is sputtered on the ridge waveguide of the laser above the dielectric layer, and each resistor 6 is connected to a set of electrodes 7.

[0068] The heat-insulating groove 3 and the hollow heat-insulating region 4 in this embodiment can be applied to areas of the thermally tunable laser chip, including but not limited to the front grating region, phase region, and rear grating region. This embodiment can be applied to specific regions individually or in combination to multiple regions.

[0069] In the embodiments of the present invention, the limiting descriptions such as "first" and "second" do not refer to a specific order. They are merely used to separate the corresponding limited objects from the same category and to facilitate the description of two or more different objects in the same category. They should not be interpreted as having a further limiting meaning.

[0070] Example 2:

[0071] This invention provides a novel method for fabricating a thermally tunable laser chip, which can be used to fabricate the novel thermally tunable laser chip described in Embodiment 1. It should be noted that this invention focuses on the method process output related to substantially differentiating features; other processes, such as the fabrication of electrode 7, are not within the scope of this invention and are conventional prior art, therefore they will not be described in detail later in this invention. In this invention embodiment, as... Figure 6 As shown, multiple functional layers 2 are sequentially grown on substrate 1 in advance, the method including:

[0072] A ridge waveguide structure is etched on the plurality of functional layers 2, wherein the channel of the ridge waveguide structure is etched to the active layer 25.

[0073] In step 201, the location of the heat insulation groove 3 is drawn by photolithography, and the first groove is obtained by etching and / or wet etching. The first groove is hollowed out to the upper etching stop layer 23.

[0074] In step 202, a second support and corrosion-resistant portion 52 is grown on the inner wall of the first groove.

[0075] In step 203, the upper etch stop layer 23, the lower sacrificial layer 22 and the lower etch stop layer 21 below the first groove are hollowed out by etching and / or wet etching to form a heat insulation groove 3 that is connected to the substrate 1.

[0076] In step 204, a first support and corrosion-resistant portion 51 is grown at intervals on the inner wall of the heat insulation groove 3.

[0077] In step 205, an etchant is injected into the second support corrosion-resistant portion 52, and the lower corrosion stop layer 21 below the ridge waveguide structure is hollowed out by wet etching to obtain the hollow heat insulation area 4.

[0078] The second support corrosion-resistant portion 52 supports the functional layer 2 above the upper corrosion-stopping layer 23 and also provides a pathway for the fabrication of the void insulation region 4. The first support corrosion-resistant portion 51 supports the entire laser chip.

[0079] As a preferred implementation, when growing the second support corrosion inhibitor 52, there is no need for interval growth; Ti and Pt metals can be directly sputtered onto the inner wall of the first groove. When growing the first support corrosion inhibitor 51, since a sputtered metal inner wall has already been grown on the inner wall of the first groove, an oxide film can be directly deposited on the sputtered metal inner wall to form the first support corrosion inhibitor 51.

[0080] In this embodiment, a first support and corrosion-resistant part 51 is set before the hollow heat insulation region 4 is made, and a second support and corrosion-resistant part 52 is used to reserve a passage for the making of the hollow heat insulation region 4. This ensures that sufficient support is provided for the ridge waveguide during the making of the hollow heat insulation region 4, so that the ridge waveguide structure does not collapse.

[0081] In this embodiment of the invention, a scenario for implementing a laser is provided, such as... Figure 7 As shown, the growth layered substrate 11 specifically includes:

[0082] A lower etch stop layer 21, a lower sacrificial layer 22, an upper etch stop layer 23, an upper sacrificial layer 24, an active layer 25, and a contact layer 26, all made of multi-element materials, are sequentially grown on substrate 1. The present invention also provides specific material parameters for the functional layer 2, including:

[0083] The lower corrosion stop layer 21 is made of InGaAsP material, the lower sacrificial layer 22 is made of InP material, the upper corrosion stop layer 23 is made of InGaAsP material, the upper sacrificial layer 24 is made of InP material, the active layer 25 is made of InGaAsP material, and the contact layer 26 is made of InGaAsP material.

[0084] The processing technology for each functional layer 2 is determined by the processing requirements of the corresponding functional layer 2 and the material of the functional layer 2. Next, taking the materials of each functional layer 2 given in this embodiment as examples, the process of generating the corresponding ridge waveguide structure and generating the heat insulation groove 3 and the void heat insulation region 4 of the present invention will be described one by one.

[0085] Laser chips are fabricated on laser wafer 8, such as... Figure 9 As shown, the method further includes:

[0086] In step 301, a plurality of laser chips are disposed on the laser wafer 8. An ultrasonic detector 9 is disposed at the contact position between the laser wafer 8 and the laser chips. The ultrasonic detector 9 includes a probe 91 and a processor 92. The probe 91 of the ultrasonic detector 9 is in seamless contact with the laser chip substrate 1 to detect the completion of the void heat insulation region 4 in the laser chip.

[0087] In step 302, when the ultrasonic detector 9 detects that the hollow heat insulation area 4 of the corresponding laser chip is fully formed, and the inner walls on both sides of the laser chip still retain part of the structure of the lower corrosion stop layer 21, the laser chip is completed and qualified.

[0088] The laser wafer 8 refers to the silicon wafer used in the fabrication of silicon semiconductor integrated circuits. Because of its circular shape, it is called a wafer. Various circuit element structures can be fabricated on the silicon wafer to become IC products with specific electrical functions (e.g., laser chips, detector chips, driver chips, etc.).

[0089] On the laser wafer 8, as Figure 10 As shown, multiple laser chips are arranged in an array, thereby enabling mass production of laser chips.

[0090] like Figure 11 As shown, the ultrasonic detector 9 includes a probe 91 and a corresponding processor 92. The probe 91 includes an ultrasonic transmitting unit and an ultrasonic receiving unit for emitting transmitted waves and receiving echoes. The processor 92 is used to determine the completion degree of the cavity insulation region 4 based on the signal feedback from the probe 91.

[0091] Each laser chip corresponds to one or more probes 91. The number of probes 91 is determined by those skilled in the art based on the internal structure and size of the laser chip. Probes 91 of multiple laser chips can belong to the same ultrasonic detector 9, that is, they are processed by the same processor 92. Alternatively, probes 91 of one laser chip can correspond to one ultrasonic detector 9.

[0092] Because the acoustic impedance of functional layer 2 and the etching solution differs, when ultrasonic waves enter the etching solution from or from the corresponding functional layer 2, the ultrasonic waves will exhibit projection and reflection. Since all functional layers 2 are solids, their acoustic impedances differ only slightly, and the transmittance of ultrasonic waves between the multiple functional layers 2 is much greater than their reflectance. Therefore, ultrasonic waves can be considered to be able to directly transmit between the multiple functional layers 2. Based on this principle, and combined with the manufacturing structure characteristics of the laser chip described in this embodiment, the following preferred embodiment is obtained, namely, the method for detecting the completion of the hollow thermal insulation region 4 in the laser chip specifically includes:

[0093] The probe 91 emits a wave towards the substrate 1. When the emitted wave enters the etching solution from the substrate 1, it is reflected once and the probe 91 receives the first echo. When the emitted wave enters the corresponding upper functional layer 2 from the etching solution, it is reflected twice and the probe 91 receives the second echo.

[0094] The completion degree of the cavity insulation region 4 is determined based on the time difference between the first and second echoes received by the probe 91.

[0095] like Figure 12 As shown, when the cavity insulation area 4 is not completely corroded, the ultrasonic wave is directly transmitted from the substrate 1 through the lower corrosion stop layer 21, and cannot generate the first and second echoes. When the lower corrosion stop layer 21 below the corresponding ridge waveguide is corroded through, as... Figure 13 As shown, when the ultrasonic wave passes through the substrate 1 and enters the corroded area, part of the ultrasonic wave is reflected by the corrosive liquid to obtain the first echo, and the other part enters the corrosive liquid to continue propagating until it passes through the corrosive liquid. Then, it is reflected by the corresponding functional layer 2 to obtain the second echo. By processing the time difference between the first echo and the second echo, the height of the corroded area can be obtained, thereby determining whether the cavity insulation area 4 is completed.

[0096] It should be noted that when the ultrasonic waves propagate between each functional layer 2, and between the corrosive liquid and functional layer 2, there are corresponding reflected and transmitted light components. However, since the acoustic impedance differences between each functional layer 2 are small, the reflected light component can be ignored in this scheme. Alternatively, the receiving and sensing range of the probe 91 can be adjusted to prevent this reflected light from being sensed and received by the probe 91, thereby avoiding its impact on the scheme. The transmitted light component that enters the functional layer 2 through the corrosive liquid only causes a significant attenuation of the second echo relative to the ultrasonic waves incident in the corrosive liquid, and has no effect on measuring the time difference between the first and second echoes.

[0097] As an extended implementation, another approach is to use the relative attenuation between the first echo, the second echo, and the emitted wave to obtain the height of the corroded area and determine whether the cavity insulation area 4 is complete.

[0098] In this embodiment, while ensuring that the lower etch stop layer 21 below the ridge waveguide is hollowed out, it is also necessary to ensure that a portion of the lower etch stop layer 21 structure is still retained on the inner walls of both sides of the laser chip to provide better support for the ridge waveguide. Therefore, ultrasonic detection is also required on both sides of the laser chip. A specific implementation is provided here:

[0099] Lasers are positioned at laser wafer position 8 directly below the ridge waveguide, and at laser wafer positions 8 on both sides of the ridge waveguide at corresponding distances from the center of the ridge waveguide. Figure 14 As shown, the first probe 91 is located directly below the ridge waveguide and is used to detect whether the lower corrosion stop layer 21 below the ridge waveguide has been corroded through. The second probe 91 and the third probe 91 are located on both sides of the ridge waveguide and are used to detect whether the lower corrosion stop layer 21 still has some structure on both sides of the channel.

[0100] The lower corrosion stop layer 21 was etched using an H2SO4 solution for a preset corrosion time. Before the corrosion was completed, the laser chip was subjected to ultrasonic testing.

[0101] Specifically, when the first probe 91 receives the first echo and the second echo, and the time difference between the first echo and the second echo is greater than or equal to a preset time difference, it is considered that the lower corrosion stop layer 21 below the ridge waveguide has been corroded through. Simultaneously, the status of the second probe 91 and the third probe 91 is assessed. If neither the second probe 91 nor the third probe 91 receives an echo, it is considered whether any portion of the lower corrosion stop layer 21 still remains on either side of the channel. If both conditions are met, the corrosion of the void insulation structure is complete.

[0102] If the second probe 91 or the third probe 91 receives an echo, it is considered that there is over-corrosion and the laser chip is not up to standard.

[0103] To more intuitively illustrate the various locations to be detected and the relationship between the emitted and echoed waves, the above implementation method uses the form of a straight probe 91 for detection in the corresponding figures and text. However, this does not mean that the type, number, or placement of the probe 91 is limited. For example, it is also feasible to use a single array of probes 91 to detect the completeness of the void insulation structure. The placement of the probe 91 is determined by those skilled in the art based on the type of probe 91 selected.

[0104] The preset corrosion time is determined by those skilled in the art by taking into account factors such as the corrosion characteristics of the lower corrosion stop layer 21, the distribution of the first support corrosion-resistant portion 51 and the second support corrosion-resistant portion 52, and the width of the lower corrosion stop layer 21 on both sides of the heat insulation groove 3. The setting is based on the fact that after corrosion for the preset corrosion time, the lower corrosion stop layer 21 located directly below the ridge waveguide of the first support corrosion-resistant portion 51 and the second support corrosion-resistant portion 52 will be corroded through, and the lower corrosion stop layer 21 on both sides of the heat insulation groove 3 will still have a retained structure, and the width of the retained structure will be greater than or equal to the preset length.

[0105] The preset length is determined by comprehensively considering the width of the spine, the thickness of the lower corrosion stop layer 21, the width of the heat insulation groove 3, and the distribution characteristics of the first support corrosion-resistant portion 51 and the second support corrosion-resistant portion 52. Generally, the wider the spine and the thinner the lower corrosion stop layer 21, the smaller the preset length needs to be. However, in order to provide sufficient support for the spine waveguide, the larger the proportion of the length of the second support corrosion-resistant portion 52 in the support corrosion-resistant structure 5, the larger the preset length needs to be. The preset time difference is derived from the thickness analysis of the lower corrosion stop layer 21.

[0106] This embodiment also provides a preset corrosion time standard, namely, the corrosive liquid is poured from the second support corrosion-resistant part 52 and undergoes planar diffusion corrosion, thereby forming a void heat-insulating area 4 at the first support corrosion-resistant part 51. The preset corrosion time is the time it takes for both the first and second support corrosion-resistant parts 51 and 52 to form void heat-insulating areas 4. The preset corrosion time is calculated and analyzed precisely based on the lower layer width of the spine, the length of the first support corrosion-resistant part 51, the length of the second support corrosion-resistant part 52, and the corrosion characteristics of the lower corrosion-stopping layer 21, or measured experimentally. By appropriately reducing the ratio of the length of the first support corrosion-resistant part 51 to the length of the second support corrosion-resistant part 52, the preset corrosion time can be reduced, thereby ensuring that the structure of the lower corrosion-stopping layer 21 on both sides of the heat-insulating groove 3 reaches the preset length.

[0107] The ridge waveguide structure obtained by etching, as shown in Figure 14, specifically includes:

[0108] In step 401, a corresponding ridge waveguide pattern is defined on the surface of the functional layer 2 grown sequentially on the substrate 1 by photolithography. Based on the defined ridge waveguide pattern, etching is performed on the semiconductor chip, and the etching depth exceeds the contact layer 26.

[0109] In step 402, an acidic etching solution is used to etch the chip waveguide layer to form trenches on the left and right sides of the semiconductor chip waveguide, extending along the direction close to the substrate 1.

[0110] The process of hollowing out the upper etch stop layer 23, lower sacrificial layer 22, and lower etch stop layer 21 below the first groove through etching and / or wet etching to form a heat-insulating groove 3 that is conductive to the substrate 1 specifically includes:

[0111] The lower sacrificial layer 22 of the InP material is etched using a hydrochloric acid solution, and the lower etching stop layer 21 of the InGaAsP material is etched using an H2SO4 acid solution to form a heat-insulating groove 3 that is connected to the substrate 1.

[0112] The upper cross section of the ridge waveguide structure and the heat insulation groove 3, which are fabricated by photolithography, can be square, circular, or other shapes, depending on the actual situation. No specific limitations are made here.

[0113] An optional formulation of the H2SO4-based solution is composed of H2O2 and H2SO4. An optional formulation of the hydrochloric acid-based solution is composed of HCl and H3PO4, wherein the ratio of HCl to H3PO4 is 1:3.

[0114] In the embodiments of the present invention, the limiting descriptions such as "first" and "second" do not refer to a specific order. They are merely used to separate the corresponding limited objects from the same category and to facilitate the description of two or more different objects in the same category. They should not be interpreted as having a further limiting meaning.

[0115] In the embodiments of this invention, expressions such as "A and / or B" actually mean that the implementation can be implemented with A as an object, or with B as an object, or with a combination of A and B. A and B can also be replaced with specific subject name objects according to the needs of the specific description scenario.

[0116] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A novel thermally tunable laser chip, characterized in that, It includes a substrate (1) and multiple functional layers (2) sequentially grown on the substrate (1), specifically: Thermal insulation grooves (3) that connect to the substrate (1) are etched on both sides of the ridge waveguide. At least one functional layer (2) below the ridge waveguide is hollowed out to form a hollow thermal insulation region (4). The two sides of the hollow thermal insulation region (4) are adjacent to the thermal insulation grooves (3). The inner wall of the heat insulation groove (3) is provided with a support corrosion-resistant structure (5). The support corrosion-resistant structure (5) is composed of a first support corrosion-resistant part (51) and a second support corrosion-resistant part (52) spaced apart. In the first support corrosion-resistant part (51), the heat insulation groove (3) is separated from the hollow heat insulation area (4). In the second support corrosion-resistant part (52), the heat insulation groove (3) is connected to the hollow heat insulation area (4).

2. The novel thermally tunable laser chip according to claim 1, characterized in that, The second support corrosion inhibitor portion (52) is sputtered metal Ti and Pt, and the first support corrosion inhibitor portion (51) is formed by a first layer of sputtered metal Ti and Pt and a second layer of deposited oxide film.

3. The novel thermally tunable laser chip according to claim 1, characterized in that, The plurality of functional layers (2) grown sequentially on the substrate (1) include at least one of the following: lower etch stop layer (21), lower sacrificial layer (22), upper etch stop layer (23), upper sacrificial layer (24), active layer (25), and contact layer (26).

4. The novel thermally tunable laser chip according to claim 1, characterized in that, It also includes two parts: resistors (6) and electrodes (7). Each resistor (6) is sputtered on the ridge waveguide of the laser above the dielectric layer, and each resistor (6) is connected to a set of electrodes (7).

5. A method for fabricating a thermally tunable laser chip with a novel structure as described in any one of claims 1-4, characterized in that, A plurality of functional layers (2) are sequentially grown on a substrate (1) in advance, the method comprising: A ridge waveguide structure is etched on the plurality of functional layers (2), wherein the channel of the ridge waveguide structure is etched to the active layer (25). The location of the heat insulation groove (3) is drawn by photolithography, and the first groove is obtained by etching and / or wet etching. The first groove is hollowed out to the upper corrosion stop layer (23); a second support corrosion inhibitor part (52) is grown on the inner wall of the first groove. The upper corrosion stop layer (23), lower sacrificial layer (22) and lower corrosion stop layer (21) below the first groove are hollowed out by etching and / or wet etching to form a heat insulation groove (3) that is connected to the substrate (1); a first support corrosion inhibitor portion (51) is grown at intervals on the inner wall of the heat insulation groove (3). Corrosion liquid is injected from the second support corrosion-resistant part (52), and the lower corrosion stop layer (21) below the ridge waveguide structure is hollowed out by wet corrosion to obtain the cavity heat insulation area (4).

6. The method for fabricating a novel thermally tunable laser chip according to claim 5, characterized in that, Fabricating a laser chip on a laser wafer (8), the method further includes: Multiple laser chips are disposed on the laser wafer (8). An ultrasonic detector (9) is disposed at the contact position between the laser wafer (8) and the laser chips. The ultrasonic detector (9) includes a probe (91) and a processor (92). The probe (91) of the ultrasonic detector (9) is in seamless contact with the laser chip substrate (1) to detect the completion of the hollow heat insulation area (4) in the laser chip. When the hollow heat insulation area (4) of the corresponding laser chip is completely formed as detected by the ultrasonic detector (9), and the inner walls on both sides of the laser chip still retain part of the structure of the lower corrosion stop layer (21), the laser chip is completed and qualified.

7. The method for fabricating a novel thermally tunable laser chip according to claim 6, characterized in that, The completion of the method for detecting the hollow thermal insulation region (4) in the laser chip specifically includes: The probe (91) emits a wave towards the substrate (1). When the emitted wave enters the etching solution from the substrate (1), it is reflected once and the first echo is received by the probe (91). When the emitted wave enters the corresponding upper functional layer (2) from the etching solution, it is reflected twice and the second echo is received by the probe (91). The completion degree of the cavity insulation area (4) is determined based on the time difference between the first echo and the second echo received by the probe (91).

8. The method for fabricating a novel thermally tunable laser chip according to claim 5, characterized in that, The etching of the ridge waveguide structure on the multiple functional layers (2) specifically includes: The corresponding ridge waveguide pattern is defined on the surface of the functional layer (2) grown sequentially on the substrate (1) by photolithography. Based on the defined ridge waveguide pattern, etching is performed on the semiconductor chip, and the etching depth exceeds the contact layer (26). An acidic etching solution is used to etch the chip waveguide layer to form grooves on the left and right sides of the semiconductor chip waveguide, which extend along the direction close to the substrate (1).

9. The method for fabricating a novel thermally tunable laser chip according to claim 5, characterized in that, The process of hollowing out the upper etch stop layer (23), lower sacrificial layer (22), and lower etch stop layer (21) below the first groove by etching and / or wet etching to form a heat-insulating groove (3) that is conductive to the substrate (1) specifically includes: The lower sacrificial layer (22) of the InP material is etched using a hydrochloric acid solution, and the lower etching stop layer (21) of the InGaAsP material is etched using an H2SO4 acid solution to form a heat-insulating groove (3) that is connected to the substrate (1).

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