A storage block structure, storage system, processing method and layout method thereof

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a storage block structure, a storage system, and a processing method and layout method thereof. The storage block structure includes a storage cell array block, and a plate line driver, which is arranged corresponding to the storage cell array block; and a contact, which is connected to the plate line driver and connected to the corresponding storage cell array block. By arranging each storage cell array block in a one-to-one correspondence with each plate line driver and connecting them through plate lines, the requirements for dense wiring can be relaxed, solving the problem of dense wiring affecting yield, and making the wiring length consistent, ensuring consistent driving performance of the storage cell array block. With this solution, a 0.8μm process node can also be achieved, reducing manufacturing difficulty and manufacturing cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a memory block structure, a memory system, and a method for processing and laying out the same. Background Technology

[0002] Currently, with the rapid development of electronic products and the increasing demands of the public for the performance of electronic products, semiconductors, as a core component, have permeated almost every aspect of our lives. From consumer electronics such as smartphones, computers, and tablets to various industries such as automobiles, medical equipment, communication equipment, home appliances, and solar panels, semiconductors are needed to realize their functions. Therefore, improving the overall performance of semiconductors has become an urgent need for all industries.

[0003] As the semiconductor industry develops, there is an urgent need to reduce the processing difficulty of semiconductors. Manufacturing semiconductor chips requires highly precise instruments and equipment, as well as complex processes. Reducing processing difficulty can improve production efficiency, lower costs, and help meet the ever-increasing market demand. Moreover, the requirements for the yield and driving performance of semiconductor devices are becoming increasingly stringent. Yield refers to the proportion of usable products in the production process. A high yield means fewer scraps and a higher yield rate. Improving yield is crucial for reducing costs and ensuring product quality. Driving performance refers to the performance of devices in their working state, such as the processing speed of a processor and the refresh rate of a display. High driving performance can provide a better performance experience and user satisfaction. Therefore, memory optimization has become a continuous and ongoing goal.

[0004] In existing technologies, board line drivers are concentrated in one area, driving multiple memory cell array blocks through dense routing. First, the excessively dense routing reduces yield; second, due to the different lengths of the routing, the resistance varies significantly, resulting in uneven driving performance of different memory cell array blocks, thus reducing the overall chip performance; third, after the memory cells are completed, the back-end requires 0.25μm and more advanced process nodes, limiting processing to dedicated fabs and resulting in relatively high product costs. To break this status quo, improve the overall driving performance and yield of memory, and reduce the manufacturing process difficulty, we propose a memory block structure, a memory system, and its processing and layout methods. Summary of the Invention

[0005] The purpose of this section is to outline some aspects of the invention and briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0006] In view of the above problems, the present invention is proposed.

[0007] Therefore, the first objective of this invention is to provide a storage block mechanism that, by arranging storage cell array blocks and board line drivers in a corresponding manner, changes the current situation where board line drivers are concentrated in one area and require dense wiring to drive multiple storage cell array blocks, thereby ensuring yield and making the driving performance more uniform.

[0008] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a storage block mechanism, comprising a storage cell array block, a board line driver corresponding to the storage cell array block, and contacts corresponding to the board line driver and connected to the corresponding storage cell array block.

[0009] In a preferred embodiment of the storage block mechanism of the present invention, the contact and the board line driver are respectively disposed on the outer sides of two adjacent sides of the storage cell array block.

[0010] As a preferred embodiment of the storage block structure of the present invention, the storage unit array block includes a plurality of storage units, and the plurality of storage units are arranged in an M*N rectangular array; M and N are both natural numbers greater than 1.

[0011] As a preferred embodiment of the storage block structure described in this invention, each storage cell further includes a corresponding switching unit; the storage cell array block further includes M word lines corresponding to M rows of storage cells and N bit lines corresponding to N columns of storage cells; the gate of each switching unit is connected to the corresponding word line, one of the source and drain terminals is connected to the corresponding bit line, and the other terminal is connected to the corresponding polarization capacitor.

[0012] As a preferred embodiment of the storage block structure of the present invention, it further includes a board line corresponding to the storage unit array block; the storage unit array block is connected to the corresponding board line driver through the board line.

[0013] In a preferred embodiment of the storage block mechanism of the present invention, an insulating layer is provided covering the storage cell array block, and the insulating layer is provided with contact through holes; a board wire is connected at one end to the storage cell array block of the storage block mechanism through the contact through holes, and at the other end to the corresponding contact.

[0014] A second objective of this invention is to provide a storage system comprising: a storage block structure arranged in an X*Y rectangular array, wherein X and Y are both natural numbers greater than or equal to 1; the storage system further comprising: row peripheral circuitry including a word line driver connected to word lines and a row address decoder connected to the word line driver; and column peripheral circuitry including an inductive amplifier connected to the storage block structure, a bit line driver connected to bit lines, and a column address decoder connected to the bit line driver.

[0015] In a preferred embodiment of the storage system described in this invention, the sensing amplifier is connected to the corresponding storage block mechanism via a corresponding bit line; and the word line driver is connected to the corresponding storage block mechanism via a corresponding word line.

[0016] A third objective of the present invention is to provide a board line driver layout method, comprising: connecting each memory cell in the same memory cell array block to a corresponding board line; assigning one board line driver to each memory cell array block; connecting each board line driver to a corresponding contact, and such that each contact is connected to the corresponding memory cell array block via the corresponding board line.

[0017] In a preferred embodiment of the board line driver layout method of the present invention, the contact and the board line driver are respectively disposed on the outer sides of two adjacent sides of the memory cell array block.

[0018] A fourth objective of the present invention is to provide a memory fabrication method, comprising: arranging the memory into a storage block structure; depositing an insulating layer on the storage block structure; forming contact through holes on the insulating layer corresponding to the positions of the contacts; and setting corresponding board lines on each contact, such that the board lines form an electrical connection with the contacts in the contact through holes.

[0019] The beneficial effects of this invention are as follows: By having the board line driver and the memory cell array blocks correspond one-to-one and arranged in a staggered manner, the routing is made more convenient, and the back-end process can use process nodes above 0.8um, which reduces the manufacturing difficulty and solves the problem of dense wiring affecting yield. This layout ensures that the routing length is consistent, and ensures that the driving performance of different memory cell array blocks will not be uneven due to large differences in resistance, which would lead to a decrease in chip performance. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0021] Figure 1 This is a schematic diagram of the layout of a board line driver in the prior art.

[0022] Figure 2 This is a schematic diagram of the structure of the storage cell array block of the present invention.

[0023] Figure 3 This is a schematic diagram of the storage block structure of the present invention.

[0024] Figure 4 This is a schematic diagram of the layout and structure of the storage block mechanism of the present invention.

[0025] Figure 5 This is a schematic diagram of the layout of the storage block structure when the polyimide deposition of the present invention is completed.

[0026] Figure 6 This is a schematic diagram of the layout of the storage block mechanism when the contact through-hole etching of the present invention is completed.

[0027] Figure 7 This is a schematic diagram of the layout of the storage block mechanism after the board wiring of this invention is completed.

[0028] Figure 8 This is a schematic diagram showing the position of the dividing lines in the storage block structure of the present invention.

[0029] Figure 9 This is a cross-sectional schematic diagram of the storage block mechanism of the present invention.

[0030] Figure 10 This is a schematic diagram of the framework structure of the storage system of the present invention.

[0031] Figure 11 This is a schematic diagram of the circuit structure of one memory cell of the present invention.

[0032] Figure 12 This is a schematic diagram of the circuit structure of the two memory cells of the present invention.

[0033] Figure 13 This is a schematic diagram of the layout of the storage block mechanism when the second type of contact through-hole etching of the present invention is completed.

[0034] Figure 14 This is a schematic diagram of the layout of the storage block mechanism after the second type of board wiring is completed according to the present invention.

[0035] Figure 15 This is a schematic diagram showing the position of the dividing line in the second type of storage block structure of the present invention.

[0036] Figure 16 This is a cross-sectional schematic diagram of the second type of storage block mechanism of the present invention. Detailed Implementation

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0039] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive of other embodiments.

[0040] Example 1

[0041] Reference Figures 1 to 5 , Figure 11 , Figure 12 This embodiment provides a storage block structure.

[0042] The storage block structure of the present invention is the specific structure between the storage cell array block, the board line driver and the contacts.

[0043] The storage block structure includes a storage cell array block 100, a board line driver 200 corresponding to each storage cell array block 100, and a contact 300 connected to each board line driver 200.

[0044] Specifically, the storage cell array block 100 and the board line driver 200 are configured corresponding to the storage cell array block 100; and the contact 300 is connected to the board line driver 200 and connected to the corresponding storage cell array block 100.

[0045] Preferably, the contact 300 and the board line driver 200 are respectively located on the outer sides of two adjacent sides of the storage cell array block 100.

[0046] like Figure 4 The contacts 300 and the board line driver 200 are located on different layers of the memory cell array block 100, and the contacts 300 and the board line driver 200 are located adjacent to the memory cell array block 100.

[0047] Preferably, the storage cell array block 100 includes a plurality of storage cells 101, and the plurality of storage cells 101 are arranged in an M*N rectangular array; M and N are both natural numbers greater than 1.

[0048] Preferably, each memory cell 101 further includes a corresponding switch unit 102; the memory cell array block 100 further includes M word lines 103 corresponding to the M rows of memory cells 101 and N bit lines 104 corresponding to the N columns of memory cells 101; the gate of each switch unit 102 is connected to the corresponding word line 103, one of the source and drain stages is connected to the corresponding bit line 104, and the other stage is connected to the corresponding polarization capacitor 105.

[0049] like Figure 11 , Figure 12 As shown, each storage unit 101 consists of one transistor and one capacitor, or two transistors and two capacitors; the switching unit 102 is preferably a transistor, used to control the charging and discharging of the capacitor to realize data storage and retrieval.

[0050] Preferably, it also includes a board line 106 corresponding to the storage cell array block 100; the storage cell array block 100 is connected to the corresponding board line driver 200 through the board line 106.

[0051] Preferably, the insulating layer 600 covers the storage cell array block 100, and the insulating layer 600 is provided with contact through holes 601; one end of the board wire 106 is connected to the storage cell array block 100 of the storage block mechanism Q through the contact through holes 601, and the other end is connected to the corresponding contact 300.

[0052] The insulating layer 600 is preferably polyimide, which can provide stable electrical isolation and protection performance, ensuring reliable operation and long life of the storage unit; the insulating layer 600 is provided with a contact through hole 601, and a metal layer is provided at the bottom area of ​​the contact through hole 601 for connection of one end of the board line 106.

[0053] Based on the above, the beneficial effects of the present invention are as follows:

[0054] 1. By adopting a staggered arrangement where the memory cell array blocks 100 and board line drivers 200 correspond one-to-one, and placing the contacts 300 below the memory cell array blocks 100, the consistent wiring length of the board lines 106 is ensured, while also guaranteeing uniform driving performance of the memory cell array blocks 100, further improving the overall chip performance. Compared to the traditional design, which mainly concentrates the board line drivers in a certain area and connects them to each memory cell array block through wiring, resulting in inconsistent wiring lengths and significant resistance differences that affect the driving performance of different memory cell array blocks, this solution can solve this problem.

[0055] The advantage of this layout is that by maintaining a consistent wiring length for the board lines 106, resistance variations caused by differences in wiring are eliminated, allowing each memory cell array block 100 to obtain balanced driving performance. This uniform performance ensures the overall reliability and stability of the chip, improves the overall performance level of the chip, and can meet the stability and reliability requirements of various applications.

[0056] 2. In traditional layout technology, due to the limited width of the memory cell array blocks, the board line driver needs to be closely connected to each memory cell array block. However, this compact wiring method results in extremely high trace density, which poses some challenges to yield. To address this issue, the back-end manufacturing process must reach 0.25μm or even more advanced nodes to process it, which undoubtedly greatly increases manufacturing costs and manufacturing difficulty.

[0057] In contrast, this solution adopts a one-to-one correspondence between each memory cell array block 100 and the corresponding board line driver 200, and connects them through board lines 106, thereby improving the routing layout. This solution eliminates the need for overly dense routing, solves the negative impact of routing density on yield, and breaks the limitation of routing in a limited width space, making the entire routing process more flexible and smooth. It significantly reduces the complexity and cost of the manufacturing process. With this arrangement, the back-end process can even use process nodes above 0.8μm, which greatly reduces the manufacturing difficulty and improves production efficiency.

[0058] 3. In traditional layout technology, due to the limitation of available space, only a fixed number of memory cell array blocks can be arranged within the same row, and they need to be closely arranged, resulting in very small gaps between each memory cell array block. This dense layout requires the back-end process to use 0.25μm or even more advanced process nodes to process. Such processes can usually only be carried out in specialized fabs, resulting in high manufacturing costs and great manufacturing difficulties.

[0059] In contrast, this solution employs a staggered arrangement of each memory cell array block 100 and the board line driver 200. The board line driver 200 makes way for the memory cell array blocks 100, allowing the same number of memory cell array blocks 100 to be arranged within the same limited space. This relaxes the spacing requirements between each memory cell array block 100, allowing for a more sparse arrangement. This configuration allows for a more rational allocation of layout space, enabling each memory cell array block 100 to occupy a larger area, no longer limited by the dense arrangement of traditional technologies. The increased spacing between each memory cell array block 100 also reduces the requirements for highly dense wiring in the back-end processes, making it possible to apply to process nodes above 0.8μm. This significantly reduces manufacturing costs. Furthermore, the sparse layout alleviates wiring congestion, improves signal transmission efficiency and reliability, helps reduce power consumption and heat generation, improves the overall performance and sustainability of the chip, and overcomes the limitations of layout constraints, thereby increasing production efficiency.

[0060] Example 2

[0061] Reference Figure 10 This embodiment provides a storage system based on Embodiment 1.

[0062] The storage system includes storage block structure, row peripheral circuits, and column peripheral circuits.

[0063] Specifically, the storage block structure Q is arranged in an X*Y rectangular array, where X and Y are both natural numbers greater than or equal to 1;

[0064] The storage system also includes: row peripheral circuitry 400, which includes a word line driver 401 connected to word line 103 and a row address decoder 402 connected to word line driver 401; and column peripheral circuitry 500, which includes an inductive amplifier 501 connected to storage block mechanism Q, a bit line driver 502 connected to bit line 104, and a column address decoder 503 connected to bit line driver 502.

[0065] Preferably, the inductive amplifier 501 is connected to the corresponding memory block mechanism Q via the corresponding bit line 104; the word line driver 401 is connected to the corresponding memory block mechanism Q via the corresponding word line 103.

[0066] In summary, the present invention provides a framework structure diagram of a storage system, wherein the word line driver 401 is connected to the storage block mechanism Q via the word line 103; the sensing amplifier 501 is connected to the storage block Q via the bit line 104, and the storage system is formed by connecting the row peripheral circuit 400 and the column peripheral circuit 500.

[0067] Example 3

[0068] Reference Figures 1-10 This embodiment provides a board line driver layout method based on Embodiment 2.

[0069] Specifically, each memory cell 101 in the same memory cell array block 100 is connected to a corresponding board line 106; each memory cell array block 100 corresponds to a board line driver 200; each board line driver 200 is connected to a corresponding contact 300, and each contact 300 is connected to the corresponding memory cell array block 100 through the corresponding board line 106.

[0070] Preferably, the contact 300 and the board line driver 200 are respectively located on the outer sides of two adjacent sides of the storage cell array block 100.

[0071] Each board line driver 200 is preferably staggered and placed on the right side of each corresponding memory cell array block 100, and the contacts 300 are preferably placed one-to-one on the lower side of the memory cell array block 100, and the memory cell array block 100 and the contacts 300 are connected by board lines 106.

[0072] In summary, by providing a layout method for the board line driver 200, the board line driver 200 and the contact 300 are respectively located on the outer sides of two adjacent sides of the memory cell array block 100. This arrangement allows for smooth routing of the board line 106, avoiding the problem of dense routing affecting yield. At the same time, this arrangement can keep the length of the traces consistent, making the driving performance of different memory cell array blocks 100 more uniform.

[0073] Example 4

[0074] Reference Figures 1-12 This embodiment provides a memory processing method based on Embodiment 3.

[0075] Specifically, the memory is laid out as a storage block structure Q; an insulating layer 600 is deposited on the storage block structure Q; contact through holes 601 are opened on the insulating layer 600 at positions corresponding to the contacts; corresponding board lines 106 are set on each contact, and the board lines are electrically connected to the contacts in the contact through holes 601.

[0076] In summary, the memory fabrication method mainly consists of three steps: first, an insulating layer 600 is used to deposit the memory block structure Q, wherein the insulating layer 600 is preferably polyimide; then, contact vias 601 are formed through the insulating layer 600; finally, the contact vias 601 are connected to the contacts 300 through the board line 106.

[0077] Example 5

[0078] Reference Figure 5 , Figures 13-16 This embodiment presents a memory processing method different from that in Embodiment 4.

[0079] Preferably, the memory is arranged in a storage block structure Q; an insulating layer 600 is deposited on the storage block structure Q; contact through holes 601 are opened on the insulating layer 600 corresponding to the positions of the contacts; and the contacts 300 are disposed inside the contact through holes 601; a corresponding board line 106 is provided on each contact, and the board line 106 is electrically connected to the contacts in the contact through holes 601.

[0080] In summary, for memory fabrication, the memory block structure Q is first deposited using an insulating layer 600, preferably polyimide. Then, a contact through-hole 601 is formed through the insulating layer 600. Unlike embodiment 4, by making the contact through-hole 601 larger, the contact 300 can be directly included. Finally, the contact through-hole 601 and the contact 300 are connected by a board line 106.

[0081] It should be recognized that embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can be implemented using standard programming techniques—including a non-transitory computer-readable storage medium configured with a computer program, wherein such a storage medium causes the computer to operate in a specific and predefined manner—according to the methods and drawings described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0082] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0083] Furthermore, the method can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described herein, the invention also includes the computer itself. A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the invention, the converted data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on a display.

[0084] As used herein, the terms “component,” “module,” “system,” etc., are intended to refer to a computer-related entity, which may be hardware, firmware, a combination of hardware and software, software, or running software. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a running thread, a program, and / or a computer. As an example, an application running on a computing device and the computing device itself can both be components. One or more components may reside in a running process and / or thread, and components may be located in a single computer and / or distributed among two or more computers. Furthermore, these components are capable of execution from various computer-readable media having various data structures thereon. These components may communicate locally and / or remotely via signals, such as based on one or more data packets (e.g., data from a component that interacts with a local system, another component in a distributed system, and / or signals that interact with other systems via a network such as the Internet).

[0085] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A storage block structure, characterized in that: include, Storage cell array block (100), and, A board line driver (200) is configured corresponding to a memory cell array block (100); and, Contact (300) is connected to the board line driver (200) and to the corresponding memory cell array block (100); The contact (300) and the board line driver (200) are respectively disposed on the outer sides of two adjacent sides of the storage cell array block (100); The contact (300) and the board line driver (200) are located in different layers of the memory cell array block (100); It also includes a connecting board line (106) corresponding to the storage unit array block (100), the length of the board line (106) is controllable and consistent within the block, and the back-end process adopts a process node of 0.8μm or higher; The storage cell array block (100) is connected to the corresponding board line driver (200) via board line (106); It also includes an insulating layer (600) covering the memory cell array block (100), the insulating layer (600) being provided with contact vias (601); and, The board wire (106) is connected at one end to the storage cell array block (100) of the storage block mechanism (Q) through the contact through hole (601), and at the other end to the corresponding contact (300).

2. The storage block structure as described in claim 1, characterized in that: The storage unit array block (100) includes a plurality of storage units (101), and the plurality of storage units (101) are arranged in an M*N rectangular array; M and N are both natural numbers greater than 1.

3. The storage block structure as described in claim 2, characterized in that: Each storage unit (101) also includes a corresponding switch unit (102); The storage cell array block (100) also includes M word lines (103) corresponding to M rows of storage cells (101) and N bit lines (104) corresponding to N columns of storage cells (101). The gate of each switching unit (102) is connected to the corresponding word line (103), one of the source and drain stages is connected to the corresponding bit line (104), and the other is connected to the corresponding polarization capacitor (105).

4. A storage system, characterized in that: The storage block structure (Q) includes any one of the storage block structures described in claims 1 to 3, wherein the storage block structure (Q) is arranged in an X*Y rectangular array, where X and Y are both natural numbers greater than or equal to 1; the storage system further includes, The row peripheral circuit (400) includes a word line driver (401) connected to the word line (103) and a row address decoder (402) connected to the word line driver (401). The column peripheral circuit (500) includes an inductive amplifier (501) connected to the memory block mechanism (Q), a bit line driver (502) connected to the bit line (104), and a column address decoder (503) connected to the bit line driver (502).

5. The storage system as described in claim 4, characterized in that: The inductive amplifier (501) is connected to the corresponding memory block mechanism (Q) via the corresponding bit line (104).

6. A board-line driver layout method, characterized in that: The storage block structure applied to any one of claims 1 to 3 includes, Each memory cell (101) in the same memory cell array block (100) is connected to the corresponding board line (106); Each memory cell array block (100) corresponds to a board line driver (200); Each board line driver (200) is connected to a corresponding contact (300), and each contact (300) is connected to the corresponding memory cell array block (100) via the corresponding board line (106).

7. The board wire driver layout method as described in claim 6, characterized in that: The contact (300) and the board line driver (200) are respectively located on the outer sides of two adjacent sides of the storage cell array block (100).

8. A method for processing a memory, characterized in that: The storage block structure applied to any one of claims 1 to 3 includes, The memory is laid out in a storage block structure (Q); An insulating layer (600) is deposited on the storage block structure (Q); A contact through hole (601) is formed on the insulating layer (600) at the position corresponding to the contact point. A corresponding board line (106) is set on each contact, and the board line is electrically connected to the contact in the contact through hole (601).

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