A method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus

Abstract

The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus, the method comprising: providing a substrate, the substrate being a wafer; forming an active structure on the substrate, the active structure comprising a first part and a second part; depositing a semiconductor material on the active structure to form a dummy gate structure; forming a source structure and a drain structure of a first transistor on both sides of a third part of the dummy gate structure; flipping the wafer and removing the substrate; forming a source structure and a drain structure of a second transistor on both sides of a fourth part of the dummy gate structure; etching the dummy gate structure to form a first groove; forming a first gate structure of the first transistor and a second gate structure of the second transistor at the first groove, respectively, the first gate structure and the second gate structure being self-aligned in a vertical direction.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In the related art, the process of manufacturing stacked transistors adopts a monolithic solution or a sequential solution, both of which have the problems of high difficulty and complexity in the manufacturing process. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus to reduce the thermal budget for preparing stacked transistors and simplify the process flow.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising: providing a substrate, the substrate being a wafer; forming an active structure on the substrate, the active structure comprising a first part and a second part; depositing a semiconductor material on the active structure to form a dummy gate structure; forming a source structure and a drain structure of a first transistor on both sides of a third part of the dummy gate structure, the third part being a part of the dummy gate structure corresponding to the first part; flipping the wafer and removing the substrate; forming a source structure and a drain structure of a second transistor on both sides of a fourth part of the dummy gate structure, the fourth part being a part of the dummy gate structure corresponding to the second part; etching the dummy gate structure to form a first groove; forming a first gate structure of the first transistor and a second gate structure of the second transistor at the first groove, respectively, the first gate structure and the second gate structure being self-aligned in a vertical direction.

[0006] In some possible implementations, before flipping the wafer, the method further includes: depositing a first insulating layer on top of the wafer, and bonding the first insulating layer to the carrier wafer.

[0007] In some possible implementations, the method further includes: depositing a gate dielectric layer on the surface of the active structure, wherein the gate dielectric layer is used to isolate the first portion from the first gate structure and the second portion from the second gate structure.

[0008] In some possible embodiments, a first gate structure of a first transistor and a second gate structure of a second transistor are respectively formed at the first groove, including: depositing a metal material in the first groove to form a gate structure; etching the gate structure corresponding to the second portion to form a first gate structure and expose the second portion; depositing an insulating material on the surface of the first gate structure to form an insulating dielectric layer, the insulating dielectric layer being used to isolate the first gate structure from the second gate structure; and depositing a metal material on the surface of the insulating dielectric layer to form a second gate structure.

[0009] In some possible embodiments, after forming the source structure and the drain structure of the first transistor on both sides of the third portion of the dummy gate structure, the method further includes: performing a back-end process above the source structure and the drain structure of the first transistor to form a first metal interconnection layer of the first transistor.

[0010] In some possible embodiments, after forming a first gate structure of the first transistor and a second gate structure of the second transistor at the first groove, respectively, the method further includes: performing a back-end process above the source structure and the drain structure of the second transistor to form a second metal interconnection layer of the second transistor.

[0011] In some possible implementations, after forming the active structure on the substrate, the method further includes: performing ion implantation at a connection between the first portion and the second portion to form an electrical isolation layer, wherein the electrical isolation layer is used to electrically isolate the first portion from the second portion.

[0012] In some possible implementations, the ions implanted include P-type ions, N-type ions, or oxygen ions.

[0013] In some possible implementations, the first transistor is one of a fin field effect transistor, a gate-all-around transistor, and a planar transistor; the second transistor is one of a fin field effect transistor, a gate-all-around transistor, and a planar transistor.

[0014] In some possible implementations, the active structure includes one of the following: at least one fin-like structure; a plurality of nanosheets or nanowires arranged in parallel; a bulk planar structure.

[0015] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by the above-mentioned semiconductor structure preparation method, and the semiconductor structure includes: a first transistor; a second transistor, and the second transistor is arranged back to back to the first transistor; wherein the first active structure of the first transistor and the second active structure of the second transistor are formed by the same process; the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned in the vertical direction.

[0016] In some possible implementations, an insulating dielectric layer is provided between the first gate structure and the second gate structure, and the insulating dielectric is used to isolate the first gate structure from the second gate structure.

[0017] In some possible implementations, an electrical isolation layer is provided between the first active structure and the second active structure.

[0018] In some possible implementations, the first transistor is one of a fin field effect transistor, a gate-all-around transistor, and a planar transistor; the second transistor is one of a fin field effect transistor, a gate-all-around transistor, and a planar transistor.

[0019] In some possible implementations, the first active structure and the second active structure constitute an active structure, and the active structure is at least one of the following: a fin-shaped structure; a nanosheet; a nanowire; or a block-shaped planar structure.

[0020] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0021] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0022] In the present application, the source structure and drain structure of the first transistor and the source structure and drain structure of the second transistor are first prepared, and then the first gate structure of the first transistor and the second gate structure of the second transistor are respectively prepared at the first groove, which can simplify the preparation process and improve the thermal budget when preparing the second transistor; at the same time, since the first gate structure and the second gate structure are both formed at the first groove, the first gate structure and the second gate structure are self-aligned in the vertical direction.

[0023] Furthermore, a first transistor is formed based on the first active structure, and after flipping the wafer, a second transistor is formed based on the second active structure, so that the active structures of the first transistor and the second transistor are "back-to-back" designs, thereby achieving self-alignment of the first transistor and the second transistor.

[0024] Furthermore, the self-alignment of the gate structure and the transistor makes the active regions and gates of the first transistor and the second transistor consistent, and simultaneously solves the problems of high defect density, complex process, fixed polarity and difficult alignment.

[0025] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0027] Figure 1 This is a schematic diagram of a first implementation process of the method for preparing a semiconductor structure in an embodiment of the present application;

[0028] Figure 2 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application;

[0029] Figure 3A A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0030] Figure 3B A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0031] Figure 3C A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0032] Figure 3D A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0033] Figure 3E A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0034] Figure 3F A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0035] Figure 4 This is a schematic diagram of a second structure of a semiconductor structure in an embodiment of the present application;

[0036] Figure 5 This is a schematic diagram of a third structure of a semiconductor structure in an embodiment of the present application;

[0037] Fig. 6A A schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0038] Figure 6B A schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0039] Figure 6C A schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0040] Fig.6D A schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0041] Fig. 6EA schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0042] Fig. 6F A schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0043] Figure 7 This is a schematic diagram of a fourth structure of a semiconductor structure in an embodiment of the present application;

[0044] Figure 8 This is a fifth structural schematic diagram of the semiconductor structure in the embodiment of the present application;

[0045] Fig. 9A A schematic diagram of a third preparation process of a semiconductor structure in an embodiment of the present application;

[0046] Fig. 9B A schematic diagram of a third preparation process of a semiconductor structure in an embodiment of the present application;

[0047] Fig. 9C A schematic diagram of a third preparation process of a semiconductor structure in an embodiment of the present application;

[0048] Fig.9D A schematic diagram of a third preparation process of a semiconductor structure in an embodiment of the present application;

[0049] Fig.9E A schematic diagram of a third preparation process of a semiconductor structure in an embodiment of the present application;

[0050] Fig.9F A schematic diagram of a third preparation process of a semiconductor structure in an embodiment of the present application;

[0051] Fig.10 This is a sixth structural schematic diagram of the semiconductor structure in the embodiment of the present application.

[0052] The above pictures:

[0053] 10. semiconductor structure; 11. first transistor; 12. second transistor; 13. insulating dielectric layer; 14. gate dielectric layer; 111. first active structure; 112. first gate structure; 113. first interlayer dielectric; 114. source structure and drain structure in the first transistor; 115. first metal interconnect layer; 116. first insulating layer; 117. carrier wafer; 121. second active structure; 122. second gate structure; 123. second interlayer dielectric; 124. source structure and drain structure in the second transistor; 125. second metal interconnect layer; 21. silicon substrate; 211. bottom silicon layer; 212. sacrificial layer; 213. top silicon layer; 22A. fin structure; 22B. nanosheet; 22C. block planar structure; 23. pseudo gate structure; 24. shallow trench isolation region; 241. shallow trench isolation layer; 25. spacer; 26. gate structure; 31. columnar structure. DETAILED DESCRIPTION

[0054] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0055] As Moore's Law continues to deepen, after the technology node of gate-all-around FET (GAA), continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0056] In one embodiment, there are two schemes for manufacturing a stacked transistor, the first is a monolithic scheme, and the second is a sequential scheme.

[0057] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate. This determines that the transistors on the same layer must be of the same type, that is, NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0058] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by sticking a wafer on top of the already manufactured lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0059] The common technical difficulties faced by the above two solutions include: (1) the thermal stability of the bottom layer devices when manufacturing the upper layer devices; (2) the performance of the top layer devices under low thermal budget; and (3) the metal interconnection of transistors between layers.

[0060] In order to solve the above technical problems, the embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, so as to reduce the thermal budget for manufacturing stacked transistors and simplify the process flow.

[0061] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0062] In one embodiment, the semiconductor structure may include at least two transistors, for example, a first transistor and a second transistor. The first transistor and the second transistor are arranged opposite to each other. The first active structure in the first transistor and the second active structure in the second transistor are formed by the same process. In this case, it can be understood that the first transistor and the second transistor share the same active structure. The first gate structure in the first transistor and the second gate structure in the second transistor are self-aligned in the vertical direction.

[0063] In an embodiment of the present application, the first transistor and the second transistor in the semiconductor structure are transistors of the same type, such as any one of the following: a fin field effect transistor, a gate-all-around transistor, and a planar transistor.

[0064] Figure 2 The semiconductor structure composed of fin field effect transistors is combined below Figure 2 The semiconductor structure shown illustrates the preparation method provided in the embodiment of the present application.

[0065] Figure 1 This is a schematic diagram of the first implementation process of the method for preparing a semiconductor structure in the embodiment of the present application, see Figure 1 As shown, the method for preparing the semiconductor structure may include:

[0066] S101, providing a substrate.

[0067] The substrate is a wafer made of silicon material. In one embodiment, the wafer may be a silicon (Si) wafer or a silicon-on-insulator (SOI) wafer. Correspondingly, the substrate may be a Si substrate or an SOI substrate, and of course, may also be a substrate of other semiconductor materials, which is not specifically limited in the embodiments of the present application.

[0068] In some embodiments, the substrate in the embodiments of the present application may be a multi-layer structure. Specifically, a sacrificial layer (such as silicon germanium (SiGe)) is epitaxially grown on the bottom silicon layer, and a top silicon layer (see Figure 3A ), the sacrificial layer is used to protect the main structure of the top silicon layer, reduce the impact and vibration from the outside, improve the durability and reliability of the top silicon layer, and extend its service life.

[0069] In one embodiment, the thickness of the sacrificial layer is about 10 to 20 nm, and the thickness of the top silicon layer is greater than 100 nm. It should be noted that the thickness of the sacrificial layer and the top silicon layer can be selected according to actual use requirements. For example, in a fin field effect transistor, the top silicon layer has a relatively large thickness to facilitate etching of the fin structure; while in a full-surround gate transistor, the sacrificial layer and the silicon layer are stacked layers, and the sacrificial layer is a semiconductor material layer arranged at intervals in the stack. At this time, the thickness of the sacrificial layer and the thickness of the silicon layer are selected according to actual use requirements; the embodiment of the present application does not specifically limit this.

[0070] S102, forming an active structure on a substrate, wherein the active structure includes a first part and a second part.

[0071] In some embodiments, one or more active structures may be formed on the substrate by etching the substrate. The active structure is divided into two parts, the upper part (i.e., the first part) is used as the active structure of the first transistor (i.e., the first active structure), and the lower part (i.e., the second part) is used as the active structure of the second transistor (i.e., the second active structure).

[0072] In some embodiments, when etching the substrate, the etching depth is the sum of the thickness of the silicon layer and the sacrificial layer in the substrate, that is, etching is performed until the connection between the sacrificial layer and the underlying silicon layer.

[0073] For example, the etching of the substrate may be performed by anisotropic etching to form a fin-like structure extending in the same direction in the active region (see Figure 3A (b)), parallel arrangement of nanosheets (see Fig. 6E (b) in), block-shaped planar structure (see Fig. 9A (b)) and other active structures. Wherein, when the active structure is a fin structure, the transistor is a fin field effect transistor (FinFET); when the active structure is a plurality of parallel nanosheets, the transistor is a gate-all-around field effect transistor (GAAFET); when the active structure is a block planar structure, the transistor is a planar transistor.

[0074] It should be noted that the etching process mentioned in the embodiments of the present application may include any one of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, which is not limited in the embodiments of the present application.

[0075] In some embodiments, after the fin structure is formed in S102 , ion implantation may be performed at the connection between the upper and lower parts of the fin structure to form an electrical isolation layer, where the electrical isolation layer is used to electrically isolate the upper and lower parts of the fin structure.

[0076] The ions implanted include P-type ions, N-type ions or oxygen ions. The P-type ions may be one of the following: boron (B), gallium (Ga), aluminum (Al). The N-type ions may be one of the following: phosphorus (P), arsenic (As), antimony (Sb).

[0077] S103, depositing a semiconductor material on the active structure to form a dummy gate structure.

[0078] In some embodiments, after the fin structure is formed by etching the substrate, a trench is formed in the etched area, a gate area is opened by photolithography at the trench position, and a semiconductor material (such as polysilicon) is deposited at the gate area, and then an oxide is continuously filled at a position other than the gate area in the trench area to form a shallow trench isolation (STI). After the shallow trench isolation area is formed, the semiconductor material deposited at the gate area is removed by etching to expose the sacrificial layer at the gate area, and the sacrificial layer not wrapped by the shallow trench isolation area is selectively removed by wet etching (see Figure 3B (c) in FIG. 1 ), and then the semiconductor material is deposited again at the location where the etched sacrificial layer is located. At this point, the pseudo gate structure is formed (see FIG. 1 ). Figure 3C (a) in the figure.

[0079] In the embodiment of the present application, the oxide forming the shallow trench isolation region may be: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO) and the like.

[0080] In some embodiments, in order to facilitate subsequent processing, after S103, the shallow trench isolation area can also be polished or chemical-mechanical planarization (CMP) treated so that when the shallow trench isolation area is subsequently etched, the corresponding corrosion depths of the shallow trench isolation areas in different areas are the same, thereby making the top height of the exposed active structure the same.

[0081] S104 , forming a source structure and a drain structure of the first transistor on both sides of the third portion of the dummy gate structure.

[0082] The third part is a part of the dummy gate structure corresponding to the first part.

[0083] It can be understood that the pseudo gate structure is also divided into two parts, the upper part (ie, the third part) is used in the first transistor, and the lower part (ie, the fourth part) is used in the second transistor.

[0084] In some embodiments, an upper portion of the shallow trench isolation region is removed by etching to expose a first portion of the fin structure covered by the shallow trench isolation region, and an upper portion of the dummy gate structure is also exposed, and spacers are formed on both sides of the upper portion of the dummy gate structure. The spacers are used as masks to epitaxially grow a source and a drain to form a source structure and a drain structure of the first transistor, and an interlayer dielectric (such as silicon dioxide (SiO2)) is deposited (see Figure 3C (b) in the figure). Then, metal contacts of the source structure and the drain structure in the first transistor are completed, and a back-end process is performed on the source structure and the drain structure to form a first metal interconnection layer of the first transistor.

[0085] In the embodiment of the present application, the solvent used for etching the shallow trench isolation region can be: DHF solution or BOE solution. The solvent used in the etching process in the embodiment of the present application can be selected according to actual conditions and is not limited to the above DHF solution or BOE solution.

[0086] S105, flipping the wafer and removing the substrate.

[0087] In some embodiments, after forming the source structure and drain structure of the first transistor, a post-process (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.) can be performed on the source structure and the drain structure to form a metal interconnect layer of the first transistor. An insulating material (such as silicon oxide) is deposited on the metal interconnect layer to form a first insulating layer, and the first insulating layer is bonded to the carrier wafer, and then the unfinished first transistor (i.e., wafer) is flipped so that the substrate (i.e., the bottom silicon layer) is placed upward, and then the same etching method as in S102 is used to etch the substrate (see Figure 3D (b) in the figure.

[0088] S106, forming a source structure and a drain structure of the second transistor on both sides of a fourth portion of the dummy gate structure, the fourth portion being a portion of the dummy gate structure corresponding to the second portion.

[0089] In some embodiments, after flipping, the wafer is thinned using a CMP process until the sacrificial layer wrapped by the shallow trench isolation region is exposed (see Figure 3D (c) in FIG. 1 ), and then the sacrificial layer wrapped by the shallow trench isolation region is selectively removed by wet etching (see FIG. Figure 3E(a) in the figure). The lower half of the shallow trench isolation region is removed by etching to expose the second part of the active structure covered by the shallow trench isolation region, and then the source structure and drain structure of the second transistor are formed by the same method as S104.

[0090] In an embodiment of the present application, after the source structure and drain structure of the first transistor and the metal interconnection layer are manufactured on the substrate, the first transistor is directly flipped over and the second transistor is manufactured on the back side of the first transistor. This can omit the lithography alignment step, simplify the process flow, and save costs.

[0091] S107, etching the dummy gate structure to form a first groove.

[0092] In some embodiments, after forming the source structure and the drain structure of the second transistor, the dummy gate structure is removed by etching to form a trench (ie, a first trench) at the gate region (see Figure 3E (b) in the figure.

[0093] S108 , forming a first gate structure of the first transistor and a second gate structure of the second transistor at the first groove, respectively, wherein the first gate structure and the second gate structure are self-aligned in a vertical direction.

[0094] In some embodiments, a metal material is deposited at the first groove to form a gate structure. The gate structure that wraps the second portion is removed by etching to expose the second portion. The unetched gate structure wraps the first portion. This portion of the gate structure is the first gate structure in the first transistor. An insulating material is deposited on the first gate structure to form an insulating dielectric layer, which is used to isolate the first gate structure from the second gate structure. Then, a metal material is deposited on the insulating dielectric layer to form a second gate structure of the second transistor (see Figure 3F (b) in the figure.

[0095] In some other embodiments, after forming the first groove, the first gate structure and the second gate structure may also be prepared by the following method: depositing a metal material at the first groove, the height of the deposition being consistent with the height of the active structure in the first transistor, thus forming the first gate structure in the first transistor. Then, depositing an insulating material on the first gate structure to form an insulating dielectric layer. Finally, depositing a metal material on the insulating dielectric layer to form the second gate structure in the second transistor.

[0096] It should be noted that the above-mentioned “isolation” can be understood as physical isolation or electrical isolation.

[0097] In some embodiments, the insulating dielectric layer between the first gate structure and the second gate structure may not be provided according to actual conditions. In this way, the first transistor and the second transistor may be interconnected through the contact between the first gate structure and the second gate structure without leading out interconnection lines.

[0098] In the embodiment of the present application, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0099] In an embodiment of the present application, the metal materials of the first gate structure and the second gate structure may include: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), and titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0100] In some embodiments, before preparing the first gate structure and the second gate structure, the above-mentioned semiconductor preparation method also includes: depositing a gate dielectric layer on the surface of the active structure, and the gate dielectric layer is used to isolate the active structure of the first transistor (i.e., the first part) from the first gate structure and the active structure of the second transistor (i.e., the second part) from the second gate structure.

[0101] It should be noted that the material of the gate dielectric layer can be set according to actual conditions, and the embodiments of the present application do not specifically limit this. When the gate dielectric layer is made of one material, the active structure of the first transistor and the active structure of the second transistor are both wrapped by the gate dielectric layer of the same material; when the gate dielectric layer is made of two materials, the active structure of the first transistor is wrapped by the first gate dielectric layer, and the active structure of the second transistor is wrapped by the first gate dielectric layer, wherein the materials of the first gate dielectric layer and the second gate dielectric layer are different.

[0102] In some embodiments, when the gate dielectric layers of the first transistor and the second transistor are different, the method for making the first gate dielectric layer and the second gate dielectric layer includes: depositing a layer of insulating material on the surface of the active structure to form a gate dielectric layer, removing the gate dielectric layer of the second part of the active structure by etching to expose the second part of the active structure, and the gate dielectric layer of the first part that is not etched is the first gate dielectric layer in the first transistor. Continuing to deposit another insulating material on the surface of the second part of the active structure to form the second gate dielectric layer in the second transistor.

[0103] In the embodiment of the present application, the first transistor and the second transistor in the semiconductor structure are transistors of the same type, such as any of the following: a fin field effect transistor, a full-surround gate transistor, and a planar transistor. Then, the semiconductor structure can also be specifically designed according to different types of transistors.

[0104] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the first transistor and the second transistor as fin field effect transistors as an example. Figure 2 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application. Figure 2 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view only shows the fin structure, gate structure, source structure and drain structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source structure and the drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., CC' direction).

[0105] See also Figure 2 As shown, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin structures. The fin structure is divided into two parts, upper and lower, respectively denoted as the first part and the second part, the first part is used as the first active structure 111 in the first transistor 11, and the second part is used as the second active structure 121 in the second transistor 12. An insulating dielectric layer 13 is provided between the first gate structure 112 in the first transistor 11 and the second gate structure 122 in the second transistor 12, and the insulating dielectric layer 13 is used to isolate the first gate structure 112 from the second gate structure 122. In addition to the gate region, a shallow trench isolation layer 241 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 241 is used to isolate the first transistor 11 from the second transistor 12.

[0106] See also Figure 2 As shown, the gate dielectric layer 14 wraps the first part and the second part of the fin structure. In the first transistor 11, at the position corresponding to the first part, the first gate structure 112 wraps the gate dielectric layer 14, and the gate dielectric layer 14 is used to isolate the fin structure and the first gate structure 112. The first interlayer dielectric 113 wraps the first part, the source structure and the drain structure 114 of the fin structure 22A in the first transistor 11 at a position other than the gate region. The second interlayer dielectric 123 wraps the second part, the source structure and the drain structure 124 of the fin structure 22A in the second transistor 12 at a position other than the gate region. The structure of the second transistor 12 is basically similar to that of the first transistor 11, and the structure of the second transistor 12 is not described in detail here.

[0107] See also Figure 2 As shown in (c) and (d) in FIG. 1 , the source structure and the drain structure 114 of the first transistor 11 are arranged opposite to the source structure and the drain structure 124 of the second transistor 12 .

[0108] In an embodiment of the present application, the first active structure of the first transistor and the second active structure of the second transistor are formed by the same process, so that self-alignment of the first transistor and the second transistor can be achieved, and the active area of ​​the first transistor and the active area of ​​the second transistor are consistent.

[0109] In combination with the above preparation method, Figure 2 The preparation process of the semiconductor structure shown is described. Figure 2 The semiconductor structure shown can be FIG. 3A to FIG. 3F The process shown is prepared FIG. 3A to FIG. 3F It is a schematic diagram of the first preparation process of the semiconductor structure in the embodiment of the present application.

[0110] In one example, taking the first transistor 11 and the second transistor 12 as fin field effect transistors as an example, a first preparation process of the semiconductor structure 10 may include the following steps:

[0111] The first step is to provide a silicon substrate 21. The silicon substrate 21 is composed of a bottom silicon layer 211, a sacrificial layer 212 and a top silicon layer 213 (see Figure 3A (a) in the figure). The material of the sacrificial layer is SiGe.

[0112] Step 2: Etching the silicon substrate 21 to form a plurality of fin structures 22A (see Figure 3A (b) in the figure.

[0113] The silicon substrate 21 is anisotropically etched to form a plurality of fin structures 22A extending in the same direction, wherein the thickness of the fin structures 22A is greater than 100 nm. The thickness of the sacrificial layer 212 is 10-20 nm. The etching depth is the sum of the thickness of the top silicon layer 213 and the sacrificial layer 212.

[0114] Step 3: Open the gate region by photolithography and deposit polysilicon (poly Si) in the gate region as a pseudo gate structure 23 (see Figure 3A Then, STI is filled in other regions except the gate region to form a shallow trench isolation region 24 (see Figure 3A The BB' direction in (c) is then planarized by CMP.

[0115] The height of the dummy gate structure 23 and the shallow trench isolation region 24 are both greater than the thickness of the fin structure 22A. Figure 3AIn the CC' direction of (c), the dummy gate structures 23 and the shallow trench isolation regions 24 are alternately deposited around the fin structure 22A.

[0116] Step 4: Remove the dummy gate structure 23 by etching to expose the fin structure 22A and the sacrificial layer 212 (see Figure 3B (a) in the figure.

[0117] Step 5: Use wet etching to selectively remove the exposed sacrificial layer 212 (see Figure 3B (b) in the figure.

[0118] Step 6: Poly Si is deposited again in the gate region to form a pseudo gate structure 23 (see Figure 3B (c) in the figure.

[0119] There is no sacrificial layer 212 at the bottom of the fin structure 22A wrapped by the dummy gate structure 23 formed for the second time.

[0120] It should be noted that after forming the dummy gate structure 23, a sidewall structure (not shown in the figure) may be formed on both sides of the dummy gate structure 23. The material of the sidewall structure may include but is not limited to: silicon nitride, silicon carbide, silicon oxynitride, etc. The sidewall structure may be completed by dielectric deposition and etching processes.

[0121] Step 7: Remove the upper half of the shallow trench isolation region 24 by etching to expose the first portion of the fin structure 22A (ie, the first active structure 111) (see Figure 3C BB' direction in (a)). Ion implantation is performed at the boundary between the exposed first portion of the plurality of fin structures 22A and the unexposed second portion to form an electrical isolation layer (not shown in the figure).

[0122] Step 8: Forming a spacer 25 on the sidewall of the exposed dummy gate structure 23 (see Figure 3C The source structure and the drain structure 114 in the first transistor 11 are epitaxially grown using the spacer 25 as a mask (see Figure 3C BB' direction and CC' direction in (b)), and deposit a first interlayer dielectric 113 on the source structure and the drain structure 114 and between the dummy gate structures 23 (see Figure 3C BB' direction and CC' direction in (b)).

[0123] The material of the first interlayer dielectric 113 is SiO2.

[0124] Step 9: Performing a back-end process on the source structure and drain structure 114 of the first transistor 11 to form a first metal interconnection layer 115 in the first transistor 11, and depositing an insulating material on the first metal interconnection layer 115 to form a first insulating layer 116, bonding the first insulating layer 116 to a carrier wafer 117, and then flipping the wafer thus prepared (see Figure 3C (c) in the figure.

[0125] In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped wafer after inversion, thereby effectively preventing the wafer from being broken during the preparation of the second transistor.

[0126] Step 10: Use CMP process to thin the wafer after flipping until the sacrificial layer 212 wrapped by the shallow trench isolation area 24 is exposed (see Figure 3D CC' direction in (a).

[0127] Step 11: Selectively remove the exposed sacrificial layer 212 by wet etching (see Figure 3D BB' direction and CC' direction in (b)).

[0128] Step 12: Etch the shallow trench isolation region 24 until the second portion of the fin structure (ie, the second active structure 121) is exposed (see Figure 3D (c) in the figure.

[0129] In the process of etching the shallow trench isolation region 24, a certain thickness of the shallow trench isolation region 24 is retained as a shallow trench isolation layer 241, and the shallow trench isolation layer 241 is used to isolate the first transistor 11 from the second transistor 12. The thickness of the shallow trench isolation layer 241 can be selected according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0130] Step 13: Forming the source structure and drain structure 124 in the second transistor 12 (see Figure 3E (a) in the figure). For the specific process, please refer to step 8, which will not be described in detail in the present embodiment.

[0131] It should be noted that the second interlayer dielectric 123 in the second transistor 12 and the first interlayer dielectric 113 in the first transistor 11 may be made of the same material or different materials, and may be selected according to actual conditions, which is not specifically limited in the embodiments of the present application.

[0132] Step 14: Remove the dummy gate structure 23 by etching, and form a gate dielectric layer 14 on the surface of the fin structure 22A (see Figure 3E Then, a metal material is deposited in the gate region to form a gate structure 26. At this time, the gate structure 26 wraps the fin structure 22A.

[0133] Step 15: Etch the upper portion of the gate structure 26 to expose the second portion of the fin structure 22A. The gate structure 26 that is not etched is the first gate structure 112 in the first transistor 11 (see FIG. 15 ). Figure 3E (c) in the figure.

[0134] Step 16: Deposit a layer of insulating material on the first gate structure 112 to form an insulating dielectric layer 13 (see Figure 3F (a) in the figure.

[0135] Step 17: Deposit a metal material on the insulating dielectric layer 13 to form a second gate structure 122 (see Figure 3F (b) in the figure.

[0136] The insulating dielectric layer 13 is used to isolate the first gate structure 112 from the second gate structure 122 .

[0137] Step 18: Perform a back-end process on the second gate structure 122 to form a second metal interconnection layer 125 of the second transistor 12 .

[0138] At this point, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors is completed.

[0139] It should be noted that the above Figure 3A and Figure 3F The substrate used in the process is a silicon substrate. When the substrate is an SOI substrate, the preparation method is the same as Figure 3A and Figure 3F The steps shown are the same, but since the BOX in the SOI substrate is a natural isolation layer, the ion implantation process can be omitted, and the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 can be electrically isolated by the BOX. The schematic diagram of the finally formed semiconductor structure 10 is as shown in FIG. Figure 4 shown. Figure 4 This is a schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application. Figure 4 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view only shows the fin structure, gate structure, source structure and drain structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source structure and drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., CC' direction). Figure 4, the BOX is located between the first active structure 111 and the second active structure 121 , and the BOX can achieve electrical isolation between the first active structure 111 and the second active structure 121 .

[0140] In some embodiments, the first transistor and the second transistor may also be all-around gate transistors. Figure 5 As shown, Figure 5 This is a schematic diagram of the third structure of the semiconductor structure in the embodiment of the present application. Figure 5 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, Figure 5 (a) in the figure only shows the nanosheet, gate structure, source structure and drain structure. Figure 5 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the nanosheet (i.e., AA' direction); Figure 5 (c) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the source structure and the drain structure (i.e., the BB' direction); Figure 5 (d) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the gate structure (ie, CC' direction).

[0141] See also Figure 5 As shown, the first active structure 111 in the first transistor 11 and the second active structure 121 in the second transistor 12 are multiple nanosheets arranged in parallel. The first active structure 111 and the second active structure 121 are active structures formed in the same process, and the upper half of the active structure is used as the first active structure 111 in the first transistor 11, and the lower half of the active structure is used as the second active structure 121 in the second transistor 12. Figure 5 The semiconductor structure 10 shown in FIG. 1 includes the first active structure 111 and the second active structure 121. Figure 2 Except for the first active structure 111 and the second active structure 121 being different, the rest of the structures are the same, which will not be described in detail in the embodiment of the present application.

[0142] In combination with the above preparation method, Figure 5 The preparation process of the semiconductor structure shown is described. Figure 5 The semiconductor structure shown can be 6A to 6F The process shown is prepared 6A to 6F Schematic diagram of the second preparation process of the semiconductor structure in the embodiment of the present application.

[0143] In another example, taking the first transistor 11 and the second transistor 12 as full-surround gate transistors as an example, the second preparation process of the semiconductor structure 10 may include the following steps:

[0144] Step 1: Provide a substrate 21 (see Fig. 6A(a) in the figure. The substrate 21 is formed by alternately depositing two semiconductor material layers (such as Si layer and SiGe layer) on the bottom silicon layer. The SiGe layer is used as a sacrificial layer to prepare the nanosheet in the all-around gate transistor.

[0145] Step 2: Etching the substrate 21 to form a columnar structure 31 on the substrate 21 (see Fig. 6A (b) in the figure.

[0146] Step 3: Open the gate region through photolithography and deposit poly Si in the gate region as a dummy gate structure 23. Then fill STI in other regions except the gate region to form a shallow trench isolation region 24, and perform planarization through CMP (see Fig. 6A For the specific process, please refer to the third step of the first method for preparing the semiconductor structure.

[0147] Step 4: Remove the dummy gate structure 23 by etching until the columnar structure 31 is exposed (see Figure 6B (a) in the figure.

[0148] Step 5: Use wet etching to selectively remove the exposed SiGe layer (i.e., the sacrificial layer at the gate area) (see Figure 6B (b) in the figure.

[0149] Step 6: Poly Si is deposited again in the gate region to form a pseudo gate structure 23 (see Figure 6B (c) in the figure). For the specific process, please refer to the sixth step of the first method for preparing the semiconductor structure.

[0150] Step 7: Remove the upper half of the shallow trench isolation region 24 by etching to expose the upper half (i.e., the first part) of the columnar structure 31 (see Figure 6C (a) in the figure). Ions are implanted at the boundary between the upper half of the exposed columnar structure 31 and the lower half (ie, the second portion) of the unexposed columnar structure 31 to form an electrical isolation layer (not shown in the figure).

[0151] Step 8: Form spacers 25 on both sides of the upper half of the dummy gate structure 23, and use the spacers 25 as a mask to form the source structure and drain structure 114 in the first transistor 11 (see Figure 6C (b) in the figure.

[0152] Step 9: Deposit a first interlayer dielectric 113 on the source structure and the drain structure 114 and between the dummy gate structures 23 (see Figure 6C (c) in the figure). For the specific process, please refer to the eighth step of the first method for preparing the semiconductor structure.

[0153] Step 10: Perform a back-end process on the source structure and drain structure 114 of the first transistor 11 to form a first metal interconnection layer 115 in the first transistor 11, and deposit an insulating material on the first metal interconnection layer 115 to form a first insulating layer 116, bond the first insulating layer 116 to the carrier wafer 117, and then flip the wafer so far (see Fig.6D (a) in the figure.

[0154] Step 11: Use CMP process to thin the wafer after flipping, remove the bottom silicon layer, until the SiGe layer at the bottom of the columnar structure 31 is exposed (see Fig.6D BB' direction in (b)).

[0155] Step 12: Etch the shallow trench isolation region 24 until the second portion of the columnar structure 31 is exposed (see Fig.6D For the specific process, please refer to the twelfth step of the first method for preparing the semiconductor structure.

[0156] Step 13: Forming the source structure and drain structure 124 in the second transistor 12 (see Fig. 6E (a)), and deposit a second interlayer dielectric 123 on the source structure and the drain structure 124 in the second transistor and between the dummy gate structures 23. For the specific process, refer to the eighth step of the first method for preparing the semiconductor structure.

[0157] Step 14: Remove the pseudo gate structure 23 by etching, and thus form a plurality of nanosheets 22B arranged in parallel in the semiconductor structure 10. Form a gate dielectric layer 14 on the surface of the plurality of nanosheets. Then deposit a metal material in the gate region to form a gate structure 26 (see Fig. 6E (b) in the figure.

[0158] Step 15: Form the first gate structure 112 and the second gate structure 122 (see Fig. 6F ). For the specific formula, please refer to the fifteenth to seventeenth steps of the first method for preparing the semiconductor structure.

[0159] Step 16: Perform a back-end process on the second gate structure 122 to form a second metal interconnection layer 125 of the second transistor 12 .

[0160] At this point, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are all-around gate transistors is completed.

[0161] It should be noted that the above Fig. 6A and Fig. 6F The substrate used in the process is a silicon substrate. When the substrate is an SOI substrate, the preparation method is the same as Fig. 6A and Fig. 6FThe steps shown are the same, but because the BOX in the SOI substrate is a natural isolation layer, the ion implantation process can be omitted. The first active structure of the first transistor and the second active structure of the second transistor can be electrically isolated by the BOX. The schematic diagram of the finally formed semiconductor structure is shown in FIG. Figure 7 shown. Figure 7 This is a schematic diagram of the fourth structure of the semiconductor structure in the embodiment of the present application. Figure 7 (a) is a top view of the semiconductor structure. It should be noted that for ease of understanding, the top view only shows the nanosheet, gate structure, source structure and drain structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the nanosheet (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source structure and drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., CC' direction). Figure 7 , BOX is located between the first active structure and the second active structure, and BOX can achieve electrical isolation between the first active structure and the second active structure.

[0162] Next, taking the first transistor and the second transistor as planar transistors as an example, a fifth structural schematic diagram of the semiconductor structure is described. Figure 8 This is a fifth structural diagram of the semiconductor structure in the embodiment of the present application. Figure 8 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view only shows the block planar structure, gate structure, source structure and drain structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the block planar structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source structure and the drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., CC' direction).

[0163] See also Figure 8 As shown, the first active structure 111 in the first transistor 11 and the second active structure 121 in the second transistor 12 are block-shaped planar structures. The first active structure 111 and the second active structure 121 are block-shaped planar structures formed in the same process, and the upper half of the active structure is used as the first active structure 111 in the first transistor 11, and the lower half of the active structure is used as the second active structure 121 in the second transistor 12. Figure 8 The semiconductor structure shown in FIG. 1 includes the first active structure 111 and the second active structure 121. Figure 2 Except for the first active structure 111 and the second active structure 121 being different, the rest of the structures are the same, which will not be described in detail in the embodiment of the present application.

[0164] In combination with the above preparation method, Figure 8 The preparation process of the semiconductor structure shown is described. Figure 8 The semiconductor structure shown can be 9A to 9F The process shown is prepared 9A to 9F Schematic diagram of the third preparation process of the semiconductor structure in the embodiment of the present application.

[0165] In another example, taking the first transistor 11 and the second transistor 12 as planar transistors as an example, the third preparation process of the semiconductor structure 10 may include the following steps:

[0166] The first step is to provide a silicon substrate 21 (see Fig. 9A (a) in the figure). The silicon substrate 21 is composed of a bottom silicon layer 211, a sacrificial layer 212 and a top silicon layer 213. The sacrificial layer 212 is made of SiGe.

[0167] Step 2: Etching both sides of the silicon substrate 21 to form a block-shaped planar structure 22C (see Fig. 9A (b) in the figure.

[0168] Step 3: Open the gate region through photolithography and deposit poly Si in the gate region as a dummy gate structure 23. Then fill STI in other regions except the gate region to form a shallow trench isolation region 24, and perform planarization through CMP (see Fig. 9A (c) in the figure.

[0169] Step 4: Remove the dummy gate structure 23 by etching to expose the block planar structure 22C and the sacrificial layer 212 (see Fig. 9B (a) in the figure.

[0170] Step 5: Use wet etching to selectively remove the exposed sacrificial layer 212 (see Fig. 9B (b) in the figure.

[0171] Step 6: Poly Si is deposited again in the gate region to form a pseudo gate structure 23 (see Fig. 9B (c) in the figure). For the specific process, please refer to the sixth step of the first method for preparing the semiconductor structure.

[0172] Step 7: Remove the upper half of the shallow trench isolation region 24 by etching to expose the first portion of the block-shaped planar structure 22C (see Fig. 9C (a) in the figure). Ion implantation is performed at the boundary between the exposed first portion of the block-shaped planar structure 22C and the unexposed second portion to form an electrical isolation layer (not shown in the figure).

[0173] Step 8: Forming the source structure and drain structure 114 of the first transistor 11 (see Fig. 9C For the specific process, please refer to the eighth step of the first method for preparing the semiconductor structure.

[0174] Step 9: Performing a back-end process on the source structure and drain structure 114 of the first transistor 11 to form a first metal interconnection layer 115 in the first transistor 11, and depositing an insulating material on the first metal interconnection layer 115 to form a first insulating layer 116, bonding the first insulating layer 116 to a carrier wafer 117, and then flipping the wafer thus prepared (see Fig. 9C (c) in the figure.

[0175] Step 10: Use CMP process to thin the wafer after flipping until the sacrificial layer 212 wrapped by the shallow trench isolation area 24 is exposed (see Fig.9D (a) in the figure.

[0176] Step 11: Selectively remove the exposed sacrificial layer 212 by wet etching (see Fig.9D (b) in the figure.

[0177] Step 12: Etch the shallow trench isolation region 24 until the second portion of the block planar structure 22C is exposed (see Fig.9D For the specific process, please refer to the twelfth step of the first method for preparing the semiconductor structure.

[0178] Step 13: Forming the source structure and drain structure 124 in the second transistor 12 (see Fig.9E (a) in the figure). For the specific process, please refer to the eighth step of the first method for preparing the semiconductor structure, which will not be described in detail in the present embodiment.

[0179] Step 14: Remove the dummy gate structure 23 by etching, and form a gate dielectric layer 14 on the surface of the block planar structure 22C. Then, deposit metal material in the gate region to form a gate structure 26 (see Fig.9E (b) in the figure.

[0180] Step 15: Form the first gate structure 112 and the second gate structure 122 (see Fig.9F ). For the specific formula, please refer to the fifteenth to seventeenth steps of the first method for preparing the semiconductor structure.

[0181] Step 16: Perform a back-end process on the second gate structure 122 to form a second metal interconnection layer 125 of the second transistor 12 .

[0182] At this point, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are planar transistors is completed.

[0183] It should be noted that the above Fig. 9A and Fig.9F The substrate used in the process is a silicon substrate. When the substrate is an SOI substrate, the preparation method is the same as Fig. 9A and Fig.9F The steps shown are the same, but since the BOX in the SOI substrate is a natural isolation layer, the ion implantation process can be omitted. The first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 can be electrically isolated by the BOX. The schematic diagram of the finally formed semiconductor structure is shown in FIG. Fig.10 shown. Fig.10 This is a sixth structural diagram of the semiconductor structure in the embodiment of the present application. Fig.10 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view only shows the block planar structure, gate structure, source structure and drain structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the block planar structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source structure and drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., CC' direction). Fig.10 , the BOX is located between the first active structure 111 and the second active structure 121 , and the BOX can achieve electrical isolation between the first active structure 111 and the second active structure 121 .

[0184] In an embodiment of the present application, a source structure and a drain structure of a first transistor and a source structure and a drain structure of a second transistor are first prepared, and then a first gate structure of the first transistor and a second gate structure of the second transistor are respectively prepared at the first groove, which can simplify the preparation process and improve the thermal budget when preparing the second transistor; at the same time, since the first gate structure and the second gate structure are both formed at the first groove, the first gate structure and the second gate structure are self-aligned in the vertical direction.

[0185] In addition, a first transistor is formed based on the first active structure, and after flipping the wafer, a second transistor is formed based on the second active structure, so that the active structures of the first transistor and the second transistor are "back-to-back" designs, thereby achieving self-alignment of the first transistor and the second transistor.

[0186] Furthermore, the self-alignment of the gate structure and the transistor makes the active regions and gates of the first transistor and the second transistor consistent, and simultaneously solves the problems of high defect density, complex process, fixed polarity and difficult alignment.

[0187] In the embodiment of the present application, the preparation method of the above-mentioned semiconductor structure is a fusion of sequential stacking and monolithic stacking solutions. The technology is mature and has high reusability. It can avoid expensive process development to save costs and has high feasibility.

[0188] In an embodiment of the present application, the first transistor and the second transistor have independent signal and power supply networks and are connected through local interconnection. Without changing the extremely miniaturized 4T track unit design, the metal wiring resources are greatly released (compared to the current solution, the improvement is more than 60%), and there is huge room for collaborative optimization of process design. Finally, the flip-chip transistor solution is compatible with existing mainstream device architectures, and can realize the front and back stacking of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors (vertical transport field effect transistors, VTFETs) without the need for special process development for specific device architectures, making it more flexible and highly extensible from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, and is highly practical and has broad prospects for expansion.

[0189] The present application embodiment provides a semiconductor device, including: the semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 4 , Figure 5 , Figure 7 , Figure 8 and Fig.10 The semiconductor structure shown will not be described in detail here.

[0190] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 4 , Figure 5 , Figure 7 , Figure 8 and Fig.10 The semiconductor structure shown will not be described in detail here.

[0191] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0192] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate is a wafer; forming an active structure on the substrate, the active structure comprising a first portion and a second portion; Depositing a semiconductor material on the active structure to form a dummy gate structure; forming a source structure and a drain structure of a first transistor on both sides of a third portion of the dummy gate structure, wherein the third portion is a portion of the dummy gate structure corresponding to the first portion; Flipping the wafer and removing the substrate; forming a source structure and a drain structure of a second transistor on both sides of a fourth portion of the dummy gate structure, wherein the fourth portion is a portion of the dummy gate structure corresponding to the second portion; Etching the dummy gate structure to form a first groove; forming a first gate structure of the first transistor and a second gate structure of the second transistor at the first groove, respectively, wherein the first gate structure and the second gate structure are self-aligned in a vertical direction; Wherein, the forming of the first gate structure of the first transistor and the second gate structure of the second transistor at the first groove respectively includes: depositing a metal material in the first groove to form a gate structure; etching the gate structure corresponding to the second portion to form a first gate structure and expose the second portion; depositing an insulating material on the surface of the first gate structure to form an insulating dielectric layer, wherein the insulating dielectric layer is used to isolate the first gate structure from the second gate structure; and depositing a metal material on the surface of the insulating dielectric layer to form a second gate structure. When the first transistor and the second transistor are all-around gate transistors, the substrate is formed by alternately depositing silicon layers and sacrificial layers on an underlying silicon layer; the method also includes: before forming the dummy gate structure, removing the sacrificial layer in the gate region of the semiconductor structure.

2. The method according to claim 1, characterized in that Before flipping the wafer, the method further includes: A first insulating layer is deposited on top of the wafer and bonded to a carrier wafer.

3. The method according to claim 1, characterized in that The method further comprises: A gate dielectric layer is deposited on the surface of the active structure, and the gate dielectric layer is used to isolate the first portion from the first gate structure and the second portion from the second gate structure.

4. The method according to claim 1, characterized in that: After forming a source structure and a drain structure of the first transistor on both sides of the third portion of the dummy gate structure, the method further includes: A back-end process is performed above the source structure and the drain structure of the first transistor to form a first metal interconnection layer of the first transistor.

5. The method according to claim 1, characterized in that After forming a first gate structure of the first transistor and a second gate structure of the second transistor at the first trench, respectively, the method further includes: A back-end process is performed above the source structure and the drain structure of the second transistor to form a second metal interconnection layer of the second transistor.

6. The method according to claim 1, characterized in that After forming an active structure on the substrate, the method further comprises: Ion implantation is performed at a connection between the first portion and the second portion to form an electrical isolation layer, wherein the electrical isolation layer is used to electrically isolate the first portion from the second portion.

7. The method according to claim 6, characterized in that The ions implanted include P-type ions, N-type ions or oxygen ions.

8. The method according to claim 1, characterized in that The first transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor; the second transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor.

9. The method according to claim 8, characterized in that The active structure includes one of the following: at least one fin-like structure; A plurality of nanosheets or nanowires arranged in parallel; Blocky planar structure.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method according to any one of claims 1 to 9, and the semiconductor structure comprises: a first transistor; a second transistor, the second transistor being arranged opposite to the first transistor; The first active structure of the first transistor and the second active structure of the second transistor are formed by the same process; the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned in a vertical direction; There is an insulating dielectric layer between the first gate structure and the second gate structure, and the insulating dielectric is used to isolate the first gate structure from the second gate structure.

11. The semiconductor structure according to claim 10, characterized in that: An electrical isolation layer is provided between the first active structure and the second active structure.

12. The semiconductor structure according to claim 10, characterized in that The first transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor; the second transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor.

13. The semiconductor structure according to claim 12, characterized in that: The first active structure and the second active structure constitute an active structure, and the active structure is at least one of the following: Fin-like structure; Nanosheets; Nanowires; Blocky planar structure.

14. A semiconductor device, characterized in that: include: A semiconductor structure as claimed in any one of claims 10 to 13.

15. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 14, wherein the semiconductor device is arranged on the circuit board.

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