Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate including a substrate and a fin structure separated from the substrate, the fin structure including a bottom fin, a sacrificial layer on the bottom fin, and a top fin on the sacrificial layer; forming an isolation layer around the bottom fin on the substrate; forming a dummy gate structure across the top fin on the isolation layer; removing the sacrificial layer on both sides of the dummy gate structure to form a gap between the bottom fin and the top fin and the remaining sacrificial layer; forming a dielectric layer sealing the gap; after forming the dielectric layer, forming source / drain doped regions in the top fin on both sides of the dummy gate structure; removing the dummy gate structure to form a gate opening; removing the remaining sacrificial layer through the gate opening to form a via in communication with the gate opening; and filling the gate opening and the via with a gate structure surrounding the top fin. The present application reduces device leakage current and improves the control of the gate structure over the conductive channel.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. In a FinFET, the gate surrounds the fin-shaped channel on three sides; in a GAA, the gate surrounds the channel area from all four sides. Compared to planar transistors, FinFETs and GAA transistors offer stronger control over the channel and better suppress short-channel effects.

[0003] However, leakage current remains a significant problem in current devices. Taking a gate-all-around (GAA) transistor as an example, the source and drain doped layers are located on and in contact with the bumps. This leads to the formation of parasitic devices in the bumps below the channel structure layer, causing leakage current to also occur in the bumps below the channel structure layer. In particular, when the source and drain doped layers are also embedded in the bumps, a raised fin structure is formed between the source and drain doped layers on both sides of the gate structure. This results in the formation of parasitic channels within the fin structure, further exacerbating the leakage current. The deeper the source and drain doped layers are embedded in the bumps, the more severe the leakage current becomes.

[0004] There are currently two methods to attempt to reduce leakage current in semiconductor structures. (Reference) Figure 1 This is a schematic diagram of a semiconductor structure, which includes: a substrate 10 on which a plurality of discrete protrusions 16 are formed; a channel structure layer 11 located on and spaced apart from the protrusions 16, the channel structure layer 11 including one or more spaced-apart channel layers 12; a gate structure 20 spanning the channel structure layer 11 and located between adjacent channel layers 12 or between a protrusion 16 and a channel layer 12 adjacent to the protrusion 16, the gate structure 20 surrounding the channel layer 12; source / drain doped layers 14 located on both sides of the gate structure 13 and covering the sidewalls of the channel structure layer 11; and an isolation layer 15 located between the protrusions 16 and the source / drain doped layers 14.

[0005] Figure 1In the semiconductor structure shown, an isolation layer 15 is disposed between the source / drain doped layer 14 and the protrusion 16 to isolate the source / drain doped layer 14 from the protrusion 16, preventing the source / drain doped layer 14 from contacting the protrusion 16 and reducing leakage current generated in the protrusion 16 below the channel structure layer 11. However, the source / drain doped layer 14 is typically formed by epitaxial processing. Distributing the isolation layer 15 between the bottom of the source / drain doped layer 14 and the protrusion 16 significantly affects the epitaxial process for forming the source / drain doped layer 14, leading to poor formation quality of the source / drain doped layer 14 and poor performance of the semiconductor structure.

[0006] refer to Figure 2 This is a schematic diagram of another semiconductor structure, which includes: a substrate 20 on which a plurality of discrete protrusions 26 are formed; an isolation layer 25 located on the protrusions 26; a channel structure layer 21 located on the isolation layer 25 and spaced apart from the isolation layer 25, the channel structure layer 21 including one or more spaced-apart channel layers 22; a gate structure 23 spanning the channel structure layer 21 and located between adjacent channel layers 22 or between the isolation layer 25 and the channel layer 22 adjacent to the isolation layer 25, the gate structure 23 surrounding the channel layer 22; and source / drain doped layers 24 located on the isolation layers 25 on both sides of the gate structure 23 and covering the sidewalls of the channel structure layer 21.

[0007] Figure 2 In the semiconductor structure shown, an isolation layer 25 is disposed below the channel structure layer 21, the gate structure 23, and the source / drain doped layer 24. This isolation layer 25 isolates the entire device from the bump 26, thereby reducing leakage current generated within the bump 26. However, the placement of the isolation layer 25 between the bottom of the source / drain doped layer 24 and the bump 26 can also affect the epitaxial process for forming the source / drain doped layer 24, leading to poor formation quality of the source / drain doped layer 24 and consequently, poor performance of the semiconductor structure. Furthermore, a specific method for forming the isolation layer 25 is currently not disclosed.

[0008] For FinFETs, the same problem exists when an isolation layer is placed at the bottom of the source / drain doped layer or below the source / drain doped layer and the effective fin.

[0009] Therefore, there is an urgent need to propose a new method to reduce the leakage current of devices. Summary of the Invention

[0010] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which reduces leakage current and improves process compatibility.

[0011] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a plurality of fin structures disposed on the substrate, each fin structure including: a bottom fin protruding from the substrate; a top fin suspended from the bottom fin at a distance, the top fin including a first portion for forming a channel region and a second portion located on both sides of the first portion; a dielectric layer sealing the gap between the bottom fin and the second portion; an isolation layer located on the substrate and surrounding the bottom fin; a gate structure located on the isolation layer, spanning the top fin and also located between the bottom fin and the first portion, the gate structure surrounding the first portion; and source / drain doped regions located within the top fins on both sides of the gate structure.

[0012] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a plurality of fin structures discretely disposed on the substrate, the fin structures including a bottom fin and a sacrificial layer located on the bottom fin, and a top fin located on the sacrificial layer; forming an isolation layer surrounding the bottom fin on the substrate, the isolation layer exposing the top fin; forming a dummy gate structure across the top fin on the isolation layer; removing the sacrificial layer located on both sides of the dummy gate structure, so that a gap is formed between the bottom fin, the top fin and the remaining sacrificial layer; forming a dielectric layer sealing the gap; after forming the dielectric layer, forming source and drain doped regions in the top fin on both sides of the dummy gate structure; removing the dummy gate structure to form a gate opening across the top fin; removing the remaining sacrificial layer through the gate opening, so that the bottom fin, the top fin and the isolation layer form a through trench, the through trench being connected to the gate opening; filling the gate opening and the through trench with a gate structure, the gate structure surrounding the top fin.

[0013] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0014] The semiconductor structure provided in this embodiment of the invention includes a finned structure comprising a bottom fin and a top fin suspended at a distance from the bottom fin. The top fin includes a first portion for forming a channel region and a second portion located on both sides of the first portion. A dielectric layer seals the gap between the bottom fin and the second portion, thereby isolating the top fin and the bottom fin. This helps reduce the probability of forming parasitic devices in the bottom fin, correspondingly reducing the leakage current of the semiconductor structure, improving the electrical performance of the device, and also being compatible with the process technology of fin field-effect transistors, which helps improve process compatibility and reduce costs. In addition, the gate structure is located on the isolation layer and spans the top fin and is also located between the bottom fin and the first portion, so that the gate structure surrounds the first portion. The first portion of the top fin is used to provide a conductive channel, which correspondingly improves the control capability of the gate structure over the conductive channel, thereby improving the performance of the semiconductor structure.

[0015] In the semiconductor structure formation method provided by the embodiments of the present invention, the fin structure further includes a sacrificial layer located between the bottom fin and the top fin. After forming the dummy gate structure, the sacrificial layers located on both sides of the dummy gate structure are removed, so that a gap is formed between the bottom fin, the top fin, and the remaining sacrificial layer. Subsequently, a dielectric layer sealing the gap is formed, thereby isolating the top fin and the bottom fin. This helps to reduce the probability of forming parasitic devices in the bottom fin, thereby reducing the leakage current of the semiconductor structure, improving the electrical performance of the device, and also being compatible with the process of forming fin field-effect transistors, which helps to improve process compatibility and reduce costs. In addition, the remaining sacrificial layer is removed through the gate opening to form a through-groove, thereby filling the gate structure in the gate opening and the through-groove, so that the gate structure surrounds the top fin. The top fin is used to provide a conductive channel, thereby improving the control capability of the gate structure over the conductive channel, and thus improving the performance of the semiconductor structure. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a semiconductor structure.

[0017] Figure 2 This is a schematic diagram of another semiconductor structure;

[0018] Figures 3 to 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0019] Figures 7 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0020] As can be seen from the background technology, there is an urgent need to propose a new method to reduce the leakage current of devices.

[0021] To address the technical problems, embodiments of the present invention provide a semiconductor structure, a finned structure including a bottom fin and a top fin suspended at a distance from the bottom fin. The top fin includes a first portion for forming a channel region and second portions located on both sides of the first portion. A dielectric layer seals the gap between the bottom fin and the second portion, thereby isolating the top fin and the bottom fin. This helps reduce the probability of parasitic devices forming in the bottom fin, correspondingly reducing the leakage current of the semiconductor structure, improving the electrical performance of the device, and also ensuring compatibility with the process technology of fin field-effect transistors, thus improving process compatibility and reducing costs. Furthermore, a gate structure is located on an isolation layer, spanning the top fin and also located between the bottom fin and the first portion, thereby surrounding the first portion. The first portion of the top fin provides a conductive channel, which correspondingly improves the control capability of the gate structure over the conductive channel, thereby enhancing the performance of the semiconductor structure.

[0022] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] refer to Figures 3 to 6 A schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 3 It's a 3D image. Figure 4 yes Figure 3 Cross-sectional view along the direction of extension of the top fin. Figure 5 yes Figure 4 Cross-sectional view along the B1-B1 direction. Figure 6 yes Figure 4 Cross-sectional view along the B2-B2 direction.

[0024] like Figures 3 to 6 As shown, in this embodiment, the semiconductor structure includes: a substrate 100; a plurality of fin structures 110, which are disposed on the substrate 100. Each fin structure 110 includes: a bottom fin 10, which protrudes from the substrate 100; a top fin 20, which is suspended from the bottom fin 10 at a distance. The top fin 20 includes a first portion 20(1) for forming a channel region and a second portion 20(2) located on both sides of the first portion 20(1); a dielectric layer 50, which seals the gap between the bottom fin 10 and the second portion 20(2); an isolation layer 420, which is located on the substrate 100 and surrounds the bottom fin 10; a gate structure 470, which is located on the isolation layer 420, spans the top fin 20, and is also located between the bottom fin 10 and the first portion 20(1). The gate structure 470 surrounds the first portion 20(1); and source / drain doped regions 200, which are located in the top fin 20 on both sides of the gate structure 270.

[0025] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0026] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0027] The fin structure 110 is used to form a top fin 20 that is suspended from the bottom fin 10 at a distance.

[0028] There is a gap between the bottom fin 10 and the second part 20(2) of the top fin 20 so as to seal the gap through the dielectric layer 50, thereby isolating the bottom fin 10 and the second part 20(2).

[0029] The bottom fin 10 serves to provide support for the top fin 20. The bottom fin 10 also serves to provide a process basis for forming the isolation layer 420, so that the isolation layer 420 can surround the bottom fin 10 and expose the top fin 20, thereby achieving isolation between adjacent bottom fins 10, and also isolating the substrate 100 and the gate structure 470.

[0030] The bottom fin 10 is made of a semiconductor material. The material of the bottom fin 10 includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0031] In this embodiment, the bottom fin 10 and the substrate 100 are an integral structure. The material of the bottom fin 10 and the substrate 100 is the same, which is silicon.

[0032] The top fin 20 serves as an effective fin, providing a conductive channel for the field-effect transistor during device operation. Specifically, the first portion 20(1) provides the conductive channel for the field-effect transistor. The top fin 20 is made of a semiconductor material. In this embodiment, the material of the top fin 20 includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0033] It should be noted that the distance between the top surface of the bottom fin 10 and the bottom surface of the top fin 20 along the direction perpendicular to the substrate 100 should not be too small or too large. If the distance between the top surface of the bottom fin 10 and the bottom surface of the top fin 20 is too small, it will easily increase the difficulty of forming the gap; if the distance between the top surface of the bottom fin 10 and the bottom surface of the top fin 20 is too large, it will easily lead to an excessively large height of the fin structure 110, which will easily increase the difficulty of forming the fin structure 110 and also increase the difficulty of forming the gate structure 470 between the bottom fin 10 and the first part 20 (1). Therefore, in this embodiment, the distance between the top surface of the bottom fin 10 and the bottom surface of the top fin 20 along the direction perpendicular to the substrate 100 is 5nm to 15nm.

[0034] It should also be noted that the fin structure 110 is formed using the process of a fin field-effect transistor. In this embodiment, the width of the top fin 20 along the direction perpendicular to the extension of the fin structure 110 is a first dimension; the height of the top fin 20 along the direction perpendicular to the substrate 100 is a second dimension; the first dimension is smaller than the second dimension, that is, the aspect ratio of the top fin 20 is relatively large, which satisfies the characteristics of a fin structure.

[0035] As an example, the ratio of the first dimension to the second dimension ranges from 1:2 to 1:5.

[0036] It should also be noted that the fin structure 110 is formed using the process of a fin field-effect transistor. In this embodiment, along the direction perpendicular to the extension of the fin structure 110, the top width of the top fin 20 is smaller than the bottom width of the top fin 20. That is, along the direction perpendicular to the extension of the fin structure 110, the cross-section of the top fin 20 is a structure that is smaller at the top and larger at the bottom, which also satisfies the morphological characteristics of a fin structure.

[0037] The dielectric layer 50 seals the gap, thereby achieving isolation between the second part 20(2) and the bottom fin 10. This helps to reduce the probability of forming parasitic devices in the bottom fin 10, correspondingly reducing the leakage current of the semiconductor structure, improving the electrical performance of the device, and also being compatible with the process of forming fin field-effect transistors, which helps to improve process compatibility and reduce costs.

[0038] The dielectric layer 50 is made of an insulating dielectric material, such as silicon oxide, silicon nitride, and silicon oxynitride, or one or more of these materials. As an example, the dielectric layer 50 may be made of the same material as the isolation layer 420, which improves process compatibility. In this embodiment, both the isolation layer 420 and the dielectric layer 50 are made of silicon oxide. In other embodiments, the dielectric layer may be made of a different material than the isolation layer.

[0039] In this embodiment, the dielectric layer 50 is used to fill the gap as an example, which helps to improve the isolation effect of the dielectric layer 50 between the bottom fin 10 and the second part 20 (2). In other embodiments, the dielectric layer may only seal the gap.

[0040] The isolation layer 420 is used to achieve electrical isolation between the bottom fins 10. In this embodiment, the isolation layer 420 surrounds the bottom fins 10 and exposes the top fins 20 so that the gate structure 470 can span the top fins 20 and cover part of the top and sidewalls of the top fins 20, thereby forming a conductive channel within the top fins 20 (i.e., the first portion) covered by the gate structure 470 when the device is in operation. Furthermore, the gate structure 470 is located on the isolation layer 420, which surrounds the bottom fins 10, thereby preventing the bottom of the gate structure 470 from being too deep. This helps to maintain a certain distance between the bottom of the gate structure 470 and the bottom fins 10, further reducing the probability of parasitic devices being generated within the bottom fins 10.

[0041] In this embodiment, the isolation layer 420 is a shallow trench isolation (STI) structure. In this embodiment, the material of the isolation layer 420 is silicon oxide. In other embodiments, the material of the isolation layer can also be other insulating materials such as silicon nitride or silicon oxynitride.

[0042] In this embodiment, the top surface of the isolation layer 420 is lower than the bottom surface of the top fin 20, and the isolation layer 420 exposes the dielectric layer 50.

[0043] During the formation of the semiconductor structure, a sacrificial layer is formed between the bottom fin 10 and the top fin 20. The gap is formed by removing the sacrificial layer on both sides of the dummy gate structure. During the formation of the semiconductor structure, the top surface of the isolation layer 420 is lower than the bottom surface of the top fin 20, thereby exposing the sacrificial layer and thus removing the sacrificial layer on both sides of the dummy gate structure.

[0044] Similarly, since the top surface of the isolation layer 420 is lower than the top fin 20, the gate opening can expose the sacrificial layer during the step of removing the dummy gate structure to form the gate opening, thereby facilitating the removal of the sacrificial layer.

[0045] Alternatively, after forming the gate opening, the bottom of the gate opening exposes the isolation layer. By removing a portion of the thick isolation layer below the gate opening, the sacrificial layer can be exposed, thus facilitating its removal. Correspondingly, after forming the gate structure 470, the top surface of the isolation layer is lower than the bottom surface of the top fin 20.

[0046] When the device is in operation, the gate structure 470 is used to control the opening and closing of the conductive channel.

[0047] The gate structure 470 surrounds the second part 20(2) of the top fin 20, which provides a conductive channel. This improves the gate structure 470's control over the conductive channel, further reducing the probability of leakage current and thus enhancing the performance of the semiconductor structure.

[0048] In this embodiment, the bottom fin 10, the top fin 29, and the insulating layer form a through groove 160 (refer to reference). Figures 15 to 17 The gate structure 470 is also located within the through slot 160, thereby surrounding the first portion 20 (1).

[0049] In this embodiment, the gate structure 470 is a metal gate structure, which is formed by forming a high k last metal gate last process after forming a high k last gate dielectric layer.

[0050] In this embodiment, the gate structure 470 includes a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer.

[0051] The work function layer is used to adjust the work function of the metal gate structure, thereby regulating the threshold voltage of the transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0052] The electrode material layer serves as an electrode, used to draw out the electrical properties of the metal gate structure, thereby achieving electrical connection between the metal gate structure and external circuitry. In this embodiment, the electrode material layer is made of W. In other embodiments, the electrode material layer may also be made of Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0053] In this embodiment, a gate dielectric layer 70 is also formed between the gate structure 470 and the top fin 20. The gate dielectric layer 70 is used to achieve electrical isolation between the gate structure 470 and the top fin 20.

[0054] In this embodiment, the gate dielectric layer 70 includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. As an example, the material of the high-k gate dielectric layer is hafnium oxide (HfO2).

[0055] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. The gate oxide layer is made of one or both of silicon oxide and silicon oxynitride. In still other embodiments, the gate dielectric layer may consist only of a gate oxide layer.

[0056] In this embodiment, a sidewall 460 is also formed on the sidewall of the gate structure 470. The sidewall 460 is used to protect the sidewall of the gate structure 470 and to define the formation location of the source and drain doped regions 200.

[0057] In this embodiment, the sidewall 460 is also formed on the sidewall of the top fin 20, so that the sidewall 460 can also protect the sidewall of the top fin 20 during the formation of the semiconductor structure.

[0058] In a specific embodiment, the sidewall 460 may include a plurality of sub-sidewalls (not shown) sequentially stacked on the sidewall of the gate structure 470; wherein at least one sub-sidewall is made of the same material as the dielectric layer 50.

[0059] At least one of the sub-sidewalls in the sidewall 460 is made of the same material as the dielectric layer 50, so that the sub-sidewalls can be formed using the process steps for forming the dielectric layer 50 during the semiconductor structure process. This allows the process for forming the dielectric layer 50 to be combined with the process for forming the sidewall 460, thereby further improving process integration and process compatibility.

[0060] As an example, the sidewall 460 can be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbon oxynitride, boron nitride, and boron carbonitride. The sidewall 460 can be a single-layer structure or a multilayer structure. In this embodiment, the sidewall 460 is a single-layer structure, and the material of the sidewall 460 is silicon nitride.

[0061] The source / drain doped region 200 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped region 200 is used to provide a source of charge carriers. In this embodiment, the source / drain doped region 200 is located within the second part 20(2).

[0062] In this embodiment, the source / drain doped region 200 includes a stress layer doped with ions. The source / drain doped region 200 is also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0063] Specifically, when forming an NMOS transistor, the source / drain doped region 200 is made of a stress layer doped with N-type ions. The stress layer material includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When forming a PMOS transistor, the source / drain doped region 200 is made of a stress layer doped with P-type ions. The stress layer material includes Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.

[0064] It should be noted that in this embodiment, the bottom surface of the source / drain doped region 200 is higher than the bottom surface of the top fin 20, thereby preventing the source / drain doped region 200 from contacting the dielectric layer 50 located below the top fin 20, thus ensuring that the formation process of the source / drain doped region 200 is not affected by the dielectric layer 50, and correspondingly ensuring the formation quality of the source / drain doped region 200.

[0065] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 90 located on the isolation layer 420 on the side of the gate structure 470. The interlayer dielectric layer 90 is used to isolate adjacent gate structures 470, thereby achieving electrical isolation between adjacent devices. The interlayer dielectric layer 90 can be a single layer or a stacked structure. The material of the interlayer dielectric layer 90 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride.

[0066] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 7 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0067] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0068] refer to Figure 7 The substrate is provided, including a substrate 100 and a plurality of fin structures 110 disposed on the substrate 100, the fin structure 110 including a bottom fin 10 and a sacrificial layer 30 on the bottom fin 10, and a top fin 20 on the sacrificial layer 30.

[0069] The substrate serves as a process platform for subsequent manufacturing processes. In this embodiment, substrate 100 is a silicon substrate, meaning the material of substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0070] The fin structure 110 is used for the subsequent formation of the top fin 20, which is suspended and spaced apart from the bottom fin 10.

[0071] The bottom fin 10 serves to provide support for the sacrificial layer 30 and the top fin 20. The bottom fin 10 also provides a process basis for the subsequent formation of an isolation layer, so that the isolation layer can surround the bottom fin 10 and expose the top fin 20, thereby achieving isolation between adjacent bottom fins 10, as well as isolating the substrate 100 from the dummy gate structure, and isolating the substrate 100 from the subsequent gate structure.

[0072] The bottom fin 10 is made of a semiconductor material. The material of the bottom fin 10 includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0073] In this embodiment, the bottom fin 10 and the substrate 100 are an integral structure. The material of the bottom fin 10 and the substrate 100 is the same, which is silicon.

[0074] In this embodiment, the fin structure 110 further includes a sacrificial layer 30. Subsequently, the sacrificial layers 30 located on both sides of the dummy gate structure are removed, creating a gap between the bottom fin 10, the top fin 20, and the remaining sacrificial layer 30. This forms a dielectric layer that seals the gap, thereby isolating the top fin 20 from the bottom fin 10. This helps reduce the probability of parasitic devices forming within the bottom fin 10, correspondingly reducing the leakage current of the semiconductor structure. Furthermore, by providing the sacrificial layer 30 in the fin structure 110, it is compatible with the process for forming fin field-effect transistors, improving process compatibility and reducing costs.

[0075] Therefore, the sacrificial layer 30 is made of a material that has etching selectivity for both the bottom fin 10 and the top fin 20, so as to achieve a high etching selectivity between the sacrificial layer 30 and the bottom fin 10 and between the sacrificial layer 30 and the top fin 20 in the subsequent step of removing the sacrificial layer 30 located on both sides of the pseudo gate structure. This reduces the difficulty of removing the sacrificial layer 30 located on both sides of the pseudo gate structure and reduces the probability of damage to the top fin 20 and the bottom fin 10.

[0076] In this embodiment, during the step of providing the substrate, the material of the sacrificial layer 30 includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The material of the sacrificial layer 30 is different from the materials of the bottom fin 10 and the top fin 20. Specifically, in this embodiment, the material of the bottom fin 10 is silicon, and the material of the sacrificial layer 30 is silicon germanide.

[0077] It should be noted that the thickness of the sacrificial layer 30 should not be too small or too large. If the thickness of the sacrificial layer 30 is too small, it will increase the difficulty of subsequent processes such as removing the sacrificial layers 30 located on both sides of the dummy gate structure, removing the remaining sacrificial layers 30, and forming the gate structure in the through-hole. If the thickness of the sacrificial layer 30 is too large, it will easily lead to an excessively large height of the fin structure 110, which will further increase the difficulty of forming the fin structure 110. Therefore, in this embodiment, the thickness of the sacrificial layer is 5nm to 15nm.

[0078] The top fin 20 serves as an effective fin, providing a conductive channel for the field-effect transistor during device operation. The top fin 20 is made of a semiconductor material. In this embodiment, the material of the top fin 20 includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0079] As an example, the step of providing a substrate includes: forming a first semiconductor layer (not shown), a sacrificial material layer (not shown), and a second semiconductor layer (not shown) stacked sequentially; patterning the second semiconductor layer, the sacrificial material layer, and a portion of the thickness of the first semiconductor layer, with the remaining second semiconductor layer used as a top fin, the remaining sacrificial material layer used as a sacrificial layer, and forming a substrate and a bottom fin protruding from the substrate in the remaining first semiconductor layer.

[0080] In this embodiment, the material of the sacrificial material layer is a semiconductor material, and the process for forming the sacrificial material layer includes an epitaxial process.

[0081] Continue to refer to Figure 7 An isolation layer 420 is formed on the substrate 100 surrounding the bottom fin 10, and the isolation layer 420 exposes the top fin 20. The isolation layer 420 is used to achieve electrical isolation between the bottom fins 10.

[0082] In this embodiment, the isolation layer 420 surrounds the bottom fin 10 and exposes the top fin 20, so that the subsequently formed dummy gate structure can span the top fin 20 and cover part of the top and sidewalls of the top fin 20. This allows a conductive channel to be formed within the top fin 20 covered by the dummy gate structure during device operation. Furthermore, the subsequent dummy gate structure is formed on the isolation layer 420, which surrounds the bottom fin 10, preventing the bottom of the dummy gate structure or gate structure from becoming too deep. This helps maintain a certain distance between the bottom of the dummy gate structure or gate structure and the bottom fin 10, further reducing the probability of parasitic devices forming within the bottom fin 10.

[0083] In a specific implementation, the isolation layer 420 can cover the sidewalls of the bottom fin 10 and the sacrificial layer 30, that is, the top surface of the isolation layer 420 is flush with the top surface of the sacrificial layer 30.

[0084] In other embodiments, the isolation layer may expose at least a portion of the sidewalls of the sacrificial layer; that is, the isolation layer may cover both the sidewalls of the bottom fin and a portion of the sidewalls of the sacrificial layer, or it may only cover the sidewalls of the bottom fin, with the top surface of the isolation layer correspondingly lower than the top surface of the sacrificial layer. Accordingly, in the subsequent step of forming the dummy gate structure, the dummy gate structure also covers a portion of the sidewalls of the sacrificial layer exposed by the isolation layer. Since at least a portion of the sidewalls of the sacrificial layer are exposed, it facilitates the removal of the sacrificial layer located on both sides of the dummy gate structure, and in the step of removing the dummy gate structure to form the gate opening, the bottom of the gate opening exposes the remaining sacrificial layer, facilitating subsequent removal of the remaining sacrificial layer.

[0085] In this embodiment, the isolation layer 420 is a shallow trench isolation structure. In this embodiment, the material of the isolation layer 420 is silicon oxide. In other embodiments, the material of the isolation layer can also be other insulating materials such as silicon nitride or silicon oxynitride.

[0086] refer to Figure 8 A pseudo-gate structure 440 is formed on the isolation layer 420, spanning the top fin 20.

[0087] The dummy gate structure 440 is used to occupy space for forming the gate structure. In this embodiment, the dummy gate structure 440 spans the top fin 20 and covers part of the top and part of the sidewalls of the top fin 20.

[0088] In other embodiments, when the isolation layer also exposes at least a portion of the sidewalls of the sacrificial layer, during the step of forming the dummy gate structure, the dummy gate structure also covers a portion of the sidewalls of the sacrificial layer exposed by the isolation layer, so that in the subsequent step of removing the dummy gate structure to form a gate opening, the bottom of the gate opening can expose the remaining sacrificial layer, thereby facilitating the removal of the remaining sacrificial layer.

[0089] In this embodiment, the dummy gate structure 440 includes a dummy gate layer. The dummy gate layer material includes polycrystalline silicon or amorphous silicon.

[0090] In this embodiment, a pseudo-gate oxide layer 430 is also formed between the pseudo-gate structure 440 and the top fin 20. The pseudo-gate oxide layer 430 is used to isolate the top fin 20 from the pseudo-gate structure 440, and also to stop the etching process during the subsequent removal of the pseudo-gate structure 440, thereby reducing the probability of damage to the top fin 20.

[0091] The pseudo-gate oxide layer 430 is made of silicon oxide or nitrogen-doped silicon oxide.

[0092] In this embodiment, a gate mask layer 450 is also formed on the top of the dummy gate structure 440. The gate mask layer 450 is used as an etching mask for forming the dummy gate structure 440 and also to protect the top of the dummy gate structure 440.

[0093] In this embodiment, the material of the gate mask layer 440 is silicon nitride.

[0094] In this embodiment, the isolation layer covers the sidewalls of the sacrificial layer; the subsequent steps also include: after forming the pseudo-gate structure and before removing the sacrificial layers located on both sides of the pseudo-gate structure, removing the portion of the isolation layer exposed by the pseudo-gate structure and the top fin, thereby exposing the sidewalls of the sacrificial layer.

[0095] In this embodiment, reference Figure 9 The method for forming the semiconductor structure further includes: after forming the dummy gate structure 440, and before removing the portion of the isolation layer 420 exposed between the dummy gate structure 440 and the top fin 20, forming a sidewall 460 on the sidewall of the dummy gate structure 440. The sidewall 460 is also formed on the sidewall of the top fin 20. The sidewall 460 serves to protect the sidewall of the dummy gate structure 440 and also defines the formation locations of subsequent source / drain doped regions.

[0096] In this embodiment, the sidewall 460 is also formed on the sidewall of the top fin 20, thereby protecting the sidewall of the top fin 20 in the subsequent steps of removing the pseudo-gate structure 440 and the exposed portion of the isolation layer 420 of the top fin 20, as well as removing the sacrificial layer 30.

[0097] The sidewall 460 can be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. The sidewall 460 can be a single-layer structure or a multilayer structure. In this embodiment, the sidewall 460 is a single-layer structure, and the material of the sidewall 460 is silicon nitride.

[0098] In this embodiment, the sidewall 460 also covers the sidewall of the gate mask layer 450.

[0099] As an example, the steps of forming the sidewall 460 include: forming a sidewall material layer (not shown) on the top and sidewalls of the pseudo-gate structure 440, the top and sidewalls of the top fin 20, and the top surface of the isolation layer 420; using an anisotropic etching process to remove the sidewall material layer located on the top of the pseudo-gate structure 440, the top fin 20, and the isolation layer 420, and the remaining sidewall material layer located on the sidewalls of the pseudo-gate structure 440 and the top fin 20 is used as the sidewall 460.

[0100] In this embodiment, reference Figure 10 The method of forming the pseudo-gate structure 440 further includes: after forming the pseudo-gate structure 440 and before removing the sacrificial layers 30 located on both sides of the pseudo-gate structure 440, removing the portion of the thickness of the isolation layer 420 exposed by the pseudo-gate structure 440 and the top fin 20, thereby exposing the sidewalls of the sacrificial layer 30.

[0101] Remove the portion of the isolation layer 420 that is exposed in the pseudo-gate structure 440 and the top fin 20 to expose the sidewalls of the sacrificial layer 30 so that the sacrificial layer 30 can be removed subsequently through the exposed sidewalls of the sacrificial layer 30.

[0102] In this embodiment, before removing the portion of the isolation layer 420 exposed in the pseudo-gate structure 440 and the top fin 20, a sidewall 460 is formed on the sidewall of the pseudo-gate structure 440 and the top fin 20. Therefore, the step of removing the portion of the isolation layer 420 exposed in the pseudo-gate structure 440 and the top fin 20 includes: removing the portion of the isolation layer 420 exposed in the pseudo-gate structure 440, the top fin 20 and the sidewall 460; removing the isolation layer 420 at the bottom of the sidewall 460 on the sidewall of the top fin 20, thereby exposing the sidewall of the sacrificial layer 30.

[0103] After removing the portion of the thickness of the isolation layer 420 exposed by the pseudo-gate structure 440, the top fin 20 and the sidewall 460, the isolation layer 420 at the bottom of the sidewall 460 located on the sidewall of the top fin 20 is also removed, thereby exposing the sidewall of the sacrificial layer 30 so that the sacrificial layer 30 can be removed subsequently through the exposed sidewall of the sacrificial layer 30.

[0104] In this embodiment, an anisotropic etching process is used to remove the exposed portion of the isolation layer 420 from the dummy gate structure 440, the top fin 20, and the sidewall 460, thereby achieving a reduction in the thickness of the isolation layer 420 along the direction perpendicular to the substrate 100. In a specific embodiment, the anisotropic etching process may include anisotropic dry etching.

[0105] In this embodiment, an isotropic etching process is used to remove the isolation layer 420 at the bottom of the sidewall 460 on the sidewall of the top fin 20. The isotropic etching process has the characteristics of isotropic etching, which enables the isolation layer 420 to be etched laterally along a direction parallel to the substrate 100, thereby removing the isolation layer 420 at the bottom of the sidewall 460 on the sidewall of the top fin 20 to expose the sidewall of the sacrificial layer 30.

[0106] In specific embodiments, the isotropic etching process can be an isotropic dry etching process, an isotropic wet etching process, or a combination of isotropic dry etching and wet etching processes.

[0107] It should be noted that, in this embodiment, the example is an isolation layer 420 with a thickness of the portion of the pseudo-gate structure 440 and the exposed portion of the top fin 20 after the sidewall 460 is formed.

[0108] In other embodiments, the method of forming a semiconductor structure further includes: after forming the dummy gate structure, and before removing the isolation layer of a portion of the thickness of the dummy gate structure and the top fin, forming a first sidewall on the sidewall of the dummy gate structure, the first sidewall also being formed on the sidewall of the top fin.

[0109] The first sidewall is used to protect the sidewall of the dummy gate structure. Furthermore, the first sidewall can be used as part of a sidewall, or it can be used as a sacrificial sidewall, which is subsequently removed accordingly. Accordingly, the first sidewall has a relatively small thickness. The step of removing the exposed portion of the isolation layer from the dummy gate structure and the top fin includes: removing the exposed portion of the isolation layer from the dummy gate structure, the top fin, and the first sidewall. In the step of removing the exposed portion of the isolation layer from the dummy gate structure, the top fin, and the first sidewall, because the first sidewall is relatively thin, it is easy to remove the portion of the isolation layer below the first sidewall located on the sidewall of the top fin by over-etching, thereby exposing the sidewall of the sacrificial layer.

[0110] Specifically, an anisotropic etching process is used to remove the exposed portion of the isolation layer from the pseudo-gate structure, the top fin, and the first sidewall.

[0111] It should be noted that in this embodiment, the isolation layer covers the sidewall of the sacrificial layer during the step of forming the isolation layer; and after forming the pseudo-gate structure, before removing the sacrificial layers located on both sides of the pseudo-gate structure, the isolation layer of the exposed portion of the pseudo-gate structure and the top fin is also removed as an example.

[0112] In other embodiments, the step of removing the dummy gate structure and the portion of the isolation layer exposed at the top fin can be omitted. For example, when the isolation layer also exposes at least a portion of the sidewalls of the sacrificial layer during the step of forming the isolation layer, the dummy gate structure also covers the portion of the sidewalls of the sacrificial layer exposed by the isolation layer, so that the portion of the sidewalls of the sacrificial layer is still exposed after the dummy gate structure is formed, thus eliminating the need to etch the isolation layer to expose the sacrificial layer.

[0113] refer to Figure 11 Remove the sacrificial layers 30 located on both sides of the pseudo-gate structure 440 to form a gap 40 between the bottom fin 10, the top fin 20, and the remaining sacrificial layers 30.

[0114] The sacrificial layers 30 located on both sides of the pseudo-gate structure 440 are removed to form gaps 40 so that a dielectric layer can be formed in the gaps 40, thereby isolating the bottom fin 10 and the top fin 20 through the dielectric layer.

[0115] In the step of removing the sacrificial layers 30 located on both sides of the dummy gate structure 440, the remaining sacrificial layers 30 covered by the dummy gate structure 440 are retained so that after the dummy gate structure 440 is subsequently removed to form a gate opening, the bottom of the gate opening exposes the remaining sacrificial layers 30, and the remaining sacrificial layers 30 can be removed through the gate opening.

[0116] In this embodiment, the process for removing the sacrificial layer 30 located on both sides of the dummy gate structure 440 includes an isotropic etching process. The isotropic etching process has the characteristics of isotropic etching, thereby enabling the sacrificial layer 30 to be etched along a direction parallel to the substrate 100, thereby removing the sacrificial layer 30.

[0117] In specific embodiments, the isotropic etching process includes one or both of isotropic dry etching and wet etching.

[0118] It should be noted that in the isotropic etching process, the sacrificial layer 30 located at the bottom of the dummy gate structure 440 is difficult to remove under the cover of the dummy gate structure 440, and thus can be preserved. In a specific embodiment, the parameters of the etching process (e.g., etching time) can also be controlled to ensure that the sacrificial layer 30 covered by the dummy gate structure 440 is preserved while the sacrificial layers 30 located on both sides of the dummy gate structure 440 are removed.

[0119] refer to Figure 12 A dielectric layer 50 is formed to create a sealing gap 40.

[0120] The dielectric layer 50 seals the gap 40, thereby isolating the top fin 20 from the bottom fin 10. This helps reduce the probability of parasitic devices forming in the bottom fin 10, thereby reducing the leakage current of the semiconductor structure, improving the electrical performance of the device, and also making it compatible with the process of forming fin field-effect transistors, which helps improve process compatibility and reduce costs.

[0121] The dielectric layer 50 is made of an insulating dielectric material, such as silicon oxide, silicon nitride, and silicon oxynitride, or one or more of these materials. As an example, the dielectric layer 50 may be made of the same material as the isolation layer 420, which improves process compatibility. In this embodiment, both the isolation layer 420 and the dielectric layer 50 are made of silicon oxide. In other embodiments, the dielectric layer may be made of a different material than the isolation layer.

[0122] In this embodiment, the dielectric layer 50 filling the gap 40 is used as an example for illustration, which helps to improve the isolation effect of the dielectric layer 50 between the bottom fin 10 and the top fin 20. In other embodiments, the dielectric layer 50 may only seal the gap.

[0123] As an example, atomic layer deposition (ALD) is used to form the dielectric layer 50. ALD has strong gap-filling capability, which is beneficial for improving the filling quality of the dielectric layer 50 within the gaps 40. In other embodiments, other suitable deposition processes can also be used to form the dielectric layer. For example, chemical vapor deposition (CVD) can be used to form the dielectric layer.

[0124] In other embodiments, after the dummy gate structure is formed and before the isolation layer of the exposed portion of the dummy gate structure and the top fin is removed, a first sidewall is also formed on the sidewall of the dummy gate structure. The first sidewall is also formed on the sidewall of the top fin. Correspondingly, in the step of forming the dielectric layer, the dielectric layer is also formed on the sidewall of the first sidewall. The dielectric layer formed on the sidewall of the first sidewall is used as a second sidewall. The second sidewall and the first sidewall are used to constitute the gate sidewall, thereby integrating the steps of forming the dielectric layer and forming the gate sidewall, which is beneficial to improving process integration and simplifying the process flow.

[0125] Alternatively, in other embodiments, after removing the sacrificial layer and before forming the dielectric layer, the method for forming the semiconductor structure further includes: removing the first sidewall; in the step of forming the dielectric layer, the dielectric layer is also formed on the sidewall of the dummy gate structure, and the dielectric layer formed on the sidewall of the dummy gate structure is used as a third sidewall, which can also integrate the steps of forming the dielectric layer and the gate sidewall, which is beneficial to improving process integration and simplifying the process flow.

[0126] It should be noted that, in this embodiment, during the step of forming dielectric layer 50, dielectric layer 50 is also formed on the top and sidewalls of top fin 20; after forming dielectric layer 50 and before forming source / drain doped regions, the method for forming semiconductor structure further includes: removing dielectric layer 50 located on top of top fin 20 to expose top fin 20 so that source / drain doped regions can be formed in top fin 20 subsequently.

[0127] refer to Figure 13 After the dielectric layer 50 is formed, source and drain doped regions 200 are formed in the top fins 20 on both sides of the pseudo-gate structure 440.

[0128] The source / drain doped region 200 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped region 200 is used to provide a source of charge carriers.

[0129] In this embodiment, the source / drain doped region 200 includes a stress layer doped with ions. The source / drain doped region 200 also provides stress to the channel, thereby improving the carrier mobility of the channel. For a description of the material of the source / drain doped region 200, please refer to the corresponding description in the foregoing embodiments; it will not be repeated here.

[0130] It should be noted that, in this embodiment, in the step of forming the source / drain doped region 200, the bottom surface of the source / drain doped region 200 is higher than the bottom surface of the top fin 20, thereby preventing the source / drain doped region 200 from contacting the dielectric layer 50 located below the top fin 20, thus ensuring that the formation process of the source / drain doped region 200 is not affected by the dielectric layer 50, and correspondingly ensuring the formation quality of the source / drain doped region 200.

[0131] In a specific embodiment, the step of forming the source / drain doped region 200 may include: forming a groove (not shown) in the top fin 20 on both sides of the pseudo-gate structure 440; and forming the source / drain doped region 200 in the groove.

[0132] Specifically, the process of forming the source / drain doped region 200 within the groove includes an epitaxial process. The bottom of the groove is correspondingly higher than the bottom surface of the top fin 20, thereby ensuring that all exposed material in the groove is from the top fin 20, thus ensuring the formation quality of the epitaxial process for forming the source / drain doped region 200 within the groove.

[0133] refer to Figures 14 to 17 , Figure 14 Based on Figure 13 3D image, Figure 15 yes Figure 14 Cross-sectional view along the direction of extension of the top fin. Figure 16 yes Figure 15 Cross-sectional view along the B1-B1 direction. Figure 17 yes Figure 15 A cross-sectional view along the B2-B2 direction shows the removal of the pseudo-gate structure 440, forming a gate opening 170 spanning the top fin.

[0134] The gate opening 170 provides space for forming the gate structure. Specifically, one or both of dry etching and wet etching processes can be used to remove the dummy gate structure 440 to form the gate opening 170.

[0135] In this embodiment, the bottom of the gate opening 170 exposes the isolation layer 420.

[0136] In other embodiments, when the dummy gate structure also covers part of the sidewall of the sacrificial layer exposed by the isolation layer, the bottom of the gate opening is exposed during the step of forming the gate opening so that the remaining sacrificial layer can be removed subsequently.

[0137] It should be noted that, in the specific implementation, during the step of forming the dummy gate structure, a dummy gate oxide layer is also formed between the dummy gate structure and the top fin; correspondingly, during the step of forming the gate opening, the gate opening exposes the dummy gate oxide layer.

[0138] It should also be noted that, in this embodiment, after forming the source / drain doped region 200 and before removing the dummy gate structure 440, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer 90 on the isolation layer 420 on the side of the dummy gate structure 440.

[0139] Interlayer dielectric layer 90 is used to isolate adjacent gate structures to achieve electrical isolation between adjacent devices. Interlayer dielectric layer 90 can be a single layer or a stacked structure. The material of interlayer dielectric layer 90 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride.

[0140] In this embodiment, during the step of forming the interlayer dielectric layer 90, the gate mask layer 450 is also removed to expose the top of the dummy gate structure 440, thereby enabling the removal of the dummy gate structure 440.

[0141] Continue to refer to Figures 14 to 17 The remaining sacrificial layer 30 is removed through the gate opening 170, so that the bottom fin 10, the top fin 29 and the isolation layer form a through groove 160, and the through groove 160 is connected to the gate opening 170.

[0142] The slot 160 is used to provide space for the formation of the gate structure so that the subsequent gate structure is formed in the slot and the gate opening 170, thereby enabling the gate structure to surround the top fin 20.

[0143] In this embodiment, the process for removing the remaining sacrificial layer 30 includes an isotropic etching process. The isotropic etching process has the characteristics of isotropic etching, which facilitates the complete removal of the remaining sacrificial layer 30.

[0144] In this embodiment, in the step of forming the isolation layer 420, the isolation layer 420 covers the sidewall of the sacrificial layer 30; the step of removing the remaining sacrificial layer 30 through the gate opening 160 includes: removing a portion of the thickness of the isolation layer 420 at the bottom of the gate opening 160 to expose the remaining sacrificial layer 30; and removing the remaining sacrificial layer 30.

[0145] In other embodiments, when the dummy gate structure also covers part of the sidewall of the sacrificial layer exposed by the isolation layer, the bottom of the gate opening exposes the remaining sacrificial layer during the step of forming the gate opening, thereby eliminating the need for the step of removing a portion of the thickness of the isolation layer below the gate opening.

[0146] Specifically, in this embodiment, during the step of forming the gate opening, the gate opening exposes the dummy gate oxide layer; correspondingly, after forming the gate opening and before removing the remaining sacrificial layer, the forming method further includes: removing the dummy gate oxide layer exposed by the gate opening in order to expose the isolation layer 420 or the sacrificial layer 30.

[0147] More specifically, in this embodiment, in the step of removing the dummy gate oxide layer exposed by the gate opening, a portion of the thickness of the isolation layer at the bottom of the gate opening is removed. This combines the step of removing the dummy gate oxide layer exposed by the gate opening with the step of removing the portion of the thickness of the isolation layer at the bottom of the gate opening, which is beneficial to improving process integration and process compatibility.

[0148] Reference Figures 18 to 21 , Figure 18 Based on Figure 14 3D image, Figure 19 yes Figure 18 Cross-sectional view along the direction of extension of the top fin. Figure 20 yes Figure 18 Cross-sectional view along the B1-B1 direction. Figure 21 yes Figure 18 A cross-sectional view along the B2-B2 direction shows that a gate structure 470 is formed within the gate opening 170 and the through slot 160, and the gate structure 470 surrounds the top fin 20.

[0149] When the device is in operation, the gate structure 470 is used to control the opening and closing of the conductive channel.

[0150] The gate structure 470 is filled in the gate opening 170 and the through slot 160, so that the gate structure 470 surrounds the top fin 20. The top fin 20 is used to provide a conductive channel, thereby improving the control capability of the gate structure 470 over the conductive channel, further reducing the probability of leakage current, and thus improving the performance of the semiconductor structure.

[0151] In this embodiment, the gate structure 470 is a metal gate structure. In this embodiment, the gate structure 470 includes a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer. For a detailed description of the materials of the gate structure 470, please refer to the corresponding descriptions in the foregoing embodiments; they will not be repeated here.

[0152] In this embodiment, a gate dielectric layer 70 is also formed between the gate structure 470 and the top fin 20. The gate dielectric layer 70 is used to achieve electrical isolation between the gate structure 470 and the top fin 20.

[0153] In this embodiment, the gate dielectric layer 70 includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. As an example, the material of the high-k gate dielectric layer is hafnium oxide (HfO2).

[0154] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. The gate oxide layer is made of one or both of silicon oxide and silicon oxynitride. In still other embodiments, the gate dielectric layer may consist only of a gate oxide layer.

[0155] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: Substrate; Multiple fin structures are disposed on a substrate. Each fin structure includes: a bottom fin that protrudes from the substrate; and a top fin that is suspended from the bottom fin at a distance. The top fin includes a first portion for forming a channel region and a second portion located on both sides of the first portion. A dielectric layer is used to seal the gap between the bottom fin and the second portion; An isolation layer is located on the substrate and surrounds the bottom fin; A gate structure is located on the isolation layer and spans the top fin and is also located between the bottom fin and the first portion, the gate structure surrounding the first portion; The source and drain doped regions are located within the top fins on both sides of the gate structure.

2. The semiconductor structure of claim 1, wherein, Along a direction perpendicular to the substrate, the distance between the top surface of the bottom fin and the bottom surface of the top fin is 5 nm to 15 nm.

3. The semiconductor structure of claim 1, wherein, The dielectric layer fills the gap between the bottom fin and the second portion.

4. The semiconductor structure of claim 1, wherein, The top surface of the isolation layer is lower than the bottom surface of the top fin, and the dielectric layer is exposed.

5. The semiconductor structure of claim 1, wherein, The width of the top fin is a first dimension along the direction perpendicular to the fin structure; the height of the top fin is a second dimension along the direction perpendicular to the substrate. The first dimension is smaller than the second dimension.

6. The semiconductor structure of claim 5, wherein, The ratio of the first dimension to the second dimension ranges from 1:2 to 1:

5.

7. The semiconductor structure of claim 1, wherein, Along a direction perpendicular to the fin structure, the top width of the top fin is smaller than the bottom width of the top fin.

8. The semiconductor structure of claim 1, wherein, The bottom surface of the source / drain doped region is higher than the bottom surface of the top fin.

9. The semiconductor structure of claim 1, wherein, The semiconductor structure further includes: a sidewall located on the sidewall of the gate structure; the sidewall includes a plurality of sub-sidewalls stacked sequentially on the sidewall of the gate structure; wherein at least one sub-sidewall is made of the same material as the dielectric layer.

10. A method of forming a semiconductor structure, comprising: include: A substrate is provided, including a substrate and a plurality of fin structures discrete on the substrate, the fin structures including a bottom fin and a sacrificial layer on the bottom fin, and a top fin on the sacrificial layer; An isolation layer is formed on the substrate surrounding the bottom fin, the isolation layer exposing the top fin; A pseudo-gate structure spanning the top fin is formed on the isolation layer; Remove the sacrificial layers located on both sides of the pseudo-gate structure to form a gap between the bottom fin, the top fin, and the remaining sacrificial layers; A dielectric layer is formed to seal the gap; Source / drain doped regions are formed in the top fins on both sides of the pseudo-gate structure; Remove the pseudo-gate structure to form a gate opening that spans the top fin; The remaining sacrificial layer is removed through the gate opening, so that the bottom fin, the top fin, and the isolation layer form a through groove, and the through groove is connected to the gate opening; A gate structure is filled within the gate opening and the through slot, the gate structure surrounding the top fin.

11. The method of forming a semiconductor structure of claim 10, wherein, In the step of providing the substrate, the material of the sacrificial layer includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

12. The method of forming a semiconductor structure of claim 10, wherein, In the step of forming the isolation layer, the isolation layer covers the sidewalls of the sacrificial layer; the method of forming the semiconductor structure further includes: after forming the dummy gate structure and before removing the sacrificial layers located on both sides of the dummy gate structure, removing a portion of the thickness of the isolation layer exposed by the dummy gate structure and the top fin, thereby exposing the sidewalls of the sacrificial layer.

13. The method of forming a semiconductor structure of claim 12, wherein, The method for forming the semiconductor structure further includes: after forming the dummy gate structure and before removing the isolation layer of a portion of the thickness of the dummy gate structure and the top fin, forming a sidewall on the sidewall of the dummy gate structure, the sidewall also being formed on the sidewall of the top fin; The step of removing the exposed portion of the isolation layer from the pseudo-gate structure and the top fin includes: removing the exposed portion of the isolation layer from the pseudo-gate structure, the top fin, and the sidewalls; removing the isolation layer at the bottom of the sidewall located on the sidewall of the top fin, thereby exposing the sidewall of the sacrificial layer.

14. The method of forming a semiconductor structure of claim 12, wherein, The method for forming the semiconductor structure further includes: after forming the dummy gate structure and before removing the isolation layer of a portion of the thickness of the dummy gate structure and the top fin, forming a first sidewall on the sidewall of the dummy gate structure, the first sidewall also being formed on the sidewall of the top fin; The step of removing the exposed portion of the thickness of the isolation layer from the pseudo-gate structure and the top fin includes: removing the exposed portion of the thickness of the isolation layer from the pseudo-gate structure, the top fin, and the first sidewall.

15. The method of forming a semiconductor structure of claim 14, wherein, In the step of forming a dielectric layer, the dielectric layer is also formed on the sidewall of the first sidewall, and the dielectric layer formed on the sidewall of the first sidewall serves as a second sidewall, and the second sidewall and the first sidewall serve to form a gate sidewall. or, After removing the sacrificial layers located on both sides of the dummy gate structure and before forming the dielectric layer, the method of forming the semiconductor structure further includes: removing the first sidewall; In the step of forming the dielectric layer, the dielectric layer is also formed on the sidewall of the dummy gate structure, and the dielectric layer formed on the sidewall of the dummy gate structure serves as a third sidewall.

16. The method of forming a semiconductor structure of claim 10, wherein, In the step of forming the isolation layer, the isolation layer also exposes at least a portion of the sidewalls of the sacrificial layer.

17. The method of forming a semiconductor structure of claim 16, wherein, In the step of forming the pseudo-gate structure, the pseudo-gate structure also covers a portion of the sidewall of the sacrificial layer exposed by the isolation layer; in the step of forming the gate opening, the bottom of the gate opening exposes the remaining sacrificial layer.

18. The method of forming a semiconductor structure of claim 10 or 12, wherein, In the step of forming the isolation layer, the isolation layer covers the sidewall of the sacrificial layer; the step of removing the remaining sacrificial layer through the gate opening includes: removing a portion of the thickness of the isolation layer at the bottom of the gate opening to expose the remaining sacrificial layer; and removing the remaining sacrificial layer.

19. The method of forming a semiconductor structure of claim 18, wherein, In the step of forming the pseudo-gate structure, a pseudo-gate oxide layer is also formed between the pseudo-gate structure and the top fin; in the step of forming the gate opening, the gate opening exposes the pseudo-gate oxide layer. After forming the gate opening and before removing the remaining sacrificial layer, the forming method further includes: removing the pseudo-gate oxide layer exposed by the gate opening; In the step of removing the dummy gate oxide layer exposed by the gate opening, a portion of the thickness isolation layer at the bottom of the gate opening is removed.

20. The method of forming a semiconductor structure of claim 10, wherein, In the step of forming the source / drain doped region, a bottom surface of the source / drain doped region is higher than a bottom surface of the top fin.

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