A data acquisition and output circuit for signal interaction in a real-time simulator

Abstract

This invention discloses a data acquisition and output circuit for signal interaction in a real-time simulator, relating to the field of signal acquisition and output technology for DSPs and FPGAs. It includes an acquisition terminal, an output terminal, an acquisition signal processing unit, an output signal processing unit, a real-time simulator, an FPGA, a DSP, and an Ethernet control circuit. The acquisition terminal includes analog signal acquisition terminals and data signal acquisition terminals. The output terminal includes analog signal output terminals and data signal output terminals. The FPGA includes FPGA module 1, FPGA module 2, and FPGA module 3. The analog signal is input to the amplification and filtering circuit through the acquisition terminal. After being converted into a digital signal using a high-speed ADC, the data is packaged by the FPGA and transmitted to the DSP. The DSP controls the gigabit Ethernet circuit to transmit the packaged data to the real-time simulator through the sending terminal. This invention improves the accuracy and precision of the sampling results and maintains high stability during data transmission.

Description

Technical Field

[0001] This invention relates to the field of signal acquisition and output technology for DSPs and FPGAs, and in particular to a data acquisition and output circuit for signal interaction in a real-time simulator. Background Technology

[0002] Currently, digital real-time simulators are widely used in electrical engineering, life sciences, materials science, energy science, aerospace, and other fields. However, when using hardware-in-the-loop experiments with real-time simulators, real-time interaction with digital and analog signals from external hardware systems is required to verify the correctness of external hardware functionality. Therefore, designing a signal acquisition and output circuit to connect the real-time simulator to the physical system and achieve signal matching input and output is a key aspect of extending the functionality of real-time simulators. Considering that communication between the real-time simulator and the host computer uses Ethernet technology, this paper proposes a signal acquisition and output system based on Gigabit Ethernet to fully utilize existing resources and solve the problem of seamless communication between the real-time simulator and external systems. Summary of the Invention

[0003] In view of the problems existing in the above and / or existing digital real-time simulators, the present invention is proposed.

[0004] Therefore, the problem to be solved by the present invention is how to provide an analog digital signal acquisition and output circuit that can achieve high transmission rate, high data accuracy, high stability and wide applicability, and can be used in the development of real-time simulator hardware-in-the-loop systems.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] In a first aspect, embodiments of the present invention provide a data acquisition and output circuit for signal interaction in a real-time simulator, comprising an acquisition end, an output end, an acquisition signal processing unit, an output signal processing unit, a real-time simulator, an FPGA, a DSP, and an Ethernet control circuit; the acquisition end includes analog signal acquisition terminals and data signal acquisition terminals; the output end includes analog signal output terminals and data signal output terminals; the FPGA includes FPGA module 1, FPGA module 2, and FPGA module 3; FPGA module 1 establishes a non-commutative weak control martingale space, performs weak boundedness identification on the acquired data after weak control martingale grouping; FPGA module 2 establishes a non-commutative martingale differential subordinate group class, and performs weak boundedness identification on the real-time... After the running model and data in the simulator are categorized and calibrated, complete boundedness identification is performed. FPGA module 3 establishes a non-commutative martingale asymmetric subordinate training set, and performs subordinate training on the identification results using the mean-field linear quadratic optimal control algorithm. The training results are then sent to the host computer via Ethernet after passing through the output signal processing unit. The acquisition terminal is connected to the acquisition signal processing unit; the acquisition signal processing unit is connected to the FPGA; the FPGA is connected to the output signal processing unit; the FPGA and the DSP are interconnected; the DSP and the Ethernet control circuit are interconnected; the Ethernet control circuit and the real-time simulator are interconnected; and the output signal processing unit is connected to the output terminal.

[0007] As a preferred embodiment of the data acquisition and output circuit for real-time simulator signal interaction described in this invention, the digital signal acquired by the acquisition end is input to the protection circuit and the limiting circuit, packaged by the DSP and controlled via Gigabit Ethernet, and transmitted to the real-time simulator via the transmitting end; the digital signal output by the real-time simulator is transmitted to the FPGA via Gigabit Ethernet controlled by the DSP, the FPGA distinguishes the signal type, demodulates the analog signal data packets and sends them to the DAC via the transmitting end, and outputs them to the analog signal terminal block after amplification and filtering; simultaneously, the FPGA demodulates the digital signal data packets and outputs them to the digital signal terminal block after passing through the protection circuit.

[0008] As a preferred embodiment of the data acquisition and output circuit for real-time simulator signal interaction described in this invention, the specific steps of the FPGA module 1 include: based on the signal characteristics of the real-time simulator control object, let H be a given sinusoidal distribution finite space, B(H) denote the set of all bounded operators on H, let M be a subalgebra of B(H) with a finite, normal, and faithful trace τ, and α be a positive dense definite operator on H. If the unitary operator u in the commutator M' of M satisfies u×αu=α, then α is said to be attached to M. If for any acquired data ε i >0, there exists a projection e i Make τi (1–e i )<ε i ,(i = 1, 2, … n), n is the number of acquisitions, then X = {τ i ,(i = 1, 2, … n)} is called a non-commutative weak control martingale space, M’ is a control martingale, if the inequality is satisfied:

[0009] ||X||α = cscM ≤ ||M′||u = ||{e i}|| 0≤i≤n {ε i , 0 ≤ i ≤ n}

[0010] Then ε i is weakly bounded, use δ A to represent this data set, if satisfied then it is strongly bounded, use δ1 to represent this data set.

[0011] As a preferred scheme of the data acquisition output circuit for real-time simulator signal interaction described in the present invention, where: the specific steps of the FPGA module 2 include, let F be the model state variable in the real-time simulator model, (F i ) n ≤0 is a non-decreasing subalgebra of F, if satisfied

[0012] P(sup|F i |≥1) ≤ 2||∝||

[0013] Then the ε i <|F i | of ε i is classified into the non-commutative martingale differential subordinate group class, and the ε i >|F i | of ε i is classified into the non-commutative martingale non-differential subordinate group class; the analog quantity ω j set to be processed in the real-time simulator is {ω j (0 < j < m), m is the total number of analog quantities, the digital quantity δ k set satisfies {δ k (0 < k < l), where l is the total number of digital quantities, if satisfied:

[0014]

[0015] Then ω j and δ k have complete boundedness, use V A to represent this data set; conversely, if it has complete unboundedness, use V B to represent this data set.

[0016] As a preferred embodiment of the data acquisition and output circuit for real-time simulator signal interaction described in this invention, the specific steps of FPGA module 3 include:

[0017] The dataset is trained to obtain the K1 training set using the following formula:

[0018]

[0019] Finally, the output signal set is obtained through the mean-field linear quadratic optimal control algorithm:

[0020]

[0021] Where, δ A δ1 represents the dataset.

[0022] As a preferred embodiment of the data acquisition and output circuit for real-time simulator signal interaction described in this invention, the acquisition end further includes a data storage module for storing sampled data; the transmission end further includes a data analysis module for processing and analyzing digital signals; and the acquisition signal processing unit includes an amplifier circuit, a filter circuit, and a DC compensation circuit for performing gain, noise reduction, and DC offset reduction processing on the sampled signal.

[0023] As a preferred embodiment of the data acquisition and output circuit for real-time simulator signal interaction described in this invention, the acquisition end and the transmission end transmit data at a rate of 10Gbps via Gigabit Ethernet for high-speed and stable data transmission; the data acquisition and output circuit for real-time simulator signal interaction uses ±15V voltage as the driving voltage and communicates with the host computer via Gigabit Ethernet; a high-precision and highly stable analog and digital signal acquisition circuit is designed using the TMS320F28335 chip as the core, with 20 analog signal acquisition channels and 20 output channels, and 64 digital signal acquisition channels and 64 output channels; a PCB is used, and the PCB adopts a six-layer board design; the signal sampling rate of the high-speed ADC is 1GHz.

[0024] Secondly, to further address the problems existing in current digital real-time simulators, the present invention provides a data acquisition and output method for signal interaction in a real-time simulator, which further includes: preprocessing the signal at the signal acquisition end; converting it into a digital signal through a high-speed ADC; transmitting the data to the transmitting end; and decoding and synchronizing the signal to restore the original signal.

[0025] As a preferred embodiment of the data acquisition and output method for real-time simulator signal interaction described in this invention, the acquisition end processes the signal to be sampled through an acquisition signal processing unit, including an amplifier circuit, a filter circuit, and a DC compensation circuit, to perform gain, noise reduction, and DC offset reduction processing on the signal to be sampled, so as to ensure the accuracy and precision of the sampling results.

[0026] As a preferred embodiment of the data acquisition and output method for real-time simulator signal interaction described in this invention, the process of decoding and synchronizing to recover the original signal is as follows: the transmitting end transmits digital signal packets from the real-time simulator to the Ethernet port, the DSP unpacks and demodulates the data packets and transmits them to the FPGA for software filtering, the data is output to the DAC for filtering and amplification, and then connected to external hardware through the output signal terminal.

[0027] The beneficial effects of this invention are as follows: It employs gigabit Ethernet transmission, which offers high transmission rates and effectively reduces the bottleneck in data transmission for the signal acquisition system; the acquisition signal processing unit and high-speed ADC at the acquisition end can effectively process and convert the sampled signals, improving the accuracy and precision of the sampling results; the gigabit Ethernet connection between the acquisition end and the transmission end maintains high stability during data transmission; and based on the weakly bounded and fully bounded identification of direction transformations on quantum rings, this invention combines mean-field linear quadratic optimal control to achieve adaptive acquisition output and accelerate data convergence. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0029] Figure 1 This is the overall framework design of the acquisition circuit in Example 1.

[0030] Figure 2 This is the circuit diagram for the 5V to 1.9V power conversion in Example 1.

[0031] Figure 3 This is the circuit diagram for the 15V to 5V power conversion in Example 1.

[0032] Figure 4 This is the circuit diagram for the 5V to 3.3V power conversion in Example 1.

[0033] Figure 5 This is the circuit diagram for the 5V to 1.2V and 2.5V power conversion in Example 1.

[0034] Figure 6 This is the signal acquisition circuit diagram in Example 1.

[0035] Figure 7 This is a circuit diagram of the signal amplification circuit in Example 1.

[0036] Figure 8 This is a diagram of the signal output interface in Example 1.

[0037] Figure 9 This is a circuit diagram of the 15V signal filtering circuit in Example 1.

[0038] Figure 10 This is the circuit diagram for the 5V signal filtering circuit in Example 1.

[0039] Figure 11 This is the ±15V filter circuit diagram in Example 1.

[0040] Figure 12 This is the reset circuit diagram in Example 1.

[0041] Figure 13 This is the circuit diagram of the network module in Example 1.

[0042] Figure 14 The circuit diagram for FPGA module 1 in Example 1 is designed.

[0043] Figure 15 Design the circuit for FPGA module 2 in Example 1.

[0044] Figure 16 The circuit diagram for FPGA module 3 in Example 1 is designed.

[0045] Figure 17 This is the DSP design circuit in Example 1. Detailed Implementation

[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0048] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0049] Example 1

[0050] Reference Figure 1 This is the first embodiment of the present invention. This embodiment provides a data acquisition and output circuit for signal interaction of a real-time simulator, including an acquisition end, an output end, an acquisition signal processing unit, an output signal processing unit, a real-time simulator, an FPGA, a DSP, and an Ethernet control circuit.

[0051] This invention amplifies and filters the acquired analog and digital signals, converts them into digital signals using a high-speed ADC, and then transmits them to a real-time simulator via gigabit Ethernet. On the other hand, it transmits the digital signals output by the real-time simulator to a DSP via gigabit Ethernet, then outputs them to a DA converter via an FPGA, and after conditioning circuitry, it can output both digital and analog signals, thus solving the problem of mismatch between the real-time interaction signals between the all-digital real-time simulator and external signals.

[0052] The acquisition end includes analog signal acquisition terminals and data signal acquisition terminals; the output end includes analog signal output terminals and data signal output terminals; the acquisition end also includes a data storage module for storing sampled data; the transmission end also includes a data analysis module for processing and analyzing digital signals. The FPGA includes FPGA module 1, FPGA module 2, and FPGA module 3.

[0053] Furthermore, FPGA module 1 establishes a non-commutative weak control martingale space, groups the collected data into weak control martingales, and then performs weak boundedness identification; FPGA module 2 establishes a non-commutative martingale differential subordinate group class, and performs full boundedness identification on the running model and data in the real-time simulator after class labeling; FPGA module 3 establishes a non-commutative martingale asymmetric subordinate training set, and performs subordinate training on the above identification results according to the mean field linear quadratic optimal control algorithm. The training results are then sent to the host computer via Ethernet after passing through the output signal processing unit.

[0054] In the analog signal acquisition stage, compressed sensing technology is used to perform non-uniform random sampling. The specific steps are as follows: analyze the sparse representation basis and related statistical characteristics of the input signal; determine the non-uniform random sampling mode based on the analysis results; design a compressed sensing sampling circuit to perform sampling and retain the sampling parameters; and then reconstruct the original signal using a compressed sensing algorithm.

[0055] The acquisition terminal connects to the acquisition signal processing unit; the acquisition signal processing unit connects to the FPGA; the FPGA connects to the output signal processing unit; the FPGA and DSP are interconnected; the DSP and Ethernet control circuit are interconnected; the Ethernet control circuit and real-time simulator are interconnected; and the output signal processing unit connects to the output terminal. The digital signal output by the real-time simulator is transmitted to the FPGA via Gigabit Ethernet controlled by the DSP. The FPGA distinguishes the signal type, demodulates the analog signal data packets, and sends them to the DAC via the transmitter. After amplification and filtering, the signal is output to the analog signal terminal. Simultaneously, the FPGA demodulates the digital signal data packets, passes them through a protection circuit, and outputs them to the digital signal terminal.

[0056] Preferably, the specific steps of FPGA module 1 include: based on the signal characteristics of the controlled object of the real-time simulator, let H be a given sinusoidal distribution finite space, B(H) denote the set of all bounded operators on H, let M be a subalgebra of B(H) with a finite, normal, and faithful trace τ, and let α be a positive dense definite operator on H. If the unitary operator u in the commutator M' of M satisfies u×αu=α, then α is said to be attached to M. If for any acquired data ε i >0, there exists a projection e i Make τ i (1–e i )<ε i ,(i=1,2,…n), where n is the number of samples, then X={τ i Let {i, (i = 1, 2, ..., n)} be the space of non-commutative weakly controlled martingales, and M' be a control martingale. If the inequality is satisfied:

[0057] ||X||α=cscM≤||M′||u=||{e i}|| 0≤i≤n {ε i ,0≤i≤n}

[0058] Then ε i For weakly bounded conditions, use δ A This represents the dataset. If it satisfies the condition, it is strongly bounded. We use δ1 to represent this dataset.

[0059] The specific steps of FPGA module 2 include: letting F be the model state variable in the real-time simulator model, (F... i ) n ≤0 is a sequence of non-subtractive subalgebras of F, if it satisfies

[0060] P(sup|F i |≥1)≤2||∝||

[0061] Then it will satisfy ε i <|F i |ε iFall into the class of non - commutative martingale differential subordination groups, ε i >|F i | of ε i Fall into the class of non - commutative martingale non - differential subordination groups;

[0062] The analog quantity ω to be processed in the real - time simulator j The set is {ω j (0 < j < m), m is the total number of analog quantities, the digital quantity δ k The set satisfies {δ k (0 < k < l), where l is the total number of digital quantities. If it satisfies

[0063]

[0064] Then ω j 、δ k Have complete boundedness, use V A To represent this data set; conversely, have complete unboundedness and use V B To represent this data set.

[0065] The specific steps of the FPGA module 3 include,

[0066] Train the data set through the following formula to obtain the K1 training set:

[0067]

[0068] Finally, obtain the output signal set through the mean - field linear - quadratic optimal control algorithm:

[0069]

[0070] Among them, δ A 、δ1 are data sets.

[0071] The signal acquisition and processing unit includes an amplifier circuit, a filter circuit, and a DC compensation circuit, which are used to perform gain, denoising, and reducing DC offset processing on the signals to be sampled.

[0072] The data transmission rate between the acquisition end and the sending end through Gigabit Ethernet is 10 Gbps, which can perform high - speed and stable data transmission;

[0073] The data acquisition output circuit for real - time simulator signal interaction uses ±15V voltage as the driving voltage and communicates with the upper computer through Gigabit Ethernet;

[0074] Use the TMS320F28335 chip as the core to design an analog and digital signal acquisition circuit with higher precision and stronger stability. There are 20 analog signal acquisition channels and output channels, and 64 digital signal acquisition channels and output channels in the circuit.

[0075] Furthermore, this circuit uses the EP3C5E144I7 chip (the model number of the FPGA) as the core to build a signal acquisition circuit (including digital signal acquisition and analog signal acquisition). Since the EP3C5E144I7 chip processes digital signals, analog signals need to be converted into digital signals by AD converter before being sent to the chip.

[0076] The analog signal voltage range is ±10V, and the digital signal 0 corresponds to 0V and 1 corresponds to 5V. The circuit takes into account overvoltage protection and reverse breakdown protection.

[0077] The circuit uses a PCB with a six-layer design. The top, second, and third layers are the signal trace layers for the TMS320F28335 chip, effectively shielding noise interference and ensuring consistent signal delay. To ensure all signals are at the same distance from the power supply, the fourth layer is designed as the power layer, the fifth layer is designed as the trace layer for the TMS320F28335 chip and other signals, and the sixth layer is the ground layer.

[0078] Furthermore, the signal acquisition of the present invention can also be applied to distributed signal acquisition, where multiple acquisition ends transmit sampled data to a single transmitter via gigabit Ethernet for processing and analysis; the acquisition output of the present invention can be applied to the hardware-in-the-loop system of a digital real-time simulator.

[0079] This embodiment also provides a data acquisition and output method for signal interaction in a real-time simulator, including:

[0080] S1: Signal preprocessing at the signal acquisition end.

[0081] The acquisition end processes the signal to be sampled through the acquisition signal processing unit, including amplifier circuits, filter circuits and DC compensation circuits, which can perform gain, noise reduction and DC offset reduction on the signal to be sampled to ensure the accuracy and precision of the sampling results.

[0082] S2: Converted into a digital signal via a high-speed ADC.

[0083] S3: Transmit the data to the sending end.

[0084] Preferably, the acquired signal is packaged into data by the DSP, and the data is transmitted to the real-time simulator via the gigabit Ethernet controlled by the DSP. Using the existing Ethernet interface of the real-time simulator for data transmission can effectively reduce the burden of adding additional hardware interfaces.

[0085] S4: Decoding and synchronization operations restore the original signal.

[0086] The process of decoding and synchronizing to restore the original signal is as follows: The transmitting end transmits the digital signal packet from the real-time emulator to the Ethernet port. The DSP unpacks and demodulates the data packet and transmits it to the FPGA for software filtering. The data is then output to the DAC for filtering and amplification, and finally connected to external hardware through the output signal terminal.

[0087] Example 2

[0088] Reference Figures 2 to 17 This is the second embodiment of the present invention. Based on the first embodiment, in order to verify its beneficial effects, the circuit diagram and related description of the present invention are provided.

[0089] like Figure 2 The diagram shows the 5V to 1.9V power conversion circuit of the AMS1117-1.8 chip, which converts the 5V input voltage to the 1.9V output voltage. Its main function is to provide a stable operating voltage for the DSP chip TMS320F28335.

[0090] like Figure 3 The diagram shows a power IC design using the LM2596-5.0 chip. The LM2596-5.0 is a DC-DC step-down regulator power chip whose main function is to convert the input voltage into a stable, lower output voltage.

[0091] like Figure 4 It uses the LM1084IS-3.3V chip, which is a linear regulator. The main features of this chip include high precision, high efficiency, and low noise. Its function is to provide a stable and reliable DC power output. It can convert a 5V input voltage into a lower, fixed 3.3V output voltage through its internal voltage regulation circuit to meet the power supply requirements of the design.

[0092] like Figure 5 This design utilizes the AMS1117-1.2 and AMS1117-2.5 chips, which are linear regulators with multiple protection functions such as overheat protection and short-circuit protection, ensuring the system will not malfunction or be damaged during long-term operation. Its main function is to convert a 5V input voltage (DC) into stable 1.2V and 2.5V output voltages. Through power supply filtering and circuit feedback control, the output voltage is maintained at a fixed and accurate level.

[0093] like Figure 6 This is the circuit design of the AD7606 chip. Its pins are connected to the external circuit of the core FPGA chip EP4CE10E22I7N and the signal amplification circuit of the LM224 chip. The AD7606 enables the 16-bit data bus to interface with the microprocessor.

[0094] like Figure 7 It is a signal amplification circuit. The LM224 amplifier circuit has many advantages: very low noise level, excellent performance in high-sensitivity signal processing scenarios such as audio; wide bandwidth range, which can support many audio signal processing applications; and relatively low distortion rate during amplification, which makes the generated signal more accurate and clear.

[0095] like Figure 8 It is a 64-channel digital signal output interface; such as Figure 9 , 10 11 is the power supply filter circuit; such as Figure 12 It is a reset circuit.

[0096] like Figure 13 It is a network module design. The W5300 chip is a gigabit Ethernet physical layer transceiver chip. It mainly works at the physical layer of Ethernet communication, communicates with the host computer, helps the computer to convert and transmit digital signals to analog signals, and converts analog signals back into digital signals to be transmitted to the computer.

[0097] like Figure 14 - Figure 16 This design provides pinout design information for the EP4CE10E22I7N FPGA module. This chip contains modules such as a digital signal processing unit, input / output unit, and clock management unit. Through this design, various digital signal processing and control logic can be implemented.

[0098] like Figure 17 The TMS320F28335 DSP module features a pinout design. This processor integrates a high-speed 32-bit RISC central processing unit (CPU) and various peripheral modules, such as analog-to-digital converters (ADCs), external device interfaces (SPI, UART, etc.), and general-purpose timers / counters (GPTs), providing powerful control, communication, and data processing capabilities.

[0099] This invention enables gigabit Ethernet interaction with a real-time simulator, achieving an actual data transmission rate of 59 Gbit per minute; sampling accuracy reaches 0.12%, and data accuracy reaches 99%.

[0100] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A data acquisition and output circuit for signal interaction in a real-time simulator, characterized in that: include: Acquisition terminal, output terminal, acquisition signal processing unit, output signal processing unit, real-time simulator, FPGA, DSP and Ethernet control circuit; The acquisition terminal includes an analog signal acquisition terminal and a data signal acquisition terminal; the output terminal includes an analog signal output terminal and a data signal output terminal. The FPGA includes FPGA module 1, FPGA module 2 and FPGA module 3; The FPGA module 1 establishes a non-commutative weak control martingale space, and performs weak boundedness identification on the collected data after grouping it into weak control martingales. The FPGA module 2 establishes a non-commutative martingale differential subordinate group class, and performs full boundedness identification on the running model and data in the real-time simulator after class labeling. The FPGA module 3 establishes a non-commutative martingale asymmetric subordinate training set, performs subordinate training on the above identification results using the mean field linear quadratic optimal control algorithm, and sends the training results to the host computer via Ethernet after passing through the output signal processing unit. The acquisition terminal is connected to the acquisition signal processing unit; the acquisition signal processing unit is connected to the FPGA; the FPGA is connected to the output signal processing unit; the FPGA and the DSP are interconnected; the DSP and the Ethernet control circuit are interconnected; the Ethernet control circuit and the real-time simulator are interconnected; and the output signal processing unit is connected to the output terminal.

2. The data acquisition and output circuit for real-time simulator signal interaction as described in claim 1, characterized in that: The digital signal acquired by the acquisition terminal is input to the protection circuit and the limiting circuit. The data is packaged by the DSP and controlled by the gigabit Ethernet. The packaged data is then transmitted to the real-time simulator through the sending terminal. The digital signal output by the real-time simulator is transmitted to the FPGA via gigabit Ethernet controlled by the DSP. The FPGA distinguishes the signal type, demodulates the analog signal data packets, and sends them to the DAC through the transmitter. After amplification and filtering, the signal is output to the analog signal terminal. Meanwhile, the FPGA demodulates the digital signal data packets and outputs them to the digital signal terminals after passing through the protection circuit.

3. The data acquisition and output circuit for real-time simulator signal interaction as described in claim 2, characterized in that: The specific steps of the FPGA module 1 include, Based on the signal characteristics of the controlled object in a real-time simulator, let H be a given sinusoidal finite space, B(H) denote the set of all bounded operators on H, let M be a subalgebra of B(H) with a finite, normal, and faithful trace τ, and let α be a positive dense definite operator on H. If the unitary operator u in the commutator M' of M satisfies u × αu = α, then α is said to be attached to M. If for any acquired data ε i >0, there exists a projection e i Make τ i (1–e i If ) < εi, and n is the number of samples, then X = {τ} i Let} be a noncommutative weakly controlled martingale space, and M' be a control martingale, if the inequality is satisfied: ‖X‖α=cscM≤‖M′‖u=‖{e i }‖ 0≤i≤n {e} i ,0≤i≤n} Then εi is weakly bounded, using δ A The dataset is denoted by δ1 if it does not satisfy the condition that it is strongly bounded.

4. The data acquisition and output circuit for real-time simulator signal interaction as described in claim 3, characterized in that: The specific steps of the FPGA module 2 include: Let F be the model state variable in the real-time simulator model, (F i ) n ≤0 is a sequence of non-subtractive subalgebras of F, if it satisfies P(sup|F i |≥1)≤2‖∝‖ Then it will satisfy ε i <|F i |ε i Classified into the noncommutative martingale differential subgroup class, ε i >|F i |ε i Classified into the class of non-commutative martingale non-differential subgroups; The analog quantity ω to be processed in the real-time emulator j The set is {ω j , (0 < j < m)}, where m is the total number of analog quantities, and the digital quantity δ k The set satisfies {δ k , (0 < k < l)}, where l is the total number of digital quantities. If it satisfies Then ωj, δ k It has complete boundedness, using V A This represents the dataset; otherwise, it is completely unbounded, represented by V. B This represents the dataset.

5. The data acquisition and output circuit for real-time simulator signal interaction as described in claim 4, characterized in that: The specific steps of the FPGA module 3 include: The dataset is trained to obtain the K1 training set using the following formula: Finally, the output signal set is obtained through the mean-field linear quadratic optimal control algorithm: Where, δ A δ1 represents the dataset.

6. The data acquisition and output circuit for real-time simulator signal interaction as described in claim 5, characterized in that: The acquisition end also includes a data storage module for storing sampled data; the transmission end also includes a data analysis module for processing and analyzing digital signals. The signal processing unit includes an amplifier circuit, a filter circuit, and a DC compensation circuit, which are used to perform gain, noise reduction, and DC offset reduction processing on the signal to be sampled.

7. The data acquisition and output circuit for real-time simulator signal interaction as described in claim 6, characterized in that: The acquisition end and the transmission end transmit data at a rate of 10Gbps via gigabit Ethernet, enabling high-speed and stable data transmission. The data acquisition and output circuit for real-time simulator signal interaction uses ±15V voltage as the driving voltage and communicates with the host computer via gigabit Ethernet. The TMS320F28335 chip is used as the core to design a high-precision and stable analog and digital signal acquisition circuit. The circuit has 20 analog signal acquisition channels and 20 output channels, and 64 digital signal acquisition channels and 64 output channels. A PCB is used, and the PCB adopts a six-layer board design; The signal sampling rate is 1 GHz using a high-speed ADC.

8. A data acquisition and output method for signal interaction in a real-time simulator, based on the data acquisition and output circuit for signal interaction in a real-time simulator as described in any one of claims 1 to 7, characterized in that: It also includes, Signal preprocessing at the signal acquisition end; Converted into digital signals via a high-speed ADC; Transmit the data to the sending end; Decoding and synchronization operations restore the original signal.

9. The data acquisition and output method for signal interaction in a real-time simulator as described in claim 8, characterized in that: The acquisition end processes the signal to be sampled through the acquisition signal processing unit, which includes an amplifier circuit, a filter circuit and a DC compensation circuit. The acquisition end performs gain, noise reduction and DC offset reduction processing on the signal to be sampled to ensure the accuracy and precision of the sampling results.

10. The data acquisition and output method for signal interaction in a real-time simulator as described in claim 9, characterized in that: The process of restoring the original signal through decoding and synchronization is as follows: The transmitter sends digital signal packets from the real-time emulator to the Ethernet port. The DSP unpacks and demodulates the data packets before transmitting them to the FPGA for software filtering. The data is then output to the DAC for filtering and amplification, and finally connected to external hardware via the output signal terminal.

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