Semiconductor device and process for making a semiconductor device

Abstract

The application discloses a semiconductor device and a process manufacturing method of the semiconductor device, relates to the technical field of semiconductors, and discloses a NAND gate circuit, which comprises a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube. The first NMOS tube and the second NMOS tube are connected in parallel and are located between the first PMOS tube and a substrate. The first PMOS tube and the second PMOS tube are connected in series and are stacked in a direction perpendicular to the substrate. In the NAND gate circuit provided in the application, the plurality of MOS tubes can be stacked in the direction perpendicular to the substrate, so that the area of the NAND gate circuit on the substrate can be reduced, and the microscale of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating a semiconductor device. Background Technology

[0002] CMOS (Complementary Metal Oxide Semiconductor) NOR gates are a common type of logic circuit used to implement NOR operations. They are often used in processors or memory and consist of two NMOS transistors (NMOS-FET, Electronic Metal Oxide Semiconductor Field Effect Transistor) connected in parallel and two PMOS transistors (PMOS-FET, Hole Metal Oxide Semiconductor Field Effect Transistor) connected in series.

[0003] In pursuit of higher device density or product integration, the size of logic circuits is constantly shrinking. The manufacturing of NMOS and PMOS transistors in current CMOS NOR gates needs further miniaturization. Summary of the Invention

[0004] This application provides a semiconductor device and a method for fabricating the semiconductor device, which can effectively further miniaturize semiconductor devices.

[0005] In a first aspect, a semiconductor device is provided, including a NOR gate circuit comprising: a first NMOS transistor 1, a second NMOS transistor 2, a first PMOS transistor 3, and a second PMOS transistor 4. The first NMOS transistor 1 and the second NMOS transistor 2 are connected in parallel and located between the first PMOS transistor 3 and a substrate. The first PMOS transistor 3 and the second PMOS transistor 4 are connected in series and stacked in a direction perpendicular to the substrate.

[0006] In one possible implementation, the first NMOS transistor 1 and the second NMOS transistor 2 are spaced apart on the substrate along a direction parallel to the substrate.

[0007] In one possible implementation, the first NMOS transistor 1 includes a first source 11, a first drain 12 and a first channel layer 13, and the second NMOS transistor 2 includes a second source 21, a second drain 22 and a second channel layer 23.

[0008] The first source 11, the first drain 12, and the first channel layer 13 are stacked in a direction perpendicular to the substrate, and the first channel layer 13 is located between the first source 11 and the first drain 12. The second source 21, the second drain 22, and the second channel layer 23 are stacked in a direction perpendicular to the substrate, and the second channel layer 23 is located between the second source 21 and the second drain 22.

[0009] In one possible implementation, the first NMOS transistor 1 includes a first gate 14 and a first gate insulating layer 15, and the second NMOS transistor 2 includes a second gate 24 and a second gate insulating layer 25.

[0010] The first gate 14 extends in a direction perpendicular to the substrate. The first source 11, the first drain 12, and the first channel layer 13 surround different regions of the sidewall of the first gate 14 and are insulated from the first gate 14 by the first gate insulating layer 15. The second gate 24 extends in a direction perpendicular to the substrate. The second source 21, the second drain 22, and the second channel layer 23 surround different regions of the sidewall of the second gate 24 and are insulated from the second gate 24 by the second gate insulating layer 25.

[0011] In one possible implementation, the first source 11 and the second source 21 are located on the first N-type semiconductor layer. The first drain 12 and the second drain 22 are located on the second N-type semiconductor layer.

[0012] In one possible implementation, the first channel layer 13 and the second channel layer 23 are located on a P-type semiconductor layer.

[0013] In one possible implementation, the first PMOS transistor 3 includes a third source 31, a third drain 32, a third channel layer 33, a third gate 34, and a third insulating layer 35, and the second PMOS transistor 4 includes a fourth source 41, a fourth drain 42, a fourth channel layer 43, a fourth gate 44, and a fourth insulating layer 45. The third source 31, the third drain 32, and the third channel layer 33 are located on a first P-type semiconductor extending perpendicular to the substrate, and the third gate 34 surrounds the first P-type semiconductor and is insulated from the first P-type semiconductor through the third insulating layer 35. The fourth source 41, the fourth drain 42, and the fourth channel layer 43 are located on a second P-type semiconductor extending perpendicular to the substrate, and the fourth gate 44 surrounds the second P-type semiconductor and is insulated from the second P-type semiconductor through the fourth insulating layer 45.

[0014] In one possible implementation, the first P-type semiconductor and the second P-type semiconductor are different portions of a third P-type semiconductor that extends perpendicularly to the substrate.

[0015] In one possible implementation, the third insulating layer 35 includes a first gate oxide layer 351 and a first silicon dioxide layer 352, with the first silicon dioxide layer 352 located between the first gate oxide layer 351 and the first P-type semiconductor. The fourth insulating layer 45 includes a second gate oxide layer 451 and a second silicon dioxide layer 452, with the second silicon dioxide layer 452 located between the second gate oxide layer 451 and the second P-type semiconductor.

[0016] In one possible implementation, the third gate 34 has a plate-like structure, is parallel to the substrate, and is connected to one of the gates of the first gate 14 and the second gate 24. The fourth gate 44 has a plate-like structure, is parallel to the substrate, and is connected to the other gate of the first gate 14 and the second gate 24.

[0017] In one possible implementation, the side of the first N-type semiconductor that is away from and parallel to the substrate is connected to an electrode, which extends perpendicular to the first N-type semiconductor layer and is connected to the output of an NOR gate.

[0018] In one possible implementation, one end of the third P-type semiconductor is connected to the power supply terminal of the NOR gate, and the other end of the third P-type semiconductor is connected to the first source 11 and the second source 21.

[0019] In one possible implementation, the first gate 14 is connected to one input of the NOR gate circuit, and the second gate 24 is connected to the other input of the NOR gate circuit.

[0020] In a second aspect, a semiconductor device is provided, including a NOR gate circuit, which comprises: a P-type semiconductor layer 51, a first N-type semiconductor layer 52, a second N-type semiconductor layer 53, two first electrodes 54, a first insulating layer 55, a P-type semiconductor 61, two second electrodes 62, and a second insulating layer 63.

[0021] P-type semiconductor layer 51, first N-type semiconductor layer 52 and second N-type semiconductor layer 53 are stacked sequentially in a direction perpendicular to the substrate. Two first electrodes 54 pass through P-type semiconductor layer 51, first N-type semiconductor layer 52 and second N-type semiconductor layer 53 respectively, and are insulated from P-type semiconductor layer 51, first N-type semiconductor layer 52 and second N-type semiconductor layer 53 respectively through first insulating layer 55.

[0022] One end of the P-type semiconductor 61 is connected to the second N-type semiconductor layer 53. The two second electrodes 62 surround different regions of the sidewall of the P-type semiconductor 61 and are insulated from the P-type semiconductor 61 by the second insulating layer 63.

[0023] In one possible implementation, the P-type semiconductor 61 extends in a direction perpendicular to the substrate.

[0024] In one possible implementation, the two second electrodes 62 are perpendicular to the P-type semiconductor 61.

[0025] In one possible implementation, two first electrodes 54 extend in a direction perpendicular to the substrate, and each first electrode 54 is connected to a second electrode 62.

[0026] In one possible implementation, the two first electrodes 54 are respectively connected to the two input terminals of the NOR gate circuit, and the other end of the P-type semiconductor 61 is connected to the power supply terminal of the NOR gate circuit.

[0027] In one possible implementation, the second insulating layer 63 includes a third gate oxide layer 631 and a third silicon dioxide layer 632, wherein the third silicon dioxide layer 632 is located between the third gate oxide layer 631 and the P-type semiconductor 61.

[0028] In one possible implementation, the NOR gate circuit further includes a third electrode 71, which extends in a direction perpendicular to the substrate. One end of the third electrode 71 is connected to the second N-type semiconductor layer 53, and the other end is connected to the output terminal of the NOR gate circuit.

[0029] Thirdly, a method for fabricating a semiconductor device is provided, the semiconductor device including a NOR gate circuit, the method comprising:

[0030] Three epitaxial layers 81 are sequentially grown on a silicon substrate. Two first vias 82 penetrating the three epitaxial layers 81 are etched in different regions of the third epitaxial layer 81. A first insulating layer 83 is deposited on the sidewalls of the two first vias 82. A fourth electrode 84 is filled in the two first vias 82 with the first insulating layer 83. The three epitaxial layers 81, from bottom to top, are a heavily doped epitaxial electrode, a lightly doped epitaxial semiconductor, and a heavily doped epitaxial electrode. On the side of the three epitaxial layers 81 away from the silicon substrate, two insulating epitaxial electrodes 91 are sequentially grown. A second via 92 penetrating the two epitaxial electrodes 91 is etched in the two epitaxial electrodes 91. A second insulating layer 93 is deposited on the sidewalls of the second vias 92. A P-type semiconductor 94 is filled in the second vias 92 with the second insulating layer 93.

[0031] In one possible implementation, two insulating epitaxial electrodes 91 are sequentially epitaxially grown on the side of the three-layer film (81) away from the silicon substrate, including: epitaxially growing a third insulating layer 95 on the side of the three-layer film (81) away from the silicon substrate, and epitaxially growing a first epitaxial electrode 91 on the third insulating layer 95; etching a first region of the first epitaxial electrode 91 until the third insulating layer 95 is exposed, wherein the projection of the first region on the silicon substrate overlaps with the projection of one of the two first vias 82 on the silicon substrate; epitaxially growing a fourth insulating layer 96 on the first epitaxial electrode 91, and epitaxially growing a second epitaxial electrode 91 on the fourth insulating layer 96; etching a second region of the second epitaxial electrode 91 until the fourth insulating layer 96 is exposed, wherein the projection of the second region on the silicon substrate overlaps with the projection of the other of the two first vias 82 on the silicon substrate; and epitaxially growing a fifth insulating layer 97 on the second epitaxial electrode 91.

[0032] In one possible implementation, after epitaxially growing the fifth insulating layer 97 on the second epitaxial electrode 91, the method further includes: etching from a third region of the fifth insulating layer 97 along a direction perpendicular to the silicon substrate to form a third via 98 penetrating the fifth insulating layer 97, the fourth insulating layer 96, the first epitaxial electrode 91, and the third insulating layer 95; etching from a fourth region of the fifth insulating layer 97 along a direction perpendicular to the silicon substrate to form a fourth via 99 penetrating the fifth insulating layer 97, the second epitaxial electrode 91, the fourth insulating layer 96, and the third insulating layer 95, wherein the orthographic projections of the third and fourth regions on the silicon substrate overlap with the orthographic projections of the first and second regions on the silicon substrate, respectively; filling the third via 98 with a fifth electrode 910, and filling the fourth via 99 with a sixth electrode 911.

[0033] In one possible implementation, after epitaxially growing the fifth insulating layer 97 on the second epitaxial electrode 91, the method further includes: etching from the fifth region of the fifth insulating layer 97 along a direction perpendicular to the silicon substrate to form a fifth via 912 penetrating the fifth insulating layer 97, the fourth insulating layer 96, and the third insulating layer 95; and filling the fifth via 912 with a seventh electrode 913, which is the output terminal of a NOR gate circuit.

[0034] In one possible implementation, the second insulating layer 93 includes a gate oxide layer 931 and a silicon dioxide layer 932; depositing the second insulating layer 93 on the sidewall of the second via 92 includes: depositing the gate oxide layer 931 on the sidewall of the second via 92; and depositing the silicon dioxide layer 932 on the sidewall of the gate oxide layer 931.

[0035] In one possible implementation, after filling the fifth electrode 910 in the third via 98, the method further includes: depositing an eighth electrode 914 on the fifth electrode 910, the eighth electrode 914 being the first input terminal of a NOR gate circuit; after filling the sixth electrode 911 in the fourth via 99, the method further includes: depositing a ninth electrode 915 on the sixth electrode 911, the ninth electrode 915 being the second input terminal of a NOR gate circuit.

[0036] In one possible implementation, after filling the second via 92 with a P-type semiconductor 94, the method further includes depositing a tenth electrode 916 on the P-type semiconductor 94, wherein the tenth electrode 916 is the power supply terminal of a NOR gate circuit.

[0037] Fourthly, a memory is provided, comprising a semiconductor device as provided in the first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect.

[0038] Fifthly, an electronic device is provided, comprising at least in part a semiconductor device provided as in the first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect.

[0039] In one possible implementation, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or smart mobile terminal.

[0040] The beneficial effects of the technical solutions provided in this application include at least the following:

[0041] In the semiconductor device provided in the embodiments of this application, the NOR gate circuit includes two PMOS transistors stacked in a direction perpendicular to the substrate, and the two PMOS transistors are also stacked on top of two NMOS transistors in a direction perpendicular to the substrate. By stacking the PMOS transistors and NMOS transistors in the NOR gate circuit in this way, device miniaturization can be further achieved, and product integration can be improved. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of a CMOS NOR gate logic circuit;

[0043] Figure 2 This is an enlarged schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0044] Figure 3 This is a schematic diagram of the structure of an NMOS transistor provided in an embodiment of this application;

[0045] Figure 4 This is a schematic diagram of a parallel NMOS transistor structure provided in an embodiment of this application;

[0046] Figure 5 This is a schematic diagram of a parallel NMOS transistor structure provided in an embodiment of this application;

[0047] Figure 6 This is a schematic diagram of a PMOS transistor provided in an embodiment of this application;

[0048] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0049] Figure 8 This is a flowchart illustrating a semiconductor device fabrication method provided in an embodiment of this application;

[0050] Figure 9 This is a schematic diagram of a semiconductor device manufacturing process provided in an embodiment of this application;

[0051] Figure 10 This is a schematic diagram of a semiconductor device manufacturing process provided in an embodiment of this application;

[0052] Figure 11 This is a schematic diagram of a semiconductor device manufacturing process provided in an embodiment of this application;

[0053] Figure 12 This is a schematic diagram of a semiconductor device manufacturing process provided in an embodiment of this application;

[0054] Figure 13 This is a schematic diagram of a semiconductor device manufacturing process provided in an embodiment of this application;

[0055] Figure 14 This is a schematic diagram of a semiconductor device manufacturing process provided in an embodiment of this application;

[0056] Figure 15 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0057] Illustration:

[0058] 1. First NMOS transistor; 11. First source; 12. First drain; 13. First channel layer; 14. First gate; 15. First gate insulating layer;

[0059] 2. Second NMOS transistor; 21. Second source; 22. Second drain; 23. Second channel layer; 24. Second gate; 25. Second gate insulating layer;

[0060] 3. First PMOS transistor; 31. Third source; 32. Third drain; 33. Third channel layer; 34. Third gate; 35. Third insulating layer; 351. First gate oxide layer; 352. First silicon dioxide layer;

[0061] 4. Second PMOS transistor; 41. Fourth source; 42. Fourth drain; 43. Fourth channel layer; 44. Fourth gate; 45. Fourth insulating layer; 451. Second gate oxide layer; 452. First silicon dioxide layer;

[0062] 51. P-type semiconductor layer; 52. First N-type semiconductor layer; 53. Second N-type semiconductor layer; 54. First electrode; 55. First insulating layer;

[0063] 61. P-type semiconductor; 62. Two second electrodes; 63. Second insulating layer; 631. Third gate oxide layer; 632. Third silicon dioxide layer;

[0064] 71. Third electrode;

[0065] 81. Three-layer film; 82. First through-hole; 83. First insulating layer; 84. Fourth electrode;

[0066] 91. Epitaxial electrode; 92. Second via; 93. Second insulating layer; 931. Gate oxide layer; 932. Silicon dioxide layer; 94. P-type semiconductor; 95. Third insulating layer; 96. Fourth insulating layer; 97. Fifth insulating layer; 98. Third via; 99. Fourth via; 910. Fifth electrode; 911. Sixth electrode; 912. Fifth via; 913. Seventh electrode; 914. Eighth electrode; 915. Ninth electrode; 916. Tenth electrode. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0068] Figure 1This is a schematic diagram of a CMOS NOR gate logic circuit. The CMOS NOR gate includes two PMOS transistors (P1 and P2) connected in series and two NMOS transistors (N1 and N2) connected in parallel, with the two series-connected PMOS transistors and the two parallel-connected NMOS transistors connected in series. The source of one of the series-connected PMOS transistors is connected to the power supply (VDD) of the CMOS NOR gate, and the drain of the other PMOS transistor is connected to the sources of both parallel NMOS transistors, and then to the output of the CMOS NOR gate. Of the four MOS transistors, the gates of one PMOS transistor and one NMOS transistor are connected to one input (input1) of the CMOS NOR gate, and the gates of the other PMOS transistor and the other NMOS transistor are connected to the other input (input2) of the CMOS NOR gate.

[0069] The circuit logic of a CMOS NOR gate is as follows: when either input1 or input2 is at a "1" level, the output is at a "0" level; when both input1 and input2 are at a "0" level, the output is at a "1" level.

[0070] Figure 2 This application provides one implementation such as Figure 1 The diagram shows the structure of the semiconductor device used in the logic circuit.

[0071] like Figure 2 As shown, the CMOS NOR gate circuit includes: a first NMOS transistor 1, a second NMOS transistor 2, a first PMOS transistor 3, and a second PMOS transistor 4. The first NMOS transistor 1 and the second NMOS transistor 2 are connected in parallel and located between the first PMOS transistor 3 and the substrate, and can be spaced apart on the substrate along a direction parallel to the substrate. The first PMOS transistor 3 and the second PMOS transistor 4 are connected in series and stacked in a direction perpendicular to the substrate.

[0072] In this configuration, the first NMOS transistor 1 and the second NMOS transistor 2 connected in parallel can be channel-around field-effect transistors (FETs). The first PMOS transistor 3 and the second PMOS transistor 4 connected in series can be gate-around field-effect transistors (FETs). For example... Figure 2As shown, the first PMOS transistor 3 and the second PMOS transistor 4, connected in series, are stacked in a direction perpendicular to the substrate, and are also stacked on top of two parallel first NMOS transistors 1 and 2 along the same direction perpendicular to the substrate. In this way, in the CMOS NOR gate circuit, only the first NMOS transistors 1 and 2 occupy the substrate area, thereby reducing the substrate area occupied by the CMOS NOR gate circuit and enabling the miniaturization of semiconductor devices. Furthermore, stacking the PMOS and NMOS transistors in the CMOS NOR gate circuit can further achieve the miniaturization of semiconductor devices and improve product integration.

[0073] Figure 3 This application Figure 2 The diagram shows an enlarged schematic of the NMOS transistor structure.

[0074] like Figure 3 As shown, the first NMOS transistor 1 includes a first source 11, a first drain 12, and a first channel layer 13. The first source 11, the first drain 12, and the first channel layer 13 are stacked in a direction perpendicular to the substrate, and the first channel layer 13 is located between the first source 11 and the first drain 12. The first source 11 and the first drain 12 can be N-type semiconductors, such as N++poly (heavily doped electron-type polysilicon). The first channel layer 13 can be a P-type semiconductor, such as P-type poly (hole-type polysilicon).

[0075] Similarly, the second NMOS transistor 2 includes a second source 21, a second drain 22, and a second channel layer 23. The second source 21, the second drain 22, and the second channel layer 23 are stacked in a direction perpendicular to the substrate, and the second channel layer 23 is located between the second source 21 and the second drain 22. The second source 21 and the second drain 22 can be N-type semiconductors, such as N++ poly. The second channel layer 23 can be a P-type semiconductor, such as P-type poly.

[0076] In one example, a first NMOS transistor 1 and a second NMOS transistor 2 may be spaced apart on the substrate along a direction parallel to the substrate, and the first source 11 of the first NMOS transistor 1 and the second source 21 of the second NMOS transistor 2 are electrically connected, for example, through electrodes. Figure 3 (Not shown in the image). The first drain 21 of the first NMOS transistor 1 is electrically connected to the second drain 22 of the second NMOS transistor 2. For example, the electrical connection is made through electrodes. Figure 3 (Not shown in the diagram). Thus, the first NMOS transistor 1 and the second NMOS transistor 2 can form two parallel NMOS transistors in a NOR gate circuit.

[0077] See also Figure 3The first NMOS transistor 1 includes a first gate 14 and a first gate insulating layer 15. The first gate 14 extends in a direction perpendicular to the substrate. The first source 11, the first drain 12 and the first channel layer 13 surround different regions of the sidewall of the first gate 14 and are insulated from the first gate 14 by the first gate insulating layer 15.

[0078] The first gate 14 is made of a conductive material, such as polysilicon or a metal electrode. The first gate 14 extends in a direction perpendicular to the substrate and may have a columnar structure. The first gate 14 penetrates the first source 11, the first drain 12, and the first channel layer 13, such that the first source 11, the first drain 12, and the first channel layer 13 respectively surround different regions of the sidewall of the first gate 14. The first gate insulating layer 15 is the gate oxide layer of the first NMOS transistor 1 and may be made of a gate dielectric material, such as High-K. The first gate insulating layer 15 is located between the first gate 14 and the first source 11, the first drain 12, and the first channel layer 13, and may have a tubular structure. The first source 11, the first drain 12, the first channel layer 13, the first gate 14, and the first gate insulating layer 15 can form a ring-channel device structure for the NMOS transistor.

[0079] The second NMOS transistor 2 includes a second gate 24 and a second gate insulating layer 25. The second gate 24 extends in a direction perpendicular to the substrate. The second source 21, the second drain 22 and the second channel layer 23 surround different regions of the sidewall of the second gate 24 and are insulated from the second gate 24 by the second gate insulating layer 25.

[0080] The second gate 24 is made of a conductive material, such as polysilicon or a metal electrode. The second gate 24 extends in a direction perpendicular to the substrate and may have a columnar structure. The second gate 24 penetrates the second source 21, the second drain 22, and the second channel layer 23, such that the second source 21, the second drain 22, and the second channel layer 23 respectively surround different regions of the sidewall of the second gate 24. The second gate insulating layer 25 is the gate oxide layer of the second NMOS transistor 2 and may be made of a gate dielectric material, such as High-K. The second gate insulating layer 25 is located between the second gate 24 and the second source 21, the second drain 22, and the second channel layer 23, and may have a tubular structure. The second source 21, the second drain 22, the second channel layer 23, the second gate 24, and the second gate insulating layer 25 can form a ring-channel NMOS transistor.

[0081] The first and second gates described above have the following characteristics: the gate extending along the substrate direction can be understood as having one main surface and two end faces. The main surface is the side surface of the gate, the shape of which conforms to the shape of the sidewall of the via where the gate is located. The extension direction of this side surface is generally approximately perpendicular to the substrate, and both end faces are approximately parallel to the substrate. Generally, the sidewall of the gate has only one extension direction, that is, there are no branches in the direction parallel to the substrate, and these branches serve as effective gates.

[0082] In another example, the first NMOS transistor and the second NMOS transistor can be stacked in a direction perpendicular to the substrate. The first source 11 of the first NMOS transistor 1 is electrically connected to the second source 21 of the second NMOS transistor 2, for example, through an electrode. The first drain 21 of the first NMOS transistor 1 is electrically connected to the second drain 22 of the second NMOS transistor 2. The first gate 14 and the second gate 24 can be insulated from each other by an insulating material. Thus, the first NMOS transistor 1 and the second NMOS transistor 2 can form two parallel NMOS transistors in a CMOS NOR gate circuit.

[0083] Figure 4 This is a schematic diagram of a parallel NMOS transistor structure provided in this application.

[0084] like Figure 4 As shown, the first source 11 and the second source 21 are located on the first N-type semiconductor layer. The first drain 12 and the second drain 22 are located on the second N-type semiconductor layer.

[0085] The first source 11 and the second source 21 can be integrally formed and located in different regions of the same N-type semiconductor layer, thereby enabling electrical connection between the first source 11 and the second source 21. This N-type semiconductor layer is composed of N-type semiconductors and can be referred to as the first N-type semiconductor layer. Alternatively, it can be understood that different regions of this first N-type semiconductor layer form two vias, and the entire first N-type semiconductor layer simultaneously surrounds one via and the other via, serving as both the first source 11 and the second source 21.

[0086] The first drain 12 and the second drain 22 can be integrally formed and located in different regions of the same N-type semiconductor layer, thereby enabling electrical connection between the first drain 12 and the second drain 22. This N-type semiconductor layer, composed of N-type semiconductors, can be referred to as a second N-type semiconductor layer. Alternatively, it can be understood that different regions of this second N-type semiconductor layer form two vias, and the entire second N-type semiconductor layer simultaneously surrounds one via and the other via, serving as both the first drain 12 and the second drain 22.

[0087] Thus, the first source 11 and the second source 21 are located on the first N-type semiconductor layer, and the first drain 12 and the second drain 22 are located on the second N-type semiconductor layer, which can realize the parallel connection of two NMOS transistors in CMOS NOR gate circuits and facilitate the processing of two NMOS transistors.

[0088] Figure 5 This is a schematic diagram of a parallel NMOS transistor structure provided in this application.

[0089] like Figure 5 As shown, in Figure 4 Based on the structure shown, the first channel layer 13 and the second channel layer 23 can also be located on a P-type semiconductor layer.

[0090] The P-type semiconductor layer is composed of P-type semiconductors, with a first channel layer 13 and a second channel layer 23 located in different regions of the P-type semiconductor layer. Specifically, the first channel layer 13 is located in the region surrounding the first gate 14 of the P-type semiconductor layer, and the second channel layer 23 is located in the region surrounding the second gate 24 of the P-type semiconductor layer. Thus, the first channel layer 13 and the second channel layer 23 can be integrally formed, facilitating the processing of both layers.

[0091] In the CMOS NOR gate circuit provided in this application, the source, drain, and channel layers of the two NMOS transistors can be located in three semiconductor layers (a first N-type semiconductor layer, a second N-type semiconductor layer, and a P-type semiconductor layer), thereby forming two parallel NMOS transistors in the CMOS NOR gate circuit. This simplifies the connection structure between the two NMOS transistors and simplifies the fabrication steps.

[0092] Figure 6 This is a schematic diagram of the structure of a PMOS transistor provided in this application.

[0093] like Figure 6 As shown, the first PMOS transistor 3 includes a third source 31, a third drain 32, a third channel layer 33, a third gate 34, and a third insulating layer 35. The third source 31, the third drain 32, and the third channel layer 33 are located on a first P-type semiconductor that extends perpendicularly to the substrate. The third gate 34 surrounds the first P-type semiconductor and is insulated from the first P-type semiconductor by the third insulating layer 35.

[0094] The first PMOS transistor 3 is a junctionless field-effect transistor. The source, drain, and channel layer of the first PMOS transistor 3, namely the third source 31, third drain 32, and third channel layer 33, are located on the same P-type semiconductor, which can be called the first P-type semiconductor and can be made of P-type poly. The gate of the first PMOS transistor 3, namely the third gate 34, surrounds the middle region of the sidewall of the first P-type semiconductor. The portion of the first P-type semiconductor surrounded by the third gate 34 is the channel layer of the first PMOS transistor 3, namely the third channel layer 33. The remaining two portions of the first P-type semiconductor not surrounded by the third gate 34 are the source and drain of the first PMOS transistor 3, namely the third source 31 and third drain 32. The third insulating layer 35 is the gate oxide layer of the first PMOS transistor 3 and can be made of a gate dielectric material, such as High-K.

[0095] Similarly, the second PMOS transistor 4 includes a fourth source 41, a fourth drain 42, a fourth channel layer 43, a fourth gate 44, and a fourth insulating layer 45. The fourth source 41, the fourth drain 42, and the fourth channel layer 43 are located on a second P-type semiconductor that extends perpendicular to the substrate. The fourth gate 44 surrounds the second P-type semiconductor and is insulated from the second P-type semiconductor by the fourth insulating layer 45.

[0096] The second PMOS transistor 4 is a junctionless field-effect transistor. The source, drain, and channel layer of the second PMOS transistor 4, namely the fourth source 41, fourth drain 42, and fourth channel layer 43, are located on the same P-type semiconductor, which can be called a second P-type semiconductor and can be made of P-type poly. The gate of the second PMOS transistor 4, namely the fourth gate 44, surrounds the middle region of the sidewall of the second P-type semiconductor. The portion of the second P-type semiconductor surrounded by the fourth gate 44 is the channel layer of the second PMOS transistor 4, namely the fourth channel layer 43. The remaining two portions of the second P-type semiconductor not surrounded by the fourth gate 44 are the source and drain of the second PMOS transistor 4, namely the fourth source 4 and fourth drain 42. The fourth insulating layer 45 is the gate oxide layer of the second PMOS transistor 4 and can be made of a gate dielectric material, such as High-K.

[0097] The fourth source 41 of the second PMOS transistor 4 can be electrically connected to the power supply terminal of the CMOS NOR gate circuit. The drain of the second PMOS transistor 4 can be electrically connected to the third source 31 of the first PMOS transistor 3, thereby forming two PMOS transistors connected in series in the NOR gate circuit. The third drain 32 of the first PMOS transistor 3 can be electrically connected to the first source 11 of the first NMOS transistor 1 and the second source 21 of the second NMOS transistor 2, and electrically connected to the output terminal of the NOR gate circuit.

[0098] See also Figure 6The first P-type semiconductor and the second P-type semiconductor are different portions of a third P-type semiconductor extending perpendicularly to the substrate. That is, the source, drain, and channel layers corresponding to the first PMOS transistor 3 and the second PMOS transistor 4 are located in different regions on the side of the same P-type semiconductor extending along the vertical direction; this P-type semiconductor can be called the third P-type semiconductor. In this way, the first P-type semiconductor and the second P-type semiconductor can be integrally formed, enabling the series connection of two first PMOS transistors 3 and 4, simplifying the connection structure between the first PMOS transistors 3 and 4, and facilitating the fabrication of the first PMOS transistors 3 and 4. Similarly, the third insulating layer 35 and the fourth insulating layer 45, respectively surrounding the sidewalls of the first and second P-type semiconductors, can also be integrally formed for ease of fabrication.

[0099] See also Figure 6 The third insulating layer 35 includes a first gate oxide layer 351 and a first silicon dioxide layer 352, with the first silicon dioxide layer 352 located between the first gate oxide layer 351 and the first P-type semiconductor. The fourth insulating layer 45 includes a second gate oxide layer 451 and a second silicon dioxide layer 452, with the second silicon dioxide layer 452 located between the second gate oxide layer 451 and the second P-type semiconductor.

[0100] The first gate oxide layer 351 can be made of a High-K material. Adding a layer of silicon dioxide (i.e., the first silicon dioxide layer 352) between the first gate oxide layer 351 and the first P-type semiconductor can improve the control effect of the third source 31 on the first PMOS transistor 3. Similarly, the second gate oxide layer 451 can be made of a High-K material. Adding a layer of silicon dioxide (i.e., the second silicon dioxide layer 452) between the second gate oxide layer 451 and the second P-type semiconductor can improve the control effect of the fourth source 41 on the second PMOS transistor 4. The first gate oxide layer 351 and the second gate oxide layer 451 can be integrally formed, as can the first silicon dioxide layer 352 and the second silicon dioxide layer 452. This facilitates processing.

[0101] In one example, the third gate 34 has a plate-like structure, is parallel to the substrate, and is connected to one of the gates of the first gate 14 and the second gate 24. The fourth gate 44 has a plate-like structure, is parallel to the substrate, and is connected to the other gate of the first gate 14 and the second gate 24.

[0102] like Figure 1 As shown, the third gate 34 may have a plate-like structure. Figure 1(Only a cross-sectional view of the plate-like structure is shown in the diagram). The second gate 24 may have a columnar structure and may extend along a direction perpendicular to the substrate to contact the third gate 34, such as the second gate 24 passing through the third gate 34. This allows for the electrical connection of the gates of the second NMOS transistor 2 and the first PMOS transistor 3. Thus, one of the gates of the second gate 24 and the third gate 34 can be electrically connected to one input terminal of a NOR gate circuit. Similarly, the fourth gate 44 may have a plate-like structure ( Figure 1 (Only a cross-sectional view of the plate-like structure is shown in the diagram). The first gate 14 may have a columnar structure and may extend in a direction perpendicular to the substrate to contact the fourth gate 44, such as the first gate 14 passing through the fourth gate 44. This enables the electrical connection between the gates of the first NMOS transistor 1 and the second PMOS transistor 4.

[0103] See also Figure 1 An insulating substrate may be present on the side of the first N-type semiconductor away from the substrate. The third gate 34, third insulating layer 35, fourth gate 44, and fourth insulating layer 45 can all be located within this insulating substrate. The height of the insulating substrate perpendicular to the substrate can be the same as the height of the third P-type semiconductor in the direction perpendicular to the substrate. Thus, one end of the third P-type semiconductor can be exposed outside the insulating substrate, allowing for electrical connection to the power supply terminal of a NOR gate. The other end of the third P-type semiconductor is connected to the first N-type semiconductor containing the first source 11 and the second source 21, and subsequently connected in series with the first NMOS transistor and the second NMOS transistor.

[0104] See also Figure 1 The first gate 14 extends through the insulating substrate in a direction perpendicular to the substrate, such that the first gate 14 contacts and passes through the fourth gate 44, and one end of the first gate 14 is exposed outside the insulating substrate, thus allowing it to be electrically connected to an input terminal of a NOR gate circuit. Similarly, the second gate 24 extends through the insulating substrate in a direction perpendicular to the substrate, such that the second gate 24 contacts and passes through the third gate 34, and one end of the second gate 24 is exposed outside the insulating substrate, thus allowing it to be electrically connected to an input terminal of a NOR gate circuit.

[0105] See also Figure 1 An electrode can be epitaxially grown on the side of the first N-type semiconductor that is away from and parallel to the substrate. The electrode extends in a direction perpendicular to the first N-type semiconductor layer and can penetrate the insulating substrate, such that one end of the electrode is electrically connected to the first N-type semiconductor and the other end is connected to the output terminal of the NOR gate circuit.

[0106] It should be noted that in the first NMOS transistor 1, the second NMOS transistor 2, the first PMOS transistor 3, and the second PMOS transistor 4 provided in the embodiments of this application, the gate and source are relative terms. That is to say, the source and drain of the above four MOS transistors can be replaced. For example, the source of the above four MOS transistors can all be called the drain, and the drain of the above four MOS transistors can all be called the source.

[0107] In the semiconductor device provided in the embodiments of this application, the NOR gate circuit includes two PMOS transistors stacked in a direction perpendicular to the substrate, and the two PMOS transistors are also stacked on top of two NMOS transistors in a direction perpendicular to the substrate. By stacking the PMOS transistors and NMOS transistors in the NOR gate circuit in this way, the area occupied by the NOR gate circuit on the substrate can be reduced, enabling device miniaturization and improving product integration.

[0108] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in this application. The semiconductor device is a NOR gate circuit. Figure 7 As shown, the NOR gate circuit comprises: a P-type semiconductor layer 51, a first N-type semiconductor layer 52, a second N-type semiconductor layer 53, two first electrodes 54, a first insulating layer 55, a P-type semiconductor 61, two second electrodes 62, and a second insulating layer 63.

[0109] The P-type semiconductor layer 51, the first N-type semiconductor layer 52, the second N-type semiconductor layer 53, the two first electrodes 54, and the two first insulating layers 55 form two parallel NMOS transistors in the NOR gate circuit. The structure of the P-type semiconductor layer 51, the first N-type semiconductor layer 52, the second N-type semiconductor layer 53, the two first electrodes 54, and the two first insulating layers 55 is as follows:

[0110] like Figure 7 As shown, the P-type semiconductor layer 51, the first N-type semiconductor layer 52, and the second N-type semiconductor layer 53 are stacked sequentially in a direction perpendicular to the substrate. Two first electrodes 54 pass through the P-type semiconductor layer 51, the first N-type semiconductor layer 52, and the second N-type semiconductor layer 53, respectively, and are insulated from the P-type semiconductor layer 51, the first N-type semiconductor layer 52, and the second N-type semiconductor layer 53 by the first insulating layer 55, respectively.

[0111] The first electrode 54 extends through the P-type semiconductor layer 51, the first N-type semiconductor layer 52, and the second N-type semiconductor layer 53, and is insulated from the P-type semiconductor layer 51, the first N-type semiconductor layer 52, and the second N-type semiconductor layer 53 by the first insulating layer 55, thus forming an NMOS transistor with a ring-channel device structure. The first electrode 54 serves as the gate of the NMOS transistor and can be made of a conductive material, such as polysilicon. The first insulating layer 55 is the gate oxide layer of the NMOS transistor, the P-type semiconductor layer 51 is the channel layer of the NMOS transistor, and the first N-type semiconductor layer 52 and the second N-type semiconductor layer 53 are the source and drain of the NMOS transistor, respectively. Furthermore, two first electrodes 54 extend through the P-type semiconductor layer 51, the first N-type semiconductor layer 52, and the second N-type semiconductor layer 53, respectively, and are insulated from the P-type semiconductor layer 51, the first N-type semiconductor layer 52, and the second N-type semiconductor layer 53 by the first insulating layer 55, thus forming two parallel NMOS transistors in a NOR gate circuit.

[0112] The P-type semiconductor 61, the two second electrodes 62, and the second insulating layer 63 form two PMOS transistors connected in series in the NOR gate circuit. The structure of the P-type semiconductor 61, the two second electrodes 62, and the second insulating layer 63 is as follows:

[0113] See also Figure 7 The two second electrodes 62 surround different regions of the sidewall of the P-type semiconductor 61, and are respectively insulated from the P-type semiconductor 61 by the second insulating layer 63.

[0114] The second electrode 62 surrounds the middle region of the sidewall of the P-type semiconductor 61 and is insulated from the P-type semiconductor 61 by the second insulating layer 63, thus forming a junctionless PMOS transistor. The second electrode 62 serves as the gate of the PMOS transistor, and the second insulating layer 63 is the gate oxide layer of the PMOS transistor. The gate, drain, and channel layer of the PMOS transistor are located on the same P-type semiconductor 61. The portion of the P-type semiconductor 61 surrounded by the second electrode 62 forms the channel layer of the PMOS transistor. The two portions of the P-type semiconductor 61 adjacent to the portion surrounded by the second electrode 62 are the source and drain of the P-type semiconductor, respectively. When two second electrodes 62 surround different regions of the sidewall of the P-type semiconductor 61, two series-connected junctionless PMOS transistors can be formed.

[0115] Furthermore, one end of the P-type semiconductor 61 is connected to the second N-type semiconductor layer 53, allowing two series-connected junctionless PMOS transistors to be connected in series with two parallel-connected ring-channel NMOS transistors, thereby forming a CMOS NOR gate circuit. It can be seen that in the semiconductor device provided in this embodiment, the CMOS NOR gate circuit includes two PMOS transistors stacked in a direction perpendicular to the substrate, and these two PMOS transistors are also stacked on top of two NMOS transistors in a direction perpendicular to the substrate. Stacking the PMOS and NMOS transistors in the CMOS NOR gate circuit in this way reduces the substrate area occupied by the CMOS NOR gate circuit, enabling the miniaturization of the semiconductor device. Furthermore, stacking the PMOS and NMOS transistors in the CMOS NOR gate circuit further enables the miniaturization of the semiconductor device and improves product integration.

[0116] See also Figure 7 The P-type semiconductor 61 extends in a direction perpendicular to the substrate and may have a columnar structure. The two second electrodes 62 surrounding the P-type semiconductor 61 may have a plate-like structure and may be perpendicular to the P-type semiconductor 61. The two first electrodes 54, serving as the gates of two parallel NMOS transistors in a CMOS NOR gate circuit, may extend in a direction perpendicular to the substrate, and each first electrode 54 contacts and is electrically connected to one of the second electrodes 62. For example, each first electrode 54 passes through one second electrode 62. The two first electrodes 54 may be connected to the two input terminals of the CMOS NOR gate circuit, and the other end of the P-type semiconductor 61 may be connected to the power supply terminal of the CMOS NOR gate circuit.

[0117] See also Figure 7 The second insulating layer 63 may encapsulate the third gate oxide layer 631 and the third silicon dioxide layer 632, with the third silicon dioxide layer 632 located between the third gate oxide layer 631 and the P-type semiconductor 61. The third gate oxide layer 631 may be made of a High-K material. Adding a layer of silicon dioxide (i.e., the third silicon dioxide layer 632) between the third gate oxide layer 631 and the P-type semiconductor 61 can improve the control effect of the two second electrodes 62 (i.e., the gates of the two series-connected PMOS transistors) on the PMOS transistors.

[0118] See also Figure 7The NOR gate circuit also includes a third electrode 71, which extends in a direction perpendicular to the substrate. One end of the third electrode 71 is connected to the second N-type semiconductor layer 53, and the other end is connected to the output terminal of the NOR gate circuit. The third electrode 71 can be made of any conductive material and may have a columnar structure. Epitaxially growing the third electrode 71 on the second N-type semiconductor layer 53 allows the third electrode 71 to be electrically connected to the sources of two parallel NMOS transistors in the CMOS NOR gate circuit. Furthermore, the third electrode 71 can be connected to the output terminal of the CMOS NOR gate circuit to realize the output of the CMOS NOR gate circuit.

[0119] Figure 8 This is a flowchart illustrating a process for fabricating a semiconductor device according to an embodiment of this application. The semiconductor device includes NOR gate circuits, such as CMOS NOR gate circuits. See [link to relevant documentation]. Figure 8 The manufacturing process includes:

[0120] Step 801: Sequentially epitaxially grow three film layers 81, the main material of which is a semiconductor material, on a silicon substrate.

[0121] See Figure 9 In the process of processing CMOS or NOT gate circuits, three epitaxial layers 81 can be grown sequentially on a silicon substrate. The three epitaxial layers 81 are, from bottom to top, a heavily doped epitaxial electrode, a lightly doped epitaxial semiconductor, and a heavily doped epitaxial electrode. The lightly doped epitaxial semiconductor layer can be a lightly doped silicon layer, and the heavily doped epitaxial electrode can be a heavily doped silicon electrode.

[0122] Step 802: Erase two first through holes 82 penetrating the third layer of the three-layer film 81 in different regions of the third layer of the three-layer film 81.

[0123] The third film layer refers to the third film layer epitaxially grown on the silicon substrate. See also... Figure 10 After epitaxially growing three film layers 81 on the silicon substrate, etching can be performed starting from two different regions of the third film layer, along a direction perpendicular to the silicon substrate, until the silicon substrate is exposed. Then, two first vias 82 are etched through the three film layers 81 and perpendicular to the silicon substrate. The two different regions do not overlap, and the shape of the regions is not limited, such as being circular.

[0124] Step 803: Deposit a first insulating layer 83 on the sidewalls of the two first through holes 82 respectively, and fill the two first through holes 82 with the first insulating layer 83 formed with a fourth electrode 84.

[0125] See Figure 11After etching the first via 82 in the three-layer film 81, insulating material can be deposited simultaneously on the sidewalls of the two first vias 82, forming a first insulating layer 83 on the sidewall of each first via 82. The insulating material can be a gate dielectric material, such as High-K.

[0126] After forming a first insulating layer 83 on the sidewall of each first through hole 82, electrode material, such as polycrystalline silicon, can be filled into the first through hole 82 at the same time to form two fourth electrodes 84 that penetrate the three-layer film 81 and are insulated by the first insulating layer 83.

[0127] In this way, a fourth electrode 84 is insulated from the three-layer film 81 by a first insulating layer 83, forming an NMOS transistor with a ring-channel device structure. The fourth electrode 84 serves as the gate of the NMOS transistor, and the two heavily doped epitaxial electrodes in the three-layer film 81 are the source and drain of the NMOS transistor, respectively. The undoped or lightly doped semiconductor forms the channel layer of the NMOS transistor. Furthermore, two fourth electrodes 84 are insulated from the three-layer film 81 by different first insulating layers 83, forming two parallel ring-channel device structures of NMOS transistors. In this structure, the sources of the two parallel NMOS transistors are located on the same heavily doped epitaxial electrode, effectively connecting the sources of the two NMOS transistors. The drains of the two parallel NMOS transistors are also located on the same heavily doped epitaxial electrode, effectively connecting the drains of the two NMOS transistors. The channel layers of the two parallel NMOS transistors are located on the same undoped or lightly doped semiconductor, and are respectively located in the region surrounding the fourth electrode 84 of the undoped or lightly doped semiconductor.

[0128] Step 804: On the side of the three-layer film 81 away from the silicon substrate, two phase-insulating epitaxial electrodes 91 are epitaxially grown sequentially.

[0129] See Figure 12 After depositing a first insulating layer 83 on the sidewalls of the two first vias 82 and filling the fourth electrode 84, two insulating epitaxial electrodes 91 can be sequentially grown on the side of the three-layer film 81 away from the silicon substrate. These two epitaxial electrodes 91 can be parallel to the silicon substrate, and are insulated from each other by the insulating layer, as well as from the film 81 by the insulating layer. Furthermore, the projections of the two epitaxial electrodes 91 onto the silicon substrate do not necessarily overlap completely.

[0130] Step 805: Etch a second via 92 through the two epitaxial electrodes 91, deposit a second insulating layer 93 on the sidewall of the second via 92, and fill the second via 92 with the second insulating layer 93 with a P-type semiconductor 94.

[0131] See Figure 13After epitaxially growing two insulating epitaxial electrode layers 91, a second via 92 can be etched through the two epitaxial electrode layers 91 and perpendicular to the silicon substrate using an etching process. The projection of the second via 92 onto the silicon substrate does not overlap with the projections of the two first vias 82 onto the silicon substrate.

[0132] See Figure 14 After etching the second via 92, an insulating material can be deposited on the sidewall of the second via 92, thereby forming a second insulating layer 93 on the sidewall of the first via 82. This insulating material can be a gate dielectric material, such as High-K. After forming the second insulating layer 93 on the sidewall of the second via 92, a P-type semiconductor 94 can be filled into the second via 92.

[0133] Thus, an epitaxial electrode 91 can be formed by surrounding a P-type semiconductor 94 and being insulated from the P-type semiconductor 94 by a second insulating layer 93. Two epitaxial electrodes 91 can be formed by surrounding different regions of the P-type semiconductor 94 and being insulated from the P-type semiconductor 94 by a second insulating layer 93.

[0134] In one possible implementation, the second insulating layer 93 includes a gate oxide layer 931 and a silicon dioxide layer 932. Depositing the second insulating layer 93 on the sidewall of the second via 92 includes: depositing the gate oxide layer 931 on the sidewall of the second via 92 and depositing the silicon dioxide layer 932 on the sidewall of the gate oxide layer 931.

[0135] like Figure 14 As shown, after etching the second via 92, a gate dielectric material, such as High-K, can be deposited on the sidewall of the second via 92 to form a gate oxide layer 931. Then, silicon dioxide can be deposited on the sidewall of the gate oxide layer 931 to form a silicon dioxide layer 932. This addition of a silicon dioxide layer (i.e., silicon dioxide layer 932) between the gate oxide layer 931 and the P-type semiconductor 94 improves the control effect of the two epitaxial electrodes 91 (i.e., the gates of the two series-connected PMOS transistors) on the PMOS transistors.

[0136] In one optional processing flow, combined with Figure 15 The schematic diagram of the semiconductor device structure shown above illustrates the following processing steps in step 804, where two layers of insulating epitaxial electrodes 91 are grown sequentially:

[0137] Step 8041: On the side of the three-layer epitaxial semiconductor 81 away from the silicon substrate, a third insulating layer 95 is epitaxially grown, and a first epitaxial electrode 91 is epitaxially grown on the third insulating layer 95.

[0138] The first epitaxial electrode 91 can be made of any conductive material, such as polysilicon. The third insulating layer 95 can be an oxide insulating layer, used to insulate the first epitaxial electrode 91 and the epitaxial semiconductor 81.

[0139] Step 8042: Etch the first region of the first epitaxial electrode 91 until the third insulating layer 95 is exposed.

[0140] In this embodiment, the projection of the first region onto the silicon substrate overlaps with the projection of one of the two first vias 82 onto the silicon substrate. In one example, the first region may be rectangular, and the projection of one of the first vias 82 onto the silicon substrate lies within the projection of the first region onto the silicon substrate.

[0141] Step 8043: Epitaxially grow a fourth insulating layer 96 on the first epitaxial electrode 91, and epitaxially grow a second epitaxial electrode 91 on the fourth insulating layer 96.

[0142] The second epitaxial electrode 91 can be made of any conductive material, such as polysilicon. The fourth insulating layer 96 can be an oxide insulating layer, used to insulate and separate the first epitaxial electrode 91 and the second epitaxial electrode 92.

[0143] Step 8044: Etch the second region of the second epitaxial electrode 91 until the fourth insulating layer 96 is exposed.

[0144] The projection of the second region onto the silicon substrate overlaps with the projection of the other of the two first vias 82 onto the silicon substrate. In one example, the second region can be rectangular, and the projection of the other of the first vias 82 onto the silicon substrate lies within the projection of the second region onto the silicon substrate.

[0145] Step 8045: Epitaxially grow a fifth insulating layer 97 on the second epitaxial electrode 91.

[0146] Accordingly, after step 8044 above, in addition to etching the second via 92, depositing the second insulating layer 93, and filling the P-type semiconductor 94, the process in step 805 may also include:

[0147] Step 8046: Etch along a direction perpendicular to the silicon substrate, starting from the third region of the fifth insulating layer 97, to form a third via 98 that penetrates the fifth insulating layer 97, the fourth insulating layer 96, the first epitaxial electrode 91, and the third insulating layer 95.

[0148] The third region can be circular, and its projection onto the silicon substrate can completely coincide with the projection of a fourth electrode 84 onto the silicon substrate. In one example, etching can begin from the third region of the fifth insulating layer 97 along a direction perpendicular to the silicon substrate until the fourth electrode 84 is exposed, thereby forming a third via 98 that penetrates the fifth insulating layer 97, the fourth insulating layer 96, the first epitaxial electrode 91, and the third insulating layer 95.

[0149] Step 8047: Etch along a direction perpendicular to the silicon substrate, starting from the fourth region of the fifth insulating layer 97, to form a fourth via 99 that penetrates the fifth insulating layer 97, the second epitaxial electrode 91, the fourth insulating layer 96, and the third insulating layer 95.

[0150] The fourth region can be circular, and its projection onto the silicon substrate can completely coincide with the projection of the other fourth electrode 84 onto the silicon substrate. In one example, etching can begin from the fourth region of the fifth insulating layer 97 along a direction perpendicular to the silicon substrate until the other fourth electrode 84 is exposed, thereby forming a fourth via 99 that penetrates the fifth insulating layer 97, the fourth insulating layer 96, the first epitaxial electrode 91, and the third insulating layer 95.

[0151] Step 8048: Fill the third through hole 98 with the fifth electrode 910 and the fourth through hole 99 with the sixth electrode 911.

[0152] Thus, the gate of an NMOS transistor can be electrically connected to the gate of a PMOS transistor via the fifth electrode 910, and the gate of another NMOS transistor can be electrically connected to the gate of another PMOS transistor via the fifth electrode and the sixth electrode 911.

[0153] In addition, after step 8045 above, the output terminals of the CMOS or NOT gate circuit can also be processed, including:

[0154] Step 8049: Etch from the fifth region of the fifth insulating layer 97 along a direction perpendicular to the silicon substrate to form a fifth via 912 that penetrates the fifth insulating layer 97, the fourth insulating layer 96, and the third insulating layer 95.

[0155] Step 80410: Fill the fifth through hole 912 with the seventh electrode 913, which is the output terminal of the NOR gate circuit.

[0156] It should be noted that the order in which the second via 92, the third via 98, the fourth via 99, and the fifth via 912 are etched in the above steps is not restricted. These multiple vias can be etched in any order or simultaneously. Similarly, the order in which the second insulating layer 93, the fifth electrode 910, the fifth electrode 911, and the seventh electrode 913 are deposited is also not restricted. The insulating layer and the multiple electrodes can be deposited in any order or simultaneously.

[0157] In one example, after filling the fifth electrode 910 in the third via 98, an eighth electrode 914 can be deposited on the fifth electrode 910. The eighth electrode 914 is the first input terminal of a CMOS NOR gate circuit. To improve the conductivity between the eighth electrode 914 and the fifth electrode 910, silicide can be deposited on the fifth electrode 910 first, and then the eighth electrode 914 can be deposited on the silicide.

[0158] See Figure 15 After filling the fourth via 99 with the sixth electrode 911, a ninth electrode 915 can be deposited on the sixth electrode 911. The ninth electrode 915 is the second input terminal of the NOR gate circuit. To improve the conductivity between the ninth electrode 915 and the sixth electrode 911, silicide can be deposited on the sixth electrode 911 first, and then the ninth electrode 915 can be deposited on the silicide.

[0159] See Figure 15 After filling the second via 92 with a P-type semiconductor 94, a tenth electrode 916 can be deposited on the P-type semiconductor 94. This tenth electrode 916 serves as the power supply terminal for a NOR gate circuit. To improve the conductivity between the P-type semiconductor 94 and the tenth electrode 916, a silicide can be deposited on the P-type semiconductor 94 first, followed by the deposition of the tenth electrode 916 on the silicide.

[0160] This application also provides a memory that includes at least one semiconductor device as described in the above embodiments, for example, including at least one semiconductor device as described in the above embodiments in the peripheral circuitry of the memory. The memory can be volatile memory, such as random access memory (RAM), or non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD).

[0161] This application also provides an electronic device that includes at least one semiconductor device as described in the above embodiments. This electronic device includes, but is not limited to, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or smart mobile terminals.

[0162] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function. It should be understood that there is no logical or temporal dependency between "first" and "second," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of various examples, a first NMOS transistor can be referred to as a second NMOS transistor, and similarly, a second NMOS transistor can be referred to as a first NMOS transistor. Both the first and second NMOS transistors can be NMOS transistors, and in some cases, they can be separate and different NMOS transistors. In this application, the term "at least one" means one or more, and the term "multiple" means two or more.

[0163] The above description is merely an exemplary embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device comprising a NOR gate circuit, characterized in that, The NOR gate circuit includes: a first NMOS transistor (1), a second NMOS transistor (2), a first PMOS transistor (3), and a second PMOS transistor (4). The first NMOS transistor (1) includes a first source (11), a first drain (12), a first channel layer (13), a first gate (14), and a first gate insulating layer (15). The second NMOS transistor (2) includes a second source (21), a second drain (22), a second channel layer (23), a second gate (24), and a second gate insulating layer (25). The first NMOS transistor (1) and the second NMOS transistor (2) are connected in parallel and located between the first PMOS transistor (3) and the substrate. The first NMOS transistor (1) and the second NMOS transistor (2) are spaced apart on the substrate along a direction parallel to the substrate. The first PMOS transistor (3) and the second PMOS transistor (4) are connected in series and stacked in a direction perpendicular to the substrate. The first source (11), the first drain (12), and the first channel layer (13) are stacked in a direction perpendicular to the substrate, and the first channel layer (13) is located between the first source (11) and the first drain (12); the first gate (14) extends in a direction perpendicular to the substrate, and the first source (11), the first drain (12), and the first channel layer (13) surround different regions of the sidewall of the first gate (14) and are insulated from the first gate (14) through the first gate insulating layer (15); The second source (21), the second drain (22) and the second channel layer (23) are stacked in a direction perpendicular to the substrate, and the second channel layer (23) is located between the second source (21) and the second drain (22); the second gate (24) extends in a direction perpendicular to the substrate, and the second source (21), the second drain (22) and the second channel layer (23) surround different regions of the sidewall of the second gate (24) and are insulated from the second gate (24) through the second gate insulating layer (25).

2. The semiconductor device according to claim 1, characterized in that, The first source (11) and the second source (21) are located on the first N-type semiconductor layer; The first drain (12) and the second drain (22) are located in the second N-type semiconductor layer.

3. The semiconductor device according to claim 1, characterized in that, The first channel layer (13) and the second channel layer (23) are located on a P-type semiconductor layer.

4. The semiconductor device according to claim 1, characterized in that, The first PMOS transistor (3) includes a third source (31), a third drain (32), a third channel layer (33), a third gate (34), and a third insulating layer (35), and the second PMOS transistor (4) includes a fourth source (41), a fourth drain (42), a fourth channel layer (43), a fourth gate (44), and a fourth insulating layer (45). The third source (31), the third drain (32), and the third channel layer (33) are located on a first P-type semiconductor that extends perpendicular to the substrate. The third gate (34) surrounds the first P-type semiconductor and is insulated from the first P-type semiconductor through the third insulating layer (35). The fourth source (41), the fourth drain (42), and the fourth channel layer (43) are located on a second P-type semiconductor that extends perpendicular to the substrate. The fourth gate (44) surrounds the second P-type semiconductor and is insulated from the second P-type semiconductor through the fourth insulating layer (45).

5. The semiconductor device according to claim 4, characterized in that, The first P-type semiconductor and the second P-type semiconductor are different portions of a third P-type semiconductor that extends perpendicularly to the substrate.

6. The semiconductor device according to claim 4, characterized in that, The third insulating layer (35) includes a first gate oxide layer (351) and a first silicon dioxide layer (352), wherein the first silicon dioxide layer (352) is located between the first gate oxide layer (351) and the first P-type semiconductor; The fourth insulating layer (45) includes a second gate oxide layer (451) and a second silicon dioxide layer (452), the second silicon dioxide layer (452) being located between the second gate oxide layer (451) and the second P-type semiconductor.

7. The semiconductor device according to claim 4, characterized in that, The third gate (34) has a plate-like structure, the third gate (34) is parallel to the substrate, and the third gate (34) is connected to one of the first gate (14) and the second gate (24); The fourth gate (44) has a plate-like structure, the fourth gate (44) is parallel to the substrate, and the fourth gate (44) is connected to another gate among the first gate (14) and the second gate (24).

8. The semiconductor device according to claim 2, characterized in that, The side of the first N-type semiconductor that is away from and parallel to the substrate is connected to an electrode, which extends perpendicular to the first N-type semiconductor layer and is connected to the output terminal of the NOR gate circuit.

9. The semiconductor device according to claim 5, characterized in that, One end of the third P-type semiconductor is connected to the power supply terminal of the NOR gate circuit, and the other end of the third P-type semiconductor is connected to the first source (11) and the second source (21).

10. The semiconductor device according to claim 7, characterized in that, The first gate (14) is connected to one input terminal of the NOR gate circuit, and the second gate (24) is connected to the other input terminal of the NOR gate circuit.

11. A semiconductor device comprising a NOR gate circuit, characterized in that, The NOR gate circuit includes: a P-type semiconductor layer (51), a first N-type semiconductor layer (52), a second N-type semiconductor layer (53), two first electrodes (54), a first insulating layer (55), a P-type semiconductor (61), two second electrodes (62), and a second insulating layer (63); The P-type semiconductor layer (51), the first N-type semiconductor layer (52), and the second N-type semiconductor layer (53) are stacked sequentially in a direction perpendicular to the substrate. The two first electrodes (54) pass through the P-type semiconductor layer (51), the first N-type semiconductor layer (52), and the second N-type semiconductor layer (53), respectively, and are insulated from the P-type semiconductor layer (51), the first N-type semiconductor layer (52), and the second N-type semiconductor layer (53) by the first insulating layer (55). One end of the P-type semiconductor (61) is connected to the second N-type semiconductor layer (53). The two second electrodes (62) surround different regions of the sidewall of the P-type semiconductor (61) and are insulated from the P-type semiconductor (61) by the second insulating layer (63).

12. The semiconductor device according to claim 11, characterized in that, The P-type semiconductor (61) extends in a direction perpendicular to the substrate.

13. The semiconductor device according to claim 12, characterized in that, The two second electrodes (62) are perpendicular to the P-type semiconductor (61).

14. The semiconductor device according to claim 13, characterized in that, The two first electrodes (54) extend in a direction perpendicular to the substrate, and each first electrode (54) is connected to a second electrode (62).

15. The semiconductor device according to claim 14, characterized in that, The two first electrodes (54) are respectively connected to the two input terminals of the NOR gate circuit, and the other end of the P-type semiconductor (61) is connected to the power supply terminal of the NOR gate circuit.

16. The semiconductor device according to claim 11, characterized in that, The second insulating layer (63) includes a third gate oxide layer (631) and a third silicon dioxide layer (632), wherein the third silicon dioxide layer (632) is located between the third gate oxide layer (631) and the P-type semiconductor (61).

17. The semiconductor device according to claim 11, characterized in that, The NOR gate circuit also includes a third electrode (71), which extends in a direction perpendicular to the substrate. One end of the third electrode (71) is connected to the second N-type semiconductor layer (53), and the other end is connected to the output terminal of the NOR gate circuit.

18. A method for fabricating a semiconductor device, said semiconductor device comprising a NOR gate circuit, characterized in that, The method includes: Three layers (81) are epitaxially grown sequentially on a silicon substrate. Two first vias (82) penetrating the three layers (81) are etched in different regions of the third layer. A first insulating layer (83) is deposited on the sidewalls of the two first vias (82). A fourth electrode (84) is filled in the two first vias (82) where the first insulating layer (83) is formed. The three layers (81) are, from bottom to top, a heavily doped epitaxial electrode, a lightly doped epitaxial semiconductor, and a heavily doped epitaxial electrode. On the side of the three-layer film (81) away from the silicon substrate, two epitaxial electrodes (91) are epitaxially grown in sequence. A second via (92) penetrating the two epitaxial electrodes (91) is etched in the two epitaxial electrodes (91). A second insulating layer (93) is deposited on the sidewall of the second via (92). A P-type semiconductor (94) is filled in the second via (92) in which the second insulating layer (93) is formed.

19. The semiconductor device according to claim 18, characterized in that, The epitaxial growth of two phase-insulating epitaxial electrodes (91) on the side of the three-layer film (81) away from the silicon substrate includes: On the side of the three-layer film (81) away from the silicon substrate, a third insulating layer (95) is epitaxially grown, and a first epitaxial electrode (91) is epitaxially grown on the third insulating layer (95). The first region of the first epitaxial electrode (91) is etched until the third insulating layer (95) is exposed, wherein the projection of the first region on the silicon substrate overlaps with the projection of one of the two first vias (82) on the silicon substrate; A fourth insulating layer (96) is epitaxially grown on the first epitaxial electrode (91), and a second epitaxial electrode (91) is epitaxially grown on the fourth insulating layer (96). The second region of the second epitaxial electrode (91) is etched until the fourth insulating layer (96) is exposed, wherein the projection of the second region on the silicon substrate overlaps with the projection of the other of the two first vias (82) on the silicon substrate; A fifth insulating layer (97) is epitaxially grown on the second layer epitaxial electrode (91).

20. The semiconductor device according to claim 19, characterized in that, After epitaxially growing the fifth insulating layer (97) on the second epitaxial electrode (91), the method further includes: Etching begins from the third region of the fifth insulating layer (97) along a direction perpendicular to the silicon substrate to form a third via (98) penetrating the fifth insulating layer (97), the fourth insulating layer (96), the first epitaxial electrode (91), and the third insulating layer (95). Etching begins from the fourth region of the fifth insulating layer (97) along a direction perpendicular to the silicon substrate to form a fourth via (99) penetrating the fifth insulating layer (97), the second epitaxial electrode (91), the fourth insulating layer (96), and the third insulating layer (95). The orthographic projections of the third region and the fourth region onto the silicon substrate overlap with the orthographic projections of the first region and the second region onto the silicon substrate, respectively. The fifth electrode (910) is filled in the third through hole (98), and the sixth electrode (911) is filled in the fourth through hole (99).

21. An electronic device, characterized in that, Includes at least in part a semiconductor device as claimed in any one of claims 1 to 17.

22. The electronic device according to claim 21, characterized in that, The electronic devices include smartphones, computers, tablets, artificial intelligence devices, wearable devices, or smart mobile terminals.

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