Etching solution for iii-v semiconductor compound isolation layer and preparation and use thereof

Abstract

The present application relates to the technical field of wet electronic chemicals, and more particularly to an etching solution for III-V semiconductor compound isolation layer and preparation and application thereof. The etching solution comprises the following raw materials in percentage by weight: inorganic acid 5-15%, oxidizing agent 5-15%, etching inhibitor 0.05-0.3%, surfactant 0.05-0.3%, and the balance being water. The inorganic acid is selected from hydrochloric acid, sulfuric acid, phosphoric acid or hydrobromic acid, the oxidizing agent is selected from hydrogen peroxide, iodic acid, nitric acid or ammonium persulfate. The etching inhibitor is selected from citric acid, ammonium molybdate, hexamethyl uracil or methyl-phenylpropyl triazole. The surfactant is selected from acetic acid, triethylene glycol or polyethylene glycol. The present application only needs one etching solution, and on the basis of etching of the semiconductor compound isolation region, the etching rate and etching uniformity of etching of the III-V semiconductor compound isolation layer are improved, the drug residue and side etching loss are reduced, and the present application has very good application prospect and large-scale industrialization potential in the field of commercial semiconductor compounds.

Description

Technical Field

[0001] The present application relates to the technical field of wet electronic chemicals, and more specifically to an etching solution for a Group III-V semiconductor compound isolation layer, and its preparation and application. Background Art

[0002] With the rapid development of informatization, traditional silicon integrated circuits are increasingly unable to meet the growing demands for data processing speed and bandwidth. Semiconductor compounds possess properties that silicon lacks or possesses only partially. For example, silicon cannot emit light, has low mobility, and has a limited bandgap. However, compound semiconductors are different. They can emit light of different wavelengths and have bandgaps of varying widths. This is why they are widely used in microwave and millimeter devices, AC and cross-frequency devices, and other applications.

[0003] Many semiconductor compounds are formed from elements in Groups III and V, and Groups II and VI of the periodic table. Group III and V semiconductors are composed of Group III elements such as aluminum, gallium, and indium, and Group V elements such as nitrogen, phosphorus, arsenic, and antimony. Group II and VI semiconductors are compounds formed from Group II elements such as zinc, cadmium, and mercury, and Group VI elements such as sulfur, selenium, and tellurium. For example, in CMOS (Complementary Metal Oxide Semiconductor) technology research, Group III and V semiconductors exhibit high electron mobility and excellent electron transport properties under both low and high fields, making them ideal channel materials for ultra-high-speed, low-power nMOS (nMOS) transistors. The most commonly used Group III and V semiconductor compounds in commercial semiconductor devices are gallium arsenide (AsGa), gallium arsenide phosphide (AsGaP), indium phosphide (InP), gallium nitride (GaN), gallium aluminum arsenide (GaAlAs), and indium gallium phosphide (InGaP).

[0004] Traditional cutting methods include laser cutting or wet cutting. Laser cutting can easily cause elements from different structural layers to penetrate, and some impurities at the edges can easily cause device failure. Wet cutting, however, often requires multiple etchant formulations to etch different layers due to the large number of different structural layers to be cut, resulting in a corresponding corrosion rate. Furthermore, current wet etching solutions have poor stability, and etching accuracy is often poor, with severe side etching. Existing etching solutions for Group III-V semiconductor compounds, field-effect transistors (FETs), bipolar transistors (HBTs), light-emitting diodes, thin-film batteries, etc. require multiple etchant formulations and do not exhibit excellent solution stability and etching accuracy. Furthermore, current etching solutions exhibit severe side etching of Group III-V semiconductor compounds.

[0005] Therefore, there is an urgent need to develop an etching solution composition that can meet the needs of cutting the III-V semiconductor isolation layer without the need to use different etching solutions for different layers, and can achieve uniform etching of the III-V semiconductor isolation layer, small side erosion, and increased effective area. Summary of the Invention

[0006] In view of the above problems, the present application provides an etching solution for a III-V semiconductor compound isolation layer, as well as its preparation and application, in order to achieve precise and uniform cutting of a multi-layer III-V semiconductor isolation layer, minimize side etching and increase the effective area using only the etching solution provided by the present invention.

[0007] To achieve the above objectives, in a first aspect, the inventors provide an etching solution for a III-V semiconductor compound isolation layer, comprising, by weight percentage:

[0008] Inorganic acid 5%-15%;

[0009] Oxidant 5-15%;

[0010] Etching inhibitor 0.05%-0.3%;

[0011] Surfactant 0.05%-0.3%; and

[0012] Remaining water.

[0013] The components of different layers of the III-V semiconductor compound isolation layer targeted by the present invention are generally determined according to specific application scenarios and requirements, and mainly include the following layers: (1) Buffer layer: Usually, a III-V semiconductor material with a lattice matching with the substrate material, such as GaAs, InP, etc., is used to relieve the lattice mismatch stress between the substrate and the epitaxial layer and improve the crystal quality of the epitaxial layer; (2) Epitaxial layer: Using III-V semiconductor compound materials, such as GaAs, InP, GaN, etc., epitaxial layers of different doping types and concentrations are prepared as needed to form the active area and ohmic contact of the device; (3) Barrier layer: Using a III-V semiconductor compound material with a high aluminum component, such as AlGaAs, AlInAs, etc., it is used to block the leakage of carriers to the substrate and improve the performance of the device; (4) Cover layer: Using a III-V semiconductor compound material with a low dielectric constant, such as AlO x, SiO2, etc., are used to protect the device surface and passivate the surface state, thereby improving the reliability and stability of the device. The specific composition, thickness and other parameters of different III-V semiconductor compound isolation layers are optimized according to specific application scenarios and requirements. These isolation layers are generally used to protect the semiconductor substrate from environmental influences and help maintain the stability of the substrate surface. A high-performance III-V semiconductor compound isolation layer etching solution can form steep sidewalls and bottoms in the isolation layer, improving the high-frequency and noise performance of the device and reducing parasitic capacitance and resistance. It can also form deep isolation trenches in the isolation layer, effectively suppressing the formation of parasitic transistors and avoiding potential leakage current and noise interference in the circuit. It can achieve smaller device spacing and denser integration, increasing the integration and functional density of the circuit. It can eliminate microscopic defects and contamination on the isolation layer surface, improve the electrical properties and thermal stability of the surface, and enhance the reliability and life of the device. It can also increase the thermal conductivity of the isolation layer, improve the thermal performance of the device, reduce the operating temperature of the device, and increase the power handling capability.

[0014] In some preferred embodiments, the inorganic acid is selected from one or more of hydrochloric acid, sulfuric acid, phosphoric acid, and hydrobromic acid. In some more preferred embodiments, the inorganic acid is hydrochloric acid. These inorganic acids have excellent corrosiveness and etching efficiency, and the etching of Group III-V compounds is an oxidation-reduction process. Commonly used oxidants such as hydrogen peroxide are very unstable in an acidic environment and undergo self-oxidation-reduction (i.e., decomposition). Adding an inorganic acid such as hydrochloric acid can cause the oxidant to release oxygen, oxidizing copper to form copper oxide, which then reacts with hydrochloric acid to form copper chloride, significantly increasing its corrosiveness and improving etching efficiency.

[0015] In some preferred embodiments, the oxidant is selected from one or more of hydrogen peroxide, iodic acid, nitric acid, and ammonium persulfate. More preferably, iodic acid is used as the oxidant. These oxidants can oxidize copper ions on the surface of the copper plate, converting them into soluble copper salts, effectively promoting the surface cleaning effect of the etching solution. They can also change the ionization acidity of the etching solution, making it more efficient and improving the etching effect.

[0016] In some preferred embodiments, the etching inhibitor is selected from one or more of citric acid, ammonium molybdate, hexamethyluracil, and methyl-phenyltriazole. More preferably, ammonium molybdate is used as the etching inhibitor. Such an etching inhibitor can ensure precise and stable etching in large-scale industrial applications, reduce or avoid conductive layer fracture, and thus improve the adhesion between the conductive layer and the polymeric material. This can significantly enhance the specific corrosion inhibition effect and meet the requirement for precise and controllable corrosion inhibition effect, possibly due to the denser film formed by the synergistic effect of the etching inhibitor and other components.

[0017] In some preferred embodiments, the surfactant is selected from one or more of acetic acid, triethylene glycol, and polyethylene glycol. More preferably, the surfactant is polyethylene glycol. Surfactants can control the etching rate, and polyethylene glycol can adjust the viscosity and density of the etching solution, thereby slowing the etching rate. It can stabilize the etching solution. Polyethylene glycol itself is a viscous substance that can reduce the volatility of the corrosive agent and inhibit water erosion and electrophoresis during anodic oxidation, thereby improving the efficiency and stability of the etching solution. This increases the stability of the etching solution, controls the etching rate, and reduces damage to the substrate.

[0018] In a preferred embodiment of the present invention, the III-V semiconductor is a direct bandgap semiconductor. The inorganic acid is primarily hydrochloric acid, and the etching effect is improved by adding the organic acid iodic acid. The reactant chemically reacts with the surface molecules of the film being etched to produce a reaction product, which removes the naturally formed oxide layer on the surface of the III-V semiconductor compound, resulting in a flat, damage-free, bright surface. This effectively reduces the concentration of surface metal cations and most organic matter. The etching tends to be essentially isotropic in nature. The etched edge sidewalls and the III-V epitaxial layer interface are smooth and distinct, with distinct boundaries between the epitaxial layers, resulting in a straighter and smoother surface. The surface recombination center density is reduced due to the reduction of defects, which reduces the recombination of photogenerated minority carriers, thereby removing the film in areas not covered by the photoresist, thereby achieving the cutting of the III-V semiconductor isolation layer. The addition of iodic acid makes the etched surface terraces steeper, the terrace bottoms smoother, and the etching rate higher, thereby achieving uniform etching of the III-V semiconductor isolation layer, minimal side etching, and an increase in effective area.

[0019] In a second aspect, the inventors provide a method for preparing an etching solution for etching a Group III-V semiconductor compound isolation layer, comprising the following steps:

[0020] Add 0.05%-0.3% etching inhibitor by weight to water, keep the temperature at 20-25°C, and mix well;

[0021] 5%-15% of inorganic acid, 5-15% of oxidant, and 0.05%-0.3% of surfactant are added in sequence, wherein the inorganic acid is selected from one or more of hydrochloric acid, sulfuric acid, phosphoric acid and hydrobromic acid.

[0022] In some preferred embodiments, the inorganic acid is selected from one or more of hydrochloric acid, sulfuric acid, phosphoric acid and hydrobromic acid. More preferably, the inorganic acid is hydrochloric acid.

[0023] In some preferred embodiments, the oxidant is selected from one or more of hydrogen peroxide, iodic acid, nitric acid, and ammonium persulfate. More preferably, the oxidant is iodic acid.

[0024] In some preferred embodiments, the etching inhibitor is selected from one or more of citric acid, ammonium molybdate, hexamethyluracil, and methyl-phenyltriazole. More preferably, the etching inhibitor is ammonium molybdate.

[0025] In some preferred embodiments, the surfactant is selected from one or more of acetic acid, triethylene glycol and polyethylene glycol. More preferably, the surfactant is polyethylene glycol.

[0026] In a third aspect, the inventors provide an application of an etching solution for etching isolation layers of Group III-V semiconductor compounds. Specifically, the etching solution provided by the present invention can be used in the production and manufacturing of field-effect transistors (FETs), bipolar transistors (HBTs), light-emitting diodes, thin-film batteries, and the like.

[0027] Different from the prior art, the etching solution for etching a Group III-V semiconductor compound isolation layer provided by the above technical solution improves the etching rate and uniformity of the etching of the Group III-V semiconductor compound isolation layer while ensuring the etching of the semiconductor compound isolation layer, reduces etching solution residue and side etching loss, and enhances the etching accuracy and stability of the etching solution. Therefore, the etching solution for etching a Group III-V semiconductor compound isolation layer provided by the present invention has very good application prospects and large-scale industrial promotion potential in the field of commercial semiconductor compounds, such as, but not limited to, the production and manufacturing processes of field effect transistors (FETs), bipolar transistors (HBTs), light-emitting diodes, and thin-film batteries.

[0028] The above-mentioned records related to the content of the invention are only an overview of the technical solution of this application. In order to enable ordinary technicians in this field to understand the technical solution of this application more clearly, and then implement it according to the text of the specification and the contents recorded in the drawings, and to make the above-mentioned purposes and other purposes, features and advantages of this application easier to understand, the following is an explanation in combination with the specific implementation methods and drawings of this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings are only used to illustrate the principles, implementation methods, applications, features and effects of the specific embodiments of the present invention and other related contents, and are not to be considered as limiting the present application.

[0030] In the drawings of the specification:

[0031] Figure 1 SEM image of side etching data of a wafer with a 2000nm GaInP compound isolation layer using a Group III-V semiconductor compound isolation layer etching solution provided in an embodiment of the present invention;

[0032] Figure 2This is an SEM image of the side etching data of a wafer with a 3000nm AsGa compound isolation layer using the III-V semiconductor compound isolation layer etching solution provided in an embodiment of the present invention;

[0033] Figure 3 The SEM image of the side etching data of the compound isolation layer of the group III-V semiconductor compound isolation layer etchant provided in the comparative example on the wafer with a compound isolation layer of 3000nm AsGa is shown in FIG. 1 , wherein all etching process conditions are the same as those in FIG. Figure 2 The same. DETAILED DESCRIPTION

[0034] In order to explain in detail the possible application scenarios, technical principles, specific solutions that can be implemented, and the purpose and effects of this application, the following is a detailed description of the specific embodiments listed in conjunction with the accompanying drawings. The embodiments described herein are only used to more clearly illustrate the technical solutions of this application and are therefore only examples and are not intended to limit the scope of protection of this application.

[0035] References to "embodiments" herein mean that the specific features, structures, or characteristics described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the word "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it particularly limit its independence or relevance to other embodiments. In principle, in this application, as long as there are no technical contradictions or conflicts, the various technical features mentioned in the embodiments can be combined in any manner to form a corresponding implementable technical solution.

[0036] Unless otherwise defined, the technical terms used herein have the same meanings as those generally understood by those skilled in the art to which this application belongs; the use of relevant terms herein is only for describing specific embodiments and is not intended to limit this application.

[0037] In the description of this application, the term "and / or" is used to describe a logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A exists, B exists, and both A and B exist. In addition, the character " / " in this document generally indicates that the objects before and after are in a logical "or" relationship.

[0038] In this application, terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual quantity, priority or sequence relationship between these entities or operations.

[0039] Without further limitations, in this application, the words "include", "comprise", "have" or other similar open-ended expressions used in sentences are intended to cover non-exclusive inclusion. These expressions do not exclude the presence of additional elements in the process, method or product that includes the elements, so that the process, method or product that includes a series of elements may include not only those defined elements, but also other elements that are not explicitly listed, or also include elements inherent to such process, method or product.

[0040] Consistent with the understanding in the Examination Guidelines, in this application, expressions such as "greater than," "less than," and "exceed" are understood to exclude the number itself; expressions such as "above," "below," and "within" are understood to include the number itself. Furthermore, in the description of the embodiments of this application, "multiple" means more than two (including two), and similar expressions related to "multiple" are also understood in this manner, such as "multiple groups," "multiple times," etc., unless otherwise specifically defined.

[0041] In the description of the embodiments of the present application, the space-related expressions used, such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the specific embodiments or drawings, and are only for the convenience of describing the specific embodiments of the present application or facilitating the reader's understanding, and do not indicate or imply that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, it should not be understood as a limitation on the embodiments of the present application.

[0042] Unless otherwise expressly specified or limited, in the description of the embodiments of the present application, the terms "installed", "connected", "connected", "fixed", "set", etc. used should be understood in a broad sense. For example, the "connection" can be a fixed connection, a detachable connection, or an integrated setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art of the present application, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0043] Unless otherwise specified, the examples of this application were performed in accordance with the techniques or conditions described in the literature in this technical field, or in accordance with the product instructions. Reagents or instruments used without manufacturer indicated were all conventional products that can be purchased through regular channels.

[0044] The wafer structure used in the embodiment of the present invention is 2000nmGaInP, 3000nmAsGa, and 2000nmInGaAs.

[0045] The components and weight ratios of the etching solutions used for etching the isolation layer of the III-V semiconductor compound of Examples 1-11 are shown in Table 1.

[0046] The steps for preparing an etching solution for etching a Group III-V semiconductor compound isolation layer are as follows: weigh each component according to the weight ratio; add the solvent water into a stirring container, start stirring, and control the temperature at 20-25°C. Slowly add the etching inhibitor along the inner wall of the stirring container. After stirring and dissolving completely, the next step begins. While maintaining stirring, the inorganic acid, oxidant, and surfactant are added in sequence to obtain an etching solution for etching a Group III-V semiconductor compound isolation layer.

[0047] Table 1 Components and weight ratios of etching solutions of Examples 1-11

[0048]

[0049]

[0050] Comparative Example 1

[0051] The components contained in the etching solution and their weight ratios are: 1.80% hydrofluoric acid, 7.21% hypochlorous acid, 27.03% sodium fluorosilicate, 0.90% triphenyl phenol polyoxyethylene ether phosphate, 9.01% methanol, and 54.05% water.

[0052] Comparative Example 2

[0053] The components contained in the etching solution and their weight ratios are: 1.72% hydrofluoric acid, 6.90% hypochlorous acid, 25.86% sodium fluorosilicate, 5.17% acetanilide, 8.62% methanol, and 51.72% water.

[0054] The preparation methods of the etching solutions of Comparative Examples 1 and 2 are as follows:

[0055] Step 1: Weigh each component separately;

[0056] Step 2: Put the organic solvent into a plastic cup and stir it at a speed of 6120r / min. Add the unsaturated hydrocarbon compound containing amino group while stirring. After stirring for 30 minutes, add pure water and continue stirring for 10 minutes. Add the fluorine-containing compound and mixed acid in sequence while stirring. After stirring for 5 minutes, add the phosphate surfactant at a speed of 1 drop / min. After stirring for 10 minutes, the etching solution can be obtained.

[0057] The etching solution obtained in Examples 1-11 and Comparative Examples 1-2 of the present application was used to conduct an etching application experiment. The specific steps are as follows:

[0058] Etching ability: Divide the prepared etching solution into three parts and spray them on a wafer with a compound isolation layer of 2000nm GaInP at a flow rate of 5L / min at 25℃ to perform etching experiments. Record the etching time at a certain thickness. The time required to be etched away is used to calculate the etching rate. After etching, the etched substrate is rinsed with ultrapure water and blown dry with high-purity nitrogen. The etching effect of the glass substrate is observed and tested by SEM. The etching rate is tested by taking the average of 5 points on a wafer and dividing it by the time. The etching uniformity is tested by subtracting the minimum etching depth from the maximum etching depth. The side etching loss is the etching distance observed under an electron microscope (see Figure 1 and Figure 2 The side etching data and the etching solution provided by the present application are respectively 2000nm GaInP and 3000nm AsGa wafers with isolation layers of the compound. Figure 3 The side etching data of the etching solution composition provided in Comparative Example 1 on a wafer having a 3000nm AsGa compound isolation layer were shown. An optical microscope was used to observe whether there was any residue. The etching ability, etching residue, and etching rate are shown in Table 2.

[0059] Table 2 Test results of Examples 1-11

[0060]

[0061] Table 2 shows the test results of the etching solutions used in Examples 1-11 for etching the III-V semiconductor compound isolation layer. Table 2 shows the etching efficiency, etching uniformity, etching residue, lateral etching loss, and etching time, as well as the corrosion status of the solutions in Examples 1-11 at different composition and weight ratios. The results in Table 2 indicate that Solution 8 achieved the best etching effect on the III-V semiconductor compound isolation layer, as demonstrated by uniform etching, minimal lateral etching loss, no residue, increased effective area, and a relatively long effective life.

[0062] The expiration time of the solution is the time during which the solution can still meet all conditions as the corrosion time increases.

[0063] The data in Table 1 and Table 2 show that the etching efficiency is improved under the composition ratio of 5%-8% hydrochloric acid, 5%-8% iodic acid, 0.05%-0.1% ammonium molybdate, 0.1% polyethylene glycol and 5%-8% hydrochloric acid, 5%-8% iodic acid, 0.1% methyl-phenyltriazole, and 0.1% polyethylene glycol, and the etching is uniform, the side etching is small, and the effective area is increased. Figures 1-3As can be seen from the comparison pictures, the scientific and reasonable compound composition and content ratio of the present application make the obtained etching solution uniform, stable and have low surface tension, which can effectively penetrate and infiltrate the parts of the III-V compound isolation layer that need to be etched, thereby improving the etching efficiency. In addition, the etching solution has relatively low corrosiveness and can be used for etching under mild conditions. There will be no residue after etching, the lines are smooth, and the etching is uniform.

[0064] The etching solution provided by the present invention can be applied to the production processes of field effect transistors (FETs), bipolar transistors (HBTs), light emitting diodes, thin film batteries, etc.

[0065] Finally, it should be noted that although the above embodiments have been described in the specification and drawings of this application, this does not limit the scope of patent protection of this application. All technical solutions generated by replacing or modifying equivalent structures or equivalent processes based on the essential concepts of this application using the contents recorded in the specification and drawings of this application, as well as directly or indirectly implementing the technical solutions of the above embodiments in other related technical fields, are included in the scope of patent protection of this application.

Claims

1. An etching solution for a III-V semiconductor compound isolation layer, characterized in that: In percentage by weight, it includes: Hydrochloric acid 5%-8%; Iodic acid 5%-8%; 0.05%-0.1% of an etching inhibitor, wherein the etching inhibitor is selected from one or more of citric acid, ammonium molybdate, hexamethyluracil and methyl-phenyltriazole; 0.1% surfactant, wherein the surfactant is selected from triethylene glycol and / or polyethylene glycol; and Remaining water.

2. A method for preparing an etching solution for a Group III-V semiconductor compound isolation layer according to claim 1, characterized in that: The steps include: Add 0.05%-0.1% etching inhibitor by weight to water, keep the temperature at 20-25°C, and mix well; 5%-8% hydrochloric acid, 5-8% iodic acid, and 0.1% surfactant are added in sequence, wherein the surfactant is selected from triethylene glycol and / or polyethylene glycol, and the etching inhibitor is selected from one or more of citric acid, ammonium molybdate, hexamethyluracil, and methyl-phenyltriazole.

3. Use of the etching solution for a Group III-V semiconductor compound isolation layer as claimed in claim 1 in etching a Group III-V semiconductor compound isolation layer.

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