Method of etching a metal barrier layer and a metal layer and method of manufacturing a semiconductor device

Abstract

A method for etching a metal barrier layer and a metal layer, and a method for manufacturing a semiconductor device, are disclosed. The method includes: forming a metal barrier layer and a metal layer on a substrate; and etching the metal barrier layer and the metal layer using an etching composition. The etching composition may include: an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methanesulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or combinations thereof; a metal etching inhibitor, including a compound represented by chemical formula 1 as shown in the specification; and a metal oxide solubilizer selected from phosphoric acid, phosphates, carboxylic acids having 3 to 20 carbon atoms, or combinations thereof.

Description

[0001] This application is a divisional application of patent application No. 201910879827.7, filed on September 18, 2019, entitled "Method for etching a metal barrier layer and a metal layer and a method for manufacturing a semiconductor device". Technical Field

[0002] This disclosure relates to etching compositions, methods of using the same to etch metal barrier layers and metal layers, and methods of using the same to manufacture semiconductor devices. Background Technology

[0003] Semiconductor devices are widely used in the electronics industry due to their small size, versatility, and / or low manufacturing cost. Semiconductor devices can include storage devices for storing data, logic devices for processing data, and hybrid devices for operating various functions simultaneously or concurrently.

[0004] With the rapid development of the electronics industry, semiconductor devices increasingly require high integration. Therefore, manufacturing semiconductor devices is becoming increasingly difficult due to the problem of reduced process margins in exposure processes that define fine patterns. Furthermore, the electronics industry is increasingly demanding high speeds for semiconductor devices. Various studies have been conducted to meet the requirements of high integration and / or high speed in semiconductor devices. Summary of the Invention

[0005] Some exemplary embodiments of this disclosure provide etching compositions capable of effectively etching metal barrier layers and metal layers, and methods for manufacturing semiconductor devices using the etching compositions.

[0006] According to some exemplary embodiments of this disclosure, a method for etching a metal barrier layer and a metal layer may include: forming a metal barrier layer and a metal layer on a substrate; and etching the metal barrier layer and the metal layer using an etching composition. In these exemplary embodiments, the etching composition may include: an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methanesulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or combinations thereof; a metal etching inhibitor, including a compound represented by the following chemical formula 1; and a metal oxide solubilizer selected from phosphoric acid, phosphates, carboxylic acids having 3 to 20 carbon atoms, or combinations thereof.

[0007] [Chemical Formula 1]

[0008]

[0009] In Formula 1, R1 and R2 are independently hydrogen, (C1-C10)alkyl, (C3-C10)alkenyl, (C3-C10)alkynyl, (C1-C10)alkoxy, or carboxyl, and R3 is hydrogen, amino, (C1-C10)alkylamino, (C3-C10)arylamino, (C1-C10)alkyl, (C3-C10)alkenyl, (C3-C10)alkynyl, (C1-C10)alkoxy, or carboxyl, n is an integer equal to or greater than 1, and R1, R2, and R3 can be unsubstituted or substituted.

[0010] According to some exemplary embodiments of this disclosure, a method for etching a titanium nitride layer and a tungsten layer may include: forming a titanium nitride layer and a tungsten layer on a substrate; and etching the titanium nitride layer and the tungsten layer using an etching composition. In these exemplary embodiments, the etching composition may include: an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methanesulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or combinations thereof; a metal etching inhibitor, including amine compounds having one or two amino groups; and a metal oxide solubilizer selected from phosphoric acid, phosphates, carboxylic acids having 3 to 20 carbon atoms, or combinations thereof.

[0011] According to some exemplary embodiments of this disclosure, a method of manufacturing a semiconductor device may include: forming a sacrificial layer and a dielectric layer alternately and repeatedly stacked on a substrate; selectively removing the sacrificial layer to form a recessed region; forming a metal barrier layer and a metal layer filling the recessed region; and partially etching the metal barrier layer and the metal layer using an etching composition to form a metal barrier pattern and a metal pattern in each recessed region. In these exemplary embodiments, the etching composition may include: an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methanesulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or combinations thereof; a metal etching inhibitor, including an amine compound having one or two amino groups; and a metal oxide solubilizer selected from phosphoric acid, phosphates, carboxylic acids having 3 to 20 carbon atoms, or combinations thereof. Attached Figure Description

[0012] Features of exemplary embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein like reference numerals indicate like elements, in which:

[0013] Figures 1 to 3 A cross-sectional view is shown illustrating a method for etching a metal layer and a metal barrier layer according to some exemplary embodiments of the present disclosure.

[0014] Figures 4 to 14 A cross-sectional view is shown illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure.

[0015] Figure 15It shows Figure 14 A perspective view of a semiconductor device depicted in the image.

[0016] Figure 16A An image showing a cross section of the result formed by an etching process using the etching composition of Example 4 in Table 4 is shown.

[0017] Figure 16B An image showing a cross section of the result formed by an etching process using the etching composition of Comparative Example 3 in Table 4 is shown.

[0018] Figure 17 A graph is shown showing the profile error rate of the sidewalls of the obtained products formed by etching processes using the etching compositions of Examples 4 and 5 in Table 4, as well as Comparative Examples 3 and 4. Detailed Implementation

[0019] Figures 1 to 3 A cross-sectional view is shown illustrating a method for etching a metal layer and a metal barrier layer according to some example embodiments of the present disclosure.

[0020] Reference Figure 1 A metal layer MT and a metal barrier layer BM can be formed on the substrate 100. The metal barrier layer BM can be adjacent to the metal layer MT. The metal layer MT can have a first etch target surface ES1, and the metal barrier layer BM can have a second etch target surface ES2. The first etch target surface ES1 and the second etch target surface ES2 can be surfaces on which the etch composition CO is applied according to some example embodiments of this disclosure, which will be discussed below. For example, the first etch target surface ES1 and the second etch target surface ES2 can be substantially coplanar with each other.

[0021] The metal layer MT may include one or more of aluminum, copper, molybdenum, and cobalt. The metal barrier layer BM may be a metal nitride layer, which may include one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0022] Reference Figure 2 According to some exemplary embodiments of this disclosure, the etching composition CO can be applied to a metal layer MT and a metal barrier layer BM. The etching composition CO can be applied directly to a first etch target surface ES1 and a second etch target surface ES2. The etching composition CO may include an oxidant, a metal etching inhibitor, a metal oxide solubilizer, and water.

[0023] Oxidizing agents can oxidize the metal layer MT and the metal barrier layer BM. Oxidizing agents can be selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methanesulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or combinations thereof.

[0024] Metal etching inhibitors can suppress the action of oxidants on the metal layer (MT). Metal etching inhibitors can be amine compounds having one or two amino groups in a single molecule. Metal etching inhibitors can include compounds represented by the following chemical formula 1.

[0025] [Chemical Formula 1]

[0026]

[0027] R1 and R2 can be independently hydrogen, (C1-C10)alkyl, (C3-C10)alkenyl, (C3-C10)alkynyl, (C1-C10)alkoxy, or carboxyl. The alkyl, alkenyl, alkynyl, or alkoxy groups can be unsubstituted or substituted with carboxyl or hydroxyl groups.

[0028] R3 can be hydrogen, amino, (C1-C10)alkylamino, (C3-C10)arylamino, (C1-C10)alkyl, (C3-C10)alkenyl, (C3-C10)alkynyl, (C1-C10)alkoxy, or carboxyl. The amino, alkylamino, arylamino, alkyl, alkenyl, alkynyl, or alkoxy group can be unsubstituted or substituted with a carboxyl or hydroxyl group.

[0029] In chemical formula 1, n is an integer equal to or greater than 1.

[0030] Compounds represented by Formula 1 may have one or two amino groups in their molecules. For example, compounds represented by Formula 1 may have one or two nitrogen atoms.

[0031] For example, metal etching inhibitors may include ethylenediamine diacetate (EDADA), ethylenediaminetetraacetic acid (EDATAA), ethylenediamine (EDA), m-phenylenediamine (MXDA), methyldiethanolamine (MDEA), dimethylmonoethanolamine (DMMEA), ethyldiethanolamine (EDEA), diethylmonoethanolamine (DEMEA), triethylamine (TEA), or tributylamine (TBA).

[0032] Metal oxide solubilizers can have boiling points from 90°C to 200°C at 1 atmosphere. Metal oxide solubilizers can be acids whose oxidizing power against the metal layer (MT) and metal barrier layer (BM) is less than that against the oxidizing agent. For example, metal oxide solubilizers can be selected from phosphoric acid, phosphates, carboxylic acids having 3 to 20 carbon atoms, or combinations thereof.

[0033] The amount of oxidant relative to the total weight of the etching composition CO can be from 10% to 30% by weight. When the amount of oxidant is less than 10% by weight, the etching rate may decrease due to the reduced oxidation rate of the metal layer MT and the metal barrier layer BM. When the amount of oxidant is greater than 30% by weight, an excessive amount of oxidant is used, thus reducing the economic efficiency of the etching composition CO. In certain embodiments, the oxidant can be present in an amount of 15% to 25% by weight.

[0034] The amount of metal etching inhibitor relative to the total weight of the etching composition CO can be from 0.01 wt% to 10 wt%. When the amount of metal etching inhibitor is less than 0.01 wt%, it is difficult to reduce the etching rate of the metal layer MT. When the amount of metal etching inhibitor is greater than 10 wt%, the etching rate of the metal layer MT will be significantly reduced, making it difficult to achieve etching selectivity, which will be discussed below. In a specific embodiment, the amount of metal etching inhibitor can be from 0.1 wt% to 3 wt%.

[0035] The amount of water relative to the total weight of the etching composition CO can be from 10% to 30% by weight. The metal oxide solubilizer can occupy the remainder of the etching composition CO. The water can be pure water or deionized water.

[0036] The etching composition CO may also include an auxiliary oxidant, a pH adjuster, or a surfactant. The auxiliary oxidant can increase the oxidation rate of the metal layer MT and the metal barrier layer BM. The auxiliary oxidant can include acidic ammonium compounds, hydrohalic acid compounds, or sulfuric acid compounds. Acidic ammonium compounds can include, for example, ammonium sulfate, ammonium persulfate, ammonium acetate, ammonium phosphate, or ammonium chloride. Hydrohalic acid compounds can include, for example, periodic acid or iodic acid. Sulfuric acid compounds can include, for example, sulfuric acid, methanesulfonic acid, or p-toluenesulfonic acid. The compounds discussed as auxiliary oxidants can be used alone or in combination of two or more.

[0037] pH adjusters can adjust the pH of the CO etching composition. pH adjusters may include, for example, one or more of ammonia, amines, and nitrogen-containing heterocyclic compounds.

[0038] Surfactants can remove byproducts (or residues) generated during etching processes. Surfactants can include anionic surfactants (e.g., C8H4O7). 17 COOH), cationic surfactants (e.g., C8H), 17 NH2) or nonionic surfactants (e.g., polyoxyethylene alkyl ethers).

[0039] The oxidant in the etching composition CO can oxidize the metal layer MT and the metal barrier layer BM. Therefore, a first metal oxide layer OX1 and a second metal oxide layer OX2 can be formed on the metal layer MT and the metal barrier layer BM, respectively.

[0040] Compared to the metal barrier layer BM, oxidants can oxidize the metal layer MT more quickly. The metal etch inhibitor can cover and protect the first etch target surface ES1 of the metal layer MT, thus preventing the oxidant from oxidizing the metal layer MT.

[0041] Reference Figure 3 The metal oxide solubilizer and water in the etching composition CO can dissolve the first metal oxide layer OX1 and the second metal oxide layer OX2, which can lead to the removal of the first metal oxide layer OX1 and the second metal oxide layer OX2. According to some example embodiments of this disclosure, the etching composition CO can oxidize and dissolve the metal layer MT and the metal barrier layer BM, resulting in the etching of the metal layer MT and the metal barrier layer BM.

[0042] For example, the etching composition CO can use a metal etching inhibitor to achieve an etching selectivity in the range of 1.0 to 2.0. Etching selectivity is the ratio of the etching rate of the metal layer MT to the etching rate of the metal barrier layer BM.

[0043] For example, refer to Figures 1 to 3 The metal layer MT and metal barrier layer BM discussed can be etched at a temperature of 50°C to 70°C for 20 to 100 minutes.

[0044] In certain embodiments, the wet etching process can be performed at a high temperature above room temperature (e.g., approximately 25°C). When the wet etching process is performed at a high temperature, the metal layer MT and the metal barrier layer BM can be etched at a high rate. Because the metal oxide solubilizer in the etching composition (CO) has a relatively high melting point, volatilization during the wet etching process can be avoided.

[0045] <Examples 1 to 3, and Comparative Examples 1 and 2>

[0046] Table 1 below lists the composition of the etching compositions according to Examples 1 to 3 and the composition of the etching compositions according to Comparative Examples 1 and 2, and also lists the etching process temperature.

[0047] [Table 1]

[0048]

[0049]

[0050] [Experiment 1]

[0051] The etching compositions of Examples 1 to 3, Comparative Examples 1 and 2 were evaluated using the following methods, and the results are shown in Table 2 below.

[0052] An etching composition is applied to a tungsten layer (metal layer) of a specific thickness. The etching process is performed for 30 minutes, and then the thickness of the tungsten layer is measured to determine the etching rate. The layer thickness is measured using X-ray fluorescence (XRF).

[0053] Additionally, an etching composition is applied to a titanium nitride layer (metal barrier layer) of a specific thickness. The etching process is performed for 30 minutes, and then the thickness of the titanium nitride layer is measured to determine the etching rate. The layer thickness measurement is performed using X-ray fluorescence (XRF).

[0054] [Table 2]

[0055]

[0056] Referring to Table 2, since the etching composition of Comparative Example 1 does not contain a metal etching inhibitor, it can be determined that the etching rate of the tungsten layer is more than twice that of the titanium nitride layer.

[0057] [Experiment 2]

[0058] To facilitate water evaporation and condensation during the etching process, a glass bath was fitted over the etching bath. The etching compositions of Examples 1 to 3 and Comparative Example 2 were evaluated using the following methods, and their results are shown in Table 3 below.

[0059] An etching composition was applied to a tungsten layer (metal layer). The etching process was performed for 30 minutes, and then the thickness of the tungsten layer was measured. The thickness of the tungsten layer was then measured every 3 hours for a total of 12 hours. The layer thickness was measured using X-ray fluorescence (XRF).

[0060] Additionally, an etching composition was applied to a titanium nitride layer (metal barrier layer). The etching process was performed for 30 minutes, after which the thickness of the titanium nitride layer was measured. The thickness of the titanium nitride layer was then measured every 3 hours for a total of 12 hours. X-ray fluorescence (XRF) was used to measure the layer thickness.

[0061] [Table 3]

[0062]

[0063]

[0064] Referring to Table 2 or the results of Experiment 1, it can be determined that the etching compositions of Examples 1 to 3 containing metal etching inhibitors have a reduced etching rate of the tungsten layer compared to the etching composition of Comparative Example 1. In this sense, the etching rate of the tungsten layer can be reduced by adjusting the amount and type of metal etching inhibitor in the etching composition according to this disclosure. For example, the ratio of the etching rate of the tungsten layer to the etching rate of the titanium nitride layer can be adjusted.

[0065] Referring to the results in Table 3 or Experiment 2, the etching rate of the tungsten layer by the etching composition of Comparative Example 2 gradually decreased between 30 minutes and 12 hours. In this sense, the etching selectivity of the etching composition of Comparative Example 2 gradually decreased between 30 minutes and 12 hours. Conversely, it can be determined that the etching rate of the tungsten layer by the etching compositions of Examples 1 to 3 remained relatively uniform between 30 minutes and 12 hours. For example, the etching selectivity of the etching compositions of Examples 1 to 3 remained uniform during the etching process.

[0066] Figures 4 to 14 A cross-sectional view is shown illustrating a method for manufacturing a semiconductor device according to some example embodiments of the present disclosure. Figure 15 It shows Figure 14 A perspective view of a semiconductor device depicted in the image.

[0067] Reference Figure 4 The thin-layer structure TS can be formed by alternately and repeatedly depositing a sacrificial layer 151 and a dielectric layer 110 on a substrate 100. The substrate 100 can be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The sacrificial layer 151 can be formed from, for example, a silicon nitride layer, a silicon oxynitride layer, or a silicon layer. The dielectric layer 110 can be formed from, for example, a silicon oxide layer. The sacrificial layer 151 and the dielectric layer 110 can be deposited using, for example, thermochemical vapor deposition (CVD), plasma-enhanced CVD, physical CVD processes, or atomic layer deposition (ALD).

[0068] A lower dielectric layer 105 can be formed between the substrate 100 and the thin-layer structure TS. The lower dielectric layer 105 can be formed of a material with high etch selectivity relative to the sacrificial layer 151 and the dielectric layer 110. For example, the lower dielectric layer 105 may include a high-k dielectric layer, such as a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer. The lower dielectric layer 105 can be formed to have a thickness smaller than that of the sacrificial layer 151 and the dielectric layer 110.

[0069] Reference Figure 5A channel hole CH can be formed to penetrate the thin-layer structure TS and expose the substrate 100. Forming the channel hole CH may include: forming a first mask pattern (not shown) on the thin-layer structure TS having an opening defining the region where the channel hole CH is formed; and performing an etching process, wherein the thin-layer structure TS is etched using the first mask pattern as an etching mask. During the etching process, the top surface of the substrate 100 may be over-etched. Therefore, the top surface of the substrate 100 may be recessed. After forming the channel hole CH, the first mask pattern may be removed.

[0070] Reference Figure 6 A lower semiconductor pattern (LSP) can be formed to fill the lower portion of the channel hole (CH). The lower semiconductor pattern (LSP) can be formed, for example, by a selective epitaxial growth (SEG) process in which a substrate 100 exposed to the channel hole (CH) is used as a seed.

[0071] Each lower semiconductor pattern LSP can be formed in the shape of a pillar protruding from the substrate 100 and filling the lower part of the channel via CH. The lower semiconductor pattern LSP can cover the sidewalls of the bottommost sacrificial layer 151.

[0072] The lower semiconductor patterned LSP may include a semiconductor material with the same conductivity type as the semiconductor material of the substrate 100. For example, when performing a selective epitaxial growth process, the lower semiconductor patterned LSP may be doped in situ with impurities. Alternatively, after performing a selective epitaxial growth process, the lower semiconductor patterned LSP may be ion implanted with impurities. The lower semiconductor patterned LSP may include a semiconductor material such as silicon having a single-crystal or polycrystalline structure.

[0073] Reference Figure 7 A vertical dielectric layer 140 and a first semiconductor layer SL1 can be sequentially formed on the inner sidewall of the channel hole CH. The vertical dielectric layer 140 and the first semiconductor layer SL1 can partially fill each channel hole CH. The channel hole CH may not be completely filled by the vertical dielectric layer 140 and the first semiconductor layer SL1.

[0074] In a particular embodiment, forming the vertical dielectric layer 140 may include, for example, sequentially forming a barrier dielectric layer, a charge storage layer, and a tunnel dielectric layer on the inner sidewall of each channel via CH. The barrier dielectric layer may be formed of, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The charge storage layer may be formed of, for example, one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a stacked trapping layer. The tunnel dielectric layer may be formed of, for example, a silicon oxide layer.

[0075] The first semiconductor layer SL1 may include a semiconductor material having a single-crystal structure or a polycrystalline structure. For example, the first semiconductor layer SL1 may be formed from a polycrystalline silicon layer, a single-crystal silicon layer, or an amorphous silicon layer. For example, atomic layer deposition or chemical vapor deposition may be used to form the first semiconductor layer SL1.

[0076] Reference Figure 8 The first semiconductor layer SL1 and the vertical dielectric layer 140 can be anisotropically etched to form a first semiconductor pillar SP1 and a vertical insulator 145 in each channel via CH. Both the first semiconductor pillar SP1 and the vertical insulator 145 can be formed into a tube shape with its top and bottom open. The first semiconductor pillar SP1 and the vertical insulator 145 can partially expose the underlying semiconductor pattern LSP.

[0077] When the first semiconductor layer SL1 and the vertical dielectric layer 140 are anisotropically etched, over-etching can occur to form a first recessed region RS1 on the corresponding lower semiconductor pattern LSP.

[0078] A second semiconductor layer SL2 can be formed in the channel via CH. The second semiconductor layer SL2 can be formed conformally to not completely fill each channel via CH. The second semiconductor layer SL2 can partially fill each first recessed region RS1. The second semiconductor layer SL2 can electrically connect the lower semiconductor pattern LSP to the first semiconductor pillar SP1. The second semiconductor layer SL2 can include a semiconductor material having a single-crystal structure or a polycrystalline structure. For example, the second semiconductor layer SL2 can be formed from a polycrystalline silicon layer, a single-crystal silicon layer, or an amorphous silicon layer. For example, atomic layer deposition or chemical vapor deposition can be used to form the second semiconductor layer SL2.

[0079] Reference Figure 9 A buried dielectric layer can be formed to completely fill each interior of the channel via CH. The buried dielectric layer can be, for example, a silicon oxide layer formed using SOG (or spin-coated glass) technology. The upper portion of the second semiconductor layer SL2 and the buried dielectric layer can be recessed to form a second semiconductor pillar SP2 and a buried dielectric pattern 150 in each channel via CH. The first semiconductor pillar SP1 can also be recessed together with the second semiconductor layer SL2. The first semiconductor pillar SP1 and the second semiconductor pillar SP2 can constitute the channel structure CS.

[0080] The second semiconductor pillar SP2 can be formed into a tube shape, a hollow cylinder shape, or a cup shape with one end closed. The buried dielectric pattern 150 can be formed into a strip shape that fills the interior of the channel hole CH.

[0081] The conductive pad 137 can be formed to connect with the corresponding channel structure CS. The conductive pad 137 can be formed by filling the channel structure CS and the recessed portions of the buried dielectric pattern with a conductive material. For example, the conductive pad 137 can be formed from silicon doped with impurities of the same conductivity type as the substrate 100.

[0082] Reference Figure 10 The thin-layer structure TS can be patterned to form a trench TR exposing the substrate 100. For example, forming the trench TR may include: forming a second mask pattern (not shown) on the thin-layer structure TS; and performing an etching process in which the thin-layer structure TS is etched using the second mask pattern as an etching mask. During the etching process, the top surface of the substrate 100 may be over-etched. Therefore, the top surface of the substrate 100 may be recessed. After forming the trench TR, the second mask pattern may be removed. The trench TR may be formed to expose the sidewalls of the sacrificial layer 151 and the dielectric layer 110.

[0083] Reference Figure 11 The second recessed region RS2 can be formed by selectively removing the sacrificial layer 151 exposed to the trench TR. The second recessed region RS2 can be the empty space where the sacrificial layer 151 has been removed. The second recessed region RS2 can partially expose the vertical insulator 145. The second recessed region RS2 can also partially expose the underlying semiconductor pattern LSP.

[0084] A gate dielectric layer GI can be formed on the exposed sidewalls of each lower semiconductor patterned LSP. For example, the exposed sidewalls of the lower semiconductor patterned LSP can undergo an oxidation process to form a gate dielectric layer GI consisting of an oxide layer.

[0085] Reference Figure 12 A gate barrier layer GB, a metal barrier layer BM, and a metal layer MT can be sequentially formed to fill the second recessed region RS2. The gate barrier layer GB, the metal barrier layer BM, and the metal layer MT can be deposited conformally. The metal layer MT can be formed to have sufficient thickness to completely fill each second recessed region RS2. The metal layer MT can also be formed to not completely fill each trench TR.

[0086] The gate barrier layer GB may include, for example, an aluminum oxide layer or a hafnium oxide layer. The metal barrier layer BM may be, for example, a metal nitride layer, which may include one or more of, for example, titanium nitride (TiN) layers, tantalum nitride (TaN) layers, tungsten nitride (WN) layers, nickel nitride (NiN) layers, cobalt nitride (CoN) layers, and platinum nitride (PtN) layers. The metal layer MT may include, for example, one or more of, aluminum, copper, molybdenum, and cobalt.

[0087] Reference Figure 13The metal layer MT and the metal barrier layer BM can be etched to form the metal pattern MTP and the metal barrier pattern BMP, respectively. The etching of the metal layer MT and the metal barrier layer BM can be substantially similar to the above reference. Figures 1 to 3 The etching of the metal layer MT and the metal barrier layer BM is discussed. For example, the etching of the metal layer MT and the metal barrier layer BM may include causing a trench TR to receive an etching composition according to an example embodiment of this disclosure.

[0088] The gate electrode GE can be composed of a metal pattern MTP and a metal barrier pattern BMP formed in each second recessed region RS2. The gate electrodes GE that are vertically adjacent to each other can be spaced apart from each other by a dielectric layer 110.

[0089] Reference Figure 14 and Figure 15 The gate barrier pattern GBP can be formed by removing the gate barrier layer GB exposed to the trench TR. The gate barrier pattern GBP can be placed between the gate electrode GE and the vertical insulator 145. The stacked structure SS can be composed of alternating and repeating stacked gate electrodes GE and dielectric layer 110.

[0090] A common source region 120 can be formed in the substrate 100. The common source region 120 can be formed by performing ion implantation on the substrate 100 exposed to the trench TR. The common source region 120 can form a PN junction with the substrate 100.

[0091] The bit line plug BPLG can be configured to connect to the conductive pad 137, and the bit line BL can be configured to connect to the bit line plug BPLG. The bit line BL can be electrically connected to the channel structure CS through the bit line plug BPLG.

[0092] <Examples 4 and 5, and Comparative Examples 3 and 4>

[0093] Table 4 below lists the components of the etching compositions according to Examples 4 to 5 and the components of the etching compositions according to Comparative Examples 3 and 4.

[0094] [Table 4]

[0095] Element Example 4 Example 5 Comparative Example 3 Comparative Example 4 Metal oxide solubilizer (phosphoric acid) 65.8 65.8 65.8 65.8 Oxidizing agent (nitric acid) 16.5 16.5 16.5 16.5 Metal Etching Inhibitor TEA 0.5 EDADA 0.5 DETA 0.5 TETA 0.5 water margin margin margin margin Total (wt%) 100 100 100 100

[0096] Triethylamine (TEA) of Example 4 is an amine compound having one nitrogen atom and the formula N(CH2CH3)3. Ethylenediamine diacetate (EDADA) of Example 5 is an amine compound having two nitrogen atoms and the formula NH2CH2CH2NH2·2CH3COOH. Diethylenetriamine (DETA) of Comparative Example 3 is an amine compound having three nitrogen atoms and the formula HN(CH2CH2NH2)2. Triethylenetetramine (TETA) of Comparative Example 4 is an amine compound having four nitrogen atoms and the formula (CH2NHCH2CH2NH2)2.

[0097] [Experiment 3]

[0098] The etching compositions of Examples 4 and 5, as well as Comparative Examples 3 and 4, were used to etch the above-mentioned reference materials. Figure 12 and Figure 13 The metal layer MT and metal barrier layer BM discussed were subjected to an etching process. A tungsten layer was used as the metal layer MT, and a titanium nitride layer was used as the metal barrier layer BM. SEM images were used to determine the sidewall profiles of the metal pattern MTP and the metal barrier pattern BMP formed by the etching process.

[0099] Figure 16A An image showing a cross-section of the result formed by an etching process using the etching composition of Example 4 is displayed. Figure 16B An image showing a cross section of the product formed by an etching process using the etching composition of Comparative Example 3 is displayed. Figure 17 A graph is shown showing the profile error rate of the sidewalls of the obtained products formed by etching processes using the etching compositions of Examples 4 and 5, and Comparative Examples 3 and 4.

[0100] Reference Figure 16A and Figure 17 As can be determined from the images, the sidewalls of the metal pattern MTP and the metal barrier pattern BMP are formed smoothly due to the etching process performed using the etching compositions of Examples 4 and 5. For example, it can be observed that the sidewalls of the metal pattern MTP and the metal barrier pattern BMP formed according to some exemplary embodiments of this disclosure have a relatively low profile error rate.

[0101] Reference Figure 16B and Figure 17As can be determined from the images, the sidewalls of the metal pattern MTP and the metal barrier pattern BMP are formed with roughness due to the etching process performed using the etching compositions of Comparative Examples 3 and 4. For example, it can be observed that the sidewalls of the metal pattern MTP and the metal barrier pattern BMP formed according to the comparative examples of this disclosure have a relatively high profile error rate. In particular, when the metal etching inhibitor comprises an amine compound having three or more nitrogen atoms, it can be determined that the profile error rate increases significantly (see...). Figure 17 ).

[0102] Therefore, the etching compositions according to some example embodiments of this disclosure may use amine compounds having two or fewer nitrogen atoms as metal etching inhibitors. Thus, the above references... Figure 14 and Figure 15 The gate electrode GE of the semiconductor device under discussion can be formed with a good profile and without defects.

[0103] The etching composition according to this disclosure can etch the metal barrier layer and the metal layer at a relatively high rate. When the etching composition according to this disclosure is used to etch the metal barrier layer and the metal layer, the etch selectivity between the metal barrier layer and the metal layer can be maintained consistently over a long period of time.

[0104] This detailed description of the present disclosure should not be construed as limiting it to the exemplary embodiments set forth herein. The present disclosure is intended to cover various combinations, modifications, and variations of the present disclosure without departing from its spirit and scope. The appended claims should be construed as including other embodiments.

Claims

1. An etching composition for etching a metal barrier layer and a metal layer, the etching composition comprising: Oxidizing agent, wherein the oxidizing agent is selected from the group consisting of nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methanesulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, and combinations thereof; Metal etching inhibitor, said metal etching inhibitor comprising a compound represented by the following formula (1); and A metal oxide solubilizer, wherein the metal oxide solubilizer is selected from the group consisting of phosphoric acid, phosphates, carboxylic acids having 3 to 20 carbon atoms, and combinations thereof. （1） In formula (1), R1 and R2 are independently hydrogen, C1-C10 alkyl, C3-C10 alkenyl, C3-C10 alkynyl, or C1-C10 alkoxy. R3 is hydrogen, amino, C1-C10 alkylamino, C3-C10 arylamino, C1-C10 alkyl, C3-C10 alkenyl, C3-C10 alkynyl, or C1-C10 alkoxy. n is an integer equal to or greater than 1. R1, R2, and R3 are independently unsubstituted or substituted with hydroxyl groups, and The ratio of the etching rate of the metal layer to the etching rate of the metal barrier layer ranges from 1.0 to 2.

0. The metal layer includes at least one of tungsten, aluminum, copper, molybdenum, or cobalt. The metal barrier layer includes at least one of titanium nitride, tantalum nitride, tungsten nitride, nickel nitride, cobalt nitride, or platinum nitride. The amount of the metal etching inhibitor is from 0.01% to 10% by weight relative to the total weight of the etching composition.

2. The etching composition according to claim 1, wherein, The amount of the oxidant is 10% to 30% by weight relative to the total weight of the etching composition.

3. The etching composition according to claim 1, wherein the etching composition further comprises water. in, The amount of water is 10% to 30% by weight relative to the total weight of the etching composition.

4. An etching composition for etching a titanium nitride layer and a tungsten layer, the etching composition comprising: Oxidizing agent, wherein the oxidizing agent is selected from the group consisting of nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methanesulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, and combinations thereof; Metal etching inhibitors, said metal etching inhibitors comprising amine compounds having one or two amino groups; and A metal oxide solubilizer, wherein the metal oxide solubilizer is selected from the group consisting of phosphoric acid, phosphates, carboxylic acids having 3 to 20 carbon atoms, and combinations thereof. Wherein, the amine compound is a compound represented by the following formula (1), （1） In formula (1), R1 and R2 are independently hydrogen, C1-C10 alkyl, C3-C10 alkenyl, C3-C10 alkynyl, or C1-C10 alkoxy. R3 is hydrogen, amino, C1-C10 alkylamino, C3-C10 arylamino, C1-C10 alkyl, C3-C10 alkenyl, C3-C10 alkynyl, or C1-C10 alkoxy. n is an integer equal to or greater than 1. R1, R2, and R3 are independently unsubstituted or substituted with hydroxyl groups, and The ratio of the etching rate of the tungsten layer to the etching rate of the titanium nitride layer ranges from 1.0 to 2.

0. The amount of the metal etching inhibitor is from 0.01% to 10% by weight relative to the total weight of the etching composition.

5. The etching composition according to claim 4, wherein, The amount of the oxidant is 10% to 30% by weight relative to the total weight of the etching composition.

6. The etching composition according to claim 4, wherein the etching composition further comprises water. in, The amount of water is 10% to 30% by weight relative to the total weight of the etching composition.

7. The etching composition according to claim 4, wherein, The amine compounds include at least one of ethylenediamine, m-phenylenediamine, methyldiethanolamine, dimethylmonoethanolamine, ethyldiethanolamine, diethylmonoethanolamine, triethylamine, or tributylamine.

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