Semiconductor chip packaging method and lead frame for reducing cutting burrs

Abstract

The present invention discloses a semiconductor chip packaging method and a lead frame for reducing cutting burrs. The method comprises the following steps: using a packaged but uncut package lead frame, the package lead frame comprising a plurality of semiconductor units, each of the semiconductor units having a plurality of pins, a connecting rib connected between each of the pins of two adjacent semiconductor units that are positioned opposite each other, the middle of the two opposite pins being the centerline position, and the connecting rib being offset from the centerline position; performing a first cut, cutting the package lead frame using a cutting tool, the cutting direction of the cutting tool being from the position of the connecting rib toward the centerline position, and removing the connecting rib; thereby reducing burrs, reducing short circuit problems that may be caused in subsequent processes, and improving the process yield.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging technology, and in particular to a semiconductor chip packaging method and a lead frame thereof for reducing cutting burrs. Background Art

[0002] The Quad Flat No-Lead Package (QFNP) is an increasingly common chip packaging trend in the semiconductor industry. Its advantages include a small size, comparable to the Chip Scale Package (CSP), relatively low cost, high production yield, and superior coplanarity and heat dissipation for high-speed and power management circuits. Furthermore, the QFNP package eliminates the need for pins from all four sides, resulting in superior electrical performance compared to traditional packages that require multiple pins from the sides.

[0003] With the development of electronic technology and semiconductor packaging technology, the size of semiconductors is getting smaller and smaller, and the spacing between integrated circuit pins is also getting smaller and smaller. The semiconductor structure of the Quad Flat No-lead Package (QFNP) can best meet this requirement. However, due to the smaller spacing between adjacent pins, burrs often occur after cutting, causing the risk of short circuit in the finished product. This burr problem occurs when the large-area package lead frame is cut into individual semiconductor structures. The main reason is that the pins are usually made of copper material, which makes it have good conductivity, but copper material also has good ductility. When cutting, good ductility causes burrs to appear on the edge of the pin. If the burr is too long and connected to two pins, it will cause the risk of short circuit in the finished product. Figure 1A The figure shows a partial enlarged view of several pins that have been packaged but not yet cut. In the figure, pins 91 at opposite positions are connected by connecting parts 92. Several pins 91 are surrounded by encapsulation glue 93. The width of the cutting path 94 for the first cutting is shown by the upper and lower imaginary lines in the figure. Figure 1B As shown in FIG. 1 , a schematic diagram of the structure for the first cutting is shown. It can be found in the figure that burrs 95 appear on two adjacent pins 91 , and the burrs 95 are connected to the two pins 91 . When the electroplating and cutting operations are subsequently performed, it is easy to cause the problem of tin connection, which makes the finished product have the risk of short circuit. Summary of the Invention

[0004] The main purpose of the present invention is to provide a semiconductor chip packaging method and lead frame that reduce the generation of cutting burrs. The method mainly uses a designed lead frame and cuts it in a specific direction during the first cut. This can reduce the generation of burrs. If burrs do occur, they are unlikely to connect two pins, thereby improving the process yield.

[0005] To achieve the aforementioned objectives, the present invention adopts the following technical solutions:

[0006] The present invention provides a semiconductor chip packaging method for reducing cutting burrs. The method comprises the following steps: using a packaged but uncut package lead frame, the package lead frame comprising a plurality of semiconductor units, each of the semiconductor units having a plurality of pins, a connecting rib connecting each of the pins of two adjacent semiconductor units at opposite positions, the center position of the two adjacent pins being the center line, and the connecting rib being offset from the center line; and performing a first cut, using a cutting tool to cut the package lead frame, the cutting direction of the cutting tool being from the location of the connecting rib toward the center line, and removing the connecting rib.

[0007] The present invention is a lead frame for reducing cutting burrs, comprising: a plurality of lead frame units, each of which includes a die seat for placing a die; and a plurality of pins formed in each lead frame unit and distributed around the die seat. A connecting rib is connected between each of the two opposing pins in each lead frame unit, and the center position between the two opposing pins is the center position. The connecting rib deviates from and is a distance away from the center position.

[0008] As one of the preferred embodiments, the width of the connecting rib connected to each pin is smaller than the maximum width of each pin.

[0009] As one of the preferred embodiments, the package lead frame includes a lead frame and a packaging colloid coated on the lead frame, the lead frame includes a plurality of lead frame units, each lead frame unit includes a die seat, the plurality of pins distributed around the die seat, and a connecting rib connected to each of the two opposite pins, the connecting rib is a double-layer structure with different sizes, namely a top rib and the connecting rib.

[0010] As one of the preferred implementation schemes, the top rib and the connecting rib are in a stacked and connected double-layer structure, the top rib is connected to the connecting rib and each pin, and the connecting rib is connected between each pin corresponding to two adjacent units.

[0011] As one of the preferred embodiments, the lead frame has a first surface and a second surface that are opposite to each other, the top rib is located on the first surface, the connecting rib is located on the second surface, and when cutting, the cutting is carried out in the direction of the second surface.

[0012] As one of the preferred embodiments, the width of the connecting rib connected to the pin is smaller than the maximum width of the pin.

[0013] As one of the preferred embodiments, after the first cutting, the subsequent steps are: performing an electroplating operation to form a metal layer on the surface of the multiple pins and the top ribs; and performing a second cutting to remove the top ribs of the connecting ribs to form a single packaged semiconductor unit.

[0014] As one of the preferred embodiments, the metal layer is a tin layer or a tin alloy layer.

[0015] As one of the preferred embodiments, the connecting rib is tapered or curved, and a portion of the connecting rib contacts the center line between the two pins.

[0016] As one of the preferred embodiments, the connecting rib forms a convex portion on the top rib, and the convex portion extends in a direction away from the center line position.

[0017] As one of the preferred embodiments, the connecting rib forms a convex portion on the top rib, and the convex portion extends on both sides of the connecting rib.

[0018] As one of the preferred embodiments, the convex portion is in an arc shape or a right-angled geometric shape.

[0019] Compared to the prior art, the present invention reduces burrs generated during cutting in a semiconductor chip packaging method and lead frame thereof. A connecting rib is provided between two adjacent semiconductor units and two opposing pins, offset from the centerline. Because the connecting rib is offset from the centerline and the cutting direction is opposite to the offset direction, burrs generated between the two pins during the first cut are reduced. Furthermore, tin bridging and tin sticking are reduced during the final cut, eliminating the problem of pin signal shorting caused by tin bridging in the finished product and improving the process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A This is an enlarged view of a portion of an existing packaged lead frame that has not yet been cut.

[0021] Figure 1B This is a partial enlarged view of an existing packaged lead frame after the first cut.

[0022] Figure 2 This is a three-dimensional diagram of the package lead frame used in the present invention.

[0023] Figure 3 for Figure 2 Cross-sectional view of the AA surface.

[0024] Figure 4 It is a partially enlarged three-dimensional view of the first surface of the lead frame of the present invention.

[0025] Figure 5 This is a partially enlarged three-dimensional view of the second surface of the lead frame of the present invention.

[0026] Figure 6 This is an enlarged plan view of the connection between the connecting rib and the pin of the present invention.

[0027] Figures 7A to 7D Partially enlarged views of various embodiments of the lead frame used in the present invention.

[0028] Figure 8 Flowchart of the present invention.

[0029] Figure 9 It is a bottom view of the package lead frame of the present invention.

[0030] Figure 10 This is a plan view of the package lead frame of the present invention after the first cutting.

[0031] Figure 11 This is a plan view of the electroplating process for the package lead frame of the present invention.

[0032] Figure 12 This is a schematic plan view of the package lead frame of the present invention after the second cutting.

[0033] 91: pin; 92: connection part; 93: encapsulation colloid

[0034] 94: cutting path; 95: burr; 10: package lead frame

[0035] 20: Lead frame; 20A: Lead frame unit; 21: Die seat

[0036] 22: Pin; 23: Connecting rib; 231: Top rib

[0037] 232: Connecting bars; 232A: Connecting bars; 232B: Connecting bars

[0038] 232C: connecting ribs; 233A: convex part; 233B: convex part

[0039] 30: packaging colloid 40: die; 50: lead

[0040] 60: cutting road; 80: metal layer; 90: semiconductor unit;

[0041] L1: Width of connecting reinforcement L2: Maximum width L3: Width of connection. DETAILED DESCRIPTION

[0042] The technical solution of the present invention will be described clearly and completely below in conjunction with specific embodiments and accompanying drawings. It should be noted that when a component is referred to as being "mounted on or fixed to" another component, it means that it can be directly on the other component or there may also be a central component. When a component is considered to be "connected" to another component, it means that it can be directly connected to the other component or there may be a central component at the same time. In the illustrated embodiments, the directions such as up, down, left, right, front and back are relative and are used to explain that the structure and movement of different components in this case are relative. These representations are appropriate when the components are in the positions shown in the figures. However, if the description of the component positions changes, it is considered that these representations will also change accordingly.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which the present invention pertains. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] The present invention reduces the generation of cutting burrs on the lead frame structure, such as Figure 2 and 3 As shown, the package lead frame 10 includes a lead frame 20 and a packaging colloid 30, please refer to Figure 4 、 5 The lead frame 20 includes a plurality of lead frame units 20A, each of which includes a die pad 21, a plurality of pins 22 distributed around the die pad 21, and a connecting rib 23 connected to the plurality of pins 22. Figure 5 In the embodiment, only one lead frame unit 20A is shown. The actual number of lead frame units 20A may be determined by the manufacturer's design. Figure 2 and Figure 3 As shown, multiple semiconductor units 90 are formed. Figure 2 and Figure 3 In the embodiment shown, only four semiconductor units 90 are shown. At least one die 40 is mounted on the die pad 21, and each die 40 is connected to a corresponding pin 22 via a plurality of leads 50. The lead frame 10 of this embodiment is manufactured using conventional packaging techniques and will not be described in detail. However, the lead frame 20 structure employed in the present invention differs slightly from conventional techniques, as will be explained below.

[0045] like Figure 4 and Figure 5It is an enlarged view of the structure of the lead frame at different angles. The lead frame 20 includes several lead frame units 20A. For the sake of convenience, only the structure of one lead frame unit 20A is drawn in the subsequent figures. The area shown by the imaginary line in the figure is the area covered by one lead frame unit 20A. Each lead frame unit 20A is composed of a die seat 21, a plurality of pins 22 distributed around the die seat 21, and a connecting rib 23 connected to the plurality of pins 22. The connecting rib 23 is a double-layer structure with different sizes, which is a double-layer structure stacked and connected by a top rib 231 and a connecting rib 232. The top rib 231 is connected to a plurality of pins 22 and a plurality of connecting ribs 232, and the connecting rib 232 is connected between the two corresponding pins 22 of two adjacent lead frame units 20A. The lead frame 20 has a first surface and a second surface that are positioned opposite to each other. The first surface is the surface on which the die 40 is placed on the die seat 21, and is also the surface of the pin 22 for the lead 50 to connect the die 40. As shown Figure 4 As shown, the top rib 231 is located on the first side and connects many adjacent pins 22. Figure 5 As shown, on the second side of the lead frame 20, the connecting rib 232 is connected between two pins 22 at opposite positions. When cutting, the entire structure is turned over and cut from the second side. Figure 6 As shown, the centerline 24 (as indicated by the centerline) is located between two adjacent pins 22. The connecting rib 232 is offset from the centerline 24. In this embodiment, the connecting rib 232 is not located at the centerline 24 but is located on the same side as the centerline 24. That is, the connecting rib 232 is some distance away from the centerline 24. In this embodiment, the connecting rib width L1 is less than the maximum width L2 of the pins 22. The connecting rib width L1 where the connecting rib 232 connects to the pins 22 is less than the width L3 of the connection between the two opposing pins 22.

[0046] 7A to 7B FIG2 is a partial enlarged view of another embodiment of a lead frame for reducing cutting burrs according to the present invention. Figure 7A and Figure 7B The connecting rib 232A is tapered or the connecting rib 232B is curved, and a portion of the connecting ribs 232A and 232B contacts the centerline 24 defined between the two leads 22. The offset structure of the connecting ribs 232A and 232B not only reduces burrs generated during cutting but also increases the strength of the connecting rib 23, thereby preventing deformation of the lead frame during the packaging process.

[0047] Figures 7C to 7D The figure shows a partial enlarged view of another embodiment of a lead frame for reducing cutting burrs according to the present invention. The surface of the top rib 231 of the lead frame 20 has a connecting rib 232C. Figure 7C As shown, the connecting rib 232C forms a convex portion 233A, which is arc-shaped and formed on both sides of the connecting rib 232C. Figure 7D As shown, a protrusion 233B is provided on one side of connecting rib 232C. Protrusion 233B is at a right angle and extends away from centerline 24. Similar to the above-described embodiment, the offset structure of connecting rib 232C, combined with protrusions 233A and 233B, reduces burrs generated during cutting while increasing the strength of connecting rib 23 and preventing deformation of lead frame 20 during the packaging process. However, the present invention is not limited to this embodiment; conical or curved connecting rib structures and arc-shaped or right-angled protrusions can be combined to create various combined shapes.

[0048] Next, a detailed description is given of the semiconductor chip packaging method for reducing cutting burrs of the present invention. Figure 8 As shown, it is a flow chart of the present invention, and its steps include:

[0049] Step 801: Use a packaged and uncut lead frame 10. The package lead frame 10 includes a plurality of semiconductor units 90. Each semiconductor unit 90 has a plurality of pins 22. A connecting rib 232 is connected between each pin 22 of two adjacent semiconductor units 90. The middle of the two adjacent pins 22 is a centerline 24. The connecting rib 232 deviates from the centerline 24. Figure 9 As shown, it is a bottom view of the package lead frame 10. Since the encapsulation colloid 30 has been packaged above the lead frame 20, only the die pad 21, multiple pins 22 and the connecting rib 232 are exposed on the second surface of the lead frame 20. The imaginary line in the figure is the predetermined position and width of the cutting street 60.

[0050] In step 802, the first cut is performed by using a cutting tool to cut the package lead frame 10. The cutting direction of the cutting tool must be from the position of the connecting rib 232 toward the center line position 24, and the connecting rib 232 is removed. The cutting tool is a rotary cutting tool, and the rotation direction is from the position of the connecting rib 232 toward the center line position. In this embodiment, only the connecting rib 232 at the bottom layer of the connecting rib 23 is removed, and the top layer rib 231 remains. The top layer rib 231 is still connected to many pins 22. In the present invention, because the connecting rib 232 deviates from the center line position 24, and the cutting direction is opposite to the deviation direction, the generation of burrs can be reduced. If burrs are generated, they will not be connected to the two adjacent pins 22 on the same side of the semiconductor unit 90, thereby reducing the short circuit problem that may occur in subsequent processing.

[0051] The subsequent operation process is similar to the conventional one, such as step 803, electroplating operation is performed to form a metal layer 80 on the surface of the plurality of pins 22 and the top rib 231. This operation requires removing the package lead frame 10 and placing it in another electroplating tank for electroplating. Figure 11 As shown, a metal layer 80 is formed on the exposed surfaces of the die pad 21 , the leads 22 and the top rib 231 . In this embodiment, the metal layer 80 is a tin layer or a tin alloy layer.

[0052] Step 804, perform a second cutting to remove the top rib 231 of the connecting rib 23, forming a single semiconductor unit 90 that has been packaged. Figure 12 As shown, a cutting tool is used to completely cut the package lead frame 10, simultaneously removing the connecting rib 23 and the package body 30 therein, forming a separate semiconductor unit 90. Only the die pad 21 and several pins 22 distributed around it remain at the bottom of the semiconductor unit 90. Because the present invention reduces burrs in step 802, the subsequent electroplating process prevents the metal layer 80 from adhering to the burred surface, which could cause tin bonding between adjacent pins 22. Therefore, during the second cutting (complete cutting), the metal layer 80 is less likely to be stretched and diffused, causing tin to adhere to two adjacent pins 22. Therefore, the finished product processed by the method of the present invention is less likely to suffer from pin short circuits. The method of the present invention can reduce burrs and effectively solve the tin bonding problem, thereby improving the process yield.

[0053] In summary, the present invention provides a semiconductor chip packaging method and lead frame for reducing cutting burrs. The lead frame 20 includes a designed lead frame wherein the connecting rib 23 connecting two adjacent pins 22 has a double-layer structure having different sizes. Furthermore, the connecting rib 232 removed during the first cut is offset from the centerline 24 and the cutting direction is opposite to the offset direction. This reduces burrs connecting the two pins 22 during the first cut. Furthermore, the occurrence of bridging and tin sticking during the final cut is reduced, eliminating the potential for short circuits in the finished product, thereby improving process yield.

[0054] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. That is, all equivalent changes and modifications made according to the scope of the patent application of the present invention are covered by the patent scope of the present invention.

Claims

1. A semiconductor chip packaging method for reducing cutting burrs, characterized in that: The following steps are involved: A packaged but uncut lead frame is used, the packaged lead frame comprising a plurality of semiconductor units, each semiconductor unit having a plurality of pins, a connecting rib connecting each pin of two adjacent semiconductor units that are positioned opposite each other, the center of each of the two adjacent pins being the center line, and the connecting rib being offset from the center line; as well as Performing the first cutting, using a cutting tool to cut the package lead frame, the cutting direction of the cutting tool must be from the position of the connecting rib toward the center line position, and the connecting rib is removed.

2. The semiconductor chip packaging method for reducing cutting burrs according to claim 1, wherein: The width of the connecting rib connected to each pin is smaller than the maximum width of each pin.

3. The semiconductor chip packaging method for reducing cutting burrs according to claim 1, wherein: The package lead frame includes a lead frame and a packaging colloid coated on the lead frame. The lead frame includes multiple lead frame units. Each lead frame unit includes a die seat, the multiple pins distributed around the die seat, and connecting ribs connected to each of the two opposite pins. The connecting ribs are a double-layer structure with different sizes, namely a top rib and the connecting rib.

4. The semiconductor chip packaging method for reducing cutting burrs according to claim 3, wherein: The top rib and the connecting rib are in a stacked and connected double-layer structure. The top rib is connected to the connecting rib and each of the pins. The connecting rib is connected between each of the pins that are opposite to each other.

5. The semiconductor chip packaging method for reducing cutting burrs according to claim 4, wherein: The lead frame has a first surface and a second surface that are opposite to each other. The top rib is located on the first surface, and the connecting rib is located on the second surface. Cutting is performed along the second surface.

6. The semiconductor chip packaging method for reducing cutting burrs according to claim 3, wherein: After making the first cut, the next steps are: Performing electroplating to form a metal layer on the surfaces of the plurality of pins and the top rib; and A second cutting is performed to remove the top layer ribs of the connecting ribs to form a single packaged semiconductor unit.

7. The semiconductor chip packaging method for reducing cutting burrs according to claim 6, wherein: The metal layer is a tin layer or a tin alloy layer.

8. A lead frame for reducing cutting burrs, characterized in that: Include: A plurality of lead frame units, each of the lead frame units comprising a die seat for placing a die; as well as A plurality of pins are formed in each lead frame unit and are distributed around the die pad. A connecting rib is connected between each of the two opposing pins in each lead frame unit. The center point between the two opposing pins is the center line position, and the connecting rib deviates from and is a distance away from the center line position.

9. The lead frame structure for reducing cutting burrs according to claim 8, wherein: The width of the connecting rib connected to each of the pins is smaller than the maximum width of each of the pins.

10. The lead frame structure for reducing cutting burrs according to claim 8, wherein: Each of the pins is connected to a connecting rib, and the connecting rib is a double-layer structure with different sizes, including a top rib and the connecting rib.

11. The lead frame structure for reducing cutting burrs according to claim 10, wherein: The top rib and the connecting rib are in a double-layer structure connected by stacking. The top rib is connected to the connecting rib and each of the pins. The connecting rib is connected between each of the two opposite pins.

12. The lead frame structure for reducing cutting burrs according to claim 8, wherein: The connecting rib is tapered or curved, and a portion of the connecting rib contacts the center line between the two pins.

13. The lead frame structure for reducing cutting burrs according to claim 10, wherein: The connecting rib forms a convex portion on the top rib, and the convex portion extends in a direction away from the center line position.

14. The lead frame structure for reducing cutting burrs according to claim 10, wherein: The connecting rib forms a convex portion on the top rib, and the convex portion extends on both sides of the connecting rib.

15. The lead frame structure for reducing cutting burrs according to claim 13, wherein: The convex portion is in an arc shape or a right-angled geometric shape.

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