Gate driving circuit, display panel, driving method and display device

Abstract

A gate drive circuit, a display panel, a driving method and a display device. The gate drive circuit (110) comprises an input module (11), a pull-up node (PU), an output module (12), a first pull-down node (PD1), a first pull-down node control module (13) and a first suppression module (14); the first pull-down node control module (13) controls the communication between the first connection node (J1) and the first pull-down node (PD1) under the control of the potential of the pull-up node (PU), controls the signal provided by the second signal end (D2) to input to the first pull-down node (PD1) under the control of the potential of the first pull-down control node (PD_CN1); the first suppression module (14) inputs the signal provided by the first level signal end (V1) to the first connection node (J1) under the control of the potential of the pull-up node (PU).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a gate driving circuit, a display panel, a driving method, and a display device. Background Technology

[0002] With the development of display technology, wearable display products are becoming increasingly popular. Wearable display products can be worn directly on the body or integrated into the user's clothing and accessories. These products can achieve powerful functions through software support and data interaction. For example, smart wearable bracelets can not only be used as watches to display the time, but also monitor vital signs and interact with mobile devices. Wearable display products are in a sleep state when not in use and are woken up when needed. Because wearable products often perform frequent and repetitive wake-up actions, coupled with factors such as operating temperature and usage time, wearable products are prone to jitter and horizontal lines, affecting display quality. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a gate driving circuit, including an input module, a pull-up node, an output module, a first pull-down node, a first pull-down node control module, and a first suppression module;

[0004] The input module is electrically connected to the input control terminal, the first input terminal and the pull-up node respectively, and is used to input the signal input from the first input terminal to the pull-up node under the control of the first input control terminal;

[0005] The output module is electrically connected to the pull-up node, the first signal terminal, and the output terminal, respectively, and is used to output the signal input from the first signal terminal through the output terminal under the control of the potential of the pull-up node;

[0006] The first pull-down node control module is electrically connected to the second signal terminal, the first pull-down control node, the first pull-down node, the pull-up node, and the first connection node, respectively. It is used to control the potential of the first pull-down control node under the control of the potential of the second signal terminal and the pull-up node, and to control the connection between the first connection node and the first pull-down node under the control of the potential of the pull-up node. Under the control of the potential of the first pull-down node, it controls the signal provided by the second signal terminal to be input to the first pull-down node.

[0007] The first suppression module is electrically connected to the pull-up node, the first connection node, and the first level signal terminal, respectively, and is used to input the signal provided by the first level signal terminal to the first connection node under the control of the potential of the pull-up node.

[0008] Optionally, the first suppression module includes a first sub-circuit, which is electrically connected to the pull-up node, the first connection node, and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the first connection node under the control of the potential of the pull-up node.

[0009] Optionally, the first pull-down node control module is also electrically connected to the second connection node, and is used to input the signal provided by the second signal terminal to the first pull-down control node under the control of the second signal terminal, and to control the connection between the first pull-down control node and the second connection node under the control of the potential of the pull-up node;

[0010] The first suppression module is also electrically connected to the second connection node, and is used to input the signal provided by the first level signal terminal to the second connection node under the control of the potential of the pull-up node.

[0011] Optionally, the first suppression module further includes a second sub-circuit, which is electrically connected to the pull-up node, the second connection node, and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the second connection node under the control of the potential of the pull-up node.

[0012] Optionally, the gate driving circuit described in at least one embodiment of this disclosure further includes a first noise reduction module;

[0013] The first noise reduction module is electrically connected to the pull-up node, the output terminal, the first pull-down node, and the first level signal terminal, respectively, and is used to input the signal provided by the first level signal terminal to the pull-up node and / or the output terminal under the potential control of the first pull-down node.

[0014] Optionally, the gate drive circuit described in at least one embodiment of this disclosure further includes a reset module, which is electrically connected to a pull-up node, a second input terminal, and a reset signal terminal, respectively, and is used to input the signal input from the second input terminal to the pull-up node under the control of the reset signal terminal.

[0015] Optionally, the gate drive circuit described in at least one embodiment of this disclosure further includes a pull-down holding module, which is electrically connected to the output terminal, the third signal terminal and the first level signal terminal respectively, and is used to input the signal input from the first level signal terminal to the output terminal under the control of the third signal terminal.

[0016] Optionally, the gate drive circuit described in at least one embodiment of this disclosure further includes an initial reset module, which is electrically connected to the pull-up node, the initial signal terminal and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the pull-up node under the control of the initial signal terminal.

[0017] Optionally, the input module includes a first transistor, the gate of which is electrically connected to the input control terminal, the first electrode of which is electrically connected to the first input terminal, and the second electrode of which is electrically connected to the pull-up node.

[0018] Optionally, the output module includes a second transistor and a first capacitor;

[0019] The gate of the second transistor is electrically connected to the pull-up node, the first terminal of the second transistor is electrically connected to the first signal terminal, and the second terminal of the second transistor is electrically connected to the output terminal.

[0020] The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the output terminal.

[0021] Optionally, the first drop-down node control module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0022] The gate and the first terminal of the sixth transistor are both electrically connected to the second signal terminal, and the second terminal of the sixth transistor is electrically connected to the gate of the third transistor; the gate of the third transistor is electrically connected to the first pull-down control node.

[0023] The first terminal of the third transistor is electrically connected to the second signal terminal, and the second terminal of the third transistor is electrically connected to the first pull-down node;

[0024] The gate of the fourth transistor is electrically connected to the pull-up node, the first terminal of the fourth transistor is electrically connected to the first pull-down node, and the second terminal of the fourth transistor is electrically connected to the first connection node.

[0025] The gate of the fifth transistor and the gate of the fourth transistor are both electrically connected to the pull-up node. The first terminal of the fifth transistor and the second terminal of the sixth transistor are both electrically connected to the gate of the third transistor. The second terminal of the fifth transistor is electrically connected to the second connection node.

[0026] Optionally, the first noise reduction module includes a seventh transistor and an eighth transistor;

[0027] The gate of the seventh transistor is electrically connected to the first pull-down node, the first terminal of the seventh transistor is electrically connected to the pull-up node, and the second terminal of the seventh transistor is electrically connected to the first level signal terminal.

[0028] The gate of the eighth transistor is electrically connected to the first pull-down node, the first terminal of the eighth transistor is electrically connected to the output terminal, and the second terminal of the eighth transistor is electrically connected to the first level signal terminal.

[0029] Optionally, the first sub-circuit includes a ninth transistor, the gate of which is electrically connected to the pull-up node, the first terminal of which is electrically connected to the second terminal of the fourth transistor, and the second terminal of which is electrically connected to the first level signal terminal.

[0030] Optionally, the second sub-circuit includes a tenth transistor, the gate of which is electrically connected to the pull-up node and the gate of the ninth transistor, the first terminal of which is electrically connected to the second terminal of the fifth transistor, and the second terminal of which is electrically connected to the first level signal terminal.

[0031] Optionally, the reset module includes an eleventh transistor, the gate of which is electrically connected to the reset signal terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the second input terminal.

[0032] Optionally, the pull-down holding module includes a twelfth transistor, the gate of which is electrically connected to the third signal terminal, the first terminal of which is electrically connected to the output terminal, and the second terminal of which is electrically connected to the first level signal terminal.

[0033] Optionally, the initial reset module includes a thirteenth transistor, the gate of which is electrically connected to the initial signal terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the first level signal terminal.

[0034] Optionally, the gate drive circuit described in at least one embodiment of this disclosure further includes a second pull-down node control module, a second pull-down node, a second noise reduction module, and a second suppression module;

[0035] The second pull-down node control module is electrically connected to the fourth signal terminal, the second pull-down node, the second pull-down control node, the pull-up node, the third connection node, and the fourth connection node, respectively. It is used to input the signal provided by the fourth signal terminal to the second pull-down control node under the control of the potential of the pull-up node, and to control the connection between the second pull-down control node and the fourth connection node under the control of the potential of the second pull-down control node. It is also used to input the signal provided by the fourth signal terminal to the second pull-down node under the control of the potential of the second pull-down control node, and to control the connection between the second pull-down node and the third connection node under the control of the potential of the pull-up node.

[0036] The second noise reduction module is electrically connected to the pull-up node, the output terminal, the second pull-down node, and the first level signal terminal, respectively, and is used to input the signal provided by the first level signal terminal to the pull-up node and / or the output terminal under the potential control of the second pull-down node;

[0037] The second suppression module is electrically connected to the pull-up node, the third connection node and the first level signal terminal respectively, and is used to input the signal provided by the first level signal terminal to the third connection node under the control of the potential of the pull-up node.

[0038] Optionally, the second suppression module includes a third sub-circuit, which is electrically connected to the pull-up node, the third connection node, and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the third connection node under the control of the potential of the pull-up node.

[0039] Optionally, the second suppression module is also electrically connected to the fourth connection node, and is used to input the signal provided by the first level signal terminal to the fourth connection node under the control of the potential of the pull-up node;

[0040] The second suppression module further includes a fourth sub-circuit, which is electrically connected to the pull-up node, the fourth connection node and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the fourth connection node under the control of the potential of the pull-up node.

[0041] Optionally, the second drop-down node control module includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

[0042] The gate and first terminal of the seventeenth transistor are both electrically connected to the fourth signal terminal, and the second terminal of the seventeenth transistor is electrically connected to the gate of the fourteenth transistor; the second terminal of the seventeenth transistor is electrically connected to the second pull-down control node.

[0043] The first terminal of the fourteenth transistor is electrically connected to the fourth signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the second pull-down node;

[0044] The gate of the fifteenth transistor is electrically connected to the pull-up node, the first terminal of the fifteenth transistor is electrically connected to the second pull-down node, and the second terminal of the fifteenth transistor is electrically connected to the third connection node.

[0045] The gate of the sixteenth transistor is electrically connected to the gate of the fifteenth transistor and the pull-up node. The first terminal of the sixteenth transistor is electrically connected to the second terminal of the seventeenth transistor and the gate of the fourteenth transistor. The second terminal of the sixteenth transistor is electrically connected to the fourth connection node.

[0046] Optionally, the third sub-circuit includes an eighteenth transistor, and the fourth sub-circuit includes a nineteenth transistor;

[0047] The gate of the eighteenth transistor is electrically connected to the pull-up node, the first terminal of the eighteenth transistor is electrically connected to the second terminal of the fifteenth transistor, and the second terminal of the eighteenth transistor is electrically connected to the first level signal terminal.

[0048] The gate of the nineteenth transistor is electrically connected to the pull-up node and the gate of the eighteenth transistor. The first terminal of the nineteenth transistor is electrically connected to the second terminal of the sixteenth transistor. The second terminal of the nineteenth transistor is electrically connected to the first level signal terminal.

[0049] Optionally, the second noise reduction module includes a twentieth transistor and a twenty-first transistor;

[0050] The gate of the twentieth transistor is electrically connected to the second pull-down node, the first terminal of the twentieth transistor is electrically connected to the pull-up node, and the second terminal of the twentieth transistor is electrically connected to the first level signal terminal.

[0051] The gate of the 21st transistor is electrically connected to the second pull-down node, the first terminal of the 21st transistor is electrically connected to the output terminal, and the second terminal of the 21st transistor is electrically connected to the first level signal terminal.

[0052] In a second aspect, embodiments of this disclosure provide a shift register including multiple cascaded gate drive circuits as described above.

[0053] In a third aspect, embodiments of this disclosure provide a display panel including the shift register described above.

[0054] In a fourth aspect, embodiments of this disclosure provide a driving method for a display panel, wherein the working time of the display panel includes a wake-up phase, wherein the wake-up phase includes a first phase, a transition phase, and a second phase, the first phase being a phase in which no data signal is written to the display panel, and the second phase being a phase in which a data signal is written to the display panel.

[0055] The display panel includes multiple cascaded gate driving circuits, each gate driving circuit including an input module, a pull-up node, an output module, a first pull-down node, and a first pull-down node control module.

[0056] The input module is electrically connected to the input control terminal, the first input terminal and the pull-up node respectively, and is used to input the signal input from the first input terminal to the pull-up node under the control of the first input control terminal;

[0057] The output module is electrically connected to the pull-up node, the first signal terminal, and the output terminal, respectively, and is used to output the signal input from the first signal terminal through the output terminal under the control of the potential of the pull-up node;

[0058] The first pull-down node control module is electrically connected to the second signal terminal, the first pull-down node, the first pull-down control node, the pull-up node, the first connection node, and the second connection node, respectively. It is used to input the signal provided by the second signal terminal to the first pull-down control node under the control of the second signal terminal, and to control the connection between the first pull-down control node and the second connection node under the control of the potential of the pull-up node. It is also used to input the signal provided by the second signal terminal to the first pull-down node under the control of the potential of the first pull-down control node, and to control the connection between the first pull-down node and the first connection node under the control of the potential of the pull-up node.

[0059] The driving method for the display panel includes:

[0060] During at least a portion of the time included in the conversion phase, under the control of the trigger signal, an effective level is input to the second signal terminal so that the first pull-down node control module controls the pull-up of the first pull-down node to a high potential.

[0061] Optionally, the driving method for the display panel includes:

[0062] During the conversion phase, under the control of the trigger signal, an effective level is input to the second signal terminal.

[0063] Optionally, the gate driving circuit further includes a second pull-down node control module; the driving method for the display panel further includes:

[0064] When a valid level is input to the second signal terminal, the second pull-down node control module controls the pull-up of the second node's potential.

[0065] Optionally, the step of inputting an effective level to the second signal terminal under the control of the trigger signal includes:

[0066] The trigger signal is converted from a first voltage signal to a second voltage signal to control the input of an effective level to the second signal terminal.

[0067] In a fifth aspect, embodiments of this disclosure provide a display device including the display panel described above, the display device further including a driver chip, the driver chip including a trigger signal generation module and a signal providing module;

[0068] The trigger signal generation module is used to generate a trigger signal to the signal providing module;

[0069] The signal providing module is used to control the input of a valid level to the second signal terminal during at least a portion of the time included in the conversion phase, under the control of the trigger signal, so that the first pull-down node control module can pull up the potential of the first pull-down node. Attached Figure Description

[0070] Figure 1 This is a structural diagram of the relevant display panel;

[0071] Figure 2 This is a structural diagram of the relevant display panel;

[0072] Figure 3 In related technologies, it displays abnormal electrical waveforms;

[0073] Figure 4 This is a schematic diagram of the potential of the drop-down node before and after the reliability test;

[0074] Figure 5 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0075] Figure 6 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0076] Figure 7 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0077] Figure 8 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0078] Figure 9 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0079] Figure 10 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0080] Figure 11 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0081] Figure 12 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0082] Figure 13 This is a circuit diagram of the gate driving circuit according to at least one embodiment of the present disclosure;

[0083] Figure 14 This is a public announcement Figure 13 The timing diagram shows the operation of at least one embodiment of the gate drive circuit.

[0084] Figure 15A This is a simulation waveform of the potential of the first pull-down node PD1 before the addition of the ninth transistor M9 and the tenth transistor M10.

[0085] Figure 15B This is a simulation waveform of the potential of the first pull-down node PD1 after the addition of the ninth transistor M9 and the tenth transistor M10.

[0086] Figure 16 This is a circuit diagram of the gate driving circuit according to at least one embodiment of the present disclosure;

[0087] Figure 17A This is a simulation waveform of the potential of the first pull-down node PD1 before the addition of the ninth transistor M9 and the tenth transistor M10.

[0088] Figure 17B This is a simulation waveform of the potential of the first pull-down node PD1 after the addition of the ninth transistor M9 and the tenth transistor M10.

[0089] Figure 18 This is a circuit diagram of the gate driving circuit according to at least one embodiment of the present disclosure;

[0090] Figure 19 This is a public announcement Figure 18 The timing diagram shows the operation of at least one embodiment of the gate drive circuit.

[0091] Figure 20 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0092] Figure 21 This is a structural diagram of the gate drive circuit according to at least one embodiment of the present disclosure;

[0093] Figure 22 This is a circuit diagram of the gate driving circuit according to at least one embodiment of the present disclosure;

[0094] Figure 23 This is a circuit diagram of the gate driving circuit according to at least one embodiment of the present disclosure;

[0095] Figure 24 This is a structural diagram of the driver chip in the display device described in the embodiments of this disclosure. Detailed Implementation

[0096] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0097] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0098] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual scale and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0099] In the embodiments of this disclosure, when the transistor is a thin-film transistor or a MOS (metal-oxide-semiconductor) transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0100] See Figure 1 and Figure 2The display device may include a display panel 100 and a timing controller 200. The display panel 100 may include multiple pixel units arranged in an array, multiple gate lines GA (e.g., first row gate line GA1, second row gate line GA2, third row gate line GA3, fourth row gate line GA4), multiple data lines DA (e.g., first column data line DA1, second column data line DA2, third column data line DA3), a gate driving circuit 110, and a source driving circuit 120. The gate driving circuit 110 is coupled to the first row gate line GA1, second row gate line GA2, third row gate line GA3, and fourth row gate line GA4, respectively, and the source driving circuit 120 is coupled to the first column data line DA1, second column data line DA2, and third column data line DA3, respectively. The timing controller 200 may input control signals to the gate driving circuit 110 via a level shift circuit, thereby driving the first row gate line GA1, second row gate line GA2, third row gate line GA3, and fourth row gate line GA4. The timing controller 200 inputs a signal to the source drive circuit 120, causing the source drive circuit 120 to input data voltage to the data lines, thereby charging the sub-pixel SPX and enabling the sub-pixel SPX to input the corresponding data voltage to achieve the screen display function. For example, the number of source drive circuits 120 can be set to two, with one source drive circuit 120 connected to half of the data lines and the other source drive circuit 120 connected to the other half. Of course, the number of source drive circuits 120 can also be set to one, three, four, or more, which can be designed and determined according to the actual application requirements and is not limited here. For example, the gate drive circuits are arranged on both sides of the display panel to achieve dual-sided driving; they can also be arranged on one side of the display panel or on both sides of the display panel, but driving different rows of displays, and are not limited here.

[0101] For example, each pixel unit includes multiple sub-pixels (SPX). For instance, a pixel unit may include red, green, and blue sub-pixels, allowing for color mixing via red-green-blue blending to achieve color display. Alternatively, a pixel unit may include red, green, blue, and white sub-pixels, also allowing for color mixing via red-green-blue-white blending to achieve color display. Of course, in practical applications, the emission color of the sub-pixels within a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0102] See Figure 2As shown, each sub-pixel SPX includes a transistor 01 and a pixel electrode 02. A row of sub-pixels SPX corresponds to a row of gate lines, and a column of sub-pixels SPX corresponds to a column of data lines. The gate of transistor 01 is electrically connected to the corresponding gate line, the source of transistor 01 is electrically connected to the corresponding data line, and the drain of transistor 01 is electrically connected to the corresponding pixel electrode 02. It should be noted that the pixel array structure of this disclosure can also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce the number of data lines by half, meaning it includes some data lines between adjacent columns of pixels, but does not include data lines between adjacent columns of pixels. The specific pixel arrangement structure and the arrangement of data lines and scan lines are not limited.

[0103] It should be noted that the display panel in this embodiment can be a liquid crystal display panel. Exemplarily, a liquid crystal display panel generally includes an upper substrate and a lower substrate of a cell, and liquid crystal molecules encapsulated between the upper and lower substrates. When displaying an image, a voltage difference exists between the data voltage applied to the pixel electrode of each sub-pixel SPX and the common electrode voltage on the common electrode. This voltage difference can form an electric field, causing the liquid crystal molecules to deflect under the influence of this electric field. Because different intensities of electric fields cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixel SPX varies, enabling the sub-pixel SPX to achieve different grayscale brightness levels, thereby realizing image display.

[0104] The following description uses a liquid crystal display panel as the display panel in the embodiments of this disclosure, and the pixel unit includes red sub-pixels, green sub-pixels and blue sub-pixels as examples. However, readers should know that the colors of the sub-pixels SPX included in the liquid crystal display panel are not limited to these.

[0105] For display products, such as wearable displays, they are in a sleep state when not in use and will be woken up when needed. Wake-up refers to the process of turning on the switch of the whole device (or the lighting device) to light up the screen. Because wearable products often perform repeated wake-up actions frequently, coupled with factors such as operating temperature and usage time, wearable products are prone to flickering and horizontal lines, which affect display quality.

[0106] The discloser discovered that in wearable display products, the wake-up time of the display panel includes three sequentially set stages: a first stage (the first stage is the internal frequency stage), a conversion stage (the conversion stage is the internal frequency to external frequency stage, also known as the frequency tracking stage), and a second stage (the second stage is the external frequency stage). The reason for the horizontal lines appearing on the display is twofold: firstly, in the wake-up sequence, during the first frame of the external frequency stage, the potential of the pull-down node in the gate drive circuit drops significantly, resulting in display defects; secondly, the stability of the pull-down node control module in the gate drive circuit decreases after reliability testing, making it easier to pull down the potential of the pull-down node in wake-up mode.

[0107] More specifically, in wearable display products, the wake-up time is divided into three stages: The first stage is the internal frequency stage, which occurs after the display device is powered on and the driver IC (integrated circuit) operates internally (i.e., black hole insertion). During this stage, the driver IC does not provide data signals to the display panel's data lines, and the gate drive circuit operates normally. The second stage is the frequency tracking stage, which is the process of synchronizing the driver IC with the display screen. During the frequency tracking stage, the driver IC does not provide start signals and clock signals to the gate drive circuit, and the gate drive circuit does not provide corresponding gate drive signals. However, reference... Figure 3 From the abnormal electrical waveform diagram, it can be seen that the potential of the pull-down node PD drops abnormally at this time. For example, the potential of the pull-down node PD may be -10.6V at this time. The second stage S2 is the external frequency stage, that is, the stage in which the IC drives the screen to display normally. During the transition between internal and external frequencies (i.e., transition phase S0), the potential of the pull-up node PU in the last row of the display panel remains at 0V until the start of the first frame of the external frequency. At this time, the potential of the pull-down node PD is -10.6V. After entering the external frequency phase, the potential of the pull-down node PD needs to be pulled up to a high potential, such as above 10.0V. Due to the large voltage difference between -10.6V and 10.0V and above, the pull-down node PD cannot be pulled up to the normal reference voltage. After the high-temperature reliability test, such as the high-temperature test at 60°C or above, the potential of the pull-down node PD becomes lower than the reference voltage. That is, the high-temperature reliability test will further deteriorate the instability of the potential of the pull-down node PD. At this time, the gate drive circuit is in an unstable working state. When a wake-up operation is performed, it will cause display defects such as horizontal lines.

[0108] After the reliability test, referring to Table 1, the characteristic changes of the transistors after 20 days of testing at 60℃ are shown. After the reliability test, the turn-on current Ion3 of the third transistor M3 and the turn-on current Ion6 of the sixth transistor M6 will decrease, while the off-state current Ioff4 of the fourth transistor M4 and the off-state current Ioff5 of the fifth transistor M5 will increase. The decrease in turn-on current Ion will lead to insufficient charging of the pull-down node PD, while the increase in off-state current Ioff will lead to an increase in the leakage current of the pull-down node PD. As a result, the potential of the pull-down node PD cannot be maintained at the normal voltage reference level, thus reducing the stability of the potential of the pull-down node PD.

[0109] Table 1

[0110]

[0111] like Figure 4 As shown, after reliability testing, such as high temperature or high humidity testing, such as testing at 60℃ or 85℃, the turn-on current Ion3 of the third transistor M3 and the turn-on current Ion6 of the sixth transistor M6 decrease, resulting in insufficient charging of the pull-down node PD. The off-state current Ioff4 of the fourth transistor M4 and the off-state current Ioff5 of the fifth transistor M5 increase, resulting in increased leakage current. The PD's potential cannot maintain a normal voltage level.

[0112] like Figure 5 As shown, the gate drive circuit described in this embodiment includes an input module 11, a pull-up node PU, an output module 12, a first pull-down node PD1, a first pull-down node control module 13, and a first suppression module 14.

[0113] The input module 11 is electrically connected to the input control terminal I1, the first input terminal VDS and the pull-up node PU, respectively, and is used to input the signal input from the first input terminal VDS to the pull-up node PU under the control of the first input control terminal I1.

[0114] The output module 12 is electrically connected to the pull-up node PU, the first signal terminal D1 and the output terminal Gn respectively, and is used to output the signal input from the first signal terminal D1 through the output terminal Gn under the control of the potential of the pull-up node PU.

[0115] The first pull-down node control module 13 is electrically connected to the second signal terminal D2, the first pull-down control node PD_CN1, the first pull-down node PD1, the pull-up node PU, and the first connection node J1, respectively. It is used to control the potential of the first pull-down control node PD_CN1 under the control of the potential of the second signal terminal D2 and the pull-up node PU, and to control the connection between the first connection node J1 and the first pull-down node PD1 under the control of the pull-up node PU. Under the control of the potential of the first pull-down node PD1, it controls the signal provided by the second signal terminal D2 to be input to the first pull-down node PD1.

[0116] The first suppression module 14 is electrically connected to the pull-up node PU, the first connection node JI1 and the first level signal terminal V1 respectively, and is used to input the signal provided by the first level signal terminal V1 to the first connection node J1 under the control of the pull-up node PU.

[0117] In at least one embodiment of this disclosure, the first signal terminal D1 may be a clock signal terminal K1, the second signal terminal D2 may be a first control voltage terminal GCH, and the first level signal terminal V1 may be a low voltage terminal VGL, but is not limited thereto.

[0118] When the display panel described in this embodiment is working, by adding a first suppression module 14, the leakage current between the first level signal terminal V1 and the first pull-down node PD1 is reduced, thereby enhancing the stability of the potential of the first pull-down node PD1. This ensures that the potential of the first pull-down node PD1 will not be pulled down significantly during the transition phase, and that the potential of the first pull-down node PD1 can be maintained at a higher potential after entering the second phase, thus avoiding wake-up jitter and horizontal line defects.

[0119] The display panel described in this embodiment can be applied to wearable products. In related technologies, wearable products often perform frequent wake-up actions, and due to the influence of other factors (temperature, usage time, etc.), during the wake-up process, the potential of the first pull-down node PD1 is severely pulled down for a period of time at the beginning of the second stage, which easily leads to jitter and horizontal stripe defects. The root cause of the horizontal stripe defects is that after a long-term high-temperature reliability test, the characteristics of the transistors included in the first pull-down node control module 13 drift, the stability decreases, the turn-on current Ino of the transistors included in the first pull-down node control module 13 for raising the potential of the first pull-down node PD1 decreases, and the pull-up capability of the second signal terminal D2 for the first pull-down node PD1 is insufficient; the leakage current Ioff of the transistors included in the first pull-down node control module 13 for lowering the potential of the first pull-down node PD1 increases, and the pull-down capability of the first level signal terminal V1 for the first pull-down node PD1 is strengthened. Based on this, the gate drive circuit described in this embodiment adds a first suppression module 14 to reduce the leakage current between the first pull-down node PD1 and the first level signal terminal V1, thereby preventing the potential of the first pull-down node PD1 from being significantly pulled down during the conversion phase. After the conversion phase ends and the second phase begins, the potential of the first pull-down node PD1 can be increased to prevent horizontal stripe defects. This solution requires minimal changes to the gate drive circuit and does not involve timing modifications, making it more suitable for wearable products with narrow bezel requirements.

[0120] The working time of the display panel may include a wake-up phase, wherein the wake-up phase includes a first phase, a transition phase and a second phase, the first phase is a phase in which no data signal is written to the display panel, and the second phase is a phase in which data signal is written to the display panel.

[0121] According to one embodiment, when the display panel described in this disclosure is working, during at least a portion of the time included in the conversion phase, under the control of the trigger signal, it inputs an effective level to the second signal terminal D2, so that the first pull-down node control module 13 controls the pull-up of the potential of the first pull-down node PD1 to be high, thereby ensuring that the potential of the first pull-down node PD1 can be maintained at the beginning of the second phase.

[0122] According to another embodiment, when the display panel described in this disclosure is working, during the conversion phase, the signal provided by the second signal terminal D2 may not be set, and the potential of the first pull-down node PD1 may be maintained during the conversion phase.

[0123] like Figure 6 As shown, in Figure 5 Based on the embodiment of the gate drive circuit shown, the first suppression module may include a first sub-circuit 61;

[0124] The first sub-circuit 61 is electrically connected to the pull-up node PU, the first connection node J1 and the first level signal terminal V1 respectively, and is used to input the signal input from the first level signal terminal V1 to the first connection node J1 under the control of the potential of the pull-up node PU.

[0125] This disclosure is as follows Figure 6 In the gate drive circuit shown, a first sub-circuit 61 is provided between the first connection node J1 and the first level signal terminal V1 to reduce the leakage current between the first pull-down node PD1 and the first level signal terminal V1.

[0126] like Figure 7 As shown, in the gate drive circuit described in at least one embodiment of this disclosure, in Figure 5 Based on the embodiment of the gate drive circuit shown, the first pull-down node control module 13 is also electrically connected to the second connection node J2, and is used to input the signal provided by the second signal terminal D2 to the first pull-down control node PD_CN1 under the control of the second signal terminal D2, and control the connection between the first pull-down control node PD_CN1 and the second connection node J2 under the control of the potential of the pull-up node PU.

[0127] The first suppression module 14 is also electrically connected to the second connection node J2, and is used to input the signal provided by the first level signal terminal V1 to the second connection node J2 under the control of the potential of the pull-up node PU.

[0128] In the gate drive circuit described in at least one embodiment of this disclosure, the first pull-down node control module 13 includes a transistor disposed between the first pull-down control node PD_CN1 and the second connection node J2, and the first suppression module 14 is also disposed between the second connection node J2 and the first level signal terminal V1, so as to reduce the leakage current between the first pull-down control node PD_CN1 and the first level signal terminal V1, which is beneficial to maintain the potential of the first pull-down control node PD_CN1 and enhance the stability of the potential of the first pull-down node PD1.

[0129] In at least one embodiment of this disclosure, the first suppression module may further include a second sub-circuit, which is electrically connected to the pull-up node, the second connection node and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the second connection node under the control of the potential of the pull-up node.

[0130] In a specific implementation, the first suppression module may further include a second sub-circuit, which is disposed between the first level signal terminal and the second connection node to reduce the leakage current between the first level signal terminal and the first pull-down control node.

[0131] like Figure 8 As shown, in Figure 7 Based on at least one embodiment of the gate drive circuit shown, the first suppression module may include a first sub-circuit 61 and a second sub-circuit 62.

[0132] The first sub-circuit 61 is electrically connected to the pull-up node PU, the first connection node J1 and the first level signal terminal V1 respectively, and is used to input the signal input from the first level signal terminal V1 to the first connection node J1 under the control of the potential of the pull-up node PU.

[0133] The second sub-circuit 62 is electrically connected to the pull-up node PU, the second connection node J2 and the first level signal terminal V1 respectively, and is used to input the signal input from the first level signal terminal V1 to the second connection node J2 under the potential control of the pull-up node PU.

[0134] The gate driving circuit described in at least one embodiment of this disclosure may further include a first noise reduction module;

[0135] The first noise reduction module is electrically connected to the pull-up node, the output terminal, the first pull-down node, and the first level signal terminal, respectively, and is used to input the signal provided by the first level signal terminal to the pull-up node and / or the output terminal under the potential control of the first pull-down node.

[0136] The gate drive circuit described in at least one embodiment of this disclosure can reduce noise in the pull-up node and / or the output terminal through a first noise reduction module.

[0137] like Figure 9 As shown, in Figure 8 Based on at least one embodiment of the gate driving circuit shown, the gate driving circuit of at least one embodiment of this disclosure may further include a first noise reduction module 91;

[0138] The first noise reduction module 91 is electrically connected to the pull-up node PU, the output terminal Gn, the first pull-down node PD1 and the first level signal terminal V1, respectively, and is used to input the signal provided by the first level signal terminal V1 to the pull-up node PU and the output terminal Gn under the potential control of the first pull-down node PD1.

[0139] This disclosure is as follows Figure 9In at least one embodiment of the gate drive circuit shown, when the potential of the first pull-down node PD1 is an effective voltage, the first noise reduction module 81 inputs the signal provided by the first level signal terminal V1 to the pull-up node PU and the output terminal Gn to reduce noise in the pull-up node PU and the output terminal Gn.

[0140] like Figure 10 As shown, in Figure 9 Based on at least one embodiment of the gate driving circuit shown, the gate driving circuit of at least one embodiment of this disclosure may further include a reset module 101;

[0141] The reset module 101 is electrically connected to the pull-up node PU, the second input terminal VSD, and the reset signal terminal R1, respectively, and is used to input the signal input from the second input terminal VSD to the pull-up node PU under the control of the reset signal terminal R1.

[0142] In a specific implementation, when the signal input to the second input terminal VSD is a low voltage signal, the reset module 101, under the control of the reset signal terminal R1, inputs the low voltage signal to the pull-up node PU to reset the potential of the pull-up node.

[0143] like Figure 11 As shown, in Figure 10 Based on at least one embodiment of the gate drive circuit shown, the gate drive circuit of at least one embodiment of this disclosure may further include a pull-down holding module 111;

[0144] The pull-down holding module 111 is electrically connected to the output terminal Gn, the third signal terminal D3 and the first level signal terminal V1 respectively, and is used to input the signal input from the first level signal terminal V1 to the output terminal Gn under the control of the third signal terminal D3, and pull down the potential of the signal output from the output terminal Gn.

[0145] In at least one embodiment of this disclosure, the third signal terminal D3 may be the second control voltage terminal GCL, but is not limited thereto.

[0146] like Figure 12 As shown, in Figure 11 Based on at least one embodiment of the gate drive circuit shown, the gate drive circuit of at least one embodiment of this disclosure may further include an initial reset module 121;

[0147] The initial reset module 121 is electrically connected to the pull-up node PU, the initial signal terminal STV0 and the first level signal terminal V1 respectively, and is used to input the signal input from the first level signal terminal V1 to the pull-up node PU under the control of the initial signal terminal STV0, so as to reset the potential of the pull-up node PU.

[0148] Optionally, the input module includes a first transistor, the gate of which is electrically connected to the input control terminal, the first electrode of which is electrically connected to the first input terminal, and the second electrode of which is electrically connected to the pull-up node.

[0149] Optionally, the output module includes a second transistor and a first capacitor;

[0150] The gate of the second transistor is electrically connected to the pull-up node, the first terminal of the second transistor is electrically connected to the first signal terminal, and the second terminal of the second transistor is electrically connected to the output terminal.

[0151] The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the output terminal.

[0152] Optionally, the first drop-down node control module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0153] The gate and the first terminal of the sixth transistor are both electrically connected to the second signal terminal, and the second terminal of the sixth transistor is electrically connected to the gate of the third transistor; the gate of the third transistor is electrically connected to the first pull-down control node.

[0154] The first terminal of the third transistor is electrically connected to the second signal terminal, and the second terminal of the third transistor is electrically connected to the first pull-down node;

[0155] The gate of the fourth transistor is electrically connected to the pull-up node, the first terminal of the fourth transistor is electrically connected to the first pull-down node, and the second terminal of the fourth transistor is electrically connected to the first connection node.

[0156] The gate of the fifth transistor and the gate of the fourth transistor are both electrically connected to the pull-up node. The first terminal of the fifth transistor and the second terminal of the sixth transistor are both electrically connected to the gate of the third transistor. The second terminal of the fifth transistor is electrically connected to the second connection node.

[0157] Optionally, the first noise reduction module includes a seventh transistor and an eighth transistor;

[0158] The gate of the seventh transistor is electrically connected to the first pull-down node, the first terminal of the seventh transistor is electrically connected to the pull-up node, and the second terminal of the seventh transistor is electrically connected to the first level signal terminal.

[0159] The gate of the eighth transistor is electrically connected to the first pull-down node, the first terminal of the eighth transistor is electrically connected to the output terminal, and the second terminal of the eighth transistor is electrically connected to the first level signal terminal.

[0160] Optionally, the first sub-circuit includes a ninth transistor, the gate of which is electrically connected to the pull-up node, the first terminal of which is electrically connected to the second terminal of the fourth transistor, and the second terminal of which is electrically connected to the first level signal terminal.

[0161] Optionally, the second sub-circuit includes a tenth transistor, the gate of which is electrically connected to the pull-up node and the gate of the ninth transistor, the first terminal of which is electrically connected to the second terminal of the fifth transistor, and the second terminal of which is electrically connected to the first level signal terminal.

[0162] Optionally, the reset module includes an eleventh transistor, the gate of which is electrically connected to the reset signal terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the second input terminal.

[0163] Optionally, the pull-down holding module includes a twelfth transistor, the gate of which is electrically connected to the third signal terminal, the first terminal of which is electrically connected to the output terminal, and the second terminal of which is electrically connected to the first level signal terminal.

[0164] Optionally, the initial reset module includes a thirteenth transistor, the gate of which is electrically connected to the initial signal terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the first level signal terminal.

[0165] like Figure 13 As shown, in Figure 11 Based on at least one embodiment of the gate drive circuit shown, the input module 11 includes a first transistor M1;

[0166] The gate of the first transistor M1 is electrically connected to the input control terminal I1, the drain of the first transistor M1 is electrically connected to the first input terminal VDS, and the source of the first transistor M1 is electrically connected to the pull-up node PU.

[0167] The output module 12 includes a second transistor M2 and a first capacitor C1;

[0168] The gate of the second transistor M2 is electrically connected to the pull-up node PU, the drain of the second transistor M2 is electrically connected to the clock signal terminal K1, and the source of the second transistor M2 is electrically connected to the output terminal Gn.

[0169] The first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the output terminal Gn.

[0170] The first drop-down node control module 13 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6;

[0171] The gate and drain of the sixth transistor M6 are both electrically connected to the first control voltage terminal GCH, and the source of the sixth transistor M6 is electrically connected to the gate of the third transistor M3; the gate of the third transistor M3 is electrically connected to the first pull-down control node PD_CN1.

[0172] The drain of the third transistor M3 is electrically connected to the first control voltage terminal GCH, and the source of the third transistor M3 is electrically connected to the first pull-down node PD1.

[0173] The gate of the fourth transistor M4 is electrically connected to the pull-up node PU, the drain of the fourth transistor M4 is electrically connected to the first pull-down node PD1, and the source of the fourth transistor M4 is electrically connected to the first connection node J1.

[0174] The gate of the fifth transistor M5 and the gate of the fourth transistor M4 are both electrically connected to the pull-up node PU. The drain of the fifth transistor M5 and the source of the sixth transistor M6 are both electrically connected to the gate of the third transistor M3. The source of the fifth transistor M5 is electrically connected to the second connection node J2.

[0175] The first noise reduction module includes a seventh transistor M7 and an eighth transistor M8;

[0176] The gate of the seventh transistor M7 is electrically connected to the first pull-down node PD1, the drain of the seventh transistor M7 is electrically connected to the pull-up node PU, and the source of the seventh transistor M7 is electrically connected to the low voltage terminal VGL.

[0177] The gate of the eighth transistor M8 is electrically connected to the first pull-down node PD1, the drain of the eighth transistor M8 is electrically connected to the output terminal Gn, and the source of the eighth transistor M8 is electrically connected to the low voltage terminal VGL.

[0178] The first sub-circuit 61 includes a ninth transistor M9;

[0179] The gate of the ninth transistor M9 is electrically connected to the pull-up node PU, the drain of the ninth transistor M9 is electrically connected to the source of the fourth transistor M4, and the source of the ninth transistor M9 is electrically connected to the low voltage terminal VGL.

[0180] The second sub-circuit 62 includes the tenth transistor M10;

[0181] The gate of the tenth transistor M10 is electrically connected to the pull-up node PU and the gate of the ninth transistor M9. The drain of the tenth transistor M10 is electrically connected to the source of the fifth transistor M5. The source of the tenth transistor M10 is electrically connected to the low voltage terminal VGL.

[0182] The reset module 101 includes an eleventh transistor M11;

[0183] The gate of the eleventh transistor M11 is electrically connected to the reset signal terminal R1, the drain of the eleventh transistor M11 is electrically connected to the pull-up node PU, and the source of the eleventh transistor M11 is electrically connected to the second input terminal VSD.

[0184] The pull-down holding module 111 includes a twelfth transistor M12;

[0185] The gate of the twelfth transistor M12 is electrically connected to the second control voltage terminal GCL, the drain of the twelfth transistor M12 is electrically connected to the output terminal Gn, and the source of the twelfth transistor M12 is electrically connected to the low voltage terminal VGL. Optionally, the GCL signal and the GCH signal are signals with opposite phases. For example, when the potential of the GCH signal is high, the potential of the GCL signal is low; when the potential of the GCH signal is low, the potential of the GCL signal is high.

[0186] exist Figure 13 In at least one embodiment of the gate drive circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0187] In this disclosure Figure 13 In at least one embodiment of the gate drive circuit shown, the first signal terminal is a clock signal terminal K1, the second signal terminal is a first control voltage terminal GCH, the third signal terminal can be a second control voltage terminal GCL, and the first level signal terminal can be a low voltage terminal VGL, but is not limited thereto.

[0188] In at least one embodiment of this disclosure, the GCL signal is a voltage signal provided by the GCL, and the GCH signal is a voltage signal provided by the GCH.

[0189] Compared with related technologies, this disclosure is as follows: Figure 13 At least one embodiment of the gate drive circuit shown only adds two transistors, without affecting the narrow bezel design requirements of wearable products.

[0190] In at least one embodiment of this disclosure, the first control voltage provided by the first control voltage terminal GCH and the second control voltage provided by the second control voltage terminal VGL can be inversely opposite phases; within one frame, the first control voltage provided by the first control voltage terminal GCH can be a high voltage;

[0191] During at least a portion of the blank time period between two adjacent frames, the second control voltage terminal can output a high voltage signal to control M12 to conduct, keeping the potential of the signal provided by the output terminal Gn at a low voltage.

[0192] However, this is not the limit.

[0193] exist Figure 13 In at least one embodiment of the gate drive circuit shown, a ninth transistor M9 is disposed between the first connection node J1 and the low voltage terminal VGL, and a tenth transistor M10 is disposed between the second connection node J2 and the low voltage terminal VGL; that is, a fourth transistor M4 and a ninth transistor M9 connected in series are disposed between the first pull-down node PD1 and the low voltage terminal VGL, and a fifth transistor M5 and a tenth transistor M10 connected in series are disposed between the first pull-down control node PD_CN1 and the low voltage terminal VGL, so as to reduce the leakage current between the first node PD1 and the low voltage terminal VGL, and reduce the leakage current between the first pull-down control node PD_CN1 and the low voltage terminal VGL, so that the potential of the first pull-down node PD1 will not be pulled down significantly during the conversion stage, thus enabling the potential of the first pull-down node PD1 to be raised at the beginning of the second stage, preventing the occurrence of horizontal stripe defects.

[0194] like Figure 14 As shown, this disclosure is as follows Figure 13 When at least one embodiment of the gate driving circuit shown is in operation, the wake-up phase of the display panel (which includes the gate driving circuit) includes a first phase S1, a transition phase S0, and a second phase S2. The first phase S1 is a phase in which no data signal is written to the display panel, and the second phase S2 is a phase in which data signal is written to the display panel.

[0195] In the first stage S1 and the second stage S2, the potential of the trigger signal F1 is low voltage, and the timing of the first control voltage provided by GCH is output according to the normal timing. Optionally, the trigger signal F1 can be unrestricted in the first and second stages and can be either low or high level.

[0196] During the conversion phase S0, the trigger signal F1 is at a high voltage, and the first control voltage provided by GCH is forcibly pulled high to enable M3 and M6, thereby making the first pull-down node PD1 at a high voltage. At this time, during the first frame of the second phase S2, the first pull-down node PD1 is not pulled down, and no defects are found after 20 days of verification. That is, this invention allows control over the GCH signal during the conversion phase, raising the GCH signal to a high potential during this phase to make the first pull-down node PD1 at a high voltage. Figure 14 The diagram illustrates that when the trigger signal switches from a low level to a high level during the transition from the first stage to the conversion stage, it triggers the GCH signal to rise to a high level. If the GCH signal was at a high level in the previous stage, it remains at a high level. If the GCH signal was at a low level before, it transitions from a low level to a high level. Alternatively, when the trigger signal switches from a high level to a low level during the transition from the first stage to the conversion stage, it triggers the GCH signal to rise to a high level. If the GCH signal was at a high level in the previous stage, it remains at a high level. If the GCH signal was at a low level before, it transitions from a low level to a high level. Here, the trigger signal serves as an indication of the controllable GCH signal. Therefore, any signal switching of the trigger signal, whether from a high level to a low level or from a low level to a high level, falls within the scope of protection of this application. Optionally, the protection scope of this case includes maintaining the potential of the GCH signal at a high potential throughout the entire conversion phase, or maintaining it at least partially during the conversion phase. Of course, in order to better improve the problem of horizontal stripes, the potential of the GCH signal should be maintained at a high potential for at least more than half of the entire conversion phase.

[0197] It should be noted that the driving method in this case can be used alone. That is, the first suppression module of this case is not set in the circuit. The GCH signal is controlled by simply adding a trigger signal in the driver to improve the problem of horizontal stripes. In this case, the timing adjustment can be done without adjusting the circuit architecture. The method is simpler and lower in cost. Moreover, no additional transistors are added to the circuit architecture, and a narrow bezel can be achieved.

[0198] It should be noted that in this case, the problem of horizontal stripes on the display could also be improved simply by adding a first suppression module to the circuit architecture, without using a driving method.

[0199] It should be noted that, in this case, the driving method and circuit architecture can also be improved by adding a first suppression module to jointly achieve the improvement of the horizontal stripe problem, and no limitation is made here.

[0200] In at least one embodiment of this disclosure, the GCH signal is a voltage signal provided by the GCH.

[0201] exist Figure 14 In the diagram, the terminal labeled STV0 is the initial voltage terminal, and the waveform corresponding to STV0 is the waveform of the initial voltage.

[0202] This disclosure is as follows Figure 13 In at least one embodiment of the gate drive circuit shown, during operation, the potential of the first control voltage can be forcibly pulled high during the switching phase, or the timing of the first control voltage provided by the GCH can be output according to the normal timing during the switching phase.

[0203] Figure 15A This is a simulation waveform of the potential of the first pull-down node PD1 before adding M9 and M10. Figure 15B This is a simulation waveform of the potential of the first pull-down node PD1 after adding M9 and M10.

[0204] exist Figure 15A and Figure 15B In the diagram, the part labeled S2 is the second stage, S2.

[0205] like Figure 15A As shown, at the start of the second stage S2, the potential of the first pull-down node PD1 is pulled down, as... Figure 15B As shown, at the start of the second stage S2, the potential of the first pull-down node is not pulled down.

[0206] exist Figure 15A and Figure 15B In the diagram, the horizontal axis represents time t, with the unit being seconds (s).

[0207] This disclosure Figure 13 In at least one embodiment of the gate drive circuit shown, when the first input terminal VDS provides a high voltage signal and the second input terminal VSD provides a low voltage signal, the shift register containing the gate drive circuit can perform a forward scan.

[0208] When the first input terminal VDS provides a low voltage signal and the second input terminal VSD provides a high voltage signal, the shift register containing the gate drive circuit can perform a reverse scan.

[0209] This disclosure Figure 13 At least one embodiment of the gate drive circuit shown is capable of bidirectional scanning.

[0210] This disclosure Figure 16 At least one embodiment of the gate drive circuit shown is consistent with this disclosure. Figure 13 The differences in at least one embodiment of the gate drive circuit shown are as follows: it does not include a tenth transistor M10; the source of M5 is electrically connected to the low voltage terminal VGL.

[0211] Figure 17A This is a simulation waveform of the potential of the first pull-down node PD1 before M9 was added. Figure 17B This is a simulation waveform of the potential of the first pull-down node PD1 after adding M9.

[0212] exist Figure 17A and Figure 17B In the diagram, the part labeled S2 is the second stage, S2.

[0213] like Figure 17A As shown, at the start of the second stage S2, the potential of the first pull-down node PD1 is pulled down, as... Figure 17B As shown, at the start of the second stage S2, the potential of the first pull-down node is not pulled down.

[0214] exist Figure 17A and Figure 17B In the diagram, the horizontal axis represents time t, with the unit being seconds (s).

[0215] like Figure 18 As shown in this disclosure Figure 13 Based on at least one embodiment of the gate drive circuit shown, the gate drive circuit of at least one embodiment of this disclosure further includes an initial reset module 121;

[0216] The initial reset module 121 includes a thirteenth transistor M13;

[0217] The gate of the thirteenth transistor M13 is electrically connected to the initial signal terminal STV0, the drain of the thirteenth transistor M13 is electrically connected to the pull-up node PU, and the source of the thirteenth transistor M13 is electrically connected to the low voltage terminal VGL.

[0218] Compared with related technologies, this disclosure is as follows: Figure 18 At least one embodiment of the gate drive circuit shown only adds two transistors, without affecting the narrow bezel design requirements of wearable products.

[0219] This disclosure is as follows Figure 18 When at least one embodiment of the gate driving circuit shown is in operation, the wake-up phase of the display panel (which includes the gate driving circuit) includes a first phase, a transition phase, and a second phase. The first phase is a phase in which no data signal is written to the display panel, and the second phase is a phase in which data signal is written to the display panel.

[0220] In the first and second phases, the timing of the first control voltage provided by the GCH is output according to the normal timing sequence.

[0221] During at least a portion of the time period included in the conversion phase, the potential of the trigger signal is high, and the potential of the first control voltage provided by GCH is forcibly pulled high to enable M3 and M6, thereby making the potential of the first pull-down node PD1 high. At this time, in the first frame of the second phase S2, the potential of the first pull-down node PD1 is not pulled down, and there are no defects after 20 days of verification. The optimized measured waveform is as follows. Figure 19 As shown.

[0222] exist Figure 19 In the diagram, S1 is the first stage, S0 is the transition stage, and S2 is the second stage.

[0223] like Figure 19 As shown, at the beginning of the second stage S2, the potential of PD1 is not pulled down.

[0224] This disclosure is as follows Figure 18 In at least one embodiment of the gate drive circuit shown, during operation, the potential of the first control voltage can be forcibly pulled high during the switching phase, or the timing of the first control voltage provided by the GCH can be output according to the normal timing during the switching phase.

[0225] Optionally, the gate drive circuit described in at least one embodiment of this disclosure may further include a second pull-down node control module, a second pull-down node, a second noise reduction module, and a second suppression module;

[0226] The second pull-down node control module is electrically connected to the fourth signal terminal, the second pull-down node, the second pull-down control node, the pull-up node, the third connection node, and the fourth connection node, respectively. It is used to input the signal provided by the fourth signal terminal to the second pull-down control node under the control of the potential of the pull-up node, and to control the connection between the second pull-down control node and the fourth connection node under the control of the potential of the second pull-down control node. It is also used to input the signal provided by the fourth signal terminal to the second pull-down node under the control of the potential of the second pull-down control node, and to control the connection between the second pull-down node and the third connection node under the control of the potential of the pull-up node.

[0227] The second noise reduction module is electrically connected to the pull-up node, the output terminal, the second pull-down node, and the first level signal terminal, respectively, and is used to input the signal provided by the first level signal terminal to the pull-up node and / or the output terminal under the potential control of the second pull-down node;

[0228] The second suppression module is electrically connected to the pull-up node, the third connection node and the first level signal terminal respectively, and is used to input the signal provided by the first level signal terminal to the third connection node under the control of the potential of the pull-up node.

[0229] Optionally, the fourth signal terminal may be the third control voltage terminal GCH1, but is not limited thereto.

[0230] In a specific implementation, the gate driving circuit described in at least one embodiment of this disclosure may include two pull-down nodes: a first pull-down node and a second pull-down node; the first pull-down node control module is used to control the potential of the first pull-down node, and the second pull-down node control module is used to control the potential of the second pull-down node, so that the potential of the first pull-down node and the potential of the second pull-down node alternately become high voltage, thereby enabling the transistor whose gate is electrically connected to the first pull-down node and the second pull-down node to be turned on alternately, improving the characteristic drift phenomenon of the transistor.

[0231] like Figure 20 As shown in this disclosure Figure 11 Based on at least one embodiment of the gate driving circuit shown, the gate driving circuit of at least one embodiment of this disclosure may further include a second pull-down node control module 181, a second pull-down node PD2, a second noise reduction module 182, and a second suppression module 183;

[0232] The second pull-down node control module 181 is electrically connected to the fourth signal terminal D4, the second pull-down node PD2, the second pull-down control node PD_CN2, the pull-up node PU, the third connection node J3, and the fourth connection node J4, respectively. It is used to input the signal provided by the fourth signal terminal D4 to the second pull-down control node PD_CN2 under the control of the potential of the pull-up node PU, and to control the connection between the second pull-down control node PD_CN2 and the fourth connection node J4 under the control of the potential of the second pull-down control node PD_CN2. It is also used to input the signal provided by the fourth signal terminal D4 to the second pull-down node PD2 under the control of the potential of the second pull-down control node PD_CN2, and to control the connection between the second pull-down node PD2 and the third connection node J3 under the control of the potential of the pull-up node PU.

[0233] The second noise reduction module 182 is electrically connected to the pull-up node PU, the output terminal Gn, the second pull-down node PD2 and the first level signal terminal V1, respectively, and is used to input the signal provided by the first level signal terminal V1 to the pull-up node PU and the output terminal Gn under the potential control of the second pull-down node PD2.

[0234] The second suppression module 183 is electrically connected to the pull-up node PU, the third connection node J3 and the first level signal terminal V1 respectively, and is used to input the signal provided by the first level signal terminal V1 to the third connection node J3 under the control of the potential of the pull-up node PU.

[0235] In at least one embodiment of this disclosure, the second suppression module includes a third sub-circuit, which is electrically connected to the pull-up node, the third connection node and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the third connection node under the control of the potential of the pull-up node.

[0236] In a specific implementation, a third sub-circuit is provided between the third connection node and the first level signal terminal to reduce leakage current between the second pull-down node and the first level signal terminal.

[0237] In at least one embodiment of this disclosure, the second suppression module is also electrically connected to the fourth connection node, and is used to input the signal provided by the first level signal terminal to the fourth connection node under the control of the potential of the pull-up node;

[0238] The second suppression module further includes a fourth sub-circuit, which is electrically connected to the pull-up node, the fourth connection node and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the fourth connection node under the control of the potential of the pull-up node.

[0239] In a specific implementation, a fourth sub-circuit is provided between the fourth connection node and the first level signal terminal to reduce the leakage current between the second pull-down control node and the first level signal terminal.

[0240] like Figure 21 As shown in this disclosure Figure 20 Based on at least one embodiment of the gate drive circuit shown, in the gate drive circuit of at least one embodiment of this disclosure, the second suppression module 183 is also electrically connected to the fourth connection node J4, and is used to input the signal provided by the first level signal terminal V1 to the fourth connection node J4 under the control of the potential of the pull-up node PU.

[0241] The second suppression module 183 includes a third sub-circuit 63 and a fourth sub-circuit 64;

[0242] The third sub-circuit 63 is electrically connected to the pull-up node PU, the third connection node J3 and the first level signal terminal V1 respectively, and is used to input the signal input from the first level signal terminal V1 to the third connection node J3 under the control of the potential of the pull-up node PU.

[0243] The fourth sub-circuit 64 is electrically connected to the pull-up node PU, the fourth connection node J4 and the first level signal terminal V1, respectively, and is used to input the signal input from the first level signal terminal V1 to the fourth connection node J4 under the control of the potential of the pull-up node PU.

[0244] Optionally, the second drop-down node control module includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

[0245] The gate and first terminal of the seventeenth transistor are both electrically connected to the fourth signal terminal, and the second terminal of the seventeenth transistor is electrically connected to the gate of the fourteenth transistor; the second terminal of the seventeenth transistor is electrically connected to the second pull-down control node.

[0246] The first terminal of the fourteenth transistor is electrically connected to the fourth signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the second pull-down node;

[0247] The gate of the fifteenth transistor is electrically connected to the pull-up node, the first terminal of the fifteenth transistor is electrically connected to the second pull-down node, and the second terminal of the fifteenth transistor is electrically connected to the third connection node.

[0248] The gate of the sixteenth transistor is electrically connected to the gate of the fifteenth transistor and the pull-up node. The first terminal of the sixteenth transistor is electrically connected to the second terminal of the seventeenth transistor and the gate of the fourteenth transistor. The second terminal of the sixteenth transistor is electrically connected to the fourth connection node.

[0249] Optionally, the third sub-circuit includes an eighteenth transistor, and the fourth sub-circuit includes a nineteenth transistor;

[0250] The gate of the eighteenth transistor is electrically connected to the pull-up node, the first terminal of the eighteenth transistor is electrically connected to the second terminal of the fifteenth transistor, and the second terminal of the eighteenth transistor is electrically connected to the first level signal terminal.

[0251] The gate of the nineteenth transistor is electrically connected to the pull-up node and the gate of the eighteenth transistor. The first terminal of the nineteenth transistor is electrically connected to the second terminal of the sixteenth transistor. The second terminal of the nineteenth transistor is electrically connected to the first level signal terminal.

[0252] Optionally, the second noise reduction module includes a twentieth transistor and a twenty-first transistor;

[0253] The gate of the twentieth transistor is electrically connected to the second pull-down node, the first terminal of the twentieth transistor is electrically connected to the pull-up node, and the second terminal of the twentieth transistor is electrically connected to the first level signal terminal.

[0254] The gate of the 21st transistor is electrically connected to the second pull-down node, the first terminal of the 21st transistor is electrically connected to the output terminal, and the second terminal of the 21st transistor is electrically connected to the first level signal terminal.

[0255] like Figure 22 As shown in this disclosure Figure 21 Based on at least one embodiment of the gate drive circuit shown, in the gate drive circuit of at least one embodiment of this disclosure, the input module 11 includes a first transistor M1;

[0256] The gate of the first transistor M1 is electrically connected to the input control terminal I1, the drain of the first transistor M1 is electrically connected to the first input terminal VDS, and the source of the first transistor M1 is electrically connected to the pull-up node PU.

[0257] The output module 12 includes a second transistor M2 and a first capacitor C1;

[0258] The gate of the second transistor M2 is electrically connected to the pull-up node PU, the drain of the second transistor M2 is electrically connected to the clock signal terminal K1, and the source of the second transistor M2 is electrically connected to the output terminal Gn.

[0259] The first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the output terminal Gn.

[0260] The first drop-down node control module 13 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6;

[0261] The gate and drain of the sixth transistor M6 are both electrically connected to the first control voltage terminal GCH, and the source of the sixth transistor M6 is electrically connected to the gate of the third transistor M3; the gate of the third transistor M3 is electrically connected to the first pull-down control node PD_CN1.

[0262] The drain of the third transistor M3 is electrically connected to the first control voltage terminal GCH, and the source of the third transistor M3 is electrically connected to the first pull-down node PD1.

[0263] The gate of the fourth transistor M4 is electrically connected to the pull-up node PU, the drain of the fourth transistor M4 is electrically connected to the first pull-down node PD1, and the source of the fourth transistor M4 is electrically connected to the first connection node J1.

[0264] The gate of the fifth transistor M5 and the gate of the fourth transistor M4 are both electrically connected to the pull-up node PU. The drain of the fifth transistor M5 and the source of the sixth transistor M6 are both electrically connected to the gate of the third transistor M3. The source of the fifth transistor M5 is electrically connected to the second connection node J2.

[0265] The first noise reduction module 91 includes a seventh transistor M7 and an eighth transistor M8;

[0266] The gate of the seventh transistor M7 is electrically connected to the first pull-down node PD1, the drain of the seventh transistor M7 is electrically connected to the pull-up node PU, and the source of the seventh transistor M7 is electrically connected to the low voltage terminal VGL.

[0267] The gate of the eighth transistor M8 is electrically connected to the first pull-down node PD1, the drain of the eighth transistor M8 is electrically connected to the output terminal Gn, and the source of the eighth transistor M8 is electrically connected to the low voltage terminal VGL.

[0268] The first sub-circuit 61 includes a ninth transistor M9;

[0269] The gate of the ninth transistor M9 is electrically connected to the pull-up node PU, the drain of the ninth transistor M9 is electrically connected to the source of the fourth transistor M4, and the source of the ninth transistor M9 is electrically connected to the low voltage terminal VGL.

[0270] The second sub-circuit 62 includes the tenth transistor M10;

[0271] The gate of the tenth transistor M10 is electrically connected to the pull-up node PU and the gate of the ninth transistor M9. The drain of the tenth transistor M10 is electrically connected to the source of the fifth transistor M5. The source of the tenth transistor M10 is electrically connected to the low voltage terminal VGL.

[0272] The reset module 101 includes an eleventh transistor M11;

[0273] The gate of the eleventh transistor M11 is electrically connected to the reset signal terminal R1, the drain of the eleventh transistor M11 is electrically connected to the pull-up node PU, and the source of the eleventh transistor M11 is electrically connected to the second input terminal VSD.

[0274] The pull-down holding module 111 includes a twelfth transistor M12;

[0275] The gate of the twelfth transistor M12 is electrically connected to the second control voltage terminal GCL, the drain of the twelfth transistor M12 is electrically connected to the output terminal Gn, and the source of the twelfth transistor M12 is electrically connected to the low voltage terminal VGL.

[0276] The second pull-down node control module 181 includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17;

[0277] The gate and drain of the seventeenth transistor M17 are both electrically connected to the third control voltage terminal GCH1, and the source of the seventeenth transistor M17 is electrically connected to the gate of the fourteenth transistor M14; the source of the seventeenth transistor M17 is electrically connected to the second pull-down control node PD_CN2.

[0278] The drain of the fourteenth transistor M14 is electrically connected to the third control voltage terminal GCH1, and the source of the fourteenth transistor M14 is electrically connected to the second pull-down node PD2.

[0279] The gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the drain of the fifteenth transistor M15 is electrically connected to the second pull-down node PD2, and the source of the fifteenth transistor M15 is electrically connected to the third connection node J3.

[0280] The gate of the sixteenth transistor M16 is electrically connected to the gate of the fifteenth transistor M15 and the pull-up node PU. The drain of the sixteenth transistor M16 and the source of the seventeenth transistor M17 are both electrically connected to the gate of the fourteenth transistor M14. The source of the sixteenth transistor M16 is electrically connected to the fourth connection node J4.

[0281] The third sub-circuit 63 includes the eighteenth transistor M18, and the fourth sub-circuit 64 includes the nineteenth transistor M19;

[0282] The gate of the eighteenth transistor M18 is electrically connected to the pull-up node PU, the drain of the eighteenth transistor M18 is electrically connected to the source of the fifteenth transistor M15, and the source of the eighteenth transistor M18 is electrically connected to the low voltage terminal VGL.

[0283] The gate of the nineteenth transistor M19 and the pull-up node PU are both electrically connected to the gate of the eighteenth transistor M18. The drain of the nineteenth transistor M19 is electrically connected to the source of the sixteenth transistor M16. The source of the nineteenth transistor M19 is electrically connected to the low voltage terminal VGL.

[0284] The second noise reduction module 182 includes a twentieth transistor M20 and a twenty-first transistor M21;

[0285] The gate of the twentieth transistor M20 is electrically connected to the second pull-down node PD2, the drain of the twentieth transistor M20 is electrically connected to the pull-up node PU, and the second terminal of the twentieth transistor M20 is electrically connected to the low voltage terminal VGL.

[0286] The gate of the 21st transistor M21 is electrically connected to the second pull-down node PD2, the drain of the 21st transistor M21 is electrically connected to the output terminal Gn, and the source of the 21st transistor M21 is electrically connected to the low voltage terminal VGL.

[0287] exist Figure 22 In at least one embodiment of the gate drive circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0288] In this disclosure Figure 22 In at least one embodiment of the gate drive circuit shown, the first signal terminal is a clock signal terminal K1, the second signal terminal is a first control voltage terminal GCH, the third signal terminal can be a second control voltage terminal GCL, the fourth signal terminal shown can be a third control voltage terminal VGH1, and the first level signal terminal can be a low voltage terminal VGL, but is not limited thereto.

[0289] exist Figure 22In at least one embodiment of the gate drive circuit shown, a ninth transistor M9 is disposed between the first connection node J1 and the low-voltage terminal VGL; a tenth transistor M10 is disposed between the second connection node J2 and the low-voltage terminal VGL; an eighteenth transistor M18 is disposed between the third connection node J3 and the low-voltage terminal VGL; and a nineteenth transistor M19 is disposed between the fourth connection node J4 and the low-voltage terminal VGL. That is, a fourth transistor M4 and a ninth transistor M9 connected in series are disposed between the first pull-down node PD1 and the low-voltage terminal VGL; and a fifth transistor M5 and a tenth transistor M10 connected in series are disposed between the first pull-down control node PD_CN1 and the low-voltage terminal VGL. This reduces the leakage current between the first node PD1 and the low-voltage terminal VGL, thereby reducing... The leakage current between the first pull-down node PD_CN1 and the low-voltage terminal VGL is reduced. A fifteenth transistor M15 and a twentieth transistor M20 are connected in series between the second pull-down node PD2 and the low-voltage terminal VGL. A sixteenth transistor M16 and a twenty-first transistor M21 are connected in series between the second pull-down control node PD_CN2 and the low-voltage terminal VGL. This reduces the leakage current between the second node PD2 and the low-voltage terminal VGL, and also reduces the leakage current between the second pull-down control node PD_CN2 and the low-voltage terminal VGL. This ensures that the potentials of the first pull-down node PD1 and the second pull-down node are not significantly pulled down during the switching phase. Therefore, at the beginning of the second phase, the potential of the first pull-down node PD1 can be increased to prevent the occurrence of horizontal striping defects.

[0290] This disclosure is as follows Figure 22 In at least one embodiment of the gate drive circuit shown, during operation, the potential of the first control voltage and the third control voltage can be forcibly pulled high during the switching phase, or the timing of the first control voltage provided by GCH and the third control voltage provided by GCH1 can be output in the normal timing during the switching phase.

[0291] This disclosure Figure 22 In at least one embodiment of the gate drive circuit shown, when the first input terminal VDS provides a high voltage signal and the second input terminal VSD provides a low voltage signal, the shift register containing the gate drive circuit can perform a forward scan.

[0292] When the first input terminal VDS provides a low voltage signal and the second input terminal VSD provides a high voltage signal, the shift register containing the gate drive circuit can perform a reverse scan.

[0293] This disclosure Figure 22 At least one embodiment of the gate drive circuit shown is capable of bidirectional scanning.

[0294] like Figure 23As shown in this disclosure Figure 22 Based on at least one embodiment of the gate drive circuit shown, the gate drive circuit of at least one embodiment of this disclosure further includes an initial reset module 121;

[0295] The initial reset module 121 includes a thirteenth transistor M13;

[0296] The gate of the thirteenth transistor M13 is electrically connected to the initial signal terminal STV0, the drain of the thirteenth transistor M13 is electrically connected to the pull-up node PU, and the source of the thirteenth transistor M13 is electrically connected to the low voltage terminal VGL.

[0297] The shift register described in this embodiment includes multiple cascaded gate drive circuits as described above.

[0298] The display panel described in this embodiment includes the shift register described above.

[0299] The display panel driving method described in this embodiment is used to drive the display panel. The working time of the display panel includes a wake-up phase, wherein the wake-up phase includes a first phase, a transition phase, and a second phase. The first phase is a phase in which no data signal is written to the display panel, and the second phase is a phase in which data signal is written to the display panel.

[0300] The display panel includes multiple cascaded gate driving circuits, each gate driving circuit including an input module, a pull-up node, an output module, a first pull-down node, and a first pull-down node control module.

[0301] The input module is electrically connected to the input control terminal, the first input terminal and the pull-up node respectively, and is used to input the signal input from the first input terminal to the pull-up node under the control of the first input control terminal;

[0302] The output module is electrically connected to the pull-up node, the first signal terminal, and the output terminal, respectively, and is used to output the signal input from the first signal terminal through the output terminal under the control of the potential of the pull-up node;

[0303] The first pull-down node control module is electrically connected to the second signal terminal, the first pull-down node, the first pull-down control node, the pull-up node, the first connection node, and the second connection node, respectively. It is used to input the signal provided by the second signal terminal to the first pull-down control node under the control of the second signal terminal, and to control the connection between the first pull-down control node and the second connection node under the control of the potential of the pull-up node. It is also used to input the signal provided by the second signal terminal to the first pull-down node under the control of the potential of the first pull-down control node, and to control the connection between the first pull-down node and the first connection node under the control of the potential of the pull-up node.

[0304] The driving method for the display panel includes:

[0305] During at least a portion of the time included in the conversion phase, under the control of the trigger signal, an effective level is input to the second signal terminal so that the first pull-down node control module controls the pull-up of the first pull-down node to a high potential.

[0306] In the display panel driving method described in the embodiments of this disclosure, during at least a portion of the time included in the conversion phase, an effective level is input to the second signal terminal under the control of the trigger signal, so that the first pull-down node control module controls the pull-up of the potential of the first pull-down node to be high, thereby ensuring that the potential of the first pull-down node can be maintained at the beginning of the second phase.

[0307] The display panel driving method described in this disclosure can be applied to the display panel described in at least one embodiment of this disclosure. That is, the display panel to which the display panel driving method described in this disclosure is applied may include the driving circuit described in at least one embodiment of this disclosure, but is not limited thereto. In actual operation, the display panel driving method described in this disclosure may not be applied to the display panel described in at least one embodiment of this disclosure; it is sufficient that the gate driving circuit in the display panel includes an input module, a pull-up node, an output module, a first pull-down node, and a first pull-down node control module.

[0308] The driving method for the display panel described in at least one embodiment of this disclosure may include:

[0309] During the conversion phase, under the control of the trigger signal, an effective level is input to the second signal terminal.

[0310] In at least one embodiment of this disclosure, when the gate driving circuit includes an n-type transistor whose gate is electrically connected to the second signal terminal, the effective voltage level can be high; when the gate driving circuit includes a p-type transistor whose gate is electrically connected to the second signal terminal, the effective voltage level can be low.

[0311] In the display panel driving method described in at least one embodiment of this disclosure, an effective level can be input to the second signal terminal throughout the entire conversion phase, so that the first pull-down node control module controls the pull-up of the potential of the first pull-down node to be high, thereby ensuring that the potential of the first pull-down node can be maintained at the beginning of the second phase.

[0312] In at least one embodiment of this disclosure, the gate driving circuit further includes a second pull-down node control module; the driving method for the display panel may further include:

[0313] When a valid level is input to the second signal terminal, the second pull-down node control module controls the pull-up of the second node's potential.

[0314] In at least one embodiment of this disclosure, the step of inputting an effective level to the second signal terminal under the control of the trigger signal includes:

[0315] The trigger signal is converted from a first voltage signal to a second voltage signal to control the input of an effective level to the second signal terminal.

[0316] Optionally, the first voltage signal can be a low voltage signal, and the second voltage signal can be a high voltage signal, but this is not a limitation.

[0317] The display device described in this disclosure includes the aforementioned display panel, such as... Figure 24 As shown, the display device further includes a driver chip 240, which includes a trigger signal generation module 241 and a signal providing module 242.

[0318] The trigger signal generation module 241 is used to generate a trigger signal to the signal providing module 242;

[0319] The signal providing module 242 is used to control the input of an effective level to the second signal terminal during at least a portion of the time included in the conversion phase, under the control of the trigger signal, so that the first pull-down node control module can pull up the potential of the first pull-down node.

[0320] Optionally, the trigger signal generation module 241 is electrically connected to the signal providing module 242 and is used to generate a trigger signal to the signal providing module 242.

[0321] Optionally, the trigger signal generation module generates a trigger signal during the conversion phase, and the driver chip controls the signal providing module to input an effective level to the second signal terminal.

[0322] Optionally, the driver chip mentioned in this case may be a timing controller or a source driver chip (source IC), etc., and there is no limitation here.

[0323] The display device described in this embodiment may further include a driver chip 240, which may include a trigger signal generation module 241 for generating a trigger signal, and a signal providing module 242 for receiving the trigger signal and inputting an effective level to a second signal terminal for at least a portion of the time during the conversion phase.

[0324] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0325] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A gate driving circuit, characterized in that, It includes an input module, a pull-up node, an output module, a first pull-down node, a first pull-down node control module, and a first suppression module; The input module is electrically connected to the input control terminal, the first input terminal and the pull-up node respectively, and is used to input the signal input from the first input terminal to the pull-up node under the control of the input control terminal; The output module is electrically connected to the pull-up node, the first signal terminal, and the output terminal, respectively, and is used to output the signal input from the first signal terminal through the output terminal under the control of the potential of the pull-up node; The first pull-down node control module is electrically connected to the second signal terminal, the first pull-down control node, the first pull-down node, the pull-up node, and the first connection node, respectively. It is used to control the potential of the first pull-down control node under the control of the potential of the second signal terminal and the pull-up node, and to control the connection between the first connection node and the first pull-down node under the control of the potential of the pull-up node. Under the control of the potential of the first pull-down node, it controls the signal provided by the second signal terminal to be input to the first pull-down node. The first suppression module is electrically connected to the pull-up node, the first connection node, and the first level signal terminal, respectively, and is used to input the signal provided by the first level signal terminal to the first connection node under the control of the potential of the pull-up node.

2. The gate driving circuit as described in claim 1, characterized in that, The first suppression module includes a first sub-circuit, which is electrically connected to the pull-up node, the first connection node, and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the first connection node under the control of the potential of the pull-up node.

3. The gate driving circuit as described in claim 2, characterized in that, The first pull-down node control module is also electrically connected to the second connection node, and is used to input the signal provided by the second signal terminal to the first pull-down control node under the control of the second signal terminal, and to control the connection between the first pull-down control node and the second connection node under the control of the potential of the pull-up node; The first suppression module is also electrically connected to the second connection node, and is used to input the signal provided by the first level signal terminal to the second connection node under the control of the potential of the pull-up node.

4. The gate driving circuit as described in claim 3, characterized in that, The first suppression module further includes a second sub-circuit, which is electrically connected to the pull-up node, the second connection node and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the second connection node under the control of the potential of the pull-up node.

5. The gate driving circuit according to any one of claims 1 to 4, characterized in that, It also includes the first noise reduction module; The first noise reduction module is electrically connected to the pull-up node, the output terminal, the first pull-down node, and the first level signal terminal, respectively, and is used to input the signal provided by the first level signal terminal to the pull-up node and / or the output terminal under the potential control of the first pull-down node.

6. The gate driving circuit according to any one of claims 2 to 4, characterized in that, It also includes a reset module, which is electrically connected to the pull-up node, the second input terminal and the reset signal terminal respectively, and is used to input the signal input from the second input terminal to the pull-up node under the control of the reset signal terminal.

7. The gate driving circuit according to any one of claims 2 to 4, characterized in that, It also includes a pull-down holding module, which is electrically connected to the output terminal, the third signal terminal and the first level signal terminal respectively, and is used to input the signal input from the first level signal terminal to the output terminal under the control of the third signal terminal.

8. The gate driving circuit according to any one of claims 2 to 4, characterized in that, It also includes an initial reset module, which is electrically connected to the pull-up node, the initial signal terminal and the first level signal terminal respectively, and is used to input the signal input from the first level signal terminal to the pull-up node under the control of the initial signal terminal.

9. The gate driving circuit as described in claim 8, characterized in that, The input module includes a first transistor, the gate of which is electrically connected to the input control terminal, the first electrode of which is electrically connected to the first input terminal, and the second electrode of which is electrically connected to the pull-up node.

10. The gate driving circuit as described in claim 9, characterized in that, The output module includes a second transistor and a first capacitor; The gate of the second transistor is electrically connected to the pull-up node, the first terminal of the second transistor is electrically connected to the first signal terminal, and the second terminal of the second transistor is electrically connected to the output terminal. The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the output terminal.

11. The gate driving circuit as described in claim 10, characterized in that, The first drop-down node control module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The gate and the first terminal of the sixth transistor are both electrically connected to the second signal terminal, and the second terminal of the sixth transistor is electrically connected to the gate of the third transistor; the gate of the third transistor is electrically connected to the first pull-down control node. The first terminal of the third transistor is electrically connected to the second signal terminal, and the second terminal of the third transistor is electrically connected to the first pull-down node; The gate of the fourth transistor is electrically connected to the pull-up node, the first terminal of the fourth transistor is electrically connected to the first pull-down node, and the second terminal of the fourth transistor is electrically connected to the first connection node. The gate of the fifth transistor and the gate of the fourth transistor are both electrically connected to the pull-up node. The first terminal of the fifth transistor and the second terminal of the sixth transistor are both electrically connected to the gate of the third transistor. The second terminal of the fifth transistor is electrically connected to the second connection node.

12. The gate driving circuit as described in claim 11, characterized in that, The gate drive circuit also includes a first noise reduction module; The first noise reduction module includes a seventh transistor and an eighth transistor; The gate of the seventh transistor is electrically connected to the first pull-down node, the first terminal of the seventh transistor is electrically connected to the pull-up node, and the second terminal of the seventh transistor is electrically connected to the first level signal terminal. The gate of the eighth transistor is electrically connected to the first pull-down node, the first terminal of the eighth transistor is electrically connected to the output terminal, and the second terminal of the eighth transistor is electrically connected to the first level signal terminal.

13. The gate driving circuit as described in claim 12, characterized in that, The first sub-circuit includes a ninth transistor, the gate of which is electrically connected to the pull-up node, the first terminal of which is electrically connected to the second terminal of the fourth transistor, and the second terminal of which is electrically connected to the first level signal terminal.

14. The gate driving circuit as described in claim 13, characterized in that, The first suppression module further includes a second sub-circuit, which includes a tenth transistor. The gate of the tenth transistor is electrically connected to the pull-up node and the gate of the ninth transistor. The first terminal of the tenth transistor is electrically connected to the second terminal of the fifth transistor. The second terminal of the tenth transistor is electrically connected to the first level signal terminal.

15. The gate driving circuit as described in claim 6, characterized in that, The reset module includes an eleventh transistor, the gate of which is electrically connected to the reset signal terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the second input terminal.

16. The gate driving circuit as described in claim 7, characterized in that, The pull-down holding module includes a twelfth transistor, the gate of which is electrically connected to the third signal terminal, the first terminal of which is electrically connected to the output terminal, and the second terminal of which is electrically connected to the first level signal terminal.

17. The gate driving circuit as described in claim 8, characterized in that, The initial reset module includes a thirteenth transistor, the gate of which is electrically connected to the initial signal terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the first level signal terminal.

18. The gate driving circuit as claimed in claim 1, characterized in that, It also includes a second drop-down node control module, a second drop-down node, a second noise reduction module, and a second suppression module; The second pull-down node control module is electrically connected to the fourth signal terminal, the second pull-down node, the second pull-down control node, the pull-up node, the third connection node, and the fourth connection node, respectively. It is used to input the signal provided by the fourth signal terminal to the second pull-down control node under the control of the potential of the pull-up node, and to control the connection between the second pull-down control node and the fourth connection node under the control of the potential of the second pull-down control node. It is also used to input the signal provided by the fourth signal terminal to the second pull-down node under the control of the potential of the second pull-down control node, and to control the connection between the second pull-down node and the third connection node under the control of the potential of the pull-up node. The second noise reduction module is electrically connected to the pull-up node, the output terminal, the second pull-down node, and the first level signal terminal, respectively, and is used to input the signal provided by the first level signal terminal to the pull-up node and / or the output terminal under the potential control of the second pull-down node; The second suppression module is electrically connected to the pull-up node, the third connection node and the first level signal terminal respectively, and is used to input the signal provided by the first level signal terminal to the third connection node under the control of the potential of the pull-up node.

19. The gate driving circuit as described in claim 18, characterized in that, The second suppression module includes a third sub-circuit, which is electrically connected to the pull-up node, the third connection node, and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the third connection node under the control of the potential of the pull-up node.

20. The gate driving circuit as described in claim 19, characterized in that, The second suppression module is also electrically connected to the fourth connection node, and is used to input the signal provided by the first level signal terminal to the fourth connection node under the control of the potential of the pull-up node; The second suppression module further includes a fourth sub-circuit, which is electrically connected to the pull-up node, the fourth connection node and the first level signal terminal, respectively, and is used to input the signal input from the first level signal terminal to the fourth connection node under the control of the potential of the pull-up node.

21. The gate driving circuit as described in claim 20, characterized in that, The second pull-down node control module includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; The gate and the first terminal of the seventeenth transistor are both electrically connected to the fourth signal terminal, and the second terminal of the seventeenth transistor is electrically connected to the gate of the fourteenth transistor. The second terminal of the seventeenth transistor is electrically connected to the second pull-down control node; The first terminal of the fourteenth transistor is electrically connected to the fourth signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the second pull-down node; The gate of the fifteenth transistor is electrically connected to the pull-up node, the first terminal of the fifteenth transistor is electrically connected to the second pull-down node, and the second terminal of the fifteenth transistor is electrically connected to the third connection node. The gate of the sixteenth transistor is electrically connected to the gate of the fifteenth transistor and the pull-up node. The first terminal of the sixteenth transistor is electrically connected to the second terminal of the seventeenth transistor and the gate of the fourteenth transistor. The second terminal of the sixteenth transistor is electrically connected to the fourth connection node.

22. The gate driving circuit as described in claim 21, characterized in that, The third sub-circuit includes an eighteenth transistor, and the fourth sub-circuit includes a nineteenth transistor; The gate of the eighteenth transistor is electrically connected to the pull-up node, the first terminal of the eighteenth transistor is electrically connected to the second terminal of the fifteenth transistor, and the second terminal of the eighteenth transistor is electrically connected to the first level signal terminal. The gate of the nineteenth transistor is electrically connected to the pull-up node and the gate of the eighteenth transistor. The first terminal of the nineteenth transistor is electrically connected to the second terminal of the sixteenth transistor. The second terminal of the nineteenth transistor is electrically connected to the first level signal terminal.

23. The gate driving circuit as described in claim 18, characterized in that, The second noise reduction module includes a twentieth transistor and a twenty-first transistor; The gate of the twentieth transistor is electrically connected to the second pull-down node, the first terminal of the twentieth transistor is electrically connected to the pull-up node, and the second terminal of the twentieth transistor is electrically connected to the first level signal terminal. The gate of the 21st transistor is electrically connected to the second pull-down node, the first terminal of the 21st transistor is electrically connected to the output terminal, and the second terminal of the 21st transistor is electrically connected to the first level signal terminal.

24. A shift register, characterized in that, Includes multiple cascaded gate drive circuits as described in any one of claims 1 to 23.

25. A display panel, characterized in that, Includes the shift register as described in claim 24.

26. A driving method for a display panel, characterized in that, The working time of the display panel includes a wake-up phase, wherein the wake-up phase includes a first phase, a transition phase and a second phase, the first phase is a phase in which no data signal is written to the display panel, and the second phase is a phase in which data signal is written to the display panel. The display panel includes multiple cascaded gate driving circuits, each gate driving circuit including an input module, a pull-up node, an output module, a first pull-down node, and a first pull-down node control module. The input module is electrically connected to the input control terminal, the first input terminal and the pull-up node respectively, and is used to input the signal input from the first input terminal to the pull-up node under the control of the input control terminal; The output module is electrically connected to the pull-up node, the first signal terminal, and the output terminal, respectively, and is used to output the signal input from the first signal terminal through the output terminal under the control of the potential of the pull-up node; The first pull-down node control module is electrically connected to the second signal terminal, the first pull-down node, the first pull-down control node, the pull-up node, the first connection node, and the second connection node, respectively. It is used to input the signal provided by the second signal terminal to the first pull-down control node under the control of the second signal terminal, and to control the connection between the first pull-down control node and the second connection node under the control of the potential of the pull-up node. It is also used to input the signal provided by the second signal terminal to the first pull-down node under the control of the potential of the first pull-down control node, and to control the connection between the first pull-down node and the first connection node under the control of the potential of the pull-up node. The driving method for the display panel includes: During at least a portion of the time included in the conversion phase, under the control of the trigger signal, an effective level is input to the second signal terminal so that the first pull-down node control module controls the pull-up of the first pull-down node to a high potential.

27. The driving method for a display panel as described in claim 26, characterized in that, The driving method for the display panel includes: During the conversion phase, under the control of the trigger signal, an effective level is input to the second signal terminal.

28. The driving method for a display panel as described in claim 26 or 27, characterized in that, The gate driving circuit further includes a second pull-down node control module; the driving method for the display panel further includes: When a valid level is input to the second signal terminal, the second pull-down node control module controls the pull-up of the second node's potential.

29. The driving method for a display panel as described in claim 26, characterized in that, The step of inputting an effective level to the second signal terminal under the control of the trigger signal includes: The trigger signal is converted from a first voltage signal to a second voltage signal to control the input of an effective level to the second signal terminal.

30. A display device, characterized in that, The display device, including the display panel as described in claim 25, further includes a driver chip, the driver chip including a trigger signal generation module and a signal providing module; The trigger signal generation module is used to generate a trigger signal to the signal providing module; The signal providing module is used to control the input of a valid level to the second signal terminal during at least a portion of the time included in the conversion phase, under the control of the trigger signal, so that the first pull-down node control module can pull up the potential of the first pull-down node.

Images