A DC detection circuit and electronic device suitable for Class D amplifiers

Abstract

This application discloses a DC detection circuit and electronic device suitable for Class D amplifiers. A charge / discharge circuit controls the supply of charging current to a capacitor to establish a pre-charge voltage or controls the supply of discharge current required for capacitor discharge. A PWM signal processing circuit controls the charge / discharge circuit based on the duty cycle difference between a first pulse width modulation signal and a second pulse width modulation signal. A reset circuit is connected between the charge / discharge node and the common terminal. A comparator compares the voltage of the charge / discharge node with a reference voltage. The reset circuit is used to reset the voltage of the charge / discharge node when the input signal is a normal audio signal at a zero-crossing point; or, when the input signal is a DC signal, not to perform a reset operation; or, when the input signal switches from a normal audio signal to a DC signal, to end the reset operation. This application incorporates a reset circuit to avoid misjudgment during normal audio signal and DC signal switching, improving the accuracy and reliability of the DC detection circuit.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a DC detection circuit and electronic device suitable for Class D amplifiers. Background Technology

[0002] The core component responsible for producing sound in audio equipment is the loudspeaker, also known as a "horn." It is a transducer that converts electrical signals into sound signals and is an indispensable part of in-vehicle entertainment and audio systems. Car loudspeakers are usually driven by high-efficiency Class D audio amplifiers. During the operation of the Class D audio amplifier driving the loudspeaker, there are many protection and detection circuits (short circuit, open circuit, DC, overcurrent, clipping, etc.) to ensure the normal operation of the loudspeaker. Among them, DC detection of the Class D audio amplifier is used to determine whether there is a DC component in the loudspeaker output voltage, and by setting a detection threshold, excessive DC signals are avoided to prevent damage to the loudspeaker, thus protecting the loudspeaker.

[0003] However, if the DC detection circuit malfunctions or becomes abnormal, it may misjudge when the input signal is a normal audio signal or when the input signal is switched from a normal audio signal to a DC signal, thus reducing the reliability of the DC detection circuit. Summary of the Invention

[0004] In view of the above-mentioned problems in the prior art, this application provides a DC detection circuit and electronic device suitable for Class D amplifiers.

[0005] In a first aspect, embodiments of this application provide a DC detection circuit suitable for a Class D amplifier, wherein the Class D amplifier generates a first pulse width modulation signal and a second pulse width modulation signal based on an input signal; the DC detection circuit includes:

[0006] A capacitor connected between a charge / discharge node and a common terminal; a charge / discharge circuit connected to the charge / discharge node.

[0007] A PWM signal processing circuit is used to generate a first control signal DC_PWMN and a second control signal DC_PWMP based on the duty cycle difference between the first pulse width modulation signal and the second pulse width modulation signal. The first control signal DC_PWMN and the second control signal DC_PWMP control the charging and discharging circuit to provide the charging current or the discharging current to the charging and discharging node.

[0008] A reset circuit is connected between the charge / discharge node and the common terminal;

[0009] A comparator is used to compare the voltage of the charge / discharge node with a reference voltage and output the comparison result.

[0010] The reset circuit is configured to perform a reset operation when the input signal is a normal audio signal and the audio signal crosses zero, wherein the reset operation resets the voltage of the charging / discharging node to the voltage of the common terminal; or, when the input signal is a DC signal, the reset operation is not performed; or, when the input signal switches from a normal audio signal to a DC signal, the reset operation is terminated.

[0011] Secondly, embodiments of this application provide an electronic device including the DC detection circuit described above.

[0012] Compared with the prior art, the beneficial technical effects achieved by this application are as follows:

[0013] The DC detection circuit provided in this application embodiment is equipped with a reset circuit. When the input signal is a normal audio signal, a reset operation is performed when the audio signal crosses zero; or, when the input signal is a DC signal, no reset operation is performed; or, when the input signal switches from a normal audio signal to a DC signal, the reset operation ends. This can avoid misjudgment by the DC detection circuit and ensure the reliability of the DC detection circuit.

[0014] The DC detection circuit provided in this application uses a charging current proportional to the battery voltage and a reference current to charge and discharge the charging and discharging nodes. The charging time is determined by the difference in the PWM signal generated by the Class D amplifier loop, thus avoiding the DC detection threshold being related to the battery voltage. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a typical Class D loop architecture for Class D audio amplifiers;

[0017] Figure 2 The circuit diagram is for a prior art DC detection circuit.

[0018] Figure 3 for Figure 2 The signal timing diagram of the DC detection circuit shown is shown.

[0019] Figure 4 This is a schematic diagram of a DC detection circuit provided in Embodiment 1 of this application;

[0020] Figure 5This is a schematic diagram of the reset signal generation circuit in the DC detection circuit provided in Embodiment 1 of this application;

[0021] Figure 6 This is a schematic diagram of the reset signal generation circuit in the DC detection circuit provided in Embodiment 2 of this application;

[0022] Figure 7 This is a schematic diagram of the first current source circuit in the DC detection circuit provided in Embodiment 3 of this application;

[0023] Figure 8 This is a schematic diagram of the second current source circuit in the DC detection circuit provided in Embodiment 3 of this application;

[0024] Figure 9 This is the normal audio signal timing of the reset circuit in the DC detection circuit provided in Embodiment 1 of this application;

[0025] Figure 10 The timing sequence of the DC signal (DC signal) for the reset circuit in the DC detection circuit provided in Embodiment 1 of this application;

[0026] Figure label:

[0027] 1-DC detection circuit, 11-charge and discharge circuit, 12-PWM signal processing circuit, 13-reset circuit, 14-comparator, 15-first timer, 101-first current mirror circuit, 102-second current mirror circuit, 111-first current source circuit, 112-second current source circuit, 131-transistor, 132-reset signal generation circuit, 1301-first reset logic unit, 1302-second reset logic unit, 1303-third reset logic unit 201 - First NOT gate, 202 - Second NOT gate, 203 - Third NOT gate, 204 - Fourth NOT gate, 205 - Fifth NOT gate, 206 - Sixth NOT gate, 207 - Seventh NOT gate, 208 - Eighth NOT gate, 301 - First NAND gate, 302 - Second NAND gate, 303 - Third NAND gate, 304 - Fourth NAND gate, 305 - Fifth NAND gate, 401 - First NOR gate, 501 - First flip-flop, 502 - Second flip-flop, 503 - Third flip-flop. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] Furthermore, the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. Since the source and drain of the transistor used in this application are symmetrical, their sources and drains are interchangeable. According to the configuration shown in the drawings, the middle terminal of the transistor is designated as the gate, the signal input terminal as the source, and the output terminal as the drain.

[0030] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0031] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0032] Figure 1 This is a typical Class D loop architecture for Class D audio amplifiers. A Class D loop refers to a feedback loop used to control a Class D audio amplifier. Figure 1 The Class D audio amplifier shown includes an input amplifier, an integrator, a comparator, a logic control module, and a driver module. This Class D audio amplifier uses a single power supply. The high and low levels of the pulse output signals SPKP and SPKN are the battery voltage VBAT and ground GND, respectively. INT1 and operational amplifier INT2 constitute the amplifier. When the Class D audio amplifier is working, the audio input signal VIN is integrated to generate signals INT2_OUTP and INT2_OUTN. These signals are then modulated by the triangular wave carrier signal VRAMP, generating a first pulse width modulation signal PWMP and a second pulse width modulation signal PWMN. These signals are then output as two pulse signals, SPKP and SPKN, through the logic control and driver modules to drive the speaker to produce sound.

[0033] In the existing technology, Figure 2 The circuit diagram of a prior art DC detection circuit is shown below. Figure 2As shown, the pulse width modulation signals PWMP and PWMN output from the Class D amplifier PWM modulation comparator are compared with a reference signal PWM_REF (representing the DC component of the PWM reference signal). After passing through an OR gate and a timer with a latching function, a DC detection and judgment signal is output. Figure 1 As shown, the pulse width modulation signal PWMP and pulse width modulation signal PWMN are generated by modulating the analog audio signal output by the integrator with a triangular wave.

[0034] Figure 3 for Figure 2 The signal timing diagram of the DC detection circuit shown is as follows; Figure 3 As shown, when there is no signal input, PWMP and PWMN are equal and have a 50% duty cycle (mismatch not considered). When there is an input signal, the duty cycle of PWMP and PWMN increases, and vice versa. When a normal audio signal is input, the duty cycles of PWMP and PWMN alternate. When a DC signal is input, the duty cycles of PWMP and PWMN remain fixed, with one end larger and the other smaller. When the reference signal PWM_REF is set to a 55% duty cycle, if the duty cycle of either PWMP or PWMN exceeds 55%, the RESET signal will go high, starting a timer with a lockout function. When the timer exceeds the set time, the DC_DETECT output will go high, indicating a DC input greater than the threshold. At this time, the system will shut down the Class D amplifier to protect the speaker.

[0035] However, this DC detection method may lead to misjudgments during normal audio signals and transitions between normal audio signals and DC signals, affecting the accuracy and reliability of the DC detection circuit. The frequency range of normal audio signals referred to in this application is typically 20Hz to 20,000Hz, a range known as the human hearing range. Frequencies below 20Hz are called infrasound, while frequencies above 20,000Hz are called ultrasound. Abnormal audio signals include ultrasound (above 20,000Hz) or infrasound (below 20Hz).

[0036] Example 1

[0037] To address the potential misjudgment issue in current DC detection circuits, this application provides a DC detection circuit 1 suitable for Class D amplifiers, whereby the Class D amplifier generates a first pulse width modulation signal PWMP and a second pulse width modulation signal PWMN to drive a speaker to produce sound.

[0038] like Figure 4As shown, the DC detection circuit 1 includes a capacitor C1, a charging and discharging circuit 11, a PWM signal processing circuit 12, a reset circuit 13, and a comparator 14.

[0039] Capacitor C1 is connected between charge / discharge node B and common terminal VSS. Charge / discharge node B is used to control the charging and discharging of capacitor C1. Charge / discharge circuit 11 is connected to charge / discharge node B and is used to receive the charging current I1 for charging capacitor C1 or the discharging current I2 required for capacitor C1 to discharge. PWM signal processing circuit 12 is used to generate a first control signal DC_PWMN and a second control signal DC_PWMP based on the difference in duty cycles of the first pulse width modulation signal PWMP and the second pulse width modulation signal PWMN to control the charge / discharge circuit 11 to provide charging current to the capacitor or provide the discharging current required for capacitor discharge. Reset circuit 13 is connected between charge / discharge node B and common terminal VSS. Comparator 14 is used to compare the voltage VCHARGE of charge / discharge node B with the reference voltage VTH_DC and output the comparison result. The reset circuit 13 is used to perform a reset operation when the audio signal crosses zero when the input signal is a normal audio signal. The reset operation is to reset the voltage of the charging and discharging node to the voltage of the common terminal VSS; or, when the input signal is a DC signal, no reset operation is performed; or, when the input signal switches from a normal audio signal to a DC signal, the reset operation ends.

[0040] The common terminal VSS (Voltage Source Ground) refers to a common ground pin or node in a circuit. VSS is typically used as a reference point for the circuit, providing a stable potential reference to ensure accurate measurement and control of potential differences between different parts of the circuit. It is usually connected to the negative terminal of the power supply, serving as a common point for all parts of the circuit. VSS can also be used to connect loads, signal grounds, and other locations in the circuit. It's important to note that VSS is not necessarily an actual ground wire (ground wire is usually the actual physical ground point), but rather a reference point defined within the circuit.

[0041] In this embodiment, the reset circuit 13 includes a transistor 131, the gate of which is connected to a reset signal, and the drain and source of the transistor 131 are connected in series between the charge / discharge node and the common terminal.

[0042] As an example, the DC detection circuit 1 also includes a reset signal generation circuit 132, which generates a detection reset signal. The reset signal generation circuit 132 includes a first reset logic unit 1301, a second reset logic unit 1302, and a third reset logic unit 1303. The first reset logic unit 1301 is used to generate reset signals for the first and second flip-flops 501 and 502 based on the enable signal and the signals output by the first and second flip-flops 501 and 502. The second reset logic unit 1302 is used to generate clock signals for the first and second flip-flops 501 and 502 based on the duty cycle of the inverted signals of the first and second pulse width modulation signals, and outputs the states of the input terminals of the first and second flip-flops 501 and 502 to the output terminals when the clock edge of the clock signal arrives. The second reset logic unit 1302 is also used to generate clock signals for the third flip-flop 503 based on the output signals of the first and second flip-flops 501 and 502. The third reset logic unit 1303 is used to generate reset signals for the third flip-flop 503 based on the clock signal of the Class D amplifier and the inverted enable signal, and the third flip-flop 503 outputs a detection reset signal.

[0043] A schematic diagram of the reset signal generation circuit 132 in the DC detection circuit provided in Embodiment 1 of this application is shown below. Figure 5 As shown, the reset signal generation circuit 132 includes a first NOT gate 201, a second NOT gate 202, a third NOT gate 203, a fourth NOT gate 204, a fifth NOT gate 205, a sixth NOT gate 206, a seventh NOT gate 207, an eighth NOT gate 208, a first NAND gate 301, a second NAND gate 302, a third NAND gate 303, a fourth NAND gate 304, a fifth NAND gate 305, a first NOR gate 401, a first flip-flop 501, a second flip-flop 502, and a third flip-flop 503.

[0044] The input of the second NOT gate 202 is connected to the inverted signal PWMP_B of the first pulse width modulation signal PWMP, and the input of the third NOT gate 203 is connected to the inverted signal PWMN_B of the second pulse width modulation signal PWMN. The output of the second NOT gate 202 and the inverted signal PWMN_B of the second pulse width modulation signal PWMN are connected to the two inputs of the second NAND gate 302, and the output signal of the third NOT gate 203 and the inverted signal PWMP_B of the first pulse width modulation signal PWMP are connected to the two inputs of the third NAND gate 303.

[0045] The output signal of the second NAND gate 302 is connected to the input of the fourth NOT gate 204, and the output of the third NAND gate 303 is connected to the input of the fifth NOT gate; the output of the fourth NOT gate 204 is connected to the clock terminal of the first flip-flop 501, and the output of the fifth NOT gate 205 is connected to the clock terminal of the second flip-flop 502.

[0046] The inputs of the first flip-flop 501 and the second flip-flop 502 are both connected to a high level. The positive outputs of the first flip-flop 501 and the second flip-flop 502 are respectively connected to the two inputs of the fourth NAND gate 304. The output of the fourth NAND gate 304 is connected to the clock terminal of the third flip-flop 503 after passing through the fifth NOT gate 205. The input of the third flip-flop 503 is connected to a high level.

[0047] One input of the first NAND gate 301 is connected to an enable signal, and the other input is connected to the output of the fourth NAND gate 304. The output of the first NAND gate 301 is connected to the input of the first NOT gate 201, and the output of the first NOT gate 201 is connected to the reset terminal of the first flip-flop 501 and the reset terminal of the second flip-flop 502.

[0048] The input of the seventh NOT gate 207 is connected to the clock signal (PWM_CLK) of the class D loop, and to one input of the fifth NAND gate 305. The output of the seventh NOT gate 207 is connected to the other input of the fifth NAND gate 305. The output of the fifth NAND gate 305 is connected to one input of the first NOR gate 401 after passing through the eighth NOT gate 208. The other input of the first NOR gate 401 is connected to the inverted signal of the enable signal. The output of the first NOR gate 401 is connected to the reset terminal of the third flip-flop 503. The input of the third flip-flop 503 is connected to a high level, and the output of the third flip-flop 503 outputs a detection reset signal.

[0049] In some embodiments, the DC detection circuit 1 further includes a first timer 15. The comparator 14 (COMP) outputs to the first timer 15. When the comparator 14 outputs high, the first timer 15, which has a latching function, counts the time. Since the minimum audio signal frequency is 20Hz, the set value of the first timer 15 must be at least greater than 50ms. Only when the comparator COMP output voltage is high for a period exceeding the timing threshold of the first timer 15 is the output DC_DETECT of the first timer 15 latched high, indicating that the Class D amplifier output is a DC signal. When the first timer 15 output DC_DETECT is latched high, the first timer 15 triggers a protection mechanism, such as shutting down the amplifier (Class D amplifier) ​​output or otherwise reducing the DC bias to ensure that the DC bias does not persist for an extended period, thereby protecting the speaker and amplifier from potential damage. It provides a mechanism for monitoring and responding to DC bias to ensure the normal operation of the amplifier and the safety of the speaker.

[0050] The DC detection circuit 1 provided in this embodiment can be used in an audio-class power amplifier to implement DC detection functionality. When the first control signal DC_PWMN is active, the unity-gain operational amplifier AMP maintains the pre-charge voltage VX of pre-charge node A equal to the voltage VCHARGE of charge / discharge node B. When the second control signal DC_PWMP is active, the pre-charge voltage VX has already been established, further facilitating the establishment of the charging voltage and improving charging efficiency. In some embodiments, a first timer 15 with a locking function is added after the comparator 14. The first timer 15 locks only after its count exceeds 50ms, preventing accidental toggling.

[0051] Example 2

[0052] A schematic diagram of the reset signal generation circuit 132 in the DC detection circuit provided in Embodiment 2 of this application is shown below. Figure 6 As shown. With Figure 5 Unlike the reset signal generation circuit 132 shown, this embodiment also includes a fourth flip-flop 504. The clock signal (PWM_CLK) of the class D loop is connected to the clock terminal of the fourth flip-flop 504, the input terminal of the fourth flip-flop 504 is connected to the inverting output terminal, and the non-inverting output terminal is connected to the seventh NOT gate 207. The phase delay or timing control of the clock signal can be achieved using the fourth flip-flop 504 and an inverting D flip-flop.

[0053] In the reset signal generation circuit 132, the first reset logic unit 1301 is the reset logic for the first flip-flop 501 (dff1) and the second flip-flop 502 (dff2), which prevents the output detection reset signal RESET from being locked high when switching from a normal audio signal to a DC signal; the second reset logic unit 1302 is the main part of the reset signal generation circuit 132. By detecting the duty cycle of the PWMP_B and PWMN_B signals, the first flip-flop 501 to the third flip-flop 503 behave differently when a normal audio signal and a DC signal are input. For details, please refer to the following reset principle introduction.

[0054] The third reset logic unit 1303 is the reset logic of the third flip-flop 503 of the second reset logic unit 1302 in the reset signal generation circuit 132. It periodically generates the reset signal dff3_rst of the third flip-flop 503 using the clock PWM_CLK of the switching frequency.

[0055] Reset Principle Introduction: This application proposes a reset logic for the voltage VCHARGE of the charge / discharge node B, such as... Figure 5 As shown. When a normal audio signal is input, the timing is as follows. Figure 9As shown, at the zero-crossing point of a normal audio signal, the voltage VCHARGE of the charging / discharging node B is briefly reset, that is, the voltage VCHARGE of the charging / discharging node B is reset to the voltage of the common terminal VSS. Specifically, near the zero-crossing point of the audio signal, the clock port dff3_ck of the third flip-flop 503 will have a low-to-high transition, and then be reset by the reset port dff3_rst of the third flip-flop 503 (generated by the switching frequency of the classD loop), thereby generating a brief high pulse width. As a result, the detection reset signal RESET output by the third flip-flop 503 will have a high pulse width, the output of comparator 14 (COMP) will become 0, and it will also reset the first timer 15. When a DC signal is input, the timing is as follows. Figure 10 As shown, because the duty cycle of PWMP_B or PWMN_B is always greater at one end than the other, the clock port dff3_ck of the third flip-flop 503 remains low, so the detection reset signal RESET output by the third flip-flop 503 will not function. When the input signal switches from a normal audio signal to a DC signal, due to the reset of the third flip-flop 503, the detection reset signal RESET will not remain high, thus exiting the reset operation and allowing normal detection of the DC signal. This reset logic performs the RESET function for normal audio signals, avoiding false judgments and improving the reliability of detection.

[0056] like Figure 4 As shown, the charging and discharging circuit 11 includes a first current mirror circuit 101, a first switch S1, a second switch S2, and a second current mirror circuit 102. The first current mirror circuit 101 is used to provide a charging current I1 to the capacitor C1; the first switch S1 is connected in series with the first current mirror circuit 101 and is also connected to the charging and discharging node B; the second switch S2 is connected in series with the first current mirror circuit 101 and is also connected to the charging and discharging node B; the second current mirror circuit 102 is connected to the charging and discharging node B to provide a discharging current I2 to discharge from the capacitor C1.

[0057] In this embodiment, the second switch S2 is electrically connected to the charge / discharge node B via an operational amplifier AMP. The inverting input of the operational amplifier AMP is connected to the second switch S2, the output of the operational amplifier AMP is connected to the inverting input, and the non-inverting input of the operational amplifier AMP is connected to the charge / discharge node B. The unity-gain operational amplifier AMP is used to clamp the pre-charge voltage VX to be equal to the voltage VCHARGE of the charge / discharge node B when the charge / discharge circuit 11 is not charging the capacitor C1, ensuring the establishment of the charging voltage during the next charge, thereby improving charging efficiency.

[0058] In this embodiment, the charging current source I_charge, which mirrors the charging current I1, is generated by the battery voltage VBAT. At this time, the charging current I1 is related to the battery voltage VBAT. If it is a DC input signal, it precisely cancels out the influence of the battery voltage VBAT. Figure 4 As shown, the first current mirror circuit 101 includes a first current source circuit 111, and the second current mirror circuit 102 includes a second current source circuit 112.

[0059] Example 3

[0060] As an example, based on the above embodiments, in Embodiment 3, the first current source circuit 111 is as follows: Figure 7 As shown, the second current source circuit 112 is as follows: Figure 8 As shown. Figure 7 As shown, in the first current source circuit 111, the charging mirror current source I_charge is generated by the battery voltage VBAT after being divided by the first resistor R1 and the second resistor R2; the first current source circuit 111 provides the charging mirror current source I_charge proportional to the battery voltage VBAT, and / or; the second current source circuit 112 provides the discharging mirror current source I_discharge based on the reference voltage VREF.

[0061]

[0062]

[0063] I1 = M * I_charge;

[0064] I2 = N * I_charge;

[0065]

[0066]

[0067]

[0068] Where VREF is the reference voltage, and M is... Figure 4 The current mirror coefficients of the first transistor M1 and the second transistor M2, N is Figure 4 The current mirror coefficients of the third transistor M3 and the fourth transistor M4 are given. D is the duty cycle difference information of the sampled first pulse width modulation signal PWMP and the second pulse width modulation signal PWMN. T is the switching period of the classD loop. VDC is the preset output DC voltage threshold of the classD loop.

[0069] In the above example, the reference voltage VTH_DC can be set according to the preset DC voltage threshold VDC of the classD loop output.

[0070] As can be seen from the above derivation, the DC detection circuit 1 provided in Embodiment 3 ensures that the DC voltage threshold VDC required for the voltage VCHARGE of the charging / discharging node B to reach the reference voltage VTH_DC remains unchanged when the battery voltage VBAT changes. The first current source circuit 111 and the second current source circuit 112 provided in this embodiment of the application avoid the influence of the battery voltage VBAT on the DC detection of the class D power amplifier. The range of vehicle battery voltage variation is large, and the application scenarios are diverse, making it suitable for the DC detection of vehicle audio power amplifiers.

[0071] In this embodiment, the first switch S1 and the second switch S2 are P-type transistors; the gate of the first switch S1 is connected to the second control signal DC_PWMP, and the gate of the second switch S2 is connected to the first control signal DC_PWMN. The PWM signal processing circuit 12 controls the on or off of the first switch S1 and the second switch S2 in the charging and discharging circuit 11.

[0072] In a specific embodiment, the first pulse width modulation signal PWMP and the second pulse width modulation signal PWMN are level-converted and then logically operated to obtain the first control signal DC_PWMN and the second control signal DC_PWMP.

[0073] In this embodiment, as Figure 4 As shown, the PWM signal processing circuit 12 includes an NAND gate and a NOT gate; the two input terminals of the NAND gate are respectively input to the inverse signal PWMP_B of the first pulse width modulation signal PWMP and the inverse signal PWMN_B of the second pulse width modulation signal PWMN, and the output terminal of the NAND gate outputs the first control signal DC_PWMN; the input terminal of the NOT gate is input to the first control signal DC_PWMN, and the output terminal of the NOT gate outputs the second control signal DC_PWMP.

[0074] In this embodiment, the difference between the first pulse width modulation signal PWMP and the second pulse width modulation signal PWMN is sampled using an XNOR gate to obtain the first control signal DC_PWMN and the second control signal DC_PWMP. Here, PWMP_B is the inverted form of the first pulse width modulation signal PWMP output from the pulse width modulation comparator in the classD loop, and PWMN_B is the inverted form of the first pulse width modulation signal PWMN. The first control signal DC_PWMN and the second control signal DC_PWMP are used to control the charging and discharging of capacitor C1 connected to the charging / discharging node B. The charging current is I1, and the discharging current is I2.

[0075] Figure 4The discharge current I2 is always present, continuously discharging the voltage VCHARGE of the charging / discharging node B. The charging time of the charging current I1 on the voltage VCHARGE of the charging / discharging node B is determined by the first control signal DC_PWMN and the second control signal DC_PWMP. When the second control signal DC_PWMP is low and the first control signal DC_PWMN is high (i.e., the first switch S1 is on and the second switch S2 is off), the charging / discharging node B is charged. When the second control signal DC_PWMP is high and the first control signal DC_PWMN is low (i.e., the second switch S2 is on and the first switch S1 is off), the charging / discharging node B is not charged. At this time, the unity-gain operational amplifier AMP clamps the pre-charge voltage VX of the pre-charge node A to ensure its establishment during the next charge. Comparator 14 includes comparator COMP, which compares the voltage VCHARGE of the charging / discharging node B with the reference voltage VTH_DC. When the voltage VCHARGE of the charging / discharging node B is greater than the reference voltage VTH_DC, the comparator COMP outputs high.

[0076] The DC detection circuit 1 provided in this embodiment has a charging current I1 generated by a charging mirror current source I_charge that is proportional to the battery voltage VBAT, and a discharging current I2 generated based on the reference voltage VREF. The charging and discharging nodes B are charged and discharged in this way. The charging time is determined by the difference of the PWM signal generated by the classD loop, thus avoiding the DC detection threshold being related to the battery voltage.

[0077] This application also provides an electronic device, including a DC detection circuit 1 provided in any of the possible implementations described above.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above embodiments are merely illustrative of several implementation methods described in detail, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the protection scope of this specification. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A DC detection circuit suitable for Class D amplifiers, characterized in that, The Class D amplifier generates a first pulse width modulation signal and a second pulse width modulation signal based on the input signal; the DC detection circuit includes: A capacitor connected between a charge / discharge node and a common terminal; The charging and discharging circuit (11) includes a first current mirror circuit (101), a second current mirror circuit (102), a first switch, and a second switch; The first current mirror circuit (101) is connected to the charge / discharge node and provides charging current to the capacitor; the first switch is connected in series with the first current mirror circuit (101) and is also connected to the charge / discharge node; the second switch is connected in series with the first current mirror circuit (101) and is also connected to the charge / discharge node; the second current mirror circuit (102) is connected to the charge / discharge node and continuously provides discharging current to the charge / discharge node, and the current mirror circuit uses the battery voltage to provide the current source required for the charging current; The first current mirror circuit (101) includes a first current source circuit (111), and the second current mirror circuit (102) includes a second current source circuit (112). The first current source circuit (111) provides a charging mirror current source proportional to the battery voltage, and / or the second current source circuit (112) provides a discharging mirror current source based on a reference voltage; the charging mirror current source is a mirror current of the charging current, and the discharging mirror current source is a mirror current of the discharging current. The PWM signal processing circuit (12) is used to generate a first control signal and a second control signal based on the duty cycle difference between the first pulse width modulation signal and the second pulse width modulation signal. The first control signal and the second control signal control the charging and discharging circuit (11) to provide charging current to the charging and discharging node through the first current mirror circuit. A reset circuit (13) is connected between the charge / discharge node and the common terminal; The reset circuit (13) includes a transistor (131), the gate of the transistor (131) is connected to a reset signal, and the drain and source of the transistor (131) are connected in series between the charging / discharging node and the common terminal. Comparator (14), the comparator (14) is used to compare the voltage of the charging and discharging node with the reference voltage and output the comparison result. The reference voltage does not change with the change of battery voltage. The reset circuit (13) is used to perform a reset operation when the input signal is a normal audio signal and the audio signal crosses zero. The reset operation is to reset the voltage of the charging and discharging node to the voltage of the common terminal; or, when the input signal is a DC signal, the reset operation is not performed; or, when the input signal is switched from a normal audio signal to a DC signal, the reset operation is terminated. When the battery voltage changes, the DC detection circuit is unaffected by the battery voltage.

2. The DC detection circuit according to claim 1, characterized in that, The DC detection circuit also includes a reset signal generation circuit (132), and the detection reset signal is generated by the reset signal generation circuit (132); The reset signal generation circuit (132) includes a first reset logic unit (1301), a second reset logic unit (1302), and a third reset logic unit (1303); The first reset logic unit (1301) is used to generate reset signals for the first flip-flop (501) and the second flip-flop (502) based on the enable signal and the signals output by the first flip-flop (501) and the second flip-flop (502). The second reset logic unit (1302) is used to generate clock signals for the first flip-flop (501) and the second flip-flop (502) according to the duty cycle of the inverted signal of the first pulse width modulation signal and the inverted signal of the second pulse width modulation signal, and output the state of the input terminals of the first flip-flop (501) and the second flip-flop (502) to the output terminal when the clock edge of the clock signal arrives; the second reset logic unit (1302) is also used to generate clock signals for the third flip-flop (503) according to the output signals of the first flip-flop (501) and the second flip-flop (502), and the third flip-flop (503) outputs the detection reset signal; The third reset logic unit (1303) is used to generate a reset signal for the third flip-flop (503) based on the clock signal of the Class D amplifier and the inverse signal of the enable signal.

3. The DC detection circuit according to claim 2, characterized in that, The reset signal generation circuit (132) includes a first NOT gate (201), a second NOT gate (202), a third NOT gate (203), a fourth NOT gate (204), a fifth NOT gate (205), a sixth NOT gate (206), a seventh NOT gate (207), an eighth NOT gate (208), a first NAND gate (301), a second NAND gate (302), a third NAND gate (303), a fourth NAND gate (304), a fifth NAND gate (305), a first NOR gate (401), a first flip-flop (501), a second flip-flop (502), and a third flip-flop (503); The input terminal of the second NOT gate (202) is connected to the inverted signal of the first pulse width modulation signal, and the input terminal of the third NOT gate (203) is connected to the inverted signal of the second pulse width modulation signal; the output signal of the second NOT gate (202) and the inverted signal of the second pulse width modulation signal are connected to the two input terminals of the second NAND gate (302), and the output signal of the third NOT gate (203) and the inverted signal of the first pulse width modulation signal are connected to the two input terminals of the third NAND gate (303); The output of the second NAND gate (302) is connected to the input of the fourth NOT gate (204), and the output of the third NAND gate (303) is connected to the input of the fifth NOT gate; the output of the fourth NOT gate (204) is connected to the clock terminal of the first flip-flop (501), and the output of the fifth NOT gate (205) is connected to the clock terminal of the second flip-flop (502); The input terminals of the first flip-flop (501) and the second flip-flop (502) are both connected to a high level. The positive output terminals of the first flip-flop (501) and the second flip-flop (502) are respectively connected to the two input terminals of the fourth NAND gate (304). The output terminal of the fourth NAND gate (304) is connected to the clock terminal of the third flip-flop (503) through the fifth NOT gate (205). The input terminal of the third flip-flop (503) is connected to a high level. One input of the first NAND gate (301) is connected to an enable signal, and the other input is connected to the output of the fourth NAND gate (304). The output of the first NAND gate (301) is connected to the input of the first NOT gate (201), and the output of the first NOT gate (201) is connected to the reset terminal of the first flip-flop (501) and the reset terminal of the second flip-flop (502). The input of the seventh NOT gate (207) is connected to the clock signal of the classD loop and to one input of the fifth NAND gate (305). The output of the seventh NOT gate (207) is connected to the other input of the fifth NAND gate (305). The output of the fifth NAND gate (305) is connected to one input of the first NOR gate (401) after passing through the eighth NOT gate (208). The other input of the first NOR gate (401) is connected to the inverted signal of the enable signal. The output of the first NOR gate (401) is connected to the reset terminal of the third flip-flop (503). The input of the third flip-flop (503) is connected to a high level. The output of the third flip-flop (503) outputs the detection reset signal.

4. The DC detection circuit according to claim 1, characterized in that, The second switch is electrically connected to the charge / discharge node via an operational amplifier; The inverting input of the operational amplifier is connected to the second switch, the output of the operational amplifier is connected to the inverting input, and the non-inverting input of the operational amplifier is connected to the charging / discharging node.

5. The DC detection circuit according to claim 4, characterized in that, The first switch and the second switch are P-type transistors; The gate of the first switch is connected to the second control signal, and the gate of the second switch is connected to the first control signal. The first control signal and the second control signal are obtained by performing level conversion on the first pulse width modulation signal and the second pulse width modulation signal and then performing logical operations.

6. The DC detection circuit according to claim 5, characterized in that, The PWM signal processing circuit (12) includes an NAND gate and a NOT gate; The two inputs of the XNOR gate are respectively the inverse of the first pulse width modulation signal and the inverse of the second pulse width modulation signal, and the output of the XNOR gate is the first control signal. The first control signal is input to the input terminal of the NOT gate, and the second control signal is output to the output terminal of the NOT gate.

7. An electronic device, characterized in that, Includes the DC detection circuit as described in any one of claims 1 to 6.

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