A method and apparatus for processing a signal

Abstract

The embodiment of the present application provides a method and device for processing signals, and specifically, the method comprises the following steps: performing signal transmission simulation based on a first reference voltage to obtain a first simulation error code time endpoint and a first simulation pass time endpoint; performing cyclic simulation based on the first simulation error code time endpoint and the first simulation pass time endpoint, updating the simulation error code time endpoint and the simulation pass time endpoint until the time interval between adjacent simulation error code time endpoints and simulation pass time endpoints is equal to a first time precision. The method and device of the embodiment of the present application can perform simulation by selecting fewer simulation time points between the simulation error code time endpoint and the simulation pass time endpoint, can reduce simulation time and simulation complexity, can reduce manual on-duty time, and can improve simulation efficiency.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more specifically, to a method and apparatus for processing signals. Background Technology

[0002] In the design and manufacturing process of chips, various simulation verification processes are usually required, including signal integrity (SI) simulation. However, SI simulation requires a significant amount of manual monitoring time, and the SI simulation process itself is time-consuming. How to reduce SI simulation time and minimize manual monitoring time is an urgent problem to be solved. Summary of the Invention

[0003] This application provides a method and apparatus for processing signals, which can reduce simulation time and complexity, reduce manual monitoring time, and improve simulation efficiency.

[0004] In a first aspect, a method for processing signals is provided, comprising: performing signal transmission simulation based on a first reference voltage to obtain a first simulated bit error time endpoint and a first simulated pass time endpoint; taking P time points as simulation time points between adjacent first simulated bit error time endpoints and first simulated pass time endpoints, performing signal transmission simulation based on the first reference voltage to obtain a second simulated bit error time endpoint and a second simulated pass time endpoint, wherein a first time interval between adjacent second simulated bit error time endpoints and second simulated pass time endpoints is greater than a first time precision, and P is a positive integer; taking Q time points as simulation time points within the first time interval, performing signal transmission simulation based on the first reference voltage to obtain a third simulated bit error time endpoint and a third simulated pass time endpoint, wherein a second time interval between adjacent third simulated bit error time endpoints and third simulated pass time endpoints is equal to the first time precision, and Q is a positive integer.

[0005] By taking multiple time points between adjacent simulation error time endpoints and simulation pass time endpoints and performing cyclic simulation until the simulation accuracy is achieved, the number of simulation sampling points can be significantly reduced, thereby reducing simulation time and complexity. Furthermore, when the above method is converted into software-controlled automatic simulation processes, manual monitoring time can be reduced and simulation efficiency can be improved.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, the step of performing signal transmission simulation based on the first reference voltage to obtain the first simulation error time endpoint and the first simulation pass time endpoint includes: using N time points as simulation time points, performing signal transmission simulation based on the first reference voltage to obtain simulation results at the N time points, wherein N is a positive integer, and the time interval between any two time points among the N time points is greater than the first time precision; and obtaining the first simulation error time endpoint and the first simulation pass time endpoint based on the simulation results.

[0007] By selecting simulation time points with coarser granularity for simulation, the initial simulation time endpoints are obtained, and the preliminary simulation direction is determined, which helps to reduce simulation time and improve simulation efficiency.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the step of performing signal transmission simulation based on a first reference voltage to obtain a first simulation error time endpoint and a first simulation pass time endpoint includes: using N time points as simulation time points, performing signal transmission simulation based on a second reference voltage to obtain simulation results at the N time points, where N is a positive integer, and the time interval between any two time points among the N time points is greater than the first time precision; obtaining the initial simulation error time endpoint and the initial simulation pass time endpoint corresponding to the second reference voltage based on the simulation results; and obtaining the first simulation error time endpoint and the first simulation pass time endpoint based on the initial simulation error time endpoint and the initial simulation pass time endpoint.

[0009] Optionally, the second reference voltage is the recommended reference voltage.

[0010] By combining the recommended reference voltage to determine the initial simulation time endpoint for other reference voltage levels, the first simulation time endpoint for other reference voltage levels can be determined more quickly, thereby reducing simulation time and improving simulation efficiency.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: receiving configuration parameters for setting the value of P and / or the value of Q.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the value of P and / or the value of Q is an integer value from 1 to M, where M is the difference between two adjacent first simulation error time endpoints, or M is the difference between two adjacent second simulation error time endpoints.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the value of P is determined according to the following formula:

[0014]

[0015] Where T represents the total simulation duration of the signal simulation; UI represents the simulation period; BDL represents the first time precision; P∈[1,M], where M represents the difference between two adjacent first simulation error time endpoints; n represents the number of simulation conditions for processing the signal; and k represents the load of the computer used to process the signal.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the value of Q is determined according to the following formula:

[0017]

[0018] Where T represents the total simulation duration of the signal simulation; UI represents the simulation period; BDL represents the first time precision; Q∈[1,M], where M represents the difference between two adjacent second simulation error time endpoints; n represents the number of simulation conditions for processing the signal; and k represents the load on the computer used to process the signal.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the first reference voltage is one or more reference voltages from a set of reference voltages.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the second reference voltage is one or more reference voltages from a set of reference voltages.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: receiving parameters for determining a second reference voltage.

[0022] By combining user-input parameters with cyclic simulation, it is possible to combine manual operation with automated software operation, thereby improving simulation efficiency.

[0023] In a second aspect, a signal processing apparatus is provided, which, when used, can realize the corresponding functions described in the first aspect above. Specifically, the apparatus includes a processing module, which is configured to: perform signal transmission simulation based on a first reference voltage to obtain a first simulated error time endpoint and a first simulated pass time endpoint; take P time points as simulation time points between adjacent first simulated error time endpoints and first simulated pass time endpoints, and perform signal transmission simulation based on the first reference voltage to obtain a second simulated error time endpoint and a second simulated pass time endpoint, wherein a first time interval between adjacent second simulated error time endpoints and second simulated pass time endpoints is greater than a first time precision, and P is a positive integer; take Q time points as simulation time points within the first time interval, and perform signal transmission simulation based on the first reference voltage to obtain a third simulated error time endpoint and a third simulated pass time endpoint, wherein a second time interval between adjacent third simulated error time endpoints and third simulated pass time endpoints is equal to the first time precision, and Q is a positive integer.

[0024] In conjunction with the second aspect, in some implementations of the second aspect, the processing module is used to perform signal transmission simulation based on a first reference voltage to obtain a first simulation error time endpoint and a first simulation pass time endpoint. Specifically, the processing module is used to: use N time points as simulation time points, perform signal transmission simulation based on the first reference voltage to obtain simulation results at the N time points, where N is a positive integer, and the time interval between any two time points among the N time points is greater than the first time precision; and obtain the first simulation error time endpoint and the first simulation pass time endpoint based on the simulation results.

[0025] In conjunction with the second aspect, in some implementations of the second aspect, the processing module is used to perform signal transmission simulation based on a first reference voltage to obtain a first simulation error time endpoint and a first simulation pass time endpoint. Specifically, the processing module is used to: use N time points as simulation time points, perform signal transmission simulation based on a second reference voltage to obtain simulation results at the N time points, where N is a positive integer, and the time interval between any two time points among the N time points is greater than the first time precision; obtain the initial simulation error time endpoint and the initial simulation pass time endpoint corresponding to the second reference voltage according to the simulation results; and obtain the first simulation error time endpoint and the first simulation pass time endpoint according to the initial simulation error time endpoint and the initial simulation pass time endpoint.

[0026] In conjunction with the second aspect, in some implementations of the second aspect, the apparatus further includes a receiving module for receiving configuration parameters for setting the value of P and / or the value of Q.

[0027] In conjunction with the second aspect, in some implementations of the second aspect, the value of P and / or the value of Q is an integer value from 1 to M, where M is the difference between two adjacent first simulation error time endpoints, or M is the difference between two adjacent second simulation error time endpoints.

[0028] In conjunction with the second aspect, in some implementations of the second aspect, the value of P is determined according to the following formula:

[0029]

[0030] Where T represents the total simulation duration of the signal simulation; UI represents the simulation period; BDL represents the first time precision; P∈[1,M], where M represents the difference between two adjacent first simulation error time endpoints; n represents the number of simulation conditions for processing the signal; and k represents the load of the computer used to process the signal.

[0031] In conjunction with the second aspect, in some implementations of the second aspect, the value of Q is determined according to the following formula:

[0032]

[0033] Where T represents the total simulation duration of the signal simulation; UI represents the simulation period; BDL represents the first time precision; Q∈[1,M], where M represents the difference between two adjacent second simulation error time endpoints; n represents the number of simulation conditions for processing the signal; and k represents the load on the computer used to process the signal.

[0034] In conjunction with the second aspect, in some implementations of the second aspect, the first reference voltage is one or more reference voltages from a set of reference voltages.

[0035] In conjunction with the second aspect, in some implementations of the second aspect, the second reference voltage is one or more reference voltages from a set of reference voltages.

[0036] In conjunction with the second aspect, in some implementations of the second aspect, the receiving module is further configured to: receive parameters for determining the second reference voltage.

[0037] Thirdly, a computer program product is provided, the computer program product including instructions that, when executed on a computer, cause the computer to perform the method described in the first aspect or any implementation thereof.

[0038] Fourthly, a computer-readable storage medium is provided, storing program code that, when run on a computer, causes the computer to perform the method described in the first aspect or any implementation thereof.

[0039] Fifthly, an apparatus for processing signals is provided, comprising a memory and a processor, the memory including a computer program running on the processor; the processor executing the computer program to implement the method described in the first aspect or any implementation thereof. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the chip design and manufacturing process applicable to the embodiments of this application.

[0041] Figure 2 This is a flowchart illustrating a signal processing method provided in an embodiment of this application.

[0042] Figure 3 This is an exemplary illustrative diagram of a simulation error time endpoint and a simulation pass time endpoint applicable to embodiments of this application.

[0043] Figure 4 This is a flowchart illustrating a signal processing method provided in an embodiment of this application.

[0044] Figure 5 This is a schematic diagram of a signal processing device provided in an embodiment of this application.

[0045] Figure 6 This is a schematic diagram of another signal processing device provided in an embodiment of this application. Detailed Implementation

[0046] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0047] A chip, also known as an integrated circuit (IC), or the carrier of an integrated circuit, is typically a method of miniaturizing circuits and is often manufactured on the surface of a semiconductor wafer. For example... Figure 1 As shown, the chip design and manufacturing process 100 can generally be divided into three parts: design 101, manufacturing 102, and packaging and testing 103.

[0048] The design phase comprises four major processes: specification definition, system design, front-end design, and back-end design. Specifically, specification definition involves defining the product specifications based on chip requirements analysis to determine the overall design direction. System design, based on the specification definition, clarifies the chip architecture, business modules, power supply, etc. Front-end design involves determining the solution based on the system design, performing specific circuit design for each module, and using a dedicated hardware description language to describe the specific circuits at the register-transfer level (RTL) level. After code generation, the correctness of the code design is repeatedly verified through simulation according to the established specification standards (this can be called front-end simulation). Then, the RTL-level code is converted into a gate-level netlist. Back-end design, based on the gate-level netlist, involves placing and routing the circuit within a given silicon area, and then performing various functional and timing simulations to verify the physical layout of the routing (this can be called back-end simulation).

[0049] The methods for front-end and back-end simulations are similar, both including signal integrity (SI) simulation, such as... Figure 1 The design section shown includes signal integrity simulation.

[0050] Signal integrity refers to a set of metrics for the quality of electronic signals. In digital circuits, a stream of binary signals is represented by voltage (or current) waveforms. Signal integrity means that, without affecting the quality of other signals in the system, the receiving end can receive signals that meet logic level requirements, timing requirements, and phase requirements. Alternatively, signal integrity can be understood as ensuring the integrity of the signal waveform and the integrity of the signal timing.

[0051] Analyzing and identifying signal integrity issues on a finished chip is challenging, and even if problems are found, implementing effective solutions on the finished chip is time-consuming and costly. Therefore, it is necessary to identify, discover, and eliminate or minimize signal integrity issues before the chip is fully formed—that is, before the physical design is complete. This necessitates the use of tools to simulate and analyze the chip's circuit parameters, thereby identifying problems early, shortening the development cycle, and reducing development costs; in other words, signal integrity simulation is required.

[0052] Signal integrity simulation: In simulation software, for a circuit in a designed chip, after inputting a signal, the presence of signal errors can be determined by comparing the expected output signal with the simulated output signal. For example, at a certain simulation time point, if the expected output signal is different from the simulated output signal, then that simulation time point is determined to be a failure time point; otherwise, it is determined to be a pass time point.

[0053] Reference voltage (vref): In signal integrity simulation, the reference voltage is used to compare with the input signal to determine whether the signal is high or low. Furthermore, the reference voltage can have multiple levels, meaning that the signal transmission characteristics can be simulated at different reference voltage levels.

[0054] Waveform diagram: A curve that represents the shape and form of a signal, and can represent the distribution of the corresponding physical quantity in time or space.

[0055] Symbol error rate (SER): A metric that measures the accuracy of data transmission within a specified time. SER = (Number of errors in transmission / Total number of errors transmitted) * 100%.

[0056] Eye diagram: This is a graphical representation of a series of digital signals accumulated on an oscilloscope. It contains a wealth of information, allowing observation of intersymbol interference (ISI) and noise effects, and reflecting the overall characteristics of the digital signal. Because its overall shape resembles a human eye, it is called an "eye diagram."

[0057] Clock cycle (Clk): Also known as oscillation period, it is defined as the reciprocal of the clock frequency. The clock cycle is the most basic and smallest unit of time in a computer. The clock cycle represents the highest frequency that computer memory can operate at; a smaller clock cycle means a higher operating frequency.

[0058] Double data rate synchronous dynamic random-access memory (DDR): This is a type of computer memory, also known as DDR memory. It can transfer data twice within one clock cycle, once during the rising phase and once during the falling phase of the clock. Therefore, it can also be called double data rate synchronous dynamic random-access memory. It can achieve a higher data transfer rate at the same bus frequency.

[0059] Furthermore, random access memory (RAM) such as DDR can directly exchange data with the computer's CPU, allowing for read and write operations at any time at high speeds. It is typically used as temporary data storage for the operating system or other running programs. A key characteristic of RAM is its volatility; the stored data is lost when power is off.

[0060] As CPU processing power continues to improve, the demands on DDR speed and capacity are also increasing, bringing with it design challenges such as signal crosstalk and jitter. Therefore, simulation testing of the DDR chip is necessary to obtain its bit error rate (BER). Only when the BER meets the requirements can the designed DDR chip be considered to meet basic requirements. It should be understood that DDR simulation testing can include the aforementioned SI simulation.

[0061] In SI simulation, a significant amount of manual monitoring time is usually required, and the SI simulation process itself is time-consuming. In order to reduce SI simulation time and manual monitoring time, this application proposes a signal processing method.

[0062] Figure 2 This illustration shows a flowchart of a signal processing method according to an embodiment of this application, which can reduce the complexity of SI simulation and the time required for manual intervention, thereby improving the efficiency of SI simulation. Specifically, the method 200 includes:

[0063] S201, perform signal transmission simulation based on the first reference voltage to obtain the first simulation error time endpoint and the first simulation pass time endpoint.

[0064] It should be understood that, in the embodiments of this application, the simulation error time endpoint can be a simulation error time endpoint that is adjacent to the simulation pass time endpoint among multiple simulation time points. Specifically, the simulation error time endpoint can include the left error time endpoint and / or the right error time endpoint. Similarly, the simulation pass time endpoint can be a simulation pass time endpoint that is adjacent to the simulation error time point among multiple simulation time points. Specifically, the simulation pass time endpoint can include the left pass time endpoint and / or the right pass time endpoint. It should also be understood that, in the embodiments of this application, "adjacent" time points can refer to adjacent time points, that is, two time points that are closest to each other and have no other time points, or they can refer to time points that are a certain distance apart, including one or more time points. For example, the simulation error time endpoint can be a simulation error time point that is adjacent to the simulation pass time point among multiple simulation time points, or the simulation error time endpoint can also be a simulation error time point that is separated from the simulation pass time point by one or more time points among multiple simulation time points; as another example, the simulation pass time endpoint can be a simulation pass time point that is adjacent to the simulation error time point among multiple simulation time points, or the simulation pass time endpoint can also be a simulation pass time point that is separated from the simulation error time point among multiple simulation time points by one or more time points.

[0065] The following combination Figure 3 The definitions of the simulation error time endpoint and the simulation pass time endpoint are illustrated by example. It should be understood that... Figure 3As an example, the above simulation error / pass time endpoint can be defined in other ways, and this application does not limit it.

[0066] Right now Figure 3 An exemplary illustrative diagram of a simulation error time endpoint and a simulation pass-through time endpoint applicable to embodiments of this application is shown. For example... Figure 3 As shown, the simulation time points include consecutive error time points 1-4 and 8-10, and consecutive pass time points 5-7 and 11-12. In the consecutive error time points 1-4, the simulation error time endpoint can be any time point from 1-4 that is adjacent to the simulation pass time point 5, for example, simulation error time point 4. Similarly, in the consecutive error time points 8-10, the simulation error time endpoint can be any time point from 8-10 that is adjacent to the simulation pass time endpoints 7 or 11, for example, simulation error time points 8 or 10. There are several ways to select the simulation pass time endpoint, such as the following two methods:

[0067] Method 1: The simulation time endpoint can be the midpoint between two adjacent simulation error time endpoints, such as the midpoint between time point 4 and time point 8;

[0068] Method 2: The simulation pass time endpoint can be any time point among simulation pass time points 5-7 that is adjacent to simulation error time point 4 or 8, for example, simulation pass time point 5 or 7; similarly, among simulation pass time points 11-12, any time point among simulation pass time points 11-12 that is adjacent to simulation error time point 10, for example, simulation pass time point 11.

[0069] Specifically, in the embodiments of this application, when processing signals, that is, when performing signal integrity simulation, the signal transmission corresponding to at least one reference voltage in the reference voltage set can be simulated. The first reference voltage can be one or more reference voltages in the reference voltage set, and this application does not limit it.

[0070] In one possible implementation, when the first reference voltage is one of the reference voltages in a set of reference voltages, the method for obtaining the first simulation error time endpoint and the first simulation pass time endpoint can be as follows: select N time points as simulation time points, perform signal transmission simulation based on the first reference voltage, obtain the simulation results at these N time points, and obtain the first simulation error time endpoint and the first simulation pass time endpoint based on the simulation results, where N is a positive integer, and the time interval between any two time points among the N time points is greater than a first time precision. That is, the first simulation error time endpoint and the first simulation pass time endpoint are obtained by setting a larger time interval between simulation time points, or in other words, by setting a coarser simulation granularity.

[0071] In this embodiment, there are multiple ways to obtain the first simulated bit error time endpoint and the first simulated pass time endpoint based on the simulation results at N time points. For example, the bit error time point and the pass time point can be selected from the N time points as the first simulated bit error time endpoint and the first simulated pass time endpoint, respectively. Another example is to select the bit error time point and the pass time point from the N time points as the initial simulated bit error time endpoint and the initial simulated pass time endpoint, and then perform cyclic simulation based on the initial simulated bit error time endpoint and the initial simulated pass time endpoint to obtain the first simulated bit error time endpoint and the first simulated pass time endpoint. In each iteration of the cyclic simulation process, one or more time points can be selected between the adjacent simulated bit error time endpoint and simulated pass time endpoint obtained in the previous simulation for signal transmission simulation to obtain the simulated bit error time endpoint and simulated pass time endpoint for that simulation.

[0072] In another possible implementation, when the first reference voltage is one of the reference voltages in the set of reference voltages, the first simulation error time endpoint and the first simulation pass time endpoint can be obtained as follows: First, using N time points as simulation time points, signal transmission simulation is performed based on the second reference voltage to obtain simulation results at N time points, where N is a positive integer, and the time interval between any two time points among the N time points is greater than the first time precision; then, based on the simulation results at the N time points, the initial simulation error time endpoint and the initial simulation pass time endpoint corresponding to the second reference voltage are obtained; finally, based on the initial simulation error time endpoint and the initial simulation pass time endpoint, the first simulation error time endpoint and the first simulation pass time endpoint are obtained.

[0073] Optionally, the second reference voltage can be a recommended reference voltage. It should be understood that the recommended reference voltage can be set by simulation software or the user; for example, the recommended reference voltage can be set to the voltage value corresponding to the crossover point of the eye diagram corresponding to the input signal. It should be understood that an output signal corresponds to an eye diagram, which can be used to observe the overall characteristics of the output signal; similarly, an input signal can also correspond to an eye diagram. The crossover point of the eye diagram can be defined as the point where the rising and falling edges of the waveform in the eye diagram intersect. In this embodiment, the method 200 may further include: receiving configuration parameters used to determine the recommended reference voltage.

[0074] In the embodiments of this application, there can be multiple ways to obtain the first simulation error time endpoint and the first simulation pass time endpoint based on the initial simulation error time endpoint and the initial simulation pass time endpoint. This application does not limit these methods.

[0075] For example, the time points corresponding to the initial simulation error time endpoint and the initial simulation pass time endpoint are used as the first simulation error time endpoint and the first simulation pass time endpoint.

[0076] For example, the time point corresponding to the initial simulated bit error time endpoint is taken as the simulation time point. Signal transmission simulation is performed based on the first reference voltage. It is determined whether the simulation time point is the simulated bit error time point. If it is, the time points corresponding to the initial simulated bit error time endpoint and the initial simulated pass time endpoint are taken as the first simulated bit error time endpoint and the first simulated pass time endpoint, respectively. If not, the simulation is performed by cyclically expanding outward by a unit time based on the initial simulated bit error time endpoint until the simulated bit error time endpoint is obtained. This simulated bit error time endpoint is taken as the first simulated bit error time endpoint, and the midpoint between two adjacent simulated bit error time endpoints is taken as the first simulated pass time endpoint.

[0077] For example, based on the initial simulation error time endpoint and the initial simulation pass time endpoint, a cyclic simulation is performed to obtain the first simulation error time endpoint and the first simulation pass time endpoint. In each cycle of the cyclic simulation process, one or more time points can be selected between the adjacent simulation error time endpoint and simulation pass time endpoint obtained in the previous simulation to perform signal transmission simulation, so as to obtain the simulation error time endpoint and simulation pass time endpoint of the current simulation.

[0078] In another possible implementation, when the first reference voltage is multiple reference voltages in the set of reference voltages, the method for obtaining the first simulation error time endpoint and the first simulation pass time endpoint of any one of the multiple reference voltages can be: 1) When the first reference voltage is a single reference voltage, the method described in the first possible implementation above will not be repeated here; 2) When the first reference voltage is a single reference voltage, the method described in the second possible implementation above will not be repeated here.

[0079] For details on the implementation of method 2) above, please refer to the following: Figure 4 The relevant description is shown in method 400.

[0080] S202, between adjacent first simulated bit error time endpoints and first simulated pass time endpoints, P time points are taken as simulation time points, and signal transmission simulation is performed based on the first reference voltage to obtain the second simulated bit error time endpoint and the second simulated pass time endpoint, wherein the first time interval between adjacent second simulated bit error time endpoints and second simulated pass time endpoints is greater than the first time precision, and P is a positive integer.

[0081] In one possible implementation, the method 200 may further include: receiving configuration parameters for setting the value of P.

[0082] Optionally, the value of P is an integer from 1 to M, where M is optionally the difference between two adjacent first simulation error time endpoints.

[0083] In another possible implementation, the value of P can be determined according to the following formula:

[0084]

[0085] Where T represents the total simulation duration of SI simulation; UI represents the simulation cycle; BDL is the first time precision; P represents the number of splits, P∈[1,M], where M represents the difference between two adjacent first simulation error time endpoints; n = the number of base voltage (vref) levels * the number of combinations of other parameters to be simulated, one possible number of combinations of other parameters to be simulated is the number of conditions for voltage and temperature (process, voltage, temperature, PVT) multiplied by the number of decision-feedback equalization (DFE) levels; k represents the computer load.

[0086] Based on the above, we can select the number of splits that minimizes T, that is, the value of P when T is minimized, as the number of splits.

[0087] Optionally, when the value of P is determined according to the above formula, the received configuration parameters may include the first time accuracy BDL, simulation period UI, vref accuracy, vref range, number of PVT conditions, number of DFE bits, and computer load k. Alternatively, the configuration parameters may include other parameters, which are not limited in this application.

[0088] S203, take Q time points in the first time interval as simulation time points, perform signal transmission simulation based on the first reference voltage, and obtain the third simulation error time endpoint and the third simulation pass time endpoint, wherein the second time interval between adjacent third simulation error time endpoints and third simulation pass time endpoints is equal to the first time precision, and Q is a positive integer.

[0089] Specifically, in the embodiments of this application, P and Q can be the same or different.

[0090] In one possible implementation, the method 200 may further include: receiving configuration parameters for setting the value of Q.

[0091] Optionally, the value of Q is an integer from 1 to M, where M is optionally the difference between two adjacent second simulation error time endpoints.

[0092] In another possible implementation, the value of Q can be determined according to the following formula:

[0093]

[0094] Where T represents the total simulation duration of SI simulation; UI represents the simulation cycle; BDL is the first time precision; Q represents the number of splits, Q∈[1,M], where M represents the difference between two adjacent second simulation error time endpoints; n = the number of base voltage (vref) levels * the number of combinations of other parameters to be simulated, one possible number of combinations of other parameters to be simulated is the number of conditions for voltage and temperature (process, voltage, temperature, PVT) multiplied by the number of decision-feedback equalization (DFE) levels; k represents the computer load.

[0095] Based on the above, we can select the number of splits that minimizes T, that is, the value of Q when T is minimized, as the number of splits.

[0096] Optionally, when the value of Q is determined according to the above formula, the received configuration parameters may include the first time accuracy BDL, simulation period UI, vref accuracy, vref range, number of PVT conditions, number of DFE bits, and computer load k. Alternatively, the configuration parameters may include other parameters, which are not limited in this application.

[0097] It should be understood that the above steps S202 and S203 are two loop steps, where S202 is the penultimate loop step and S203 is the penultimate loop step, that is, the last loop step. After S203, the simulation accuracy is achieved, that is, the time interval between the adjacent simulation error time endpoint and the simulation pass time endpoint reaches the first time accuracy.

[0098] Therefore, by taking one or more time points between adjacent simulation error time endpoints and simulation pass time endpoints for cyclic simulation until the simulation accuracy is achieved, the number of simulation sampling points can be significantly reduced, thereby reducing simulation time and complexity. Furthermore, when the above method is converted into software-controlled automatic simulation process, manual monitoring time can be reduced and simulation efficiency can be improved.

[0099] In this embodiment of the application, after completing the above steps S201-S204, the results at the total simulation time points are statistically analyzed, an eye diagram is drawn, and operations such as measurement and report output are performed.

[0100] The following, by way of example, combines Figure 4 Taking the first reference voltage as an example of all reference voltages in the reference voltage set, the above method 200 will be further described.

[0101] It should be noted that, Figure 4 Some of the steps shown are the same as some of the steps in method 200 above, and will not be repeated here.

[0102] Right now Figure 4 A flowchart illustrating a signal processing method according to an embodiment of this application is shown. The method 400 includes:

[0103] S401, Receive configuration parameters used to determine the number of splits and / or simulation accuracy.

[0104] Specifically, in the embodiments of this application, the number of splits can refer to the number of simulation time points, such as the value of N, the value of P, and the value of Q. For the relevant descriptions of N, P, and Q, please refer to the introductions in S201, S202, and S203 of the above method 200, which will not be repeated here.

[0105] In this embodiment of the application, the simulation accuracy can be determined based on the first time accuracy, and the configuration parameter can be the value of the first time accuracy.

[0106] S402 performs signal transmission simulation based on the recommended reference voltage to obtain the initial simulation error time endpoint and the initial simulation pass time endpoint.

[0107] Specifically, in this embodiment, N time points are used as simulation time points, and signal transmission simulation is performed based on a recommended reference voltage to obtain the initial simulation error time endpoint and the initial simulation pass time endpoint among the N time points. Here, N is a positive integer, and the time interval between any two time points among the N time points is greater than a first time precision. That is, a coarser-grained simulation is performed first.

[0108] S403, based on the initial simulation error time endpoint and initial simulation pass time endpoint corresponding to the recommended reference voltage, determine the initial simulation error time endpoint and initial simulation pass time endpoint corresponding to other recommended reference voltages in the reference voltage set besides the recommended reference voltage.

[0109] Specifically, in the embodiments of this application, the initial simulation time endpoints corresponding to other reference voltages besides the recommended reference voltage can be determined according to the initial simulation time endpoint corresponding to the recommended reference voltage.

[0110] Optionally, at the time point corresponding to the initial simulation error time endpoint of the recommended reference voltage, signal transmission simulation is performed based on each of the other reference voltages. It is determined whether the signal has an error at that corresponding time point. If so, that time point is taken as the initial simulation error time endpoint for that reference voltage; otherwise, the simulation is cyclically extended by one unit of time until the signal at the extended time point has an error. Then, at the intermediate time point between adjacent initial simulation error time endpoints corresponding to that reference voltage, signal transmission simulation is performed based on that reference voltage. It is determined whether the signal at that intermediate time point passes. If so, that intermediate time point is taken as the initial simulation pass time endpoint for that reference voltage, and the reference voltage is recorded as the open-eye reference voltage; otherwise, that is, the signal at that intermediate time point has an error, the reference voltage is recorded as the closed-eye reference voltage.

[0111] In this embodiment, for the initial simulation time endpoint corresponding to the unopened reference voltage, the initial simulation time endpoint corresponding to the nearest open-eye reference voltage can be used as the initial simulation time endpoint corresponding to the unopened reference voltage. The open-eye reference voltage nearest to the unopened reference voltage can be the open-eye reference voltage whose range is closest to the unopened reference voltage.

[0112] S404, based on the initial simulation error time endpoint and the initial simulation pass time endpoint corresponding to the first reference voltage, perform signal transmission simulation based on the first reference voltage to obtain the first simulation error time endpoint and the first simulation pass time endpoint.

[0113] Specifically, in the embodiments of this application, for each reference voltage in the set of reference voltages, a cyclic signal transmission simulation is performed based on the reference voltage according to the initial simulation time endpoint corresponding to the reference voltage to obtain the first simulation time endpoint.

[0114] In one possible implementation, for each of the aforementioned reference voltages, in each iteration of the aforementioned cyclic signal transmission simulation process, P time points can be selected between the adjacent simulation error time endpoints and simulation pass time endpoints obtained from the previous simulation to perform signal transmission simulation, thereby obtaining the simulation error time endpoints and simulation pass time endpoints for this iteration. It should be understood that the first step of the aforementioned cyclic signal transmission simulation process is to select P time points as simulation time points between the adjacent initial simulation error time endpoints and initial simulation pass time endpoints corresponding to the reference voltage, and perform signal transmission simulation based on this reference voltage.

[0115] S405, between adjacent first simulated bit error time endpoints and first simulated pass time endpoints, P time points are taken as simulation time points, and signal transmission simulation is performed based on the first reference voltage to obtain the second simulated bit error time endpoint and the second simulated pass time endpoint, wherein the first time interval between adjacent second simulated bit error time endpoints and second simulated pass time endpoints is greater than the first time precision, and P is a positive integer.

[0116] S406, P time points are taken as simulation time points in the first time interval, and signal transmission simulation is performed based on the first reference voltage to obtain the third simulation error time endpoint and the third simulation pass time endpoint, wherein the second time interval between adjacent third simulation error time endpoints and third simulation pass time endpoints is equal to the first time precision, and P is a positive integer.

[0117] For a description of steps S405 and S406 above, please refer to the descriptions in methods S202 and S203 above; they will not be repeated here.

[0118] This application also provides a device for signal integrity simulation, such as... Figure 4 As shown, the device can be used to perform the corresponding functions of the method described in method 200 above. For detailed functions, please refer to the corresponding description in method 200, which will not be repeated here.

[0119] Right now Figure 5 A schematic diagram of a signal integrity simulation apparatus 500 provided in an embodiment of this application is shown. The apparatus 500 includes a receiving module 501 and a processing module 502.

[0120] In one possible implementation, the processing module 502 is used to perform signal transmission simulation based on a first reference voltage to obtain a first simulated bit error time endpoint and a first simulated pass time endpoint; between adjacent first simulated bit error time endpoints and first simulated pass time endpoints, P time points are taken as simulation time points, and signal transmission simulation is performed based on the first reference voltage to obtain a second simulated bit error time endpoint and a second simulated pass time endpoint, wherein a first time interval between adjacent second simulated bit error time endpoints and second simulated pass time endpoints is greater than a first time precision, and P is a positive integer; within the first time interval, Q time points are taken as simulation time points, and signal transmission simulation is performed based on the first reference voltage to obtain a third simulated bit error time endpoint and a third simulated pass time endpoint, wherein a second time interval between adjacent third simulated bit error time endpoints and third simulated pass time endpoints is equal to the first time precision, and Q is a positive integer.

[0121] In another possible implementation, the receiving module 401 is used to receive configuration parameters for setting the value of P and / or the value of Q.

[0122] For a detailed description of the functions of the receiving module 401 and the processing module 402, please refer to the corresponding descriptions in the above method embodiments, which will not be repeated here.

[0123] Figure 6 A schematic diagram of a signal processing apparatus according to an embodiment of this application is shown. Figure 6 The computer device 600 includes a memory 601 and a processor 602. The memory 601 contains a computer program that can run on the processor; the processor 602 executes the computer program, thereby enabling the implementation of the relevant content in the above method embodiments. Further details are omitted here.

[0124] This application also provides a computer program product, including instructions that, when executed on a computer, cause the computer to perform the methods described in the above method embodiments.

[0125] This application also provides a computer-readable storage medium storing program code, which, when executed on a computer, causes the computer to perform the methods described in the above-described method embodiments. These computer-readable storage media include, but are not limited to, one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), flash memory, electrically EPROM (EEPROM), and hard drive.

[0126] This application also provides a chip system comprising: at least one processor, at least one memory, and an interface circuit. The interface circuit is responsible for information interaction between the chip system and the outside world. The at least one memory, the interface circuit, and the at least one processor are interconnected via circuits. The at least one memory stores instructions; the instructions are executed by the at least one processor to perform the operations involved in the methods described in the above aspects. In specific implementation, the chip system can be implemented in the form of a central processing unit (CPU), a microcontroller unit (MCU), a microprocessor (MPU), a digital signal processor (DSP), a system-on-chip (SoC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a programmable logic device (PLD).

[0127] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0128] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0129] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0130] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0131] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0132] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0133] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of processing a signal, characterized by, The method comprises: performing signal transmission simulation based on a first reference voltage to obtain a first simulation error time endpoint and a first simulation pass time endpoint; taking P time points between adjacent first simulation error time endpoints and first simulation pass time endpoints as simulation time points, and performing signal transmission simulation based on the first reference voltage to obtain a second simulation error time endpoint and a second simulation pass time endpoint, wherein a first time interval between adjacent second simulation error time endpoints and second simulation pass time endpoints is greater than a first time precision, and P is a positive integer; taking Q time points in the first time interval as simulation time points, and performing signal transmission simulation based on the first reference voltage to obtain a third simulation error time endpoint and a third simulation pass time endpoint, wherein a second time interval between adjacent third simulation error time endpoints and third simulation pass time endpoints is equal to the first time precision, and Q is a positive integer.

2. The method of claim 1, wherein, The method comprises: taking N time points as simulation time points, and performing signal transmission simulation based on the first reference voltage to obtain simulation results at the N time points, wherein N is a positive integer, and a time interval between any two time points in the N time points is greater than the first time precision; obtaining the first simulation error time endpoint and the first simulation pass time endpoint according to the simulation results.

3. The method of claim 1, wherein, The method comprises: taking N time points as simulation time points, and performing signal transmission simulation based on the second reference voltage to obtain simulation results at the N time points, wherein N is a positive integer, and a time interval between any two time points in the N time points is greater than the first time precision; obtaining an initial simulation error time endpoint and an initial simulation pass time endpoint corresponding to the second reference voltage according to the simulation results; obtaining the first simulation error time endpoint and the first simulation pass time endpoint according to the initial simulation error time endpoint and the initial simulation pass time endpoint.

4. The method according to any one of claims 1 to 3, characterized in that, The method further comprises: receiving configuration parameters, wherein the configuration parameters are used to set a value of P and / or a value of Q.

5. The method of claim 4, wherein, The value of P and / or the value of Q is an integer value in 1 to M, wherein M is a difference between two adjacent first simulation error time endpoints, or M is a difference between two adjacent second simulation error time endpoints.

6. The method according to any one of claims 1 to 3, characterized in that, The value of P is determined according to the following formula: wherein T represents a total simulation time length of the signal simulation; UI represents a simulation period; BDL represents a first time precision; P [1, M], M represents a difference value of two adjacent first simulation error code time endpoints; n represents a simulation condition number of the processed signal; k represents a load amount of the computer used for processing the signal.

7. The method according to any one of claims 1 to 3, characterized in that, The value of Q is determined according to the following formula: wherein T represents a total simulation time length of the signal simulation; UI represents a simulation period; BDL represents a first time precision; Q [1, M], M represents a difference value of two adjacent second simulation error code time endpoints; n represents a simulation condition number of the processed signal; k represents a load amount of the computer used for processing the signal.

8. The method according to any one of claims 1 to 3, characterized in that, The first reference voltage is one or more reference voltages in a reference voltage set.

9. The method of claim 3, wherein, The second reference voltage is one or more reference voltages in a reference voltage set.

10. The method of claim 3, wherein, The method further comprises: receiving parameters used to determine a second reference voltage.

11. An apparatus for processing a signal, characterized by The device comprises a processing module configured to: perform signal transmission simulation based on a first reference voltage to obtain a first simulation error time endpoint and a first simulation pass time endpoint; P time points are taken as simulation time points between adjacent second simulation error time end points and second simulation pass time end points, and signal transmission simulation is performed based on the first reference voltage to obtain third simulation error time end points and third simulation pass time end points, wherein a second time interval between adjacent third simulation error time end points and third simulation pass time end points is equal to the first time precision, and Q is a positive integer. P time points are taken as simulation time points between adjacent second simulation error time end points and second simulation pass time end points, and signal transmission simulation is performed based on the first reference voltage to obtain third simulation error time end points and third simulation pass time end points, wherein a second time interval between adjacent third simulation error time end points and third simulation pass time end points is equal to the first time precision, and Q is a positive integer.

12. The apparatus of claim 11, wherein, The processing module is configured to perform signal transmission simulation based on a first reference voltage to obtain first simulation error time end points and first simulation pass time end points, and specifically configured to: N time points are taken as simulation time points, and signal transmission simulation is performed based on the first reference voltage to obtain simulation results at the N time points, wherein N is a positive integer, and a time interval between any two time points of the N time points is greater than the first time precision; According to the simulation results, the first simulation error time end points and the first simulation pass time end points are obtained.

13. The apparatus of claim 11, wherein, The processing module is configured to perform signal transmission simulation based on a first reference voltage to obtain first simulation error time end points and first simulation pass time end points, and specifically configured to: N time points are taken as simulation time points, and signal transmission simulation is performed based on the first reference voltage to obtain simulation results at the N time points, wherein N is a positive integer, and a time interval between any two time points of the N time points is greater than the first time precision; According to the simulation results, the first simulation error time end points and the first simulation pass time end points are obtained. The device further includes a receiving module configured to receive configuration parameters for setting a value of P and / or a value of Q.

14. The apparatus of any one of claims 11-13, wherein, The value of P and / or the value of Q is an integer value in 1 to M, wherein M is a difference between two adjacent first simulation error time end points, or M is a difference between two adjacent second simulation error time end points.

15. The apparatus of claim 14, wherein, The value of P is determined according to the following formula:

16. The apparatus of any one of claims 11-13, wherein, The value of Q is determined according to the following formula: wherein T represents a total simulation time length of the signal simulation; UI represents a simulation period; BDL represents a first time precision; P [1, M], M represents a difference value of two adjacent first simulation error code time endpoints; n represents a simulation condition number of the processed signal; k represents a load amount of the computer used for processing the signal.

17. The apparatus of any one of claims 11-13, wherein, The first reference voltage is one or more reference voltages in a reference voltage set. wherein T represents a total simulation time length of the signal simulation; UI represents a simulation period; BDL represents a first time precision; Q [1, M], M represents a difference value of two adjacent second simulation error code time endpoints; n represents a simulation condition number of the processed signal; k represents a load amount of the computer used for processing the signal.

18. The apparatus of any one of claims 11-13, wherein, The second reference voltage is one or more reference voltages in a reference voltage set.

19. The apparatus of claim 13, wherein, The receiving module is further configured to:

20. The apparatus of claim 14, wherein, receive parameters for determining the second reference voltage. The memory includes a computer program running on the processor; 21. An apparatus for processing a signal, comprising a memory and a processor, wherein The processor executes the computer program to implement the method of any one of claims 1-10. ​ 22. A computer program product comprising instructions, characterized in that, When the instructions are executed on a computer, they cause the computer to perform a method according to any of claims 1-10.

23. A computer-readable storage medium, the computer-readable storage medium storing program codes, characterized in that, When the program code is run on a computer, it causes the computer to perform a method according to any of claims 1-10.

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