Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel. In the array substrate, because the first electrode and the gate are arranged in the same layer on the side of the active layer close to the substrate, the second electrode and the gate can share the first insulating layer, eliminating the need for additional steps to prepare and etch the gate insulating layer. Furthermore, the arrangement of the first electrode and the gate in the same layer can reduce the risk of parasitic capacitance generated by the first electrode and the gate overlapping in a direction perpendicular to the plane of the substrate. Because the first electrode and the gate are arranged in the same layer, a first trace connected to the first electrode and the gate and arranged in the same layer as the first electrode and the gate is disconnected at the intersection with the second trace to form a first connecting end and a second connecting end. A bridging electrode is provided between the first connecting end and the second connecting end to ensure signal transmission of the first trace.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to an array substrate and a display panel. Background Art

[0002] In conventional array substrates, the gate, second electrode, and first electrode are arranged in separate layers. Therefore, multiple insulating layers are required to insulate the gate, second electrode, and first electrode, respectively, resulting in a cumbersome process. Furthermore, since the gate, second electrode, and first electrode are arranged in separate layers, the gate and second electrode, or the first electrode, are prone to overlap in the vertical direction of the array substrate, generating parasitic capacitance.

[0003] Therefore, there is an urgent need for an array substrate that can reduce the risk of parasitic capacitance between the first electrode and the gate while saving the extra steps of preparing and etching the gate insulation layer. Summary of the Invention

[0004] The purpose of the present application is to provide an array substrate and a display panel, which can reduce the risk of parasitic capacitance generated by the first electrode and the gate while saving additional preparation and etching steps of the gate insulation layer.

[0005] To solve the above technical problems, the present application provides an array substrate, comprising:

[0006] substrate;

[0007] a conductive layer disposed on the substrate, the conductive layer comprising a first trace extending along a first direction, a second trace extending along a second direction, and a first electrode and a gate disposed at intervals, the first trace connected to one of the gate or the first electrode, the second trace connected to the other of the gate or the first electrode, the first direction intersecting the second direction, the first trace being disconnected at the intersection with the second trace to form a first connection end and a second connection end;

[0008] a first insulating layer, the first insulating layer being disposed on the conductive layer and the substrate, and having a first via hole extending through the first electrode;

[0009] an active layer, the active layer being disposed on the first insulating layer and overlapping with the gate in a direction perpendicular to the plane of the substrate, the active layer comprising a first doped portion, a channel portion, and a second doped portion connected in sequence, the first doped portion being connected to the first electrode through the first via hole;

[0010] a second insulating layer, the second insulating layer being disposed on the active layer and the first insulating layer, and having a second via hole extending through the second doped portion;

[0011] a second electrode, the second electrode being disposed on the second insulating layer and connected to the second doped portion through the second via hole;

[0012] A bonding electrode is located on the first insulating layer and / or the second insulating layer, and is connected between the first connection end and the second connection end.

[0013] In one embodiment, the strapping electrode is located on the first insulating layer, and the material of the strapping electrode is the same as that of the first doped portion, or the material of the strapping electrode is the same as that of the second doped portion.

[0014] In one embodiment, the first trace includes a metal layer and a conductive protection layer covering the metal layer.

[0015] The first insulating layer is provided with a third via hole and a fourth via hole penetrating the conductive protection layer. The bonding electrode is connected to the conductive protection layer of the first connection end through the third via hole and is connected to the conductive protection layer of the second connection end through the fourth via hole.

[0016] In one embodiment, the first doped portion includes a first sub-portion and a second sub-portion, wherein the second sub-portion is connected between the first sub-portion and the channel portion, and the ion concentration of the first sub-portion is higher than the ion concentration of the second sub-portion.

[0017] The bonding electrode is located on the first insulating layer, and the material of the bonding electrode is the same as that of the first sub-section.

[0018] In one embodiment, the strapping electrode is located on the second insulating layer, and the material of the strapping electrode is the same as that of the second electrode.

[0019] In one embodiment, the thickness of the bonding electrode is greater than the thickness of the first trace.

[0020] In one embodiment, the bonding electrode includes a first sub-electrode and a second sub-electrode.

[0021] The first sub-electrode is located on the first insulating layer. The material of the first sub-electrode is the same as that of the first doping part.

[0022] The second sub-electrode is located on the second insulating layer and is made of the same material as the second electrode.

[0023] One end of the first sub-electrode is connected to one end of the second sub-electrode, and the other end of the first sub-electrode is connected to the other end of the second sub-electrode.

[0024] In one embodiment, the width of the bonding electrode is smaller than the width of the first wiring, or the width of the bonding electrode is equal to the width of the first wiring.

[0025] In one embodiment, the width of the bonding electrode is greater than the width of the first wiring, and an opening is provided at a position where the bonding electrode and the second wiring overlap.

[0026] The present application provides a display panel, comprising the above-mentioned array substrate.

[0027] In the array substrate provided by the embodiment of the present application, since the first electrode and the gate are arranged in the same layer on the side of the active layer close to the substrate, the second electrode and the gate can share the first insulating layer, saving the steps of preparing and etching the gate insulating layer separately, and the first electrode and the gate are arranged in the same layer, which can reduce the risk of the first electrode and the gate overlapping in a direction perpendicular to the plane of the substrate to generate parasitic capacitance. Since the first electrode and the gate are arranged in the same layer, the first trace connected to the first electrode and the gate and arranged in the same layer as the first electrode and the gate is disconnected at the intersection with the second trace to form a first connection end and a second connection end. By setting a lap electrode connected between the first connection end and the second connection end, the signal transmission of the first trace is ensured. The embodiment of the present application also provides a display panel, including the above-mentioned array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of an array substrate provided in the first embodiment of the present application;

[0029] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure at A-A';

[0030] Figure 3 yes Figure 1 Schematic diagram of the cross-sectional structure at BB';

[0031] Figure 4 is a schematic diagram of an array substrate provided in a second embodiment of the present application;

[0032] Figure 5 is a schematic diagram of an array substrate provided in a third embodiment of the present application;

[0033] Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure at C-C';

[0034] Figure 7 is a schematic diagram of an array substrate provided in a fourth embodiment of the present application;

[0035] Figure 8 yes Figure 7 Schematic diagram of the cross-sectional structure at D-D';

[0036] Figure 9 is a schematic diagram of a first cross-sectional structure of a display panel provided in a fifth embodiment of the present application;

[0037] Figure 10 2 is a schematic diagram of a second cross-sectional structure of a display panel provided in the fifth embodiment of the present application.

[0038] Reference numerals:

[0039] Display panel 1000; array substrate 100; liquid crystal layer 200; opposite substrate 300; light emitting device layer 400; protective layer 500;

[0040] Substrate 110; conductive layer 120; first insulating layer 130; active layer 140; second insulating layer 150; second electrode 160; strapping electrode 170;

[0041] First wiring 121 ; second wiring 122 ; gate 123 ; first electrode 124 ; first doped portion 141 ; channel portion 142 ; second doped portion 143 ; sub-insulating layer 151 ; planar layer 152 ; first sub-electrode 171 ; second sub-electrode 172 ;

[0042] Metal layer 1211; conductive protection layer 1212; first sub-section 1411; second sub-section 1412;

[0043] First connection end E1; second connection end E2; first via K1; second via K2; third via K3; fourth via K4; fifth via K5; sixth via K6; opening U in first direction X; second direction Y. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, any modifications made by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0045] It should be noted that in the description of this application, it should be understood that the orientations or positional relationships indicated by “up”, “down”, “front”, “back”, “left”, “right”, “inside”, and “outside” are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0046] In order to better describe the structures of the conductive layer, the active layer, the second electrode and the strapping electrode, Figure 1 、 Figure 4 、 Figure 5 and Figure 7 This is a schematic diagram ignoring the substrate, the first insulating layer and the second insulating layer.

[0047] Please refer to Figure 1 and Figure 2 The first embodiment of the present application provides an array substrate 100 . The array substrate 100 includes a substrate 110 , a conductive layer 120 , a first insulating layer 130 , an active layer 140 , a second insulating layer 150 , a second electrode 160 , and a bonding electrode 170 .

[0048] The conductive layer 120 is disposed on the substrate 110. The conductive layer 120 includes a first trace 121 extending along a first direction X, a second trace 122 extending along a second direction Y, and a gate 123 and a first electrode 124 spaced apart. The first trace 121 is connected to either the gate 123 or the first electrode 124, while the second trace 122 is connected to the other of the gate 123 and the first electrode 124. The first direction X intersects the second direction Y. The first trace 121 is disconnected at the intersection with the second trace 122, forming a first connection end E1 and a second connection end E2.

[0049] The first insulating layer 130 is disposed on the conductive layer 120 and the substrate 110. A first via hole K1 is defined in the first insulating layer 130, extending through the first electrode 124. The active layer 140 is disposed on the first insulating layer 130 and overlaps the gate 123 in a direction perpendicular to the plane of the substrate 110. The active layer 140 includes a first doped portion 141, a channel portion 142, and a second doped portion 143, which are sequentially connected. The first doped portion 141 is connected to the first electrode 124 via the first via hole K1.

[0050] The second insulating layer 150 is disposed on the active layer 140 and the first insulating layer 130. The second insulating layer 150 is provided with a second via hole K2 penetrating to the second doped portion 143. The second electrode 160 is disposed on the second insulating layer 150 and connected to the second doped portion 143 through the second via hole K2.

[0051] The strapping electrode 170 is located on the first insulating layer 130 and / or the second insulating layer 150. The strapping electrode 170 is connected between the first connection terminal E1 and the second connection terminal E2.

[0052] In the array substrate 100 provided in the embodiment of the present application, since the first electrode 124 and the gate 123 are disposed in the same layer on the side of the active layer 140 close to the substrate 110, the second electrode 160 and the gate 123 can share the first insulating layer 130, eliminating the need for additional steps of preparing and etching the insulating layer of the gate 123. Furthermore, the co-layered arrangement of the first electrode 124 and the gate 123 can reduce the risk of parasitic capacitance generated by the overlap of the first electrode 124 and the gate 123 in a direction perpendicular to the plane of the substrate 110. Since the first electrode 124 and the gate 123 are disposed in the same layer, the first trace 121, which is connected to the first electrode 124 and the gate 123 and is disposed in the same layer as the first electrode 124 and the gate 123, is disconnected at the intersection with the second trace 122 to form a first connection end E1 and a second connection end E2. A bonding electrode 170 is provided to connect between the first connection end E1 and the second connection end E2, thereby ensuring signal transmission of the first trace 121.

[0053] In this embodiment, the first insulating layer 130 is an interlayer dielectric layer. While providing insulation properties, the interlayer dielectric layer ensures circuit stability and reliability. Furthermore, the interlayer dielectric layer provides encapsulation and protection, protecting the circuit from dust and moisture. The second insulating layer 150 includes a sub-insulating layer 151 and a planarizing layer 152. The sub-insulating layer 151 is disposed on the active layer 140, and the planarizing layer 152 is disposed on the sub-insulating layer 151. The planarizing layer 152 can be used to flatten the surface of a film layer, facilitating the fabrication of other films thereon.

[0054] The bonding electrode 170 is located on the first insulating layer 130. A third via hole K3 and a fourth via hole K4 are also formed in the first insulating layer 130, penetrating the first insulating layer 130. One end of the bonding electrode 170 is connected to the first connection terminal E1 through the third via hole K3. The other end of the bonding electrode 170 is connected to the second connection terminal E2 through the fourth via hole K4.

[0055] Optionally, the minimum diameter of the third via K3 is greater than the width of the first trace 121, so that the bonding electrode 170 in the third via K3 completely covers the first trace 121, increasing the contact area between the bonding electrode 170 and the first trace 121, thereby reducing the bonding impedance.

[0056] Optionally, the width of the bonding electrode 170 is greater than, equal to, or less than the width of the first trace 121 . In this embodiment, the width of the bonding electrode 170 is equal to the width of the first trace 121 .

[0057] The material of the strapping electrode 170 is the same as that of the first doped portion 141, or the material of the strapping electrode 170 is the same as that of the second doped portion 143. The strapping electrode 170 is disposed in the same layer as the active layer 140. During the fabrication process, a semiconductor material layer is first formed on the first insulating layer 130. The semiconductor material layer is patterned to form a preliminary pattern for the strapping electrode 170 and a preliminary pattern for the active layer 140. Ion doping is then performed on both ends of the preliminary pattern for the strapping electrode 170 and the preliminary pattern for the active layer 140 to make them conductive. Alternatively, deposition or ion implantation can be used for conductive formation. The conductive preliminary pattern for the strapping electrode 170 forms the strapping electrode 170. The conductive formation of both ends of the preliminary pattern for the active layer 140 forms the first doped portion 141 and the second doped portion 143. A channel portion 142 is formed in the middle of the preliminary pattern for the active layer 140. The first doped portion 141, the second doped portion 143, and the channel portion 142 constitute the active layer 140. Because the strapping electrode 170 is formed in the same layer as the active layer 140 and patterned and fabricated using the same process, process steps can be streamlined. The resistance of the conductive strapping electrode 170, the first doped portion 141, and the second doped portion 143 is lower than that of the channel portion 142, resulting in higher conductivity. The resulting conductive strapping electrode 170 exhibits excellent electrical conductivity.

[0058] In this embodiment, the active layer 140 is made of indium gallium zinc oxide (IGZO). Alternatively, the active layer 140 can be made of one of indium zinc oxide (IZO), indium tin zinc oxide (ITZO), amorphous silicon, and amorphous germanium. The bonding electrode 170, the first doped portion 141, and the second doped portion 143 can be made conductive by ion doping with boron (B), phosphorus (P), fluorine (F), hydrogen (H), nitrogen (N), or the like.

[0059] In this embodiment, the first trace 121 is connected to the first electrode 124, and the second trace 122 is connected to the gate 123. The first trace 121 and the gate 123 are arranged on the same layer to avoid overlapping of the first trace 121 and the gate 123 in the vertical direction of the substrate 110, thereby reducing the risk of parasitic capacitance.

[0060] Optionally, the distance between the disconnected first connection end E1 and the disconnected second connection end E2 of the first trace 121 is less than, equal to, or greater than the width of the gate 123 in the first direction X. The first connection end E1 and the second connection end E2 only need to be spaced apart from the second trace 122 to avoid short circuiting, and this application does not impose any restrictions on this. The distance between the disconnected first connection end E1 and the disconnected second connection end E2 of the first trace 121 is greater than the width of the gate 123 in the first direction X, which can reduce the overlapping area in a direction perpendicular to the first direction X, thereby reducing the risk of parasitic capacitance.

[0061] Please refer to Figure 3 The first trace 121 includes a metal layer 1211 and a conductive protective layer 1212 covering the metal layer 1211. The third via K3 and the fourth via K4 penetrate the conductive protective layer 1212. The bonding electrode 170 is connected to the conductive protective layer 1212 at the first connection end E1 through the third via K3, and is connected to the conductive protective layer 1212 at the second connection end E2 through the fourth via K4. During the preparation process, a semiconductor material layer is formed on the first insulating layer 130, in the third via K3 and in the fourth via K4, and contacts the conductive protective layer 1212. The conductive protective layer 1212 protects the metal layer 1211 and reduces the probability of the metal layer 1211 being etched. The semiconductor material layer is patterned and conductive to form the bonding electrode 170. Oxygen needs to be introduced when forming the semiconductor material layer, and the oxygen contacts the first trace 121 through the third via K3 and the fourth via K4. The provision of the conductive protection layer 1212 can reduce the contact between oxygen and the metal layer 1211 , thereby reducing the probability of oxidation of the metal layer 1211 . Furthermore, the conductive protection layer 1212 is conductive, ensuring electrical connection between the bonding electrode 170 and the first trace 121 .

[0062] The first electrode 124 also includes a metal layer and a conductive protective layer covering the metal layer. When forming the semiconductor material layer, the conductive protective layer of the first electrode 124 protects the metal layer of the first electrode 124 and reduces the probability of the metal layer of the first electrode 124 being etched.

[0063] Specifically, during the manufacturing process, a conductive material layer is formed on a substrate 110. The conductive material layer includes a metal material layer and a conductive protective material layer. The metal material layer and the conductive protective material layer are patterned to form a conductive layer 120 comprising a metal layer and a conductive protective layer. The conductive layer 120 includes a first electrode 124, a gate 123, a first trace 121, and a second trace 122. In other words, both the first electrode 124 and the first trace 121 have a double-layer structure consisting of a metal layer and a conductive protective layer covering the metal layer.

[0064] In this embodiment, the material of the metal layer 1211 includes one or more metals selected from molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The metal layer 1211 may be a molybdenum layer or a copper layer, or may be a stack of a molybdenum layer and an aluminum layer (Mo / Al), a stack of a molybdenum layer and a copper layer (Mo / Cu), a stack of a molybdenum-titanium alloy layer and a copper layer (MoTi / Cu), or a stack of a molybdenum-titanium alloy layer, a copper layer, and a molybdenum-titanium alloy layer (MoTi / Cu / MoTi). The conductive protective layer 1212 may be a metal oxide layer, such as one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (TaO2), or indium tin oxide (ITO).

[0065] Please refer to Figure 4 The second embodiment of the present application provides an array substrate 100 . The second embodiment is similar to the first embodiment. The difference between the second embodiment and the first embodiment is that the first doped portion 141 includes a first sub-portion 1411 and a second sub-portion 1412 , as well as the material of the bonding electrode 170 .

[0066] In this embodiment, the first doped portion 141 includes a first sub-portion 1411 and a second sub-portion 1412. The second sub-portion 1412 is connected between the first sub-portion 1411 and the channel portion 142. The ion concentration of the first sub-portion 1411 is higher than the ion concentration of the second sub-portion 1412. When ion doping is performed on the first doped portion 141, the ion doping concentration of the first sub-portion 1411 is higher than the ion doping concentration of the second sub-portion 1412, thereby reducing the resistance of the first sub-portion 1411 compared to the resistance of the second sub-portion 1412. The first electrode 124 is connected to the first sub-portion 1411 to reduce the impedance of the electrical connection between the active layer 140 and the first electrode 124.

[0067] The strapping electrode 170 is located on the first insulating layer 130, that is, the strapping electrode 170 is provided in the same layer as the active layer 140. The material of the strapping electrode 170 is the same as that of the first sub-portion 1411. That is, the semiconductor material layer is patterned to form a preliminary strapping electrode 170 pattern and a preliminary active layer 140 pattern. While ion doping is performed on the end of the preliminary active layer 140 pattern to form the first sub-portion 1411, ion doping is also performed on the preliminary strapping electrode 170 pattern to make it conductive, thereby making the material of the strapping electrode 170 the same as that of the first sub-portion 1411. The strapping electrode 170 has a high ion doping concentration, low resistance, and high conductivity, which is conducive to the strapping of the first trace 121 and the conduction of electrical signals.

[0068] In this embodiment, the first wiring 121 is connected to the gate 123, and the second wiring 122 is connected to the first electrode 124. The overlapping of the overlapping electrode 170 ensures the transmission of the gate 123 access signal.

[0069] In this embodiment, the width of the bonding electrode 170 is greater than the width of the first trace 121, and an opening U is defined at the intersection of the bonding electrode 170 and the second trace 122. By increasing the width of the bonding electrode 170, the electrical conductivity of the bonding electrode 170 is ensured. Meanwhile, the opening U can reduce the overlapping area between the bonding electrode 170 and the second trace 122 in a direction perpendicular to the substrate 110, thereby reducing the parasitic capacitance generated by the coupling between the bonding electrode 170 and the second trace 122.

[0070] Please refer to Figure 5 and Figure 6 The third embodiment of the present application provides an array substrate 100 . The third embodiment is similar to the first embodiment, but differs from the first embodiment in the position and material of the bonding electrode 170 .

[0071] In this embodiment, the first wiring 121 is connected to the first electrode 124, and the second wiring 122 is connected to the gate 123. Or the first wiring 121 is connected to the gate 123, and the second wiring 122 is connected to the first electrode 124. The overlapping electrode 170 overlaps the first connection end E1 and the second connection end E2 that are disconnected from the first wiring 121. The overlapping electrode 170 is located on the second insulating layer 150, and the overlapping electrode 170 and the second electrode 160 are arranged in the same layer. The material of the overlapping electrode 170 is the same as that of the second electrode 160. During the preparation process, an electrode material layer is first formed on the second insulating layer 150, and then the electrode material layer is patterned to form the overlapping electrode 170 and the second electrode 160. That is, the overlapping electrode 170 and the second electrode 160 are formed in the same layer and patterned by the same process, which saves process and production steps.

[0072] The second insulating layer 150 is provided with a fifth via K5 and a sixth via K6 that penetrate the first trace 121. One end of the bonding electrode 170 is connected to the first connection end E1 through the fifth via K5, and the other end of the bonding electrode 170 is connected to the second connection end E2 through the sixth via K6.

[0073] In this embodiment, the width of the strapping electrode 170 is smaller than the width of the first trace 121. Since the strapping electrode 170 and the second trace 122 are arranged in different layers and cross each other, the width of the strapping electrode 170 being smaller than the width of the first trace 121 can reduce the overlapping area between the strapping electrode 170 and the second trace 122 in a direction perpendicular to the substrate 110, thereby reducing the parasitic capacitance generated by the coupling between the strapping electrode 170 and the second trace 122.

[0074] In this embodiment, the thickness of the bonding electrode 170 is greater than the thickness of the first trace 121. Because impedance is generated at the junction between the bonding electrode 170 and the first trace 121, increasing the thickness of the bonding electrode 170 can reduce the impedance of the bonding electrode 170 and improve the conductivity of the bonding electrode 170, thereby enhancing the electrical transmission capability of the bonding electrode 170 and reducing electrical transmission losses. Because the bonding electrode 170 and the second electrode 160 are formed on the same layer and patterned using the same process, and the first trace 121 and the first electrode 124 are formed on the same layer and patterned using the same process, the thickness of the second electrode 160 is greater than the thickness of the first electrode 124.

[0075] Please refer to Figure 7 and Figure 8 The fourth embodiment of the present application provides an array substrate 100. The fourth embodiment is similar to the first embodiment. The difference between the fourth embodiment and the first embodiment is that the structure of the bonding electrode 170 is different.

[0076] In this embodiment, the strapping electrode 170 includes a first sub-electrode 171 and a second sub-electrode 172. The first sub-electrode 171 is located on the first insulating layer 130 and is made of the same material as the first doped portion 141. The first sub-electrode 171 is disposed in the same layer as the active layer 140 and is patterned and conductively fabricated using the same process as the active layer 140.

[0077] The second sub-electrode 172 is located on the second insulating layer 150 and is made of the same material as the second electrode 160. The second sub-electrode 172 and the second electrode 160 are disposed in the same layer and patterned in the same manner.

[0078] The first insulating layer 130 is provided with a third via hole K3 and a fourth via hole K4 that penetrate the first insulating layer 130. One end of the first sub-electrode 171 is connected to the first connection end E1 through the third via hole K3, and the other end of the first sub-electrode 171 is connected to the second connection end E2 through the fourth via hole K4. The second insulating layer 150 is provided with a fifth via hole K5 and a sixth via hole K6 that penetrate the second insulating layer 150. One end of the second sub-electrode 172 is connected to one end of the first sub-electrode 171 through the fifth via hole K5, and the other end of the second sub-electrode 172 is connected to the other end of the first sub-electrode 171 through the sixth via hole K6.

[0079] By overlapping the first sub-electrode 171 and the second sub-electrode 172 , the resistance of the overlapping electrode 170 is further reduced, and the overlapping of the overlapping electrode 170 to the first trace 121 is further ensured, thereby ensuring the transmission of electrical signals.

[0080] Please refer to Figure 9 and Figure 10The fifth embodiment of the present application provides a display panel 1000. The display panel 1000 includes the array substrate 100 provided in any one of the first to fourth embodiments.

[0081] Optionally, the display panel 1000 is a liquid crystal display panel, an organic light emitting display panel, or a micro light emitting diode display panel, etc. The display panel 1000 can be driven by the array substrate 100, and this application does not impose any restrictions on this.

[0082] The array substrate 100 is used for a liquid crystal display panel, and the display panel 1000 further includes a liquid crystal layer 200 and an opposite substrate 300. The array substrate 100 and the opposite substrate 300 are disposed opposite to each other, and the liquid crystal layer 200 is disposed between the array substrate 100 and the opposite substrate 300.

[0083] In some embodiments, the display panel 1000 includes a light-emitting device layer 400, and the light-emitting device layer 400 is disposed on the array substrate 100. The light-emitting device layer 400 is one of an organic light-emitting diode device layer, a micro light-emitting diode device layer, or a sub-millimeter light-emitting diode device layer. Accordingly, the display panel 1000 is an organic light-emitting display panel, a micro light-emitting diode display panel, or a sub-millimeter light-emitting diode display panel.

[0084] Optionally, the display panel 1000 further includes a protection layer 500 disposed on the light emitting device layer 400 to protect the light emitting device layer 400 .

[0085] The array substrate 100 and the display panel 1000 provided in this application are introduced in detail above.

[0086] In the array substrate provided by the embodiment of the present application, since the first electrode and the gate are arranged in the same layer on the side of the active layer close to the substrate, the second electrode and the gate can share the first insulating layer, saving the steps of preparing and etching the gate insulating layer separately, and the first electrode and the gate are arranged in the same layer, which can reduce the risk of the first electrode and the gate overlapping in a direction perpendicular to the plane of the substrate to generate parasitic capacitance. Since the first electrode and the gate are arranged in the same layer, the first trace connected to the first electrode and the gate and arranged in the same layer as the first electrode and the gate is disconnected at the intersection with the second trace to form a first connection end and a second connection end. By setting a lap electrode connected between the first connection end and the second connection end, the signal transmission of the first trace is ensured. The embodiment of the present application also provides a display panel, including the above-mentioned array substrate.

[0087] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above examples is only intended to help understand the core ideas of this application. It should be noted that for those skilled in the art, without departing from the principles of this application, various improvements and modifications can be made to this application, and such improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. An array substrate, characterized in that: The array substrate includes: substrate; a conductive layer disposed on the substrate, the conductive layer comprising a first trace extending along a first direction, a second trace extending along a second direction, and a first electrode and a gate disposed at intervals, the first trace connected to one of the gate or the first electrode, the second trace connected to the other of the gate or the first electrode, the first direction intersecting the second direction, the first trace being disconnected at the intersection with the second trace to form a first connection end and a second connection end; a first insulating layer, the first insulating layer being disposed on the conductive layer and the substrate, and having a first via hole extending through the first electrode; an active layer, the active layer being disposed on the first insulating layer and overlapping with the gate in a direction perpendicular to the plane of the substrate, the active layer comprising a first doped portion, a channel portion, and a second doped portion connected in sequence, the first doped portion being connected to the first electrode through the first via hole; a second insulating layer, the second insulating layer being disposed on the active layer and the first insulating layer, and having a second via hole extending through the second doped portion; a second electrode, the second electrode being disposed on the second insulating layer and connected to the second doped portion through the second via hole; A bonding electrode is located on the first insulating layer and / or the second insulating layer, and is connected between the first connection end and the second connection end.

2. The array substrate according to claim 1, wherein: The strapping electrode is located on the first insulating layer, and the material of the strapping electrode is the same as that of the first doping portion, or the material of the strapping electrode is the same as that of the second doping portion.

3. The array substrate according to claim 2, wherein: The first trace includes a metal layer and a conductive protective layer covering the metal layer; A third via and a fourth via are provided on the first insulating layer and penetrate the conductive protective layer. The bonding electrode is connected to the conductive protective layer of the first connection end through the third via and is connected to the conductive protective layer of the second connection end through the fourth via.

4. The array substrate according to claim 1, wherein: The first doping portion includes a first sub-portion and a second sub-portion, the second sub-portion is connected between the first sub-portion and the channel portion, and the ion concentration of the first sub-portion is higher than the ion concentration of the second sub-portion; The bonding electrode is located on the first insulating layer, and the material of the bonding electrode is the same as that of the first sub-section.

5. The array substrate according to claim 1, wherein: The bonding electrode is located on the second insulating layer, and the material of the bonding electrode is the same as that of the second electrode.

6. The array substrate according to claim 5, wherein: The thickness of the bonding electrode is greater than the thickness of the first wiring.

7. The array substrate according to claim 1, wherein: The bonding electrode includes a first sub-electrode and a second sub-electrode; The first sub-electrode is located on the first insulating layer, and the material of the first sub-electrode is the same as the material of the first doped part; The second sub-electrode is located on the second insulating layer, and the material of the second sub-electrode is the same as that of the second electrode; One end of the first sub-electrode is connected to one end of the second sub-electrode, and the other end of the first sub-electrode is connected to the other end of the second sub-electrode.

8. The array substrate according to claim 1, wherein: The width of the bonding electrode is smaller than the width of the first wiring; or the width of the bonding electrode is equal to the width of the first wiring.

9. The array substrate according to claim 1, wherein: The width of the bonding electrode is greater than the width of the first wiring, and an opening is provided at a position where the bonding electrode and the second wiring overlap.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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