Video stream compression synchronization control circuit, method and device

Abstract

The present application provides a video stream compression synchronization control circuit, method and device. The video stream compression synchronization control circuit includes a synchronization information generation module and a data caching module, wherein: The synchronization information generation module is configured to receive a timing signal for video stream data; perform retiming processing on the timing signal to generate a synchronization signal; and send the synchronization signal to the data caching module. The data caching module is configured to receive the timing signal and the video stream data; perform recombination and caching processing on the video stream data according to the timing signal to obtain valid video stream data; and output the valid video stream data according to the synchronization signal. The solution of the present application can ensure the strict synchronization of the synchronization signal and the valid video stream data, so that the valid video stream data can be correctly input into the downstream display device, ensuring the correct display of the display device.

Description

Technical Field

[0001] This application relates to the technical field of video processing, and in particular, to a video stream compression synchronization control circuit, method, and device. Background Art

[0002] The High-Definition Multimedia Interface (HDMI) is a fully digital video and audio transmission interface that can be used to transmit compressed or uncompressed video signals and transmit audio and video signals to a video display device for display.

[0003] In a video system where HDMI is the data receiving end, HDMI will perform corresponding processing on the data sent by the data sending end, including data stream separation, data decryption, data decompression, etc., and finally output the processed data to subsystems such as downstream display devices. Since the data format at the input end of the display device is fixed, the data output by HDMI needs to meet the timing requirements of the display device so that the display device can correctly perform subsequent operations.

[0004] However, in different modes of HDMI, the data after decompression by Video Stream Compression (VESA DSC) is not synchronized with the timing required by the display device, resulting in the display device being unable to display correctly. Summary of the Invention

[0005] This application provides a video stream compression synchronization control circuit, method, and device to solve the problem that the data after DSC decompression is not synchronized with the timing required by the display device, resulting in the display device being unable to display correctly.

[0006] In a first aspect, this application provides a video stream compression synchronization control circuit, including a synchronization information generation module and a data cache module, where:

[0007] The synchronization information generation module is configured to receive a timing signal for video stream data; perform retiming processing on the timing signal to generate a synchronization signal; and send the synchronization signal to the data cache module;

[0008] The data cache module is configured to receive the timing signal and the video stream data; perform recombination and caching processing on the video stream data according to the timing signal to obtain valid video stream data; and output the valid video stream data according to the synchronization signal.

[0009] In a possible implementation, the timing signal includes a frame start signal, a line start signal, and a data validity signal, and the synchronization information generation module includes a vertical synchronization sub-module, a horizontal synchronization sub-module, and an indication signal sub-module; where:

[0010] The vertical synchronization sub-module is configured to determine, in the current clock cycle, a line cumulative value of the current frame indicated by the frame start signal in the video stream data according to the frame start signal, the line start signal, and the data validity signal;

[0011] The horizontal synchronization sub-module is configured to determine, in the current clock cycle, a pixel cumulative value in the current line indicated by the line start signal in the current frame according to the line start signal and the data validity signal;

[0012] The indication signal sub-module is configured to generate the synchronization signal according to the line cumulative value and the pixel cumulative value.

[0013] In a possible implementation, the horizontal synchronization sub-module is specifically configured to:

[0014] Initialize the pixel cumulative value to a first value according to the line start signal, where the first value is the number of pixels between the first pixel of the current line and the first valid pixel of the current line;

[0015] Determine, according to the line start signal and the data validity signal, a time period to which the current clock cycle belongs during a time period corresponding to the current line, where the time period corresponding to the current line includes a line start time period, a valid pixel time period, and an invalid pixel time period of the current line;

[0016] When the time period to which the current clock cycle belongs is the valid pixel time period and the pixel cumulative value is less than a first pixel threshold, update the pixel cumulative value, and the updated pixel cumulative value is the previous pixel cumulative value plus one;

[0017] When the time period to which the current clock cycle belongs is the invalid pixel time period and the pixel cumulative value is less than a second pixel threshold, update the pixel cumulative value, and the updated pixel cumulative value is the previous pixel cumulative value plus one.

[0018] In a possible implementation, the vertical synchronization sub-module is specifically configured to:

[0019] Initialize the line cumulative value to a second value according to the frame start signal, where the second value is the number of lines between the first line of the current frame and the first valid line indicated by the line start signal;

[0020] According to the frame start signal, the line start signal, and the data validity signal, determine the time period to which the current clock cycle belongs during the time period corresponding to the current frame, where the time period corresponding to the current frame includes the frame start time period, the valid line time period, or the invalid line time period of the current frame;

[0021] When the time period to which the current clock cycle belongs is the valid line time period and the line cumulative value is less than a preset line threshold, update the line cumulative value, and the updated line cumulative value is the previous line cumulative value plus one;

[0022] When the time period to which the current clock cycle belongs is the invalid line time period and the pixel point cumulative value is equal to the first pixel point threshold, update the line cumulative value, and the updated line cumulative value is the previous line cumulative value plus one.

[0023] In a possible implementation manner, the indication signal sub-module is specifically configured to:

[0024] Generate a frame synchronization signal according to the line cumulative value and the second value;

[0025] Generate a line synchronization signal according to the pixel point cumulative value and the first value;

[0026] Generate a valid data indication signal according to the line cumulative value and the pixel point cumulative value, where the synchronization signal includes the frame synchronization signal, the line synchronization signal, and the valid data indication signal.

[0027] In a possible implementation manner, the step of the indication signal sub-module generating a valid data indication signal according to the line cumulative value and the pixel point cumulative value includes:

[0028] During the time period corresponding to the current frame, determine the time period corresponding to the line cumulative value, and the time period corresponding to the line cumulative value is the valid line time period or the invalid line time period;

[0029] Generate the valid data indication signal according to the time period corresponding to the line cumulative value and the pixel point cumulative value;

[0030] Wherein, when the time period corresponding to the line cumulative value is the valid line time period and the pixel point cumulative value is greater than a third value, the valid data indication signal is in an effective state, and the third value is the first value minus one;

[0031] When the time period corresponding to the line cumulative value is the invalid line time period and / or the pixel point cumulative value is less than or equal to the third value, the valid data indication signal is in an invalid state.

[0032] In a possible implementation, the data cache module includes a recombination sub-module, a write enable control sub-module, a cache sub-module, and a read enable control sub-module;

[0033] The recombination sub-module is configured to recombine the valid video stream data according to the target data format matched by the receiving device, so as to obtain the valid video stream data in the target data format;

[0034] The write enable control sub-module is configured to store the valid video stream data in the target data format into the cache sub-module according to the frame start signal and the line start signal when the data validity signal is in an effective state;

[0035] The read enable control sub-module is configured to output the valid video stream data in the target data format from the cache sub-module according to the frame synchronization signal and the line synchronization signal when the valid data indication signal is in an effective state.

[0036] In a possible implementation, it further includes a register synchronization module, and the register synchronization module is configured to:

[0037] Perform synchronous configuration on the registers in the synchronization information generation module and the data cache module; after the register synchronous configuration is completed, send a register synchronization signal to the synchronization information generation module and the data cache module;

[0038] The steps of the synchronization information generation module performing retiming processing on the timing signal to generate a synchronization signal include:

[0039] After receiving the register synchronization signal, perform retiming processing on the timing signal to generate the synchronization signal;

[0040] The steps of the data cache module performing recombination and caching processing on the video stream data according to the timing signal to obtain valid video stream data include:

[0041] After receiving the register synchronization signal, perform recombination and caching processing on the video stream data according to the timing signal to obtain the valid video stream data.

[0042] In a second aspect, the present application provides a video stream compression synchronization control method, including:

[0043] Receiving video stream data and a timing signal for the video stream data;

[0044] Performing retiming processing on the timing signal to generate a synchronization signal;

[0045] Reorganize and cache the video stream data according to the timing signal to obtain valid video stream data;

[0046] Output the valid video stream data according to the synchronization signal.

[0047] In a possible implementation manner, the timing signal includes a frame start signal, a line start signal, and a data validity signal. The retiming process on the timing signal to generate a synchronization signal includes:

[0048] In the current clock cycle, according to the frame start signal, the line start signal, and the data validity signal, determine the line cumulative value of the current frame indicated by the frame start signal in the video stream data;

[0049] In the current clock cycle, according to the line start signal and the data validity signal, determine the pixel cumulative value in the current line indicated by the line start signal in the current frame;

[0050] Generate the synchronization signal according to the line cumulative value and the pixel cumulative value.

[0051] In a possible implementation manner, the determining the pixel cumulative value in the current line indicated by the line start signal in the current frame according to the line start signal and the data validity signal includes:

[0052] Initialize the pixel cumulative value to a first value according to the line start signal, where the first value is the number of pixels between the first pixel of the current line and the first valid pixel of the current line;

[0053] According to the line start signal and the data validity signal, determine the time period to which the current clock cycle belongs during the time period corresponding to the current line. The time period corresponding to the current line includes the line start time period, the valid pixel time period, and the invalid pixel time period of the current line;

[0054] When the time period to which the current clock cycle belongs is the valid pixel time period and the pixel cumulative value is less than the first pixel threshold, update the pixel cumulative value, and the updated pixel cumulative value is the previous pixel cumulative value plus one;

[0055] When the time period to which the current clock cycle belongs is the invalid pixel time period and the pixel cumulative value is less than the second pixel threshold, update the pixel cumulative value, and the updated pixel cumulative value is the previous pixel cumulative value plus one.

[0056] In a possible implementation, determining the line cumulative value of the current frame indicated by the frame start signal in the video stream data according to the frame start signal, the line start signal, and the data validity signal includes:

[0057] Initializing the line cumulative value to a second value according to the frame start signal, where the second value is the number of lines between the first line of the current frame and the first valid line indicated by the line start signal;

[0058] Determining the time period to which the current clock cycle belongs in the time period corresponding to the current frame according to the frame start signal, the line start signal, and the data validity signal, where the time period corresponding to the current frame includes the frame start time period, the valid line time period, or the invalid line time period of the current frame;

[0059] When the time period to which the current clock cycle belongs is the valid line time period and the line cumulative value is less than a preset line threshold, updating the line cumulative value, and the updated line cumulative value is the previous line cumulative value plus one;

[0060] When the time period to which the current clock cycle belongs is the invalid line time period and the pixel point cumulative value is equal to the first pixel point threshold, updating the line cumulative value, and the updated line cumulative value is the previous line cumulative value plus one.

[0061] In a possible implementation, generating the synchronization signal according to the line cumulative value and the pixel point cumulative value includes:

[0062] Generating a frame synchronization signal according to the line cumulative value and the second value;

[0063] Generating a line synchronization signal according to the pixel point cumulative value and the first value;

[0064] Generating a valid data indication signal according to the line cumulative value and the pixel point cumulative value, and the synchronization signal includes the frame synchronization signal, the line synchronization signal, and the valid data indication signal.

[0065] In a possible implementation, generating the valid data indication signal according to the line cumulative value and the pixel point cumulative value includes:

[0066] Determining the time period corresponding to the line cumulative value in the time period corresponding to the current frame, and the time period corresponding to the line cumulative value is the valid line time period or the invalid line time period;

[0067] Generating the valid data indication signal according to the time period corresponding to the line cumulative value and the pixel point cumulative value;

[0068] Among them, when the time period corresponding to the line cumulative value is the valid line time period, and when the pixel cumulative value is greater than a third value, the valid data indication signal is in an effective state, and the third value is the first value minus one;

[0069] When the time period corresponding to the line cumulative value is the invalid line time period, and / or when the pixel cumulative value is less than or equal to the third value, the valid data indication signal is in an invalid state.

[0070] In a possible implementation manner, the outputting the valid video stream data according to the synchronization signal includes:

[0071] Recombining the valid video stream data according to the target data format matched by the receiving device to obtain the valid video stream data in the target data format;

[0072] When the data validity signal is in an effective state, storing the valid video stream data in the target data format into the cache sub-module according to the frame start signal and the line start signal;

[0073] When the valid data indication signal is in an effective state, outputting the valid video stream data in the target data format from the cache sub-module according to the frame synchronization signal and the line synchronization signal.

[0074] In a possible implementation manner, the method further includes:

[0075] Performing synchronous configuration on the registers in the synchronization information generation module and the data cache module;

[0076] After the register synchronous configuration is completed, sending a register synchronous signal to the synchronization information generation module and the data cache module;

[0077] The retiming the timing signal to generate a synchronization signal includes:

[0078] After receiving the register synchronous signal, retiming the timing signal to generate the synchronization signal;

[0079] The reorganizing and caching the video stream data according to the timing signal to obtain valid video stream data includes:

[0080] After receiving the register synchronous signal, reorganizing and caching the video stream data according to the timing signal to obtain the valid video stream data.

[0081] In a third aspect, the present application provides an electronic device, including the video stream compression synchronization control circuit according to any one of the first aspect.

[0082] In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the video stream compression synchronization control method according to the second aspect is implemented.

[0083] The video stream compression synchronization control circuit provided by the present application includes a synchronization information generation module and a data caching module. The synchronization information generation module is configured to receive a timing signal for video stream data, then perform retiming processing on the timing signal to generate a synchronization signal, and send the synchronization signal to the data caching module. The data caching module is configured to receive the timing signal and the video stream data, perform reorganization and caching processing on the video stream data according to the timing signal to obtain valid video stream data, and input the valid video stream data according to the synchronization signal. For the video stream data output by the DSC, since the video stream data is reorganized and cached according to the timing information indicated by the timing signal, and the synchronization signal generated after the retiming processing of the timing signal by the synchronization information generation module indicates the output of the valid video stream data, it can ensure the strict synchronization between the synchronization signal and the valid video stream data, so that the valid video stream data can be correctly input to the downstream display device, ensuring the correct display of the display device. Description of the Drawings

[0084] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0085] Figure 1 Structural schematic of the video stream compression synchronization control circuit provided by the embodiment of the present application Figure 1 ;

[0086] Figure 2 Structural schematic of the video stream compression synchronization control circuit provided by the embodiment of the present application Figure 2 ;

[0087] Figure 3 Schematic diagram of the time period division corresponding to the current row provided by the embodiment of the present application;

[0088] Figure 4 Schematic diagram of the process for determining the cumulative value of pixel points provided by the embodiment of the present application;

[0089] Figure 5 Schematic diagram of the time period division corresponding to the current frame provided by the embodiment of the present application;

[0090] Figure 6 Schematic diagram of the process for determining the row cumulative value provided by the embodiment of the present application;

[0091] Figure 7 Schematic diagram of the classified arrangement of DSC output data provided by the embodiment of the present application Figure 1 ;

[0092] Figure 8 Schematic diagram of the classified arrangement of DSC output data provided by the embodiment of the present application Figure 2 ;

[0093] Figure 9 Schematic diagram of data recombination provided by the embodiment of the present application Figure 1 ;

[0094] Figure 10 Schematic diagram of data recombination provided by the embodiment of the present application Figure 2 ;

[0095] Figure 11 Schematic diagram of the process of the video stream compression synchronization control method provided by the embodiment of the present application;

[0096] Figure 12 Schematic diagram of the physical structure of an electronic device provided by the embodiment of the present application. Detailed implementation manners

[0097] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below in conjunction with the accompanying drawings in the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0098] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. Among them, A and B may be singular or plural. In the written description of the present application, the character " / " generally represents an "or" relationship between the associated objects before and after.

[0099] HDMI is a fully digital video and audio transmission interface, which can be used to transmit uncompressed or compressed audio and video signals, and can transmit audio-visual digital signals such as DVD players, set-top boxes, and computers to video display devices such as televisions and projectors.

[0100] HDMI 2.1 supports DSC compression technology. When the bandwidth exceeds 48 Gbps, such as in the case of 4K 120Hz, color depth 30 or 36 bits, DSC is required. Through the combination of a Fixed Rate Link (FRL) and DSC, high-quality images can be compressed and transmitted in a visually lossless manner.

[0101] In an audio-video system where HDMI is the data receiving end, HDMI will perform corresponding processing on the audio-video data sent by the data sending end, including the separation of data streams, data decryption, data decompression, etc. Finally, the processed audio-video data will be output to downstream display devices, subsystems such as Audio. Since the data format at the input end of the display device is already fixed, that is, it conforms to the standard video format, the data output by DSC needs to meet the timing requirements of the display device so that the display device can correctly perform subsequent operations.

[0102] Since HDMI is in different modes, the data after DSC decompression is slightly different from the timing required by the display device, resulting in the display device being unable to correctly display the audio-video data. For example, the timing signals output by DSC, such as Horizontal synchronization (HSYNC), will be abnormal, that is, during the Vertical Blanking (VBLANK) period in some DSC modes, there is no HSYNC output. For example, there is a drift between the data output by DSC and the timing signals, that is, the distance from HSYNC to the valid pixel data is not fixed, and the distance from Vertical synchronization (VSYNC) to the valid line is not fixed.

[0103] Based on this, the embodiments of the present application provide a video stream compression synchronization control circuit to achieve the synchronization of data signals and synchronization signals, thereby meeting the timing requirements at the input end of the downstream display device. The solutions of the embodiments of the present application will be introduced below with reference to the accompanying drawings.

[0104] Figure 1 Structural schematic of the video stream compression synchronization control circuit provided by the embodiments of the present application Figure 1 , as Figure 1 shown, the circuit includes a synchronization information generation module 11 and a data cache module 12, where:

[0105] The synchronization information generation module 11 is used to receive the timing signals for video stream data; perform retiming processing on the timing signals to generate synchronization signals; and send the synchronization signals to the data cache module 12;

[0106] The data caching module 12 is configured to receive a timing signal and video stream data; perform recombination and caching processing on the video stream data according to the timing signal to obtain valid video stream data; and output the valid video stream data according to a synchronization signal.

[0107] The DSC sends the video stream data and a timing signal for the video stream data to the video stream compression synchronization control circuit. Among them, the timing signal is input to the synchronization information generation module 11, and the timing signal and the video stream data are input to the data caching module 12.

[0108] In the timing signal, the timing information output by the DSC is included. After receiving the timing signal, the data caching module 12 performs recombination and caching processing on the video stream data according to the timing information indicated in the timing signal. This process is the process of caching the video stream data into the data caching module 12, that is, the process of writing data.

[0109] The recombination and caching processing includes two processes: data recombination and caching. The process of data recombination is mainly to recombine the video stream data according to the data format required by the downstream display device, so that the video stream data after data recombination matches the data format required by the display device. The caching process is the process of writing the data into the data caching module 12 after data recombination. In the embodiment of the present application, the video stream data may include some invalid data. Therefore, the caching process will eliminate this part of the invalid data, and finally the cached is the valid video stream data.

[0110] For the synchronization information generation module 11, after receiving the timing signal for the video stream data, the synchronization information generation module 11 performs retiming processing on the timing signal. The retiming processing is mainly to generate relevant synchronization signals to indicate the output of the valid video stream data. After the synchronization information generation module 11 generates the synchronization signal, the synchronization information generation module 11 sends the synchronization signal to the data caching module, and the data caching module 12 inputs the valid video stream data according to the received synchronization signal.

[0111] The video stream compression synchronization control circuit provided by the embodiment of the present application includes a synchronization information generation module and a data cache module. The synchronization information generation module is used to receive the timing signal for the video stream data, then perform retiming processing on the timing signal to generate a synchronization signal, and send the synchronization signal to the data cache module. The data cache module is used to receive the timing signal and the video stream data, and perform recombination and caching processing on the video stream data according to the timing signal to obtain valid video stream data, and input the valid video stream data according to the synchronization signal. For the video stream data output by the DSC, since the video stream data is subjected to recombination and caching processing based on the timing information indicated by the timing signal, and the synchronization signal generated after the retiming processing of the timing signal by the synchronization information generation module indicates the output of the valid video stream data, it can ensure the strict synchronization of the synchronization signal and the valid video stream data, so that the valid video stream data can be correctly input into the downstream display device, ensuring the correct display of the display device.

[0112] Based on any of the above embodiments, the solution of the embodiment of the present application will be introduced in detail below with reference to the accompanying drawings.

[0113] Figure 2 Structural schematic of the video stream compression synchronization control circuit provided by the embodiment of the present application Figure 2 , as Figure 2 shown, the circuit includes a synchronization information generation module 11 and a data cache module 12. Optionally, the circuit further includes a register synchronization module 13, where,

[0114] The register synchronization module 13 is used to perform synchronous configuration on the registers in the synchronization information generation module 11 and the data cache module 12; after the register synchronous configuration is completed, a register synchronization signal is sent to the synchronization information generation module 11 and the data cache module 12.

[0115] In the embodiment of the present application, the register synchronization module 13 is mainly used to perform synchronous configuration on the registers in the synchronization information generation module 11 and the data cache module 12 to eliminate the metastability problem caused by multi-bit transmission. There may be many registers in the synchronization information generation module 11 and the data cache module 12 that need to be pre-configured. For example, in both the synchronization information generation module 11 and the data cache module 12, there are some preset thresholds. Before these preset thresholds are called by the synchronization information generation module 11 or the data cache module 12, specific values need to be pre-configured into the corresponding registers before they can be correctly used. The register synchronization module 13 can complete the synchronous configuration of these registers.

[0116] As Figure 2As shown in the figure, the register synchronization module 13 synchronizes the ud signal, which is used to indicate whether the register synchronization configuration of the register synchronization module 13 is completed. For example, when the ud signal changes from 1 to 0, it means that the circuit has used the new configuration, and the relevant registers of the video stream compression synchronization control circuit will latch the configured values. In this case, the synchronization information generation module 11 and the data cache module 12 cannot perform subsequent operations temporarily. For example, when the ud signal changes from 0 to 1, it means that the register synchronization configuration is completed. At this time, the register synchronization module 13 extends the ud signal using a 16-bit shift register to obtain a register synchronization signal. The purpose of the register synchronization signal is to generate a static clear state for 16 cycles to ensure that all configurations are valid.

[0117] Then the register synchronization module 13 sends the register synchronization signal to the synchronization information generation module 11 and the data cache module 12. After receiving the register synchronization signal, the synchronization information generation module 11 and the data cache module 12 can know that the register synchronization configuration is completed and can perform subsequent operations. That is, after receiving the register synchronization signal, the synchronization information generation module 11 performs retiming processing on the timing signal to generate a synchronization signal; after receiving the register synchronization signal, the data cache module 12 reorganizes and caches the video stream data according to the timing signal to obtain valid video stream data.

[0118] The following combines Figure 2 to introduce the specific processing process of the synchronization information generation module 11 for the timing signal.

[0119] The DSC sends video stream data to the video stream compression synchronization control circuit according to the timing signal. In the embodiments of the present application, the timing signal includes a frame start signal, a line start signal, and a data validity signal.

[0120] Among them, the frame start signal indicates the start of the next frame and the end of the previous frame, the line start signal indicates the start of the next line and the end of the previous line, and the data validity signal indicates the valid data in the video stream data.

[0121] As Figure 2 shown, the synchronization information generation module 11 includes a vertical synchronization sub-module 201, a horizontal synchronization sub-module 202, and an indication signal sub-module 203.

[0122] The vertical synchronization sub-module 201 is used to determine the row cumulative value of the current frame indicated by the frame start signal in the video stream data according to the frame start signal, the line start signal, and the data validity signal in the current clock cycle.

[0123] The horizontal synchronization sub-module 202 is used to determine the cumulative value of pixel points in the current row indicated by the row start signal in the current frame according to the row start signal and the data validity signal in the current clock cycle.

[0124] The indication signal sub-module 203 is used to generate a synchronization signal according to the row cumulative value and the pixel point cumulative value.

[0125] For video stream data, the video stream data includes frame data transmitted in sequence. For any frame of data, this frame of data includes pixel point data transmitted in sequence. In the embodiments of the present application, the data is transmitted in clock cycles, and each clock cycle corresponds to a pixel point data. That is to say, one pixel point data is transmitted in one clock cycle. The transmission of video stream data is a continuous process. As the clock cycle changes, the corresponding pixel point data transmitted also changes.

[0126] For the vertical synchronization sub-module 201, it receives the frame start signal, the row start signal, and the data validity information, and then determines the row cumulative value of the current frame in the video stream data according to the frame start signal, the row start signal, and the data validity signal in the current clock cycle.

[0127] The current frame in the embodiments of the present application refers to the current frame indicated by the frame start signal. Since the frame start signal indicates the end of the previous frame or the start of the next frame, based on the frame start signal, the frame that has started and not ended can be determined as the current frame.

[0128] For the current frame, the current frame includes many rows. Among them, each row of pixel points constitutes a row in the current frame. The row cumulative value represents how many rows in the current frame are included in the video stream data that the DSC has sent in the current clock cycle. As described above, the process of the DSC sending video stream data is a continuous process. In the current clock cycle, the current frame data is being sent. For the current frame, it also takes a certain amount of time to transmit each row in the current frame. The row cumulative value is used to indicate how many rows in the current frame have been sent. As time changes, the row cumulative value will also change accordingly.

[0129] For the horizontal synchronization sub-module 202, it receives the row start signal and the data validity signal, and then determines the cumulative value of pixel points in the current row in the current frame according to the row start signal and the data validity signal in the current clock cycle.

[0130] The current row in the embodiments of the present application refers to the current row indicated by the row start signal. In the current frame, since the row start signal indicates the end of the previous row or the start of the next row, based on the row start signal, the row that has started and not ended can be determined as the current row.

[0131] For the current line, the current line includes many pixel points, and the pixel point cumulative value represents how many pixel points in the current line of the current frame are included in the video stream data already sent by the DSC in the current clock cycle. As described above, the process of the DSC sending video stream data is a continuous process. In the current clock cycle, the current line data in the current frame is being sent. For the current line, it also takes a certain amount of time to transmit each pixel point in the current line, and the pixel point cumulative value is used to indicate how many pixel points in the current line have been sent. As time changes, the pixel point cumulative value will also change accordingly.

[0132] The processes of determining the line cumulative value and the pixel point cumulative value are introduced separately below.

[0133] First, the process of the horizontal synchronization sub-module determining the pixel point cumulative value is introduced.

[0134] The horizontal synchronization sub-module 202 initializes the pixel point cumulative value to a first value according to the line start signal. The first value is the number of pixel points between the first pixel point of the current line and the start of the first valid pixel point of the current line, and the first value is a preset value. The line start signal can indicate the start of the current line. At the start of the current line, until the data validity signal indicates the start of the transmission of valid data, there are the first number of invalid pixel points. Therefore, the pixel point cumulative value can be initialized to the first value, and the first value is greater than or equal to 0. For any line in the current frame, at the moment when the data of that line starts to be transmitted, the pixel point cumulative value will be initialized to the first value.

[0135] Then, the horizontal synchronization sub-module 202 determines the time period to which the current clock cycle belongs in the time period corresponding to the current line according to the line start signal and the data validity signal. The time period corresponding to the current line includes the line start time period, the valid pixel time period, and the invalid pixel time period of the current line.

[0136] The line start time period is the time period between the start of the current line and the start of the first valid pixel point in the current line. The valid pixel time period is the time period between the start of the first valid pixel point and the end of the last valid pixel point in the current line. The invalid pixel time period is the time period between the end of the last valid pixel point and the end of the current line.

[0137] The division of the three time periods can be referred to Figure 3 for the introduction.

[0138] Figure 3 is the schematic diagram of the time period division corresponding to the current line provided by the embodiment of the present application. As Figure 3 shown, taking the current line including 20 pixel points as an example, in Figure 3These 20 pixel points are identified in [description], and it takes 20 clock cycles to transmit the data of these 20 pixel points.

[0139] As Figure 3 shown, the row start signal can indicate the start time of the first pixel point in the current row, i.e., t1, and the end time of the 20th pixel point in the current row, i.e., t4. The data validity signal can indicate the start time and end time of the valid data in the current row, i.e., Figure 3 t2 and t3 in [description]. Then, the time period between t1 and t2 belongs to the row start period, the time period between t2 and t3 belongs to the valid pixel period, and the time period between t3 and t4 belongs to the invalid pixel period.

[0140] It should be noted that the number of pixel points included between t1 and t2 is called hstart, which represents the distance between the first pixel point and the first valid pixel point in the current row. In the embodiments of the present application, the value of hstart is a fixed value, i.e., the first numerical value. In Figure 3 [description], the second numerical value is set to 4, that is, in the current row, the first 4 pixel points are invalid pixel points, and starting from the 5th pixel point belongs to the valid pixel points.

[0141] The horizontal synchronization sub-module 202 can determine the time period to which the current clock cycle belongs according to the row start signal and the data validity signal. Since the pixel points transmitted during the row start period are invalid pixel points, the pixel points transmitted during this period are not counted, and only counted during the valid pixel period and the invalid pixel period.

[0142] Specifically, when the time period to which the current clock cycle belongs is the row start period, it indicates that the transmission of the valid row has started. Then, the horizontal synchronization sub-module 202 determines whether the data validity signal is in the valid state under the current clock cycle. If so, the pixel point cumulative value is initialized to the first numerical value.

[0143] When the time period to which the current clock cycle belongs is the valid pixel period, and the pixel point cumulative value is less than the first pixel point threshold, update the pixel point cumulative value, and the updated pixel point cumulative value is the pixel point cumulative value before the update plus one;

[0144] When the time period to which the current clock cycle belongs is the invalid pixel period, and the pixel point cumulative value is less than the second pixel point threshold, update the pixel point cumulative value, and the updated pixel point cumulative value is the pixel point cumulative value before the update plus one. In the embodiments of the present application, the first pixel point threshold and the second pixel point threshold may be equal or unequal.

[0145] In a possible implementation manner, a pixel point counter hcnt can be set to record the pixel point cumulative value. The following combines Figure 4Introduce this process.

[0146] Figure 4 This is a schematic flowchart of the process for determining the cumulative value of pixel points provided by the embodiments of this application. As Figure 4 shown, it includes:

[0147] S41, reset hcnt.

[0148] The process of resetting hcnt is to reset the value of hcnt to the first value hstart. For a new line, that is, after the line start signal indicates a new line, reset hcnt to the first value hstart.

[0149] S42, determine whether the register synchronization signal is 1. If it is, execute S48; if not, execute S43.

[0150] When the register synchronization signal is 0, it means that the horizontal synchronization sub-module has received the indication from the register synchronization module and the register synchronization configuration has been completed, and the subsequent process can be executed; when the register synchronization signal is 1, it means that the horizontal synchronization sub-module has not received the indication from the register synchronization module, the register synchronization configuration has been completed, and the subsequent process cannot be executed temporarily.

[0151] S43, determine whether the line start signal and the data validity signal are 1. If they are, execute S41; if not, execute S44.

[0152] The steps from S41 to S43, that is, when the current clock cycle is in the line start period of the current line, it indicates that the transmission of the current line data has started. First, it is necessary to determine the register synchronization signal. After the register synchronization signal is pulled low, then determine whether the line start signal input by DSC is valid. Once it is valid, the hcnt count value of the previous line needs to be cleared.

[0153] S44, determine whether the period to which the current clock cycle belongs is an invalid pixel period. If it is, execute S45; if not, execute S46.

[0154] S45, determine whether hcnt reaches the second pixel point threshold. If it does, execute S48; if not, execute S47.

[0155] When the period to which the current clock cycle belongs is an invalid pixel period, it indicates that the data of invalid pixel points is being transmitted at this time. No valid data is transmitted during this period, but hcnt still needs to continue counting so as to correctly indicate the information of the current row during data transmission. However, during this period, it cannot be directly judged according to the data validity signal because the data validity signal is in an invalid state during this period. At this time, the second pixel threshold pre-configured in the horizontal synchronization sub-module needs to be used as the hcnt counter threshold condition. That is, if the pixel cumulative value hcnt is less than the second pixel threshold, update the pixel cumulative value hcnt = hcnt + 1; if the pixel cumulative value hcnt is equal to the second pixel threshold, perform a reset operation on hcnt.

[0156] S46, determine whether hcnt reaches the first pixel threshold. If so, execute S41; if not, execute S47.

[0157] When the period to which the current clock cycle belongs is a valid pixel period, it indicates that the data of valid pixel points is being transmitted at this time and it is in the period of valid data. Therefore, determine whether the pixel cumulative value hcnt is less than the first pixel threshold. If so, update the pixel cumulative value hcnt = hcnt + 1; if not, the hcnt counter latches the current value.

[0158] S47, increment hcnt by 1.

[0159] S48, latch the hcnt counter.

[0160] In the above embodiments, the process of the horizontal synchronization sub-module determining the pixel cumulative value is introduced. Next, the process of the vertical synchronization sub-module determining the row cumulative value is introduced.

[0161] The vertical synchronization sub-module 201 initializes the row cumulative value to a second value according to the frame start signal. The second value is the number of rows between the first row of the current frame and the first valid row indicated by the row start signal, and the second value is a pre-set value. The frame start signal can indicate the start of the current frame. At the moment when the current frame starts, until the data validity signal indicates the start of the transmission of valid data, there are a second number of invalid rows. Therefore, the row cumulative value can be initialized to the second value, and the second value is greater than or equal to 0. For the current frame, at the moment when the data of this frame starts to be transmitted, the row cumulative value is initialized to the second value.

[0162] Then, the vertical synchronization sub-module 201 determines the period to which the current clock cycle belongs in the period corresponding to the current frame according to the frame start signal, the row start signal, and the data validity signal, where the period corresponding to the current frame includes the frame start period, the valid row period, or the invalid row period of the current frame.

[0163] The frame start period is the period between the start time of the current frame and the start time of the first valid line in the current frame. The valid line period is the period between the start time of the first valid line and the end time of the last valid line in the current frame. The invalid line period is the period between the end time of the last valid line and the end time of the current frame.

[0164] The division of the three periods can be referred to Figure 5 for the introduction.

[0165] Figure 5 is the schematic diagram of the period division corresponding to the current frame provided by the embodiment of the present application. As Figure 5 shown, taking the current frame including 10 lines as an example, in Figure 5 these 10 lines are marked. Each line includes multiple pixel points. Since the transmission of each pixel point requires one clock cycle, the data transmission of each line requires multiple clock cycles.

[0166] As Figure 5 shown, the frame start signal can indicate the start time of the first line in the current frame, that is, t5, and the end time of the tenth line in the current frame, that is, t8. The data validity signal can indicate the start time and end time of the valid data in the current frame, that is, Figure 5 t6 and t7 in. Then, the period between t5 and t6 belongs to the frame start period, the period between t6 and t7 belongs to the valid line period, and the period between t7 and t8 belongs to the invalid line period.

[0167] It should be noted that the number of lines included between t5 and t6 is called vstart, which represents the distance between the first line and the first valid line in the current frame. In the embodiment of the present application, the value of vstart is a fixed value, that is, the second numerical value. In Figure 5 it, the second numerical value is set to 1, that is to say, in the current frame, the first 1 line is an invalid line, and the valid lines start from the second line.

[0168] The vertical synchronization sub-module 201 can determine the period to which the current clock cycle belongs according to the frame start signal, the line start signal and the data validity signal. Since the lines transmitted in the frame start period are invalid lines, the lines transmitted in this period are not counted, and only the valid line period and the invalid line period are counted.

[0169] Specifically, when the period to which the current clock cycle belongs is the frame start period, it indicates that the transmission of the valid frame has started. Then, the vertical synchronization sub-module 201 judges whether the data validity signal is in the valid state under the current clock cycle. If so, the line cumulative value is initialized to zero.

[0170] When the period to which the current clock cycle belongs is an active line period and the line cumulative value is less than a preset line threshold, update the line cumulative value. The updated line cumulative value is the previous line cumulative value plus one.

[0171] When the period to which the current clock cycle belongs is an inactive line period and the pixel cumulative value is equal to the first pixel threshold, update the line cumulative value. The updated line cumulative value is the previous line cumulative value plus one.

[0172] In a possible implementation, a line counter vcnt can be set to record the line cumulative value. The following combines Figure 6 to introduce this process.

[0173] Figure 6 is a schematic flow diagram for determining the line cumulative value provided by an embodiment of this application. As Figure 6 shown, it includes:

[0174] S601, reset vcnt.

[0175] The process of resetting vcnt is to reset the value of vcnt to the second value vstart. For a new frame, that is, after the frame start signal indicates a new frame, reset vcnt to the first value vstart.

[0176] S602, determine whether the register synchronization signal is 1. If so, execute S608; if not, execute S603.

[0177] When the register synchronization signal is 0, it means that the vertical synchronization sub-module has received the indication from the register synchronization module and the register synchronization configuration has been completed, and the subsequent process can be executed; when the register synchronization signal is 1, it means that the vertical synchronization sub-module has not received the indication from the register synchronization module and the register synchronization configuration has been completed, and the subsequent process cannot be executed temporarily.

[0178] S603, determine whether the frame start signal and the data validity signal are 1. If so, execute S604; if not, execute S606.

[0179] The steps from S601 to S603, that is, when the current clock cycle is in the frame start period of the current frame, it indicates that the transmission of frame data has started at this time. First, it is necessary to determine the register synchronization signal. After the register synchronization signal is pulled low, then determine whether the frame start signal input by DSC is valid. Once it is valid, the vcnt count value of the previous line needs to be cleared.

[0180] S604, determine whether vcnt reaches the preset line threshold. If so, execute S608; if not, execute S605.

[0181] The preset line threshold can be determined according to the maximum number of pixel points supported by the HDMI video format. After determining the maximum number of pixel points supported by the HDMI video format, divide the maximum number of pixel points supported by the HDMI video format by the number of pixel points included in each line to obtain the preset line threshold.

[0182] When the period to which the current clock cycle belongs is an active line period, it indicates that the data being transmitted at this time is active line data and is in the period of valid data. Therefore, it is judged whether the line cumulative value vcnt is less than the preset line threshold. If so, update the line cumulative value vcnt = vcnt + 1. If not, the vcnt counter latches the current value.

[0183] S605, increment vcnt by 1.

[0184] S606, judge whether the period to which the current clock cycle belongs is an inactive line period. If so, execute S607. If not, execute S601.

[0185] S607, judge whether hcnt reaches the first pixel point threshold. If so, execute S604. If not, execute S605.

[0186] When the period to which the current clock cycle belongs is an inactive line period, it indicates that the data being transmitted at this time is inactive line data and no valid data is transmitted during this period. However, it cannot be triggered based on the line start signal and the frame start signal, but needs to be judged according to the pixel point counter hcnt. That is, if the pixel point cumulative value hcnt is equal to the first pixel point threshold, it indicates the end of an inactive line, and update the line cumulative value vcnt = vcnt + 1; if the pixel point cumulative value hcnt is less than the first pixel point threshold, it indicates that an inactive line has not ended, and at this time, vcnt is not updated.

[0187] S608, latch the vcnt counter.

[0188] After the vertical synchronization sub-module obtains the line cumulative value, it sends the line cumulative value to the indication signal sub-module; after the horizontal synchronization sub-module obtains the pixel point cumulative value, it sends the pixel point cumulative value to the indication signal sub-module, and the indication signal sub-module generates a synchronization signal according to the line cumulative value and the pixel point cumulative value. The following will introduce this process.

[0189] The indication signal sub-module can generate a frame synchronization signal according to the line cumulative value and the second value. The second value is the number of lines between the first line of the current frame and the first effective line indicated by the line start signal, that is, vstart in the above embodiment.

[0190] Specifically, when the line cumulative value is less than or equal to (vstart - 1), it indicates that invalid lines are still being transmitted in the current clock cycle. At this time, the frame synchronization signal is in the high state, used to indicate that invalid lines are being transmitted currently; when the line cumulative value is greater than (vstart - 1), it indicates that valid lines are being transmitted in the current clock cycle. At this time, the frame synchronization signal is in the low state, used to indicate that valid lines are being transmitted currently. For each frame in the video stream data, this operation is cycled to output the frame synchronization signal.

[0191] The indication signal sub-module can generate a line synchronization signal according to the pixel cumulative value and the first value. The first value is the number of pixels between the first pixel of the current line and the first valid pixel of the current line, that is, hstart in the above embodiment.

[0192] Specifically, when the pixel cumulative value is less than or equal to (hstart - 1), it indicates that invalid pixels are still being transmitted in the current clock cycle. At this time, the line synchronization signal is in the high state, used to indicate that invalid pixels are being transmitted currently; when the pixel cumulative value is greater than (hstart - 1), it indicates that valid pixels are being transmitted in the current clock cycle. At this time, the frame synchronization signal is in the low state, used to indicate that valid pixels are being transmitted currently. For each line in the current frame, this operation is cycled to output the line synchronization signal.

[0193] Furthermore, the indication signal sub-module can also generate a valid data indication signal according to the line cumulative value and the pixel cumulative value. The synchronization signals output by the indication signal sub-module include the frame synchronization signal, the line synchronization signal, and the valid data indication signal.

[0194] Specifically, the indication signal sub-module determines the time period corresponding to the line cumulative value during the time period corresponding to the current frame. The time period corresponding to the line cumulative value is a valid line time period or an invalid line time period.

[0195] Then, a valid data indication signal is generated according to the time period corresponding to the line cumulative value and the pixel cumulative value.

[0196] Among them, when the time period corresponding to the line cumulative value is a valid line time period, and the pixel cumulative value is greater than the third value, the valid data indication signal is in a valid state. The third value is the first value minus one; when the time period corresponding to the line cumulative value is an invalid line time period, and / or when the pixel cumulative value is less than or equal to the third value, the valid data indication signal is in an invalid state.

[0197] The following introduces the specific processing process of the data cache module 12 for the timing signal and the synchronization signal in conjunction with the accompanying drawings.

[0198] The data cache module 12 is mainly used to cache the data output by the DSC and reorganize the data according to the protocol standard to meet the requirements of aligning the synchronization signal and the data signal.

[0199] As Figure 2 shown, the data cache module 12 includes a write enable control sub-module 211, a write address control sub-module 212, a reorganization sub-module 213, a write data control sub-module 214, a cache sub-module 215, a read enable control sub-module 216, a read address control sub-module 217, and a read data control sub-module 218. The write enable control sub-module 211, the write address control sub-module 212, the reorganization sub-module 213, and the write data control sub-module 214 jointly perform reorganization and caching processing on the video stream data based on the timing signal to obtain valid video stream data and cache it in the cache sub-module 215. The read enable control sub-module 216, the read address control sub-module 217, and the read data control sub-module 218 jointly output the valid video stream data cached in the cache sub-module 215 based on the synchronization signal.

[0200] The reorganization sub-module 213 is used to reorganize the valid video stream data according to the target data format matched by the receiving device to obtain the valid video stream data in the target data format.

[0201] Figure 7 Schematic diagram of the classification and arrangement of DSC output data provided by an embodiment of the present application Figure 1 , Figure 8 Schematic diagram of the classification and arrangement of DSC output data provided by an embodiment of the present application Figure 2 , such as Figure 7 and Figure 8 shown, where Figure 7 takes the DSC output data of 128 bits as an example to illustrate the components included in each pixel point, such as the luminance component and the chrominance components. The chrominance components include the blue chrominance component (Cb) and the red chrominance component (Cr), etc. In Figure 7 , each component is 16 bits.

[0202] Since most video transmission systems' DSCs support color depths of 8, 10, or 12 bits, it is unnecessary to transmit invalid bits. The extra bits need to be truncated to save bandwidth. Also, since each luminance component or chrominance component is at most 12 bits, and a pixel point can accommodate at most 6 components (including 4 luminance components and 2 chrominance components), the final effective data bandwidth is 12 * 6 = 72 bits. As Figure 8 shown, relative Figure 7 to Figure 8 , after removing the invalid bits, the data arrangement of the pixel points in the valid video stream data can be obtained. In Figure 7The arrangement in it can save storage space

[0203] The cache sub-module 215 can, for example, use a static random-access memory (SRAM) with a depth of 2048 and a width of 72 to store data. Before writing the video stream data output by the DSC into the SRAM, the data needs to be reorganized according to the protocol standard and the data format required by the display device.

[0204] Common data formats include, for example, DSC422 and DSC444 / 420. DSC422, DSC444, and DSC420 are all video coding formats. DSC444 coding is lossless, DSC422 coding is highly lossless with a one-third color loss, and DSC420 is highly lossless with a half color distortion. The following will introduce with these data formats as examples.

[0205] Due to the different color component arrangements of DSC 422 and DSC 444 / 420, data rearrangement needs to be performed according to the specific mode. For example, in the DSC 422 data format, each pixel contains 4 luminance components, 2 red difference components, and 2 blue difference components; while in the DSC 420 data format, each pixel contains 4 luminance components, 2 blue difference components or 2 red difference components. In addition, when DSC outputs data in the 420 data format, it is configured to output in 2-pixel mode, that is, 128-bit data contains 2 pixels; when outputting 422, it is configured to output in 1-pixel mode, that is, 128-bit data contains 1 pixel.

[0206] To meet the requirements, the data is reorganized. Figure 9 Schematic diagram of data reorganization provided for the embodiments of this application Figure 1 , as Figure 9 shown, the data format is DSC 444 / 420, and each pixel includes 4 luminance components (i.e., Figure 9 the component "Y0" with a storage address from 15 bits to 31 bits, the component "Y1" with a storage address from 31 bits to 47 bits, the component "Y2" with a storage address from 79 bits to 95 bits, and the component "Y3" with a storage address from 95 bits to 111 bits in Figure 9 ), and, 2 blue difference components or 2 red difference components (i.e., Figure 9 the component "Cb or Cr" with a storage address from 0 bits to 15 bits, and the component "Cb or Cr" with a storage address from 64 bits to 79 bits in

[0207] It can be seen from Figure 9 that the storage space required for each component is 16 bits.

[0207] For the above data reorganization, the reorganized data can be seen in Figure 9As shown. For each pixel, it includes 4 luminance components (i.e., Figure 9 the component "Y0" with storage address from 11 bits to 23 bits, the component "Y1" with storage address from 23 bits to 35 bits, the component "0" with storage address from 35 bits to 47 bits, the component "Y2" with storage address from 59 bits to 71 bits, the component "Y3" with storage address from 71 bits to 83 bits, and the component "0" with storage address from 83 bits to 95 bits in Figure 9 ), and 2 blue-difference components or 2 red-difference components (i.e., Figure 9 the component "Cb or Cr" with storage address from 0 bits to 11 bits, and the component "Cb or Cr" with storage address from 48 bits to 59 bits in

[0208] Figure 10 ). As can be seen from Figure 2 , the storage space required for each component is 12 bits. Figure 10 As shown in

[0209] , the data format is DSC422, and each pixel includes 4 luminance components, 2 blue-difference components, and 2 red-difference components. Figure 10 DSC 422 is different from other modes. In this mode, only low bits are used to transmit valid component information. Therefore, the data needs to be reorganized as shown in

[0210] the example, and the valid component information of high bits is removed. Figure 10 After reorganizing the above data, the reorganized data can be seen in Figure 10 . As can be seen from

[0211] The write address control sub-module 212, when detecting the frame start signal, indicates the start of a frame. At this time, the address information recorded in the previous frame needs to be cleared. Then, according to the line start signal, it is judged whether the address exceeds the depth of the cache sub-module 215 during the valid line period. If it exceeds the depth of the cache sub-module 215, the address is forced to be cleared to 0; otherwise, the address is incremented.

[0212] The write enable control sub-module 211 is used to store the valid video stream data in the target data format into the cache sub-module 215 according to the frame start signal and the line start signal when the data validity signal is in the valid state. The generation of the write enable signal needs to use the data validity signal as the enable judgment. Once the data validity signal is in the valid state, it indicates that the data is valid at this time, and then the write enable becomes valid, indicating that the data output by DSC can be written into the cache sub-module 215.

[0213] The write data control sub-module 214, when the write enable is valid, first determines whether the video stream data output by the DSC is in the 422 data format. If so, the video stream data is reorganized according to the arrangement of the 422 data format, and then the reorganized data is written into the cache sub-module 215, and the address of the write address control sub-module 212 is incremented accordingly. If the video stream data output by the DSC is in other data formats, the video stream data is reorganized according to the 420 / 444 arrangement, and then the reorganized data is written into the cache sub-module 215, and the address of the write address control sub-module 212 is incremented accordingly.

[0214] The read address control sub-module 217 is used to clear the read address space. Since it is necessary to ensure the consistency of the data signal and the synchronization signal, the generated frame synchronization signal is used as a judgment condition at this time. Once the frame synchronization signal is in the valid state, it indicates that the synchronization signal has been generated at this time, and the read address space needs to be cleared to provide a clean address for the subsequent valid data lines. When the valid data indication signal is detected, it indicates that the valid data has started. At this time, the read address needs to be incremented. Once the read address approaches the depth of the cache sub-module 215, the read address is forced to be cleared to 0. Since it is a synchronous operation and the write address is about one line later than the read address, the phenomenon of the cache sub-module 215 being full or empty will not occur.

[0215] The read enable control sub-module 216 is used to output the valid video stream data in the target data format from the cache sub-module according to the frame synchronization signal and the line synchronization signal when the valid data indication signal is in the valid state. The read enable control sub-module 216 controls the output of the valid video stream data through the read enable signal, and the generation of the read enable signal needs to use the generated valid data indication signal as the enable judgment. If the valid data indication signal is in the valid state, the data in the cache sub-module 215 is immediately read out, indicating that the synchronization signal and the data signal are aligned at this time, and the data output at this time is valid data.

[0216] The read data control sub-module 218 reads out the data of the cache sub-module 215 when it detects that the generated data validity signal is in the valid state, and the read address is incremented accordingly.

[0217] In summary, for the video stream data output by the DSC in the solution of the embodiment of the present application, since the video stream data is reorganized and cached based on the timing information indicated by the timing signal, and the synchronization signal generated after the timing signal is retimed by the synchronization information generation module indicates the output of the valid video stream data, the strict synchronization between the synchronization signal and the valid video stream data can be ensured, so that the valid video stream data can be correctly input into the downstream display device, ensuring the correct display of the display device.

[0218] Figure 11 This is a schematic flowchart of the video stream compression synchronization control method provided by the embodiments of the present application. As Figure 11 shown, it includes:

[0219] S111, receiving video stream data and a timing signal for the video stream data;

[0220] S112, performing retiming processing on the timing signal to generate a synchronization signal;

[0221] S113, performing reorganization and caching processing on the video stream data according to the timing signal to obtain valid video stream data;

[0222] S114, outputting the valid video stream data according to the synchronization signal.

[0223] In a possible implementation manner, the timing signal includes a frame start signal, a line start signal, and a data validity signal. The performing retiming processing on the timing signal to generate a synchronization signal includes:

[0224] In the current clock cycle, according to the frame start signal, the line start signal, and the data validity signal, determining the line cumulative value of the current frame indicated by the frame start signal in the video stream data;

[0225] In the current clock cycle, according to the line start signal and the data validity signal, determining the pixel cumulative value in the current line indicated by the line start signal in the current frame;

[0226] Generating the synchronization signal according to the line cumulative value and the pixel cumulative value.

[0227] In a possible implementation manner, the determining the pixel cumulative value in the current line indicated by the line start signal in the current frame according to the line start signal and the data validity signal includes:

[0228] According to the line start signal, initializing the pixel cumulative value to a first value, where the first value is the number of pixels between the first pixel of the current line and the first valid pixel of the current line;

[0229] According to the line start signal and the data validity signal, in the period corresponding to the current line, determining the period to which the current clock cycle belongs. The period corresponding to the current line includes the line start period, the valid pixel period, and the invalid pixel period of the current line;

[0230] When the period to which the current clock cycle belongs is the valid pixel period and the pixel point cumulative value is less than the first pixel point threshold, update the pixel point cumulative value, and the updated pixel point cumulative value is the pixel point cumulative value before update plus one;

[0231] When the period to which the current clock cycle belongs is the invalid pixel period and the pixel point cumulative value is less than the second pixel point threshold, update the pixel point cumulative value, and the updated pixel point cumulative value is the pixel point cumulative value before update plus one.

[0232] In a possible implementation manner, the determining the line cumulative value of the current frame indicated by the frame start signal in the video stream data according to the frame start signal, the line start signal, and the data validity signal includes:

[0233] Initialize the line cumulative value to a second value according to the frame start signal, where the second value is the number of lines between the first line of the current frame and the first valid line indicated by the line start signal;

[0234] Determine the period to which the current clock cycle belongs in the period corresponding to the current frame according to the frame start signal, the line start signal, and the data validity signal, where the period corresponding to the current frame includes the frame start period, the valid line period, or the invalid line period of the current frame;

[0235] When the period to which the current clock cycle belongs is the valid line period and the line cumulative value is less than the preset line threshold, update the line cumulative value, and the updated line cumulative value is the line cumulative value before update plus one;

[0236] When the period to which the current clock cycle belongs is the invalid line period and the pixel point cumulative value is equal to the first pixel point threshold, update the line cumulative value, and the updated line cumulative value is the line cumulative value before update plus one.

[0237] In a possible implementation manner, the generating the synchronization signal according to the line cumulative value and the pixel point cumulative value includes:

[0238] Generate a frame synchronization signal according to the line cumulative value and the second value;

[0239] Generate a line synchronization signal according to the pixel point cumulative value and the first value;

[0240] Generate a valid data indication signal according to the line cumulative value and the pixel point cumulative value, and the synchronization signal includes the frame synchronization signal, the line synchronization signal, and the valid data indication signal.

[0241] In a possible implementation manner, generating an effective data indication signal according to the line cumulative value and the pixel point cumulative value includes:

[0242] In a time period corresponding to the current frame, determining a time period corresponding to the line cumulative value, where the time period corresponding to the line cumulative value is the effective line time period or the invalid line time period;

[0243] Generating the effective data indication signal according to the time period corresponding to the line cumulative value and the pixel point cumulative value;

[0244] Wherein, when the time period corresponding to the line cumulative value is the effective line time period and the pixel point cumulative value is greater than a third value, the effective data indication signal is in an effective state, and the third value is the first value minus one;

[0245] When the time period corresponding to the line cumulative value is the invalid line time period, and / or when the pixel point cumulative value is less than or equal to the third value, the effective data indication signal is in an invalid state.

[0246] In a possible implementation manner, outputting the effective video stream data according to the synchronization signal includes:

[0247] Reorganizing the effective video stream data according to a target data format matched by a receiving device to obtain the effective video stream data in the target data format;

[0248] When the data validity signal is in an effective state, storing the effective video stream data in the target data format into the cache sub-module according to the frame start signal and the line start signal;

[0249] When the effective data indication signal is in an effective state, outputting the effective video stream data in the target data format from the cache sub-module according to the frame synchronization signal and the line synchronization signal.

[0250] In a possible implementation manner, the method further includes:

[0251] Performing synchronous configuration on registers in the synchronization information generation module and the data cache module;

[0252] After the register synchronous configuration is completed, sending a register synchronization signal to the synchronization information generation module and the data cache module;

[0253] The retiming process of the timing signal to generate a synchronization signal includes:

[0254] After receiving the register synchronization signal, perform retiming processing on the timing signal to generate the synchronization signal;

[0255] The reorganizing and caching the video stream data according to the timing signal to obtain valid video stream data includes:

[0256] After receiving the register synchronization signal, reorganize and cache the video stream data according to the timing signal to obtain the valid video stream data.

[0257] Figure 12 An example of the physical structure diagram of an electronic device is shown as Figure 12 As shown, the electronic device may include: a processor 1210, a communication interface 1220, a memory 1230, and a communication bus 1240. Among them, the processor 1210, the communication interface 1220, and the memory 1230 complete communication with each other through the communication bus 1240. The processor 1210 can call the logical instructions in the memory 1230 to execute the video stream compression synchronization control method, which includes: receiving video stream data and a timing signal for the video stream data; performing retiming processing on the timing signal to generate a synchronization signal; reorganizing and caching the video stream data according to the timing signal to obtain valid video stream data; outputting the valid video stream data according to the synchronization signal.

[0258] In addition, when the logical instructions in the above-mentioned memory 1230 are implemented in the form of software functional units and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. And the aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0259] In another aspect, the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the video stream compression synchronization control method provided by the above-mentioned various methods. The method includes: receiving video stream data and a timing signal for the video stream data; performing retiming processing on the timing signal to generate a synchronization signal; performing reorganization and caching processing on the video stream data according to the timing signal to obtain effective video stream data; and outputting the effective video stream data according to the synchronization signal.

[0260] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative efforts.

[0261] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0262] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present application.

Claims

1. A video stream compression synchronization control circuit, characterized in that, it includes a synchronization information generation module and a data cache module, where: The synchronization information generation module is used to receive a timing signal for video stream data; perform retiming processing on the timing signal to generate a synchronization signal; and send the synchronization signal to the data cache module; The data cache module is used to receive the timing signal and the video stream data; perform reorganization and caching processing on the video stream data according to the timing signal to obtain valid video stream data; and output the valid video stream data according to the synchronization signal; Specifically, the data cache module is used to: remove invalid bit data in the video stream data according to the target data format matched by the receiving device and the timing information indicated by the timing signal to obtain valid video stream data in the target data format; The timing signal includes a frame start signal, a line start signal, and a data validity signal, and the synchronization information generation module includes a vertical synchronization sub-module, a horizontal synchronization sub-module, and an indication signal sub-module; where: The vertical synchronization sub-module is used to determine, in the video stream data, the line cumulative value of the current frame indicated by the frame start signal according to the frame start signal, the line start signal, and the data validity signal in the current clock cycle; The horizontal synchronization sub-module is used to determine, in the current frame, the pixel cumulative value in the current line indicated by the line start signal according to the line start signal and the data validity signal in the current clock cycle; The indication signal sub-module is used to generate the synchronization signal according to the line cumulative value and the pixel cumulative value; Specifically, the indication signal sub-module is used to: Generate a frame synchronization signal according to the line cumulative value and a second value; the second value is obtained by initializing the line cumulative value according to the frame start signal; the second value is the number of lines between the first line of the current frame and the first valid line indicated by the line start signal; Generate a line synchronization signal according to the pixel cumulative value and a first value; the first value is obtained by initializing the pixel cumulative value according to the line start signal; the first value is the number of pixels between the first pixel of the current line and the first valid pixel of the current line; Generate a valid data indication signal according to the line cumulative value and the pixel cumulative value, and the synchronization signal includes the frame synchronization signal, the line synchronization signal, and the valid data indication signal.

2. The video stream compression synchronization control circuit according to claim 1, characterized in that, Specifically, the horizontal synchronization sub-module is used to: Determine the time period to which the current clock cycle belongs in the time period corresponding to the current line according to the line start signal and the data validity signal, and the time period corresponding to the current line includes the line start time period, the valid pixel time period, and the invalid pixel time period of the current line; When the period to which the current clock cycle belongs is the valid pixel period and the pixel point cumulative value is less than the first pixel point threshold, update the pixel point cumulative value, and the updated pixel point cumulative value is the pixel point cumulative value before the update plus one; When the period to which the current clock cycle belongs is the invalid pixel period and the pixel point cumulative value is less than the second pixel point threshold, update the pixel point cumulative value, and the updated pixel point cumulative value is the pixel point cumulative value before the update plus one.

3. The video stream compression synchronization control circuit according to claim 1 or 2, characterized in that, The vertical synchronization sub-module is specifically used for: According to the frame start signal, the line start signal and the data validity signal, determine the period to which the current clock cycle belongs in the period corresponding to the current frame, where the period corresponding to the current frame includes the frame start period, the valid line period or the invalid line period of the current frame; When the period to which the current clock cycle belongs is the valid line period and the line cumulative value is less than the preset line threshold, update the line cumulative value, and the updated line cumulative value is the line cumulative value before the update plus one; When the period to which the current clock cycle belongs is the invalid line period and the pixel point cumulative value is equal to the first pixel point threshold, update the line cumulative value, and the updated line cumulative value is the line cumulative value before the update plus one.

4. The video stream compression synchronization control circuit according to claim 3, characterized in that, The step of the indication signal sub-module generating the valid data indication signal according to the line cumulative value and the pixel point cumulative value includes: In the period corresponding to the current frame, determine the period corresponding to the line cumulative value, and the period corresponding to the line cumulative value is the valid line period or the invalid line period; Generate the valid data indication signal according to the period corresponding to the line cumulative value and the pixel point cumulative value; Wherein, when the period corresponding to the line cumulative value is the valid line period and the pixel point cumulative value is greater than the third value, the valid data indication signal is in an effective state, and the third value is the first value minus one; When the period corresponding to the line cumulative value is the invalid line period, and / or when the pixel point cumulative value is less than or equal to the third value, the valid data indication signal is in an invalid state.

5. The video stream compression synchronization control circuit according to claim 1 or 2, characterized in that, The data cache module includes a recombination sub-module, a write enable control sub-module, a cache sub-module and a read enable control sub-module; The recombination sub-module is used to recombine the valid video stream data according to the target data format matched by the receiving device to obtain the valid video stream data in the target data format; The write enable control sub-module is used to store the valid video stream data in the target data format into the cache sub-module according to the frame start signal and the line start signal when the data validity signal is in an effective state; The read enable control sub-module is configured to output valid video stream data in the target data format from the buffer sub-module according to the frame synchronization signal and the line synchronization signal when the valid data indication signal is in an active state.

6. The video stream compression synchronization control circuit according to claim 1 or 2, wherein, it further includes a register synchronization module, and the register synchronization module is configured to: perform synchronous configuration on the registers in the synchronization information generation module and the data buffer module; after the register synchronous configuration is completed, send a register synchronization signal to the synchronization information generation module and the data buffer module; The step of the synchronization information generation module performing retiming processing on the timing signal to generate a synchronization signal includes: after receiving the register synchronization signal, performing retiming processing on the timing signal to generate the synchronization signal; The step of the data buffer module performing recombination and caching processing on the video stream data according to the timing signal to obtain valid video stream data includes: after receiving the register synchronization signal, performing recombination and caching processing on the video stream data according to the timing signal to obtain the valid video stream data.

7. A video stream compression synchronization control method, wherein, applied to the video stream compression synchronization control circuit according to any one of claims 1-6, the method includes: receiving video stream data and a timing signal for the video stream data; performing retiming processing on the timing signal to generate a synchronization signal; performing recombination and caching processing on the video stream data according to the timing signal to obtain valid video stream data; outputting the valid video stream data according to the synchronization signal.

8. An electronic device, wherein, it includes the video stream compression synchronization control circuit according to any one of claims 1-6.

9. A computer-readable storage medium, on which a computer program is stored, wherein, when the computer program is executed by a processor, it implements the video stream compression synchronization control method according to claim 7.

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