Instruction scheduling method and device, and electronic equipment

Abstract

The present disclosure provides an instruction scheduling method and device, and an electronic device. The instruction scheduling method is applied to a graphics processor, and the method includes: retrieving a first instruction; checking whether the first instruction meets a scheduling condition, and the scheduling condition includes: the first instruction does not depend on other unexecuted instructions; if the first instruction meets the scheduling condition, scheduling the first instruction; executing the first instruction, and broadcasting the execution information of the first instruction.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of computer technology, and in particular to an instruction scheduling method and device, and an electronic device. Background Art

[0002] Graphics Processing Unit (GPU), also known as display core, visual processor, display chip, is a microprocessor that specializes in performing image and graphics related calculations on personal computers, workstations, game consoles and some mobile devices (such as tablets, smart phones, etc.).

[0003] In the related technology, in some GPU architectures (for example, SIMD (Single Instruction Multiple Data), SIMT (Single Instruction Multiple Threads), etc.), the instruction scheduling process includes a series of serial operations such as instruction scheduling, instruction fetching, decoding, and checking, so that instruction scheduling is completely coupled with decoding, checking, etc. At this time, if the scheduled instruction is in a missing state (miss state) or the dependency relationship is not resolved, it cannot be executed normally, and then it needs to be re-scheduled, which not only wastes the transmission bandwidth, but also reduces the effective scheduling, thereby reducing the execution efficiency of the instruction. Summary of the invention

[0004] Embodiments of the present disclosure provide an instruction scheduling method and device, and an electronic device.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] The present disclosure provides an instruction scheduling method, which is applied to a graphics processor. The method includes:

[0007] Retrieve the first instruction;

[0008] Checking whether the first instruction meets a scheduling condition, wherein the scheduling condition includes: the first instruction does not depend on other unexecuted instructions;

[0009] If the first instruction meets the scheduling condition, scheduling the first instruction;

[0010] The first instruction is executed, and execution information of the first instruction is broadcasted.

[0011] The embodiment of the present disclosure provides an instruction scheduling device, which is applied to a graphics processor, and includes an instruction fetch unit, a check unit, an instruction scheduling unit, and an execution unit, wherein:

[0012] The instruction fetch unit is used to fetch the first instruction;

[0013] The checking unit is used to check whether the first instruction meets the scheduling condition, obtain a checking result, and transmit the checking result to the instruction scheduling unit; wherein the scheduling condition includes that the first instruction does not depend on other unexecuted instructions;

[0014] The instruction scheduling unit is configured to schedule the first instruction to the execution unit if the checking result indicates that the first instruction meets the scheduling condition;

[0015] The execution unit is used to execute the first instruction and broadcast execution information of the first instruction.

[0016] An embodiment of the present disclosure provides an electronic device, comprising the instruction scheduling device described above.

[0017] In the disclosed embodiment, the first instruction is retrieved; the first instruction is checked to see if it meets the scheduling conditions, and the scheduling conditions include: the first instruction is not dependent on other unexecuted instructions; if the first instruction meets the scheduling conditions, the first instruction is scheduled; the first instruction is executed, and the execution information of the first instruction is broadcast. In this way, on the one hand, before the instruction is scheduled, it is checked whether the first instruction meets the scheduling conditions, thereby achieving the decoupling between instruction scheduling and instruction fetching, and instruction scheduling and checking; on the other hand, the instruction is scheduled only when it is determined that the instruction can be scheduled, so that the scheduled instruction can be executed, which not only reduces the possibility of wasting the instruction transmission bandwidth, but also improves the effectiveness of instruction scheduling, thereby improving the execution efficiency of the instruction.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0020] Figure 1A An interactive schematic diagram of instruction scheduling in the related art;

[0021] Figure 1B A schematic diagram of an implementation flow of an instruction scheduling method provided in an embodiment of the present disclosure;

[0022] Figure 2A A schematic diagram of the structure of an instruction scheduling device provided in an embodiment of the present disclosure;

[0023] Figure 2B A schematic diagram of the structure of an instruction scheduling device provided in an embodiment of the present disclosure;

[0024] Figure 2C A schematic diagram of the structure of an instruction scheduling device provided in an embodiment of the present disclosure;

[0025] Figure 3 A hardware entity schematic diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0027] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0030] In a GPU with SIMD architecture, multiple threads form a group, and multiple groups are scheduled to increase parallelism and hide execution latency. Multiple threads in a group share the same instruction program address, and scheduling between groups is actually scheduling between instructions.

[0031] Figure 1A A schematic diagram of a scheduling process of an instruction in the related art is shown in FIG. Figure 1A As shown, the scheduling process includes: an instruction scheduling unit 101, an instruction fetch unit 102, a decoding unit 103, a checking unit 104, and an execution unit 105. During implementation:

[0032] The instruction scheduling unit 101 selects a thread group to be executed from multiple thread groups, and the thread group carries the program address for instruction fetching;

[0033] Before the instruction fetch unit 102 fetches an instruction, a hit-miss test is first performed. If a hit is found, it indicates that the instruction already exists in the storage unit 106, and the instruction is retrieved from the storage 106 and sent to the decoding unit 103; if a miss is found, the miss is transmitted to the checking unit 104 through the decoding unit 103, and the instruction fetch continues to be performed in the next level of storage;

[0034] The decoding unit 103 decodes the instruction to generate decoding information, and sends the decoding information to the checking unit 104;

[0035] The inspection unit 104 makes a judgment based on the decoding information and the instruction status. If the instruction is in the hit status and there is no dependency relationship between the instruction and other instructions, it is sent to the execution unit 105 for processing; if the instruction is in the miss status, or there is a dependency relationship between the instruction and other instructions, the instruction scheduling unit 101 is notified to record it, and waits for the instruction to be stored in the storage unit 106, or the dependency relationship is resolved before rescheduling.

[0036] Then, since instruction scheduling, instruction fetching, decoding, checking, etc. are a series of serial operations, instruction scheduling is completely coupled with decoding, checking, etc. If the instruction is missing or the dependency is not resolved, the instruction cannot be normally emitted to the downstream for execution and needs to be rescheduled, which wastes the emission bandwidth and reduces the effective scheduling, thereby reducing the execution efficiency of the instruction.

[0037] The disclosed embodiment provides an instruction scheduling method. On the one hand, before the instruction is scheduled, it is first checked whether the first instruction meets the scheduling conditions, so as to realize the decoupling between instruction scheduling and instruction fetching, and instruction scheduling and checking; on the other hand, the instruction is scheduled only when it is determined that the instruction can be scheduled, so that the scheduled instruction can be executed, which not only reduces the possibility of instruction transmission bandwidth being wasted, but also improves the effectiveness of instruction scheduling, thereby improving the execution efficiency of the instruction. The method provided by the disclosed embodiment can be executed by an electronic device, and the electronic device can be a laptop, a tablet computer, a desktop computer, a set-top box, a mobile device (for example, a mobile phone, a portable music player, a personal digital assistant, a dedicated messaging device, a portable gaming device) and other types of terminals, and can also be implemented as a server. The server can be an independent physical server, or a server cluster or a distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and big data and artificial intelligence platforms.

[0038] Below, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings in the embodiments of the present disclosure.

[0039] Figure 1B A schematic diagram of an implementation flow of an instruction scheduling method provided in an embodiment of the present disclosure is applied to a graphics processor, such as Figure 1B As shown, the method includes steps S11 to S14, wherein:

[0040] Step S11, retrieve the first instruction.

[0041] Here, the graphics processor includes at least an instruction fetch unit and a storage unit. The instruction fetch unit is mainly used to fetch instructions from the storage unit. The first instruction can be any suitable instruction that can be executed.

[0042] At least the first instruction is stored in the storage unit. The storage unit can be any suitable unit that can realize the storage function. For example, a cache memory. In some embodiments, the storage unit has at least one level. For example, a first-level instruction cache L1, a second-level instruction cache L2, etc. Among them, L1 stores instructions frequently accessed by the GPU, and L1 includes at least one cache unit, each cache unit has the same data structure, and the data structure may include but is not limited to a flag bit, a data bit, an extension bit, etc. In some embodiments, the storage unit receives the address of the instruction sent by the instruction fetch unit of the graphics processor, and reads the instruction according to the address of the instruction. In some embodiments, if the state of the first instruction in the first-level instruction cache is a miss state, indicating that the first instruction is not located in the first-level instruction cache, at this time, continue to fetch instructions from the downstream multi-level instruction cache until the first instruction is retrieved; if the state of the first instruction in the first-level instruction cache is a hit state, indicating that the first instruction is already in the first-level instruction cache, the first instruction can be retrieved from the first-level instruction cache.

[0043] In some embodiments, the step S11 includes step S111, wherein:

[0044] Step S111 : performing a hit-miss check in a first-level instruction cache based on the address of the first instruction, and retrieving the first instruction from the first-level instruction cache in response to the address hit.

[0045] Here, the first-level instruction cache stores instructions frequently accessed by the GPU. During implementation, a hit-miss check is performed in the first-level instruction cache according to the address of the first instruction. If the first instruction is already stored in the first-level instruction cache, the result of the hit-miss check is hit. Otherwise, if the first instruction is not stored in the first-level instruction cache, the result of the hit-miss check is miss.

[0046] In some embodiments, the step S11 further includes step S112, wherein:

[0047] Step S112: In response to the address miss, retrieve the first instruction from a downstream multi-level instruction cache.

[0048] Here, the downstream multi-level instruction cache can be at least one level of instruction cache in the storage unit. Since the result of the hit-miss check in the first-level instruction cache is miss, it is necessary to continue to fetch instructions in the next-level instruction cache until the first instruction is retrieved. During implementation, the instruction fetching process in the next-level instruction cache is similar to the instruction fetching process in the first-level instruction cache. In this way, it is ensured that the instruction must exist when it is scheduled, reducing the possibility of missing instructions when specifying scheduling, and improving the effectiveness of instruction scheduling and the execution efficiency of instructions.

[0049] In some embodiments, the graphics processor further includes an instruction scheduling unit. The instruction scheduling unit is used to schedule instructions and translate binary machine codes into operations such as calculations, controls, or data read and write operations that can be recognized by hardware. During implementation, the instruction fetch unit can pass the retrieved first instruction to the instruction scheduling unit for caching. The first instruction can be passed in any suitable manner, such as sending, broadcasting, etc. When the instruction fetch unit is connected to the instruction scheduling unit, the first instruction can be sent to the instruction scheduling unit.

[0050] In some embodiments, the graphics processor further includes a decoding unit. The decoding unit is mainly used to decode the instruction to obtain the dependency information of the instruction. The dependency information of the instruction may include but is not limited to a dependency flag, a dependent flag, etc. Among them, the dependency flag indicates whether the instruction depends on other instructions that have not been executed, and the dependent flag indicates whether the instruction is dependent on other instructions. In some embodiments, the instruction scheduling unit caches the first instruction and passes the first instruction to the decoding unit. The instruction scheduling unit and the decoding unit may be connected or not connected. In the case where the instruction scheduling unit and the decoding unit are not connected, the first instruction is passed to the decoding unit by broadcasting or other means.

[0051] Step S12: Check whether the first instruction meets the scheduling conditions, and the scheduling conditions include: the first instruction does not depend on other unexecuted instructions.

[0052] Here, the graphics processor also includes a checking unit, which is mainly used to check whether the first instruction meets the scheduling condition. In some embodiments, the checking unit determines whether the first instruction meets the scheduling condition based on the dependency relationship of the first instruction. During implementation, if the dependency relationship of the first instruction indicates that the first instruction does not depend on other unexecuted instructions, then the first instruction meets the scheduling condition; if the dependency relationship of the first instruction indicates that the first instruction depends on other unexecuted instructions, then the first instruction does not meet the scheduling condition.

[0053] In some embodiments, the dependency relationship of the first instruction is determined based on the dependency information of the first instruction. During implementation, the decoding unit transmits the dependency information to the checking unit. The decoding unit and the checking unit may be connected or not connected. In the case where the decoding unit and the checking unit are not connected, the dependency information of the first instruction is transmitted to the checking unit by broadcasting or other means.

[0054] Each instruction contains corresponding dependency information. The dependency information may include but is not limited to a dependency flag, a dependent flag, etc. The dependency flag / dependent flag may be empty or not empty. In some embodiments, the dependency flag and the dependent flag may be the same or different. When the dependency flag and the dependent flag are the same, it indicates that the instruction does not depend on other instructions that have not been executed; when the dependent instruction and the dependent instruction are different, if the dependent instruction is empty, then the instruction does not depend on other instructions that have not been executed, and if the dependent instruction is not empty, then the instruction depends on other instructions that have not been executed. During implementation, the dependency flag of the first instruction can be used to determine whether the first instruction depends on other instructions, and the dependent flag of the first instruction can be used to determine whether the first instruction is dependent on other instructions.

[0055] For example, if instruction B depends on instruction A, at this time, A acts as a producer and B acts as a consumer, then the dependent flag of instruction A is the same as the dependent flag of instruction B. For another example, if instruction C does not depend on other unexecuted instructions, then the dependent flag of instruction C can be empty, or the dependent flag and the dependent flag of instruction C can be the same.

[0056] Step S13: If the first instruction meets the scheduling condition, schedule the first instruction.

[0057] Here, the instruction scheduling unit may include a cache part, which is used to cache multiple instructions, so that when an instruction can be scheduled, the instruction is taken out from the cache part and sent to the execution unit. In implementation, the cache part can be any suitable part that can realize the storage function, such as a queue. In this way, caching instructions in the instruction scheduling unit shortens the physical distance between the two parties and reduces the delay time of instruction reading compared to obtaining instructions from the storage unit.

[0058] Step S14: execute the first instruction and broadcast the execution information of the first instruction.

[0059] Here, the graphics processor also includes an execution unit. The execution unit is mainly used to execute instructions. In some embodiments, different execution units can be set accordingly in the GPU for different categories of instructions. The execution unit may include but is not limited to arithmetic units, memory execution units, coprocessors, etc. Among them, the arithmetic unit is used to perform operations according to operands and output operation results. In some embodiments, the arithmetic unit can be any suitable unit capable of performing operations, such as an arithmetic logic unit, an integer processing unit, a vector operation unit, etc. The memory execution unit is used to access the memory according to the instruction to read data in the memory or write specified data to the memory. A coprocessor is a chip used to reduce specific processing tasks of the system microprocessor. In this way, the instruction is read from the instruction scheduling unit and scheduled to the execution unit for execution, ensuring that the instruction can be hit during scheduling, reducing the possibility of the instruction being in a missing state, improving the convenience and effectiveness of instruction fetching, and thus improving the effectiveness of scheduling.

[0060] In some implementations, the number of the execution unit may be at least one.

[0061] The execution information of the first instruction may include but is not limited to a dependent flag, a dependent flag, etc. For example, instruction B depends on instruction A, then after instruction A is executed, the execution information including the dependent flag producer id (x) is broadcast to the checking unit.

[0062] In the embodiments disclosed herein, on the one hand, before instruction scheduling, it is first checked whether the first instruction meets the scheduling conditions, thereby realizing the decoupling between instruction scheduling and instruction fetching, and between instruction scheduling and checking; on the other hand, instructions are scheduled only when it is determined that the instruction can be scheduled, so that the scheduled instruction can definitely be executed, which not only reduces the possibility of wasting instruction issuance bandwidth, but also improves the effectiveness of instruction scheduling, thereby improving the execution efficiency of instructions.

[0063] In some embodiments, the method further comprises steps S15 to S16, wherein:

[0064] Step S15: Decode the first instruction to obtain dependency information of the first instruction.

[0065] Here, the dependency information includes a dependency flag and a dependent flag. During implementation, the decoding unit can decode the first instruction to obtain the dependency information. The dependency flag can be used to determine whether the first instruction depends on other instructions, and the dependent flag can be used to determine whether the first instruction is dependent on other instructions. For example, the dependency information of the first instruction includes producer() and consumer(), that is, the dependency flag and the dependent flag are both empty, indicating that the first instruction neither depends on other instructions nor is dependent on other instructions. For another example, the dependency information includes producer(1) and consumer(), that is, the dependency flag is "1", indicating that the first instruction depends on other instructions, the dependent flag of the instruction is also 1, and the dependent flag is empty, indicating that the first instruction is not dependent on other instructions.

[0066] Step S16: Determine the dependency relationship of the first instruction based on the dependency flag and the dependent flag of the first instruction.

[0067] Here, the dependency relationship indicates whether the first instruction depends on other instructions that have not been executed. In implementation, if the dependency flag and the dependent flag are the same, it indicates that the first instruction does not depend on other instructions that have not been executed; if the dependency flag and the dependent flag are different, the first instruction may depend on other instructions that have not been executed.

[0068] In some embodiments, the step S16 includes step S161, wherein:

[0069] Step S161: When the dependency flag and the dependent flag of the first instruction are the same, determine that the first instruction does not depend on other instructions that have not been executed completely.

[0070] Here, the dependency flag and the dependent flag can be the same and can be empty or not empty. In implementation, if both are empty, it indicates that the first instruction neither depends on other instructions nor is depended on by other instructions; if they are not empty, it indicates that the first instruction depends on itself.

[0071] In some embodiments, the step S16 includes step S162, wherein:

[0072] Step S162: When the dependency flag of the first instruction is empty and the dependent flag is not empty, determine that the first instruction does not depend on other instructions that have not been executed completely.

[0073] Here, the dependency flag is different from the dependent flag. The dependency flag is empty, indicating that the first instruction does not depend on other instructions, and the dependent flag is not empty, indicating that the first instruction is dependent on other instructions.

[0074] In some embodiments, the step S16 includes step S163, wherein:

[0075] Step S163: When the dependency flag of the first instruction is not empty and the dependent flag is different from the dependency flag, determine that the dependency relationship of the first instruction is dependency on other instructions.

[0076] Here, the dependency flag is different from the dependent flag. If the dependency flag is not empty, it indicates that the first instruction depends on other unexecuted instructions, and if the dependent flag is not empty, it indicates that the first instruction is also dependent on other instructions.

[0077] In the disclosed embodiment, the dependency relationship of the instruction is quickly determined through the dependency information of the instruction, which improves the accuracy of the dependency relationship and thus improves the accuracy of scheduling of the first instruction.

[0078] In some embodiments, the method further comprises step S17, wherein:

[0079] Step S17: Determine the target instruction on which the first instruction depends based on the dependency flag of the first instruction.

[0080] Here, the dependent flag of the target instruction is the same as the dependent flag of the first instruction. Since the dependent flag of the first instruction is not empty and the dependent flag is different from the dependent flag, the first instruction depends on other instructions that have not been executed. During implementation, by searching the dependent flags of multiple instructions, if the dependent flag of a certain instruction is the same as the dependent flag of the first instruction, the instruction is used as the target instruction. In some embodiments, the number of the target instruction can be at least one.

[0081] In the disclosed embodiment, the dependent instruction can be quickly determined through the dependency flag of the instruction, thereby improving the accuracy of the dependent instruction.

[0082] In some embodiments, the method further comprises step S18, wherein:

[0083] Step S18: In response to receiving the execution information of the target instruction, releasing the dependency relationship between the first instruction and the target instruction.

[0084] Here, the execution information of the target instruction may include the execution completion information of the target instruction. It may also include a dependent flag of the target instruction, or a dependent flag and a dependent flag, etc. Since the first instruction depends on the target instruction, the dependent flag of the first instruction is the same as the dependent flag of the target instruction.

[0085] After the target instruction is executed, the execution unit may broadcast execution information including at least a dependent flag of the target instruction to the checking unit. The checking unit searches for a dependency flag identical to the dependent flag of the target instruction, and releases the dependency relationship between the target instruction and other instructions. The dependency flag of the other instruction is identical to the dependent flag of the target instruction. During implementation, the other instructions include at least the first instruction.

[0086] In the disclosed embodiment, the dependency between the first instruction and the target instruction is promptly released through the execution information of the target instruction, so that the first instruction can be scheduled normally, thereby improving the integrity and effectiveness of instruction scheduling.

[0087] In some embodiments, the method further comprises step S19, wherein:

[0088] Step S19: broadcast the dependency relationship of the first instruction.

[0089] Here, the checking unit may broadcast the dependency relationship to the instruction scheduling unit in a broadcasting manner, so that the instruction scheduling unit can schedule the first instruction in a timely manner.

[0090] In the disclosed embodiment, the dependency relationship is transmitted by broadcasting, and both parties do not need to establish a communication connection, thereby reducing the occupation of communication resources.

[0091] Based on the above embodiments, the present disclosure provides an instruction scheduling device. Figure 2A A schematic diagram of the structure of an instruction scheduling device provided in an embodiment of the present disclosure is applied to a graphics processor, such as Figure 2A As shown, the instruction scheduling device 20 includes an instruction fetch unit 21, a check unit 22, an instruction scheduling unit 23 and an execution unit 24, wherein:

[0092] The instruction fetch unit 21 is used to fetch the first instruction;

[0093] The checking unit 22 is used to check whether the first instruction meets the scheduling condition, obtain the checking result, and transmit the checking result to the instruction scheduling unit; wherein the scheduling condition includes that the first instruction does not depend on other unexecuted instructions;

[0094] The instruction scheduling unit 23 is used to schedule the first instruction to the execution unit if the checking result indicates that the first instruction meets the scheduling condition;

[0095] The execution unit 24 is configured to execute the first instruction and broadcast execution information of the first instruction.

[0096] Here, the instruction fetch unit 21 is used for instruction fetching. In implementation, when an instruction is executed, it is first necessary to fetch the instruction from the storage unit according to the instruction address stored in the PC (Program Counter), and this process is called "instruction fetching". The storage unit can be located in the graphics processor. The storage unit can be any suitable unit that can implement a storage function. For example, the storage unit is a multi-level instruction cache. In some embodiments, the storage unit receives the instruction address sent by the instruction fetch unit 21, and reads the instruction according to the instruction address. If the state of the first instruction in the first-level instruction cache is a miss state, at this time, continue to fetch instructions in the next-level instruction cache until the first instruction is retrieved.

[0097] In some embodiments, the instruction fetch unit is further used to perform a hit-miss check in a first-level instruction cache based on the address of the first instruction, and retrieve the first instruction from the first-level instruction cache in response to the address hit.

[0098] Here, the first-level instruction cache can cache multiple instructions. During implementation, a hit-miss check is performed in the first-level instruction cache according to the address of the first instruction. If the first instruction has been cached in the first-level instruction cache, then the result of the hit-miss check is hit, otherwise, it is miss.

[0099] In some implementations, the instruction fetch unit is further configured to retrieve the first instruction from a downstream multi-level instruction cache in response to the address miss.

[0100] Here, the downstream multi-level instruction cache refers to at least one level of instruction cache in the storage unit. When the first instruction is not cached in the first level instruction cache, it is necessary to continue to fetch instructions from the downstream multi-level instruction cache until the first instruction is retrieved. In implementation, the instruction fetching process in the next level instruction cache is similar to the instruction fetching process in the first level instruction cache.

[0101] In some embodiments, the device further includes an instruction fetch scheduling unit; the instruction fetch scheduling unit is used to determine a target thread group from at least one thread group, and the instruction fetch request of the target thread group includes the address of the first instruction.

[0102] Here, the instruction fetch scheduling unit is used for scheduling instruction fetches. During implementation, the instruction fetch scheduling unit is connected to the instruction fetch unit, so that the address of the instruction is sent to the instruction fetch unit, so that the instruction fetch unit can fetch the first instruction from the storage unit.

[0103] The graphics processor includes at least one thread group. During implementation, multiple threads are first divided into multiple thread groups, and the same thread group will be assigned to the same execution unit for execution. Different thread groups can be executed in the same execution unit or in different execution units.

[0104] In some implementations, each thread group has a program counter (PC) that records the address of the next instruction to be executed in the thread group, i.e., the instruction fetch address. The value in the program counter is used to indicate the location of the next instruction in the memory. When an instruction is fetched, the value in the PC will automatically increase. After the instruction is executed, the address of the next instruction is obtained from the PC.

[0105] The target thread group may be determined in any appropriate manner, such as randomly, in a specified order, etc.

[0106] During implementation, since multiple thread groups may initiate instruction fetch requests to the instruction fetch scheduling unit at the same time, the instruction fetch scheduling unit will first cache the instruction fetch requests of multiple thread groups. Each instruction fetch request contains the address of the instruction requested to be fetched by the corresponding thread group. Within the clock cycle, a thread group is selected according to the selection rule to perform instruction fetch operations for it, that is: the address of the instruction requested to be fetched by the thread group is sent to the instruction fetch unit, and the instruction fetch unit performs a hit-miss check in the first-level instruction cache based on the address of the instruction. If the instruction is already cached at the address, then the instruction is retrieved from the address; if the instruction is not cached at the address, then the instruction is retrieved from the downstream multi-level instruction cache.

[0107] The inspection result indicates whether the first instruction meets the scheduling condition. In implementation, the inspection unit 22 may be connected to the instruction scheduling unit 23 or not. When the inspection unit 22 is not connected to the instruction scheduling unit 23, the inspection unit 22 transmits the inspection result to the instruction scheduling unit 23 by broadcasting or other means.

[0108] The instruction scheduling unit is mainly used to schedule instructions. In implementation, if an instruction meets the scheduling conditions, the instruction is scheduled.

[0109] The execution unit is mainly used to execute instructions. In some embodiments, the number of the execution unit may be at least one, and different execution units may execute different types of instructions.

[0110] The execution information of the first instruction may include but is not limited to a dependent flag, or a dependent flag and a dependent flag, etc. In this way, the execution information of the first instruction is broadcast to the checking unit so that the checking unit can promptly release the dependency relationship between the second instruction and the first instruction. The dependent flag of the second instruction is the same as the dependent flag of the first instruction.

[0111] In some embodiments, the device also includes a decoding unit; the decoding unit is used to decode the first instruction to obtain dependency information of the first instruction; wherein the dependency information of the first instruction includes a dependency flag and a dependent flag; the checking unit is used to determine the dependency relationship of the first instruction based on the dependency flag and the dependent flag of the first instruction.

[0112] Here, the dependency flag indicates whether the first instruction depends on other instructions that have not been executed, and the dependent flag indicates whether the first instruction is dependent on other instructions. During implementation, after the decoding unit decodes the first instruction, it passes the dependency information of the first instruction to the inspection unit. In some embodiments, the decoding unit and the inspection unit may be connected or not. In the case where the decoding unit and the inspection unit are not connected, the decoding unit passes the dependency information to the inspection unit by broadcasting or other means.

[0113] The dependency relationship represents whether the first instruction depends on other instructions that have not been executed completely. During implementation, if the dependency flag and the dependent flag are the same, it indicates that the first instruction does not depend on other instructions that have not been executed completely; if the dependency flag and the dependent flag are different, the first instruction may depend on other instructions that have not been executed completely. For example, if the dependency flag and the dependent flag are both empty, it indicates that the first instruction neither depends on other instructions nor is it depended on by other instructions. For another example, if the dependency flag is empty and the dependent flag is not empty, it indicates that the first instruction does not depend on other instructions but is depended on by other instructions. For another example, if the dependency flag is not empty, the dependent flag is not empty and is different from the dependency flag, it indicates that the first instruction depends on other instructions and is also depended on by other instructions.

[0114] In some implementations, the checking unit 22 is further configured to broadcast the dependency relationship of the first instruction.

[0115] In some embodiments, the dependency relationship may be broadcast to the instruction scheduling unit by broadcasting.

[0116] In some embodiments, the inspection unit 22 is also used to release the dependency relationship between the first instruction and the target instruction in response to receiving execution information of the target instruction, and to update the inspection result and broadcast the updated inspection result; wherein, the execution information of the target instruction is broadcast by the execution unit to the inspection unit, and the dependent flag of the target instruction is the same as the dependent flag of the first instruction.

[0117] Here, the execution information of the target instruction may include but is not limited to a dependent flag, or a dependent flag and a dependent flag, etc. Since the target instruction is dependent on other instructions, the execution information of the target instruction at least includes the dependent flag. During implementation, after the inspection unit releases the dependency relationship between the first instruction and the target instruction, it promptly updates the inspection result of the first instruction, and the updated inspection result indicates that the first instruction does not depend on other instructions that have not been executed and meets the scheduling conditions. In some embodiments, the inspection unit broadcasts the updated inspection result to the instruction scheduling unit so that the instruction scheduling unit can schedule the first instruction in a timely manner.

[0118] Figure 2B A schematic diagram of the structure of an instruction scheduling device provided in an embodiment of the present disclosure is shown in FIG. Figure 2B As shown, the instruction scheduling device 20 includes an instruction fetch unit 21, a check unit 22, an instruction scheduling unit 23, an execution unit 24, a decoding unit 25, and an instruction fetch scheduling unit 26, wherein:

[0119] an instruction fetch scheduling unit 26, configured to determine a target thread group from at least one thread group, obtain the address of the first instruction from the instruction fetch request of the target thread group, and send the address of the first instruction to the instruction fetch unit 21;

[0120] The instruction fetch unit 21 is used to fetch the first instruction from the storage unit 27 of the graphics processor according to the address of the first instruction, and send the first instruction to the instruction scheduling unit 23;

[0121] An instruction scheduling unit 23, used for caching the first instruction and sending the first instruction to the decoding unit 25;

[0122] The decoding unit 25 is used to decode the first instruction, obtain the dependency information of the first instruction, and send the dependency information of the first instruction to the checking unit 22;

[0123] The checking unit 22 is used to check whether the first instruction meets the scheduling condition based on the dependency information of the first instruction, obtain the checking result, and broadcast the checking result to the instruction scheduling unit 23;

[0124] An instruction scheduling unit 23, configured to schedule the first instruction to the execution unit 24 if the checking result indicates that the first instruction meets the scheduling condition;

[0125] The execution unit 24 is configured to execute the first instruction and broadcast execution information of the first instruction.

[0126] Figure 2C A schematic diagram of the structure of an instruction scheduling unit provided in an embodiment of the present disclosure is shown in FIG. Figure 2C As shown, the instruction scheduling unit 20 includes an instruction fetch unit 21, a check unit 22, an instruction scheduling unit 23, an execution unit 24, a decoding unit 25, and an instruction fetch scheduling unit 26, wherein:

[0127] an instruction fetch scheduling unit 26, configured to determine a target thread group from at least one thread group, obtain the address of the first instruction from the instruction fetch request of the target thread group, and send the address of the first instruction to the instruction fetch unit 21;

[0128] The instruction fetch unit 21 is used to fetch the first instruction from the storage unit 27 of the graphics processor according to the address of the first instruction, and send the first instruction to the instruction scheduling unit 23; wherein, if the state of the first instruction in the L1 of the storage unit 27 is a hit state, the first instruction is fetched, otherwise, the instruction continues to be fetched from the next level cache of the L1 until the first instruction is fetched;

[0129] An instruction scheduling unit 23, used for caching the first instruction and sending the first instruction to the decoding unit 25;

[0130] The decoding unit 25 is used to decode the first instruction, obtain the dependency information of the first instruction, and send the dependency information of the first instruction to the checking unit 22;

[0131] The checking unit 22 is used to check whether the first instruction meets the scheduling condition based on the dependency information of the first instruction, obtain the checking result, and broadcast the checking result to the instruction scheduling unit 23; wherein, if the dependency flag and the dependent flag of the first instruction are the same, it indicates that the first instruction meets the scheduling condition; if the dependency flag of the first instruction is empty and the dependent flag is not empty, it indicates that the first instruction meets the scheduling condition; if the dependency flag of the first instruction is not empty and is different from the dependent flag, it indicates that the first instruction does not meet the scheduling suite;

[0132] An instruction scheduling unit 23, configured to schedule the first instruction to the execution unit 24 if the checking result indicates that the first instruction meets the scheduling condition;

[0133] The execution unit 24 is configured to execute the first instruction and broadcast execution information of the first instruction.

[0134] Here, after the execution of the first instruction is completed, the execution information of the first instruction is broadcast to the checking unit, so that the checking unit determines whether to release the dependency relationship between other instructions and the first instruction based on the execution information. For example, if instruction B depends on instruction A, then after the execution of instruction A is completed, the dependent flag of instruction A is broadcast to the checking unit, and the checking unit determines that the dependent flag in the waiting instruction B can match the dependent flag based on the dependent flag, indicating that the dependency relationship between instruction B and instruction A can be released, and updates the inspection result of instruction B, and broadcasts the updated inspection result to the instruction scheduling unit, and then the instruction scheduling unit can schedule instruction B to the execution unit for execution.

[0135] In the disclosed embodiments, firstly, before instruction scheduling, the instruction fetch unit is used to retrieve the first instruction from the storage unit and then stores it in the instruction scheduling unit, thereby ensuring that the instruction can be hit when the instruction is scheduled, reducing the possibility of the instruction being in a missing state, and improving the convenience and effectiveness of instruction fetching; secondly, before instruction scheduling, the inspection unit is used to determine the inspection result of the instruction based on the dependency information obtained by the decoding unit, thereby realizing the decoupling between the instruction scheduling unit and the decoding unit, and between the instruction scheduling unit and the inspection unit; finally, the instruction is scheduled only when it is determined that the instruction can be scheduled, so that the instruction scheduled by the instruction scheduling unit can be executed, which not only reduces the possibility of wasting the instruction issuance bandwidth, but also improves the effectiveness of instruction scheduling, thereby improving the execution efficiency of the instruction.

[0136] It should be noted that in the embodiments of the present disclosure, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present disclosure is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions to enable an electronic device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiments of the present disclosure are not limited to any specific combination of hardware and software.

[0137] An embodiment of the present disclosure provides an electronic device, comprising any of the above-mentioned instruction scheduling devices.

[0138] The embodiment of the present disclosure provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. The computer-readable storage medium may be transient or non-transient.

[0139] It should be noted that Figure 3 A hardware entity diagram of an electronic device provided in an embodiment of the present disclosure, such as Figure 3 As shown, the hardware entity of the electronic device 300 includes: a processor 301, a communication interface 302 and a memory 303, wherein:

[0140] The processor 301 generally controls the overall operation of the electronic device 300 .

[0141] The communication interface 302 enables the electronic device to communicate with other terminals or servers through a network.

[0142] The memory 303 is configured to store instructions and applications executable by the processor 301, and can also cache data to be processed or processed by the processor 301 and each module in the electronic device 300 (for example, image data, audio data, voice communication data, and video communication data), which can be implemented by flash memory (FLASH) or random access memory (Random Access Memory, RAM). Data transmission can be performed between the processor 301, the communication interface 302, and the memory 303 through the bus 304.

[0143] It should be noted that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0144] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0145] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0146] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0147] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0148] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately configured as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0149] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0150] Alternatively, if the above-mentioned integrated unit of the present disclosure is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for an electronic device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0151] The above description is only an implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. An instruction scheduling method, characterized in that: Applied in a graphics processor, the method comprises: Retrieving a first instruction from a storage unit of the graphics processor; Checking whether the first instruction meets a scheduling condition, wherein the scheduling condition includes: the first instruction does not depend on other unexecuted instructions; If the first instruction meets the scheduling condition, scheduling the first instruction; executing the first instruction and broadcasting execution information of the first instruction; The method further comprises: Decoding the first instruction to obtain dependency information of the first instruction, wherein the dependency information includes a dependency flag and a dependent flag; Determining a dependency relationship of the first instruction based on a dependency flag and a dependent flag of the first instruction; Broadcast the dependency of the first instruction.

2. The method according to claim 1, wherein broadcasting the execution information of the first instruction comprises: The dependency relationship of the first instruction is broadcasted.

3. The method according to claim 1, characterized in that The determining the dependency relationship of the first instruction based on the dependency flag and the dependent flag of the first instruction includes: When the dependency flag and the dependent flag of the first instruction are the same, it is determined that the first instruction does not depend on other instructions that have not been executed completely.

4. The method according to claim 1, characterized in that: The determining the dependency relationship of the first instruction based on the dependency flag and the dependent flag of the first instruction includes: When the dependency flag of the first instruction is empty and the dependent flag is not empty, it is determined that the first instruction does not depend on other instructions that have not been executed completely.

5. The method according to claim 1, characterized in that The determining the dependency relationship of the first instruction based on the dependency flag and the dependent flag of the first instruction includes: When the dependency flag of the first instruction is not empty and the dependent flag is different from the dependency flag, it is determined that the dependency relationship of the first instruction is dependency on other instructions.

6. The method according to claim 5, characterized in that The method further comprises: Based on the dependency flag of the first instruction, a target instruction on which the first instruction depends is determined, wherein the dependent flag of the target instruction is the same as the dependency flag of the first instruction.

7. The method according to claim 6, characterized in that The method further comprises: In response to receiving the execution information of the target instruction, the dependency relationship between the first instruction and the target instruction is released.

8. The method according to any one of claims 1 to 7, characterized in that The retrieving the first instruction from the storage unit of the graphics processor comprises: A hit-miss check is performed in a first-level instruction cache of the storage unit based on the address of the first instruction, and in response to the address hit, the first instruction is retrieved from the first-level instruction cache.

9. The method according to claim 8, characterized in that The method further comprises: In response to the address miss, the first instruction is retrieved from a downstream multi-level instruction cache of the storage unit.

10. An instruction scheduling device, characterized in that: Applied in graphics processors, including storage units, instruction fetch units, check units, instruction scheduling units, execution units and decoding units, among which: The instruction fetch unit is used to fetch the first instruction from the storage unit; The checking unit is used to check whether the first instruction meets the scheduling condition, obtain a checking result, and transmit the checking result to the instruction scheduling unit; wherein the scheduling condition includes that the first instruction does not depend on other unexecuted instructions; The instruction scheduling unit is configured to schedule the first instruction to the execution unit if the checking result indicates that the first instruction meets the scheduling condition; The execution unit is used to execute the first instruction and broadcast execution information of the first instruction; The decoding unit is used to decode the first instruction to obtain dependency information of the first instruction; broadcast the dependency relationship of the first instruction; wherein the dependency information of the first instruction includes a dependency flag and a dependent flag; The checking unit is used to determine the dependency relationship of the first instruction based on the dependency flag and the dependent flag of the first instruction.

11. The device according to claim 10, characterized in that The instruction fetch unit is further used to perform a hit-miss check in the first-level instruction cache of the storage unit based on the address of the first instruction, and retrieve the first instruction from the first-level instruction cache in response to the address hit.

12. The device according to claim 11, characterized in that The instruction fetch unit is further configured to retrieve the first instruction from a downstream multi-level instruction cache of the storage unit in response to the address miss.

13. The device according to claim 11, characterized in that The device also includes an instruction fetch scheduling unit, wherein: The instruction fetch scheduling unit is used to determine a target thread group from at least one thread group, and the instruction fetch request of the target thread group includes the address of the first instruction.

14. The device according to claim 10, characterized in that The execution unit is further used to broadcast the dependency relationship of the first instruction.

15. The device according to claim 10, characterized in that The inspection unit is also used to release the dependency relationship between the first instruction and the target instruction in response to receiving execution information of the target instruction, and to update the inspection result and broadcast the updated inspection result; wherein, the execution information of the target instruction is broadcast by the execution unit to the inspection unit, and the dependent flag of the target instruction is the same as the dependent flag of the first instruction.

16. An electronic device, characterized in that: The invention comprises the instruction scheduling device according to any one of claims 10 to 15.

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