A circuit wiring method, integrated circuit, chip and storage medium

Abstract

The present application relates to the technical field of circuit design, and particularly relates to a circuit wiring method, an integrated circuit, a chip and a storage medium, the circuit wiring method is used for wiring in different metal layers of a circuit, comprising the following steps: connecting a same wire net, and wiring in different metal layers of the circuit by using a plurality of wire nets; obtaining timing information based on wiring results in each metal layer; screening a critical path in the wired wire net in a preset sorting manner based on the timing information, and screening a wire net that does not meet a preset requirement based on the critical path; re-wiring the wire net that does not meet the preset requirement in the metal layer based on the critical path to meet the preset requirement; and optimizing a re-wiring result to improve timing of the wire net after re-wiring. By wiring in different metal layers, and re-wiring the wire net that does not meet the preset requirement after obtaining timing information, the timing at the place is additionally optimized, and thus signal delay is reduced.

Description

[0001] The application relates to a circuit wiring method, an integrated circuit, a chip and a storage medium.

[0002] In modern chip design, as the circuit scale continues to grow, directly wiring the circuit takes too much time, which is unacceptable in the design process. Therefore, global wiring is needed first when wiring to determine the general wiring method, and then detailed wiring is performed to meet the design rules. When global wiring, improving the timing performance of the circuit is an important optimization goal, which will affect the frequency and stability of the chip.

[0003] The timing performance of the circuit has a short board effect and is more affected by the path with poor timing performance. In the past, the minimum wire length or the wire length and the path length from the signal source to the sink were considered when establishing the connection line network pin in the first step of global wiring, that is, initial wiring, and smaller wire length was used as much as possible in the subsequent rewiring to improve the timing performance. However, these methods cannot be optimized in general because they do not consider specific timing information, and there is no way to perform additional optimization on the path with poor timing performance and signal delay, which is a key factor affecting the timing performance of the circuit.

[0004] To optimize the path with poor timing performance, the application provides a circuit wiring method, an integrated circuit, a chip and a storage medium.

[0005] The technical problem of the application is solved by providing a circuit wiring method for wiring a line network in different metal layers of a circuit, comprising: connecting the same line network and wiring the line network in different metal layers of the circuit using a plurality of line networks; calculating and obtaining timing information based on the wiring results in each metal layer; based on the timing information, screening a critical path in the laid line network in a preset sorting manner, and screening a line network that does not meet a preset requirement based on the critical path, wherein the preset requirement includes that the wiring resources in the wiring result are not overflowed and have no delay; disconnecting the line network that does not meet the preset requirement in the metal layer based on the critical path, and then performing rewiring to meet the preset requirement; optimizing the rewiring result to improve the timing of the rewired line network; based on the timing information, screening a critical path in the laid line network in a preset sorting manner, comprising: based on the timing information, sorting the sum of the line network itself delay and the maximum dynamic delay from high to low; continuously screening the line network, calculating the wiring resources consumed when using different line networks in each metal layer using virtual wiring, obtaining all line network paths in the result with the least wiring resource consumption, and outputting the critical path.

[0006] ​​​Preferably, the continuous screening of the line net and the calculation of the consumed routing resources in each metal layer using the virtual routing include: screening the line net, and skipping the routing mode meeting the preset demand; continuously screening the line net not meeting the preset demand until the preset demand is met or the line net is completely screened.

[0007] Preferably, the optimization of the rerouting result to improve the timing of the line net after the rerouting includes: optimizing the parameters of the critical path, including the winding range and the number of rerouting rounds; and optimizing the critical path after the rerouting based on the optimized parameters to improve the timing of the line net after the rerouting.

[0008] Preferably, the optimization of the critical path after the rerouting based on the optimized parameters to improve the timing of the line net after the rerouting includes reducing the line length and reducing the routing resource overflow, and the weight of reducing the line length based on the critical path is greater than that of the non-critical path, and the weight of reducing the routing resource overflow is less than that of the non-critical path.

[0009] Preferably, the critical path is the shortest path, and the number of rounds of rerouting based on the critical path is one round.

[0010] The application also provides an integrated circuit for a chip preparation process, which is prepared by using the circuit routing method.

[0011] The application also provides a storage medium for storing a computer program for electronic data exchange, wherein the computer program enables a computer to execute the circuit routing method.

[0012] The application also provides a chip for a chip preparation process, which includes the integrated circuit.

[0013] Compared with the prior art, the circuit routing method, the integrated circuit, the chip and the storage medium have the following advantages:

[0014] 1. The circuit routing method is used for routing a line net in different metal layers of a circuit, including: connecting the same line net, and routing the line net in different metal layers of the circuit using a plurality of line nets; obtaining timing information based on the routing result in each metal layer; screening a critical path in the routed line net in a preset sorting manner based on the timing information, and screening a line net not meeting a preset demand based on the critical path; performing rerouting on the line net not meeting the preset demand in the metal layer based on the critical path to meet the preset demand; and optimizing the rerouting result to improve the timing of the line net after the rerouting. By routing in different metal layers, obtaining timing information, and performing rerouting on the line net not meeting the preset demand to make the line net meet the preset demand, and additionally optimizing the timing of the rerouting result, signal delay is reduced.

[0015] 2. The circuit routing method of the present application, based on timing information, screening the critical path in the laid wire network in a preset sorting manner, comprising: based on timing information, sorting the sum of the wire network's own delay and maximum dynamic delay from high to low; continuously screening the wire network, using virtual routing to calculate the consumed routing resources in each metal layer when using different wire networks, obtaining all wire network paths in the result with the least routing resource consumption, and outputting as the critical path. By combining the virtual routing of the computing system, the wire network that meets the preset requirements can be quickly screened out, and the wire network is sorted according to the timing relationship, which can make it preferentially use the dynamic delay high and integrate together for calculation, so that the dynamic delay high wire network can be efficiently laid out, providing convenience for the layout of subsequent other wire networks.

[0016] 3. The circuit routing method of the present application, based on the critical path, re-routing the wire network of the metal layer to change the timing, comprising: optimizing the parameters of the critical path; based on the optimization parameters, optimizing the re-routed critical path to improve the timing after re-routing. When virtual resources are calculated, it cannot be fully guaranteed that all critical paths meet the preset requirements, so it is necessary to optimize the paths that do not meet the preset requirements. By optimizing the parameters to improve the timing, the critical path with poor timing performance and signal delay can be additionally optimized, which is more targeted and more comprehensive.

[0017] 4. The circuit routing method of the present application, based on the optimized parameters, optimizing the re-routed critical path to improve the timing of the re-routed wire network, comprising reducing the wire length and reducing the routing resource overflow. Based on the critical path, the weight of reducing the wire length is greater than that of the non-critical path, and the weight of reducing the routing resource overflow is less than that of the non-critical path. Re-routing is to reduce the wire length and reduce the routing resource overflow, so that the wire network meets the preset requirements. Then, the re-routing has not all positive effects on the timing, which may cause timing degradation, so it is necessary to further optimize the critical path or the non-critical path to improve the timing. By this method, the critical path and the non-critical path are comprehensively optimized for reducing the wire length and reducing the routing resource overflow, so that all wire networks can be optimized with minimal impact on the surrounding, which is more targeted, with minimal changes and better optimization effect.

[0018] 5. The present application also provides a storage medium storing a computer program for electronic data exchange, wherein the computer program enables the computer to execute the circuit routing method as described above. The storage medium has the same beneficial effects as the above-mentioned circuit routing method, which will not be repeated here.

[0019] 6. The present application also provides an integrated circuit applied to chip preparation process and prepared by using the circuit routing method as described above. The integrated circuit has the same beneficial effects as the above-mentioned circuit routing method, which will not be repeated here.

[0020] 7. The application further provides a chip, which is applied to a chip preparation process and comprises the integrated circuit as described above, and has the same beneficial effects as the circuit wiring method described above, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0022] Figure 1 is a step flow chart of a circuit wiring method provided by the first embodiment of the present application.

[0023] Figure 2 is a step flow chart of step S3 in the circuit wiring method provided by the first embodiment of the present application.

[0024] Figure 3 is a step flow chart of step S32 in the circuit wiring method provided by the first embodiment of the present application.

[0025] Figure 4 is a step flow chart of step S5 in the circuit wiring method provided by the first embodiment of the present application.

[0026] Figure 5 is a data schematic diagram before timing optimization in the circuit wiring method provided by the first embodiment of the present application.

[0027] Figure 6 is a single wire mesh path schematic diagram before timing optimization in the circuit wiring method provided by the first embodiment of the present application.

[0028] Figure 7 is a data schematic diagram after timing optimization in the circuit wiring method provided by the first embodiment of the present application.

[0029] Figure 8 is a single wire mesh path schematic diagram after timing optimization in the circuit wiring method provided by the first embodiment of the present application.

[0030] Figure 9 is a schematic diagram of a chip provided by the third embodiment of the present application.

[0031] Figure 10 is a schematic diagram of a storage medium provided by the fourth embodiment of the present application.

[0032] BRIEF DESCRIPTION OF DRAWINGS

[0033] 1, integrated circuit; 2, chip; 3, storage medium;

[0034] 31, computer program.

DETAILED DESCRIPTION

[0035] For the purpose of the present application, the technical solutions and advantages are more clear and explicit, the following will be combined with the drawings and examples, the present application is further described in detail. It should be understood that the specific examples described herein are only used to explain the present application, and are not used to limit the present application.

[0036] In the design of large-scale integrated circuits, physical design is a very important stage, and the routing stage is a very important stage in physical design. Global routing usually considers many routing constraints, and the timing of the laid wire network will seriously affect the efficiency of the layout and the quality of the final chip. In order to optimize the timing of the laid wire network, the present application provides a routing method which can automatically select the critical path affecting the timing performance and perform additional optimization on them, thereby improving the timing performance.

[0037] Please refer to Figure 1 , the first embodiment of the present application provides a circuit routing method for laying wire network in different metal layers of circuit, comprising:

[0038] S1: connecting the same wire network and using multiple wire networks to route in different metal layers of circuit;

[0039] S2: calculating and obtaining timing information based on the routing results in each metal layer;

[0040] S 3: based on the timing information, screening the critical path in the laid wire network in a preset sorting manner, and based on the critical path, screening the wire network that does not meet the preset requirement;

[0041] S 4: based on the critical path, re-routing the wire network in the metal layer that does not meet the preset requirement to meet the preset requirement;

[0042] S 5: optimizing the re-routing result to improve the timing of the wire network after re-routing.

[0043] It should be noted that the number of metal layers is not limited, which is used to distribute the wires in different layers to avoid short circuit, generally about 10 layers, which is specified by foundry and related to process; the metal layer is the layer where the connection metal for laying wire network is located, the connection metal in this layer is discontinuously arranged, some places have connection metal, such as the place where the wire is laid or the place where the component is arranged, some places are insulated, such as the place between two adjacent wires, the place between different connection metals, and the insulation is to prevent short circuit between wire network or wire networks.

[0044] The number of the wire nets is not limited, and each wire net has at least one pin. When wiring the wire net with only one pin, the wiring is performed according to a conventional wiring mode. When wiring the wire net with at least two pins, the pins of different wire nets are preferentially electrically connected to form a path, and the remaining pins are used to connect the wire net to a metal in a metal layer. A plurality of wire nets are arranged in the same metal layer, but the same metal is arranged with only one wire net to avoid short circuit between different wire nets.

[0045] It can be understood that, by wiring in different metal layers, and obtaining timing information, the wire net not meeting the preset requirement is re-wired to make the wire net meet the preset requirement, and the timing of the re-wiring result is additionally optimized to reduce signal delay.

[0046] Specifically, in the embodiments of the present application, each wire net is initially wired in a metal layer, and then the wire net overflowing the wiring resource is disconnected and re-wired, so as to reduce the delay while preventing short circuit between different wire nets.

[0047] More specifically, the wiring resource calculation process is as follows:

[0048] The metal plane in the metal layer is divided into a plurality of grids;

[0049] The wire net path is added to the grid for virtual wiring until the wire net resource in the grid overflows.

[0050] Each grid can accommodate a certain number of wirings, and adding virtual wiring is to increase the use amount of the grid passed by the wire net. The wiring resource overflow means that the use amount exceeds the accommodation amount.

[0051] Further, based on the timing information, the critical path is screened from the arranged wire net in a preset sorting mode, including: Figure 2

[0052] S 31: based on the timing information, the sum of the wire net self-delay and the maximum dynamic delay is sorted from high to low;

[0053] S 32: continuously screening the wire net, calculating the consumed wiring resource when using different wire nets in each metal layer by using virtual wiring, obtaining all wire net paths in the result with the least wiring resource consumption, and outputting as the critical path.

[0054] It should be noted that the wire net self-delay is the delay possessed by the wire net itself, and the maximum dynamic delay is the delay expected to be increased after re-wiring.

[0055] In addition, the timing information will affect the arrangement direction of the wire net path, that is, the bending or extending direction of the wire net in the metal layer.

[0056] ​It can be understood that by combining the virtual wiring of the computing system, the line network meeting the preset requirements can be quickly screened out, and the line network is sorted according to the timing relationship, so that the dynamic delay high line network can be efficiently laid out, and the subsequent layout of other line networks is facilitated.

[0057] Further, please refer to Figure 3 , continuously screen the line network, and calculate the wiring resources consumed in each metal layer using different line networks by virtual wiring, including:

[0058] S 321: Screen the line network, and skip the wiring mode meeting the preset requirements;

[0059] S 322: Continuously screen the line network that does not meet the preset requirements until the preset requirements are met or the line network is completely screened.

[0060] Further, meeting the preset requirements includes that the wiring resources in the final wiring result are not overflowed and there is no delay.

[0061] It should be noted that when detecting the use of wiring resources, the line network layout mode that does not cause the overflow of wiring resources or does not have delay is skipped, and the path of the line network finally added to the virtual wiring in this layout mode is defined as a critical path.

[0062] Further, please refer to Figure 4 , optimizing the re-wiring result to improve the timing of the line network after re-wiring includes:

[0063] S 51: Optimize the parameters of the critical path;

[0064] S 52: Optimize the critical path after re-wiring based on the optimization parameters to improve the timing of the line network after re-wiring.

[0065] Specifically, the parameters of the critical path include the winding range and the number of re-wiring rounds.

[0066] More specifically, the optimization of the parameters of the critical path is to adjust the proportion of the consideration of the wiring resources during the wiring by controlling the utilization rate of the wiring resources. In the specific embodiment of the present application, the proportion of the utilization rate of the wiring resources is relatively smaller, and the proportion of the line length is relatively larger.

[0067] It should be noted that the virtual resource calculation cannot completely guarantee that all critical paths meet the preset requirements, so optimization and re-wiring are needed, and the re-wiring process may cause short circuit of part of the line, so the re-wiring process will also optimize the place where the short circuit exists. The optimized result ensures that there is no short circuit in all metal layers.

[0068] It can be understood that the paths that do not meet the preset requirements are re-routed to correct the line network paths in the initial routing that do not meet the preset requirements, and then the parameters of the critical path are optimized to improve the timing, that is, the critical path with poor timing performance and signal delay is additionally optimized, which is more targeted and more comprehensive.

[0069] Further, the optimization of the critical path after re-routing based on the optimized parameters to improve the timing of the line network after re-routing includes reducing the line length and reducing the overflow of routing resources, and the weight of reducing the line length based on the critical path is greater than that of the non-critical path, and the weight of reducing the overflow of routing resources is less than that of the non-critical path.

[0070] Among them, based on the critical path, the weight of reducing the line length is greater than that of reducing the overflow of routing resources.

[0071] It should be noted that the re-routing is to reduce the line length and reduce the overflow of routing resources, so that the line network meets the preset requirements, and then the influence of re-routing on timing is not all positive, which may cause timing degradation, so further optimization of the critical path or non-critical path is needed to improve the timing, and when the range of the re-routed line network is longer than the range of the two pins, the line length is longer than the range of the re-routed line network, and the delay is also higher.

[0072] Further, the critical path is the shortest path, and the number of rounds of re-routing based on the critical path is one round.

[0073] Specifically, in the routing method, the algorithm of the critical path is different from that of the initial routing method, and the algorithm of the critical path is a search algorithm, including a screening process of the line network.

[0074] It should be noted that the critical path is the shortest path that can reduce the resource occupation of other routing positions to the lowest extent, however, in the routing, it cannot be guaranteed that all critical paths are actually the shortest paths, therefore, the shortest path here is a result as a whole, for the line network layout of the entire metal layer, the total line length of the critical line is the shortest, and at this time all the critical paths are the shortest paths.

[0075] In addition, the more the number of re-routing rounds, the higher the difficulty of layout; increasing the re-routing path may cause the overflow of the originally unoverflowed routing resources, thereby increasing the optimization difficulty.

[0076] It can be understood that by this method, the critical path and the non-critical path are comprehensively optimized to reduce the line length and reduce the overflow of routing resources, so that all the line networks can be optimized with the least impact on the surroundings, which is more targeted, has the least change, and has better optimization effect.

[0077] Specifically, please refer to Figures 5-8 In the embodiments of the present application:

[0078] The initial routing is performed using about one hundred thousand wire nets;

[0079] Timing information is calculated for the result after initial routing, and routing resource calculation is performed, wherein about six thousand wire nets are finally determined as critical paths;

[0080] Parameter optimization is performed on the critical paths, wherein the expansion of the wire nets selected as the critical paths on the winding range is 1 / 9 of other wire nets, and the influence on resource utilization rate is halved compared with other wire nets when re-routing;

[0081] The re-routing is performed based on the optimized parameters to optimize the routing method of the overflow of the routing resource.

[0082] Wherein, the setup WNS (worst path timing violation) is the worst delay, and the setup TNS (total timing violation) is the total delay, and after the circuit routing method is used, the delay is obviously reduced, the path does not go up the winding road, the wire length is shortened, and the timing performance is obviously improved.

[0083] Referring to Figure 9 The second embodiment of the present application provides an integrated circuit 1 applied to a chip preparation process and prepared by using the circuit routing method. The integrated circuit 1 has the same beneficial effects as the circuit routing method, and details are not repeated here.

[0084] Further, the wiring method of the integrated circuit 1 is automatic wiring.

[0085] It should be noted that automatic wiring can greatly reduce the labor input and the result is more accurate, and the integrated circuit obtained by using the circuit routing method of the present application can automatically select the critical path affecting the timing performance, and additional optimization is performed on the critical path, so as to improve the timing performance and reduce the signal delay.

[0086] The third embodiment of the present application provides a chip 2 applied to a chip preparation process, comprising the integrated circuit 1 described above, and has the same beneficial effects as the integrated circuit 1, and details are not repeated here.

[0087] Referring to Figure 10 The fourth embodiment of the present application provides a storage medium 3 storing a computer program 31 for electronic data exchange, wherein the computer program 31 enables the computer to execute the circuit routing method described above, and the storage medium 3 has the same beneficial effects as the circuit routing method, and details are not repeated here.

[0088] It is appreciated that the processes described above with reference to the flowcharts can be implemented as computer software programs according to the embodiments disclosed in the present application. For example, the embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program codes for executing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by a communication part, and / or installed from a detachable medium. When the computer program is executed by a central processing unit (CPU), the above-mentioned functions defined in the methods of the present application are executed. It is to be noted that the computer readable medium in the present application can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium includes, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, device or apparatus. In the present application, the computer readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, in which a computer readable program code is carried. Such a propagated data signal can take many forms, including but not limited to, an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium that can send, propagate or transfer a program for use by or in connection with an instruction execution system, device or apparatus. The program code contained on the computer readable medium can be transmitted in any suitable medium, including but not limited to, wireless, wire line, optical fiber cable, RF, etc., or any suitable combination of the above.

[0089] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0090] In the embodiments provided in the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that the determination of B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0091] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0092] In various embodiments of the present application, it should be understood that the size of the sequence number of each process described above does not mean the inevitable sequence of execution order, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0093] The flow diagrams and the block diagrams in the drawings are illustrations of architectures, functional processes, and operational processes according to various embodiments of the present application. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code that comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams and combinations thereof can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions.

[0094] Compared with the prior art, the circuit wiring method, integrated circuit, chip and storage medium of the present application have the following advantages:

[0095] 1. The circuit wiring method of the present application is used for wiring in different metal layers of a circuit, comprising: connecting a same wire net and using a plurality of wire nets to wire in different metal layers of the circuit; calculating and obtaining timing information based on the wiring result in each metal layer; screening a critical path in the wired wire net in a preset sorting manner based on the timing information, and screening a wire net that does not meet a preset requirement based on the critical path; re-wiring the wire net that does not meet the preset requirement in the metal layer based on the critical path to meet the preset requirement; and optimizing the re-wiring result to improve the timing of the wire net after re-wiring. By wiring in different metal layers, obtaining timing information, re-wiring the wire net that does not meet the preset requirement to meet the preset requirement, and additionally optimizing the timing of the re-wiring result, the signal delay is reduced.

[0096] 2. The circuit wiring method of the present application, which screens a critical path in a wired wire net in a preset sorting manner based on timing information, comprises: sorting the sum of the wire net self-delay and the maximum dynamic delay from high to low based on the timing information; continuously screening the wire net, calculating the wiring resources consumed when using different wire nets in each metal layer using virtual wiring, obtaining all wire net paths in the result with the least wiring resource consumption, and outputting as the critical path. By combining the virtual wiring of the calculation system, the wire net that meets the preset requirement can be quickly screened, and the wire net is sorted according to the timing relationship, so that the wire net with high dynamic delay can be efficiently laid out, providing convenience for the layout of subsequent other wire nets.

[0097] 3. The circuit routing method of the present invention, after rerouting the network of the metal layer based on the critical path to change the timing, includes: optimizing the parameters of the critical path; and optimizing the rerouted critical path based on the optimized parameters to improve the timing after rerouting. Virtual resource calculation cannot guarantee that all critical paths will meet preset requirements. Therefore, it is necessary to optimize paths that do not meet preset requirements. By optimizing parameters to improve timing, additional optimization can be performed on critical paths with poor timing performance and signal delays, making the optimization more targeted and comprehensive.

[0098] 4. The circuit routing method of the present invention optimizes the critical path after rerouting based on optimized parameters to improve the timing of the rerouted network. This includes reducing line length and reducing routing resource overflow. Based on the critical path, reducing line length has a greater weight than non-critical paths, while reducing routing resource overflow has a smaller weight than non-critical paths. Rerouting aims to reduce line length and routing resource overflow to ensure the network meets preset requirements. However, the impact of rerouting on timing is not entirely positive and may lead to timing degradation. Therefore, further optimization of critical or non-critical paths is necessary to improve timing. This method comprehensively optimizes both critical and non-critical paths to reduce line length and routing resource overflow, thus optimizing the entire network with minimal impact on the surrounding environment. It is more targeted, requires minimal modifications, and achieves better optimization results.

[0099] 5. The present invention also provides a storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to execute the circuit wiring method described above. The storage medium has the same beneficial effects as the circuit wiring method described above, and will not be elaborated further here.

[0100] 6. This invention also provides an integrated circuit, applied in chip fabrication processes, and fabricated using the circuit wiring method described above. The integrated circuit has the same beneficial effects as the circuit wiring method described above, and will not be elaborated further here.

[0101] 7. The present invention also provides a chip for use in chip fabrication processes, including the integrated circuit described above, which has the same beneficial effects as the circuit wiring method described above, and will not be elaborated here.

[0102] The circuit wiring method, the integrated circuit, the chip and the storage medium disclosed in the embodiments of the present application are described in detail, the principles and implementation manners of the present application are described by applying specific examples, the above embodiment description is only used to help understand the method of the present application and the core idea; meanwhile, for the general technical personnel in the art, according to the idea of the present application, the specific implementation manner and the application range will be changed, and the above description should not be understood as the limitation of the present application, any modification, equivalent replacement and improvement within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A circuit wiring method for laying wire meshes in different metal layers of a circuit, characterized in that, include: Connect the same net and use multiple nets to wire in different metal layers of the circuit; Timing information is calculated and obtained based on the wiring results in each metal layer; Based on the timing information, critical paths are selected in the deployed network using a preset sorting method, and networks that do not meet preset requirements are selected based on the critical paths. Meeting the preset requirements includes that the wiring resources in the wiring result do not overflow and there is no delay. Based on the critical path, the nets in the metal layer that do not meet the preset requirements are disconnected and then rewired to meet the preset requirements. Optimize rerouting results to improve network timings after rerouting; Based on the aforementioned timing information, key paths are selected from the deployed network using a preset sorting method, including: Based on the timing information, the nets are sorted from high to low according to the sum of their own delay and the expected increase in delay after rewiring; Continuously filter nets, use virtual routing to calculate the routing resources consumed when using different nets in each metal layer, obtain all net paths in the result with the least routing resource consumption, and output them as critical paths.

2. The circuit wiring method as described in claim 1, characterized in that, Continuously screen nets and use virtual routing to calculate the routing resources consumed when using different nets in each metal layer, including: Filter the nets and skip the wiring methods that meet the preset requirements; Continuously filter wires that do not meet the preset requirements until the preset requirements are met or all wires have been filtered.

3. The circuit wiring method as described in claim 2, characterized in that, Optimizing rerouting results to improve network timings after rerouting includes: Optimize the parameters of the critical path, including the routing range and the number of rewire turns; The critical path with signal delay after rewiring is optimized based on the optimization parameters to improve the network timing after rewiring.

4. The circuit wiring method as described in claim 3, characterized in that: Optimize the critical path after rerouting based on optimized parameters to improve the network timing after rerouting. This includes reducing cable length and reducing cabling resource overflow. Based on the critical path, reducing cable length has a greater weight than non-critical paths, while reducing cabling resource overflow has a smaller weight than non-critical paths.

5. The circuit wiring method as described in claim 1, characterized in that: The critical path is the shortest path, and the number of rounds for rewiring based on the critical path is one round.

6. An integrated circuit used in chip fabrication processes, characterized in that: It is prepared using the circuit wiring method as described in any one of claims 1-5.

7. A storage medium, characterized in that: The storage medium stores a computer program for electronic data interchange, wherein the computer program causes a computer to perform the circuit wiring method as described in any one of claims 1-5.

8. A chip used in chip fabrication processes, characterized in that: Including the integrated circuit described in claim 6.

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