Gate driving circuit and display panel
By setting up multi-level cascaded modules in the gate driving unit, zone-driven display was realized, solving the problem of insufficient pixel charging in high-resolution LCD panels and improving the display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-31
- Publication Date
- 2026-03-10
AI Technical Summary
When traditional LCD panels scan line by line at high resolution, insufficient pixel charging can easily occur, resulting in abnormal color mixing in the displayed image. Existing technologies make it difficult to achieve effective zone driving to improve the display effect.
The system employs a multi-stage cascaded gate drive unit, including an input module, a pull-down control module, a first output module, a zone control module, a second output module, and a pull-down module. The combination of these modules enables zoned drive display, ensuring the normal transmission of the cascaded signal while controlling the output of the scan signal.
It implements zone-driven display, improves the display effect of the display panel, alleviates the problem of insufficient charging, and reduces grayscale changes between adjacent subframes.
Smart Images
Figure CN117524131B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of display, in particular to a gate driving circuit and display panel. BACKGROUND
[0002] Array substrate row driving, that is, using the array process of the existing thin film transistor liquid crystal display to manufacture the gate row scanning driving signal circuit on the array substrate, to realize the driving mode of scanning the gate row by row.
[0003] The traditional liquid crystal display panel is scanned row by row, and the row-by-row scanning is to open the display row scanning signal one by one, to scan the picture row by row. For high-resolution products, the scanning opening time allocated to each row becomes shorter, and the high-resolution products have larger load, which is easy to cause insufficient charging of the pixels, so that when the gray scale change between adjacent sub-frame pictures is large, it is easy to cause abnormal color mixing of the display picture.
[0004] Therefore, how to propose a gate driving circuit which can realize partition driving display to improve the display effect of the display panel is a problem to be solved urgently. SUMMARY
[0005] The purpose of the embodiment of the present application is to provide a gate driving circuit and display panel, which can realize partition driving display and improve the display effect of the display panel.
[0006] In one aspect, the embodiment of the present application provides a gate drive circuit, comprising a plurality of gate drive units arranged in cascade, wherein the gate drive unit comprises an input module, a pull-down control module, a first output module, a partition control module, a second output module and a pull-down module; the input module is electrically connected with a forward scanning signal end, an upper two-stage stage transmission signal end and a first node, and is used for pulling up the potential of the first node; the pull-down control module is electrically connected with the forward scanning signal end, a lower two-stage clock signal end, a reverse scanning signal end, an upper two-stage clock signal end, a first global signal end, a lower two-stage stage transmission signal end, a reference low-level signal end, the first node, a second node and a third node, and is used for controlling the potential of the second node; the first output module is electrically connected with the first node, a current-stage clock signal end and a current-stage stage transmission signal end, and is used for outputting a current-stage stage transmission signal; the partition control module is electrically connected with the first control signal end, the first node and a fourth node, and is used for controlling the output of a current-stage scanning signal; the second output module is electrically connected with the fourth node, the current-stage clock signal end and a current-stage scanning signal end, and is used for outputting the current-stage scanning signal; and the pull-down module is electrically connected with the first node, the second node, the current-stage stage transmission signal end, the current-stage scanning signal end and the reference low-level signal end, and is used for pulling down the potential of the first node, the current-stage stage transmission signal end and the current-stage scanning signal end.
[0007] Optionally, in some embodiments of the present application, the first output module comprises a first transistor, a gate of the first transistor is electrically connected with the first node, a first electrode of the first transistor is electrically connected with the current-stage clock signal end, and a second electrode of the first transistor is electrically connected with the current-stage stage transmission signal end.
[0008] Optionally, in some embodiments of the present application, the first output module further comprises a second transistor, a gate of the second transistor is electrically connected with a reference high-level signal end, a first electrode of the second transistor is electrically connected with the first node, and a second electrode of the second transistor is electrically connected with the gate of the first transistor.
[0009] Optionally, in some embodiments of the present application, the partition control module comprises a third transistor, a gate of the third transistor is electrically connected with the first control signal end, a first electrode of the third transistor is electrically connected with the first node, and a second electrode of the third transistor is electrically connected with the fourth node.
[0010] Optionally, in some embodiments of the present application, the partition control module further comprises a fourth transistor, a gate of the fourth transistor is electrically connected with the second control signal terminal, a first electrode of the fourth transistor is electrically connected with the reference low voltage signal terminal, and a second electrode of the fourth transistor is electrically connected with the fourth node.
[0011] Optionally, in some embodiments of the present application, the first control signal terminal is configured to input a first control signal, and the second control signal terminal is configured to input a second control signal, a potential of the first control signal is opposite to a potential of the second control signal.
[0012] Optionally, in some embodiments of the present application, the second output module comprises a fifth transistor, a gate of the fifth transistor is electrically connected with the fourth node, a first electrode of the fifth transistor is electrically connected with the local clock signal terminal, and a second electrode of the fifth transistor is electrically connected with the local scan signal terminal.
[0013] Optionally, in some embodiments of the present application, the second output module further comprises a sixth transistor, a gate of the sixth transistor and a first electrode of the sixth transistor are electrically connected with the second global signal terminal, and a second electrode of the sixth transistor is electrically connected with the local scan signal terminal.
[0014] Optionally, in some embodiments of the present application, the gate driving unit further comprises: a first capacitor, a second capacitor, an input module, a pull-down control module and a pull-down module; one end of the first capacitor is electrically connected with the first node, and the other end of the first capacitor is electrically connected with the reference low-level signal end; one end of the second capacitor is electrically connected with the second node, and the other end of the second capacitor is electrically connected with the reference low-level signal end; the input module comprises a seventh transistor, a gate of the seventh transistor is electrically connected with the upper two-stage stage transmission signal end, a first electrode of the seventh transistor is electrically connected with the forward scanning signal end, and a second electrode of the seventh transistor is electrically connected with the first node; the pull-down control module comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, a gate of the eighth transistor is electrically connected with the forward scanning signal end, a first electrode of the eighth transistor is electrically connected with the lower two-stage clock signal end, and a second electrode of the eighth transistor is electrically connected with a third node; a gate of the ninth transistor is electrically connected with the reverse scanning signal end, a first electrode of the ninth transistor is electrically connected with the upper two-stage clock signal end, and a second electrode of the ninth transistor is electrically connected with the third node; a gate of the tenth transistor is electrically connected with the third node, a first electrode of the tenth transistor is electrically connected with the first global signal end, and a second electrode of the tenth transistor is electrically connected with the second node; a gate of the eleventh transistor is electrically connected with the lower two-stage stage transmission signal end, a first electrode of the eleventh transistor is electrically connected with the reverse scanning signal end, and a second electrode of the eleventh transistor is electrically connected with the first node; a gate of the twelfth transistor is electrically connected with the first node, a first electrode of the twelfth transistor is electrically connected with the second node, and a second electrode of the twelfth transistor is electrically connected with the reference low-level signal end; the pull-down module comprises a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, a gate of the thirteenth transistor, a gate of the fourteenth transistor and a gate of the fifteenth transistor are all electrically connected with the second node; a first electrode of the thirteenth transistor is electrically connected with the first node; a first electrode of the fourteenth transistor is electrically connected with the current-stage stage transmission signal end, and a first electrode of the fifteenth transistor is electrically connected with the current-stage scanning signal end; a second electrode of the thirteenth transistor, a second electrode of the fourteenth transistor and a second electrode of the fifteenth transistor are all electrically connected with the reference low-level signal end.
[0015] In another aspect, the present application provides a display panel comprising the gate driving circuit as described above.
[0016] In the gate driving circuit and display panel provided in the embodiments of this application, the gate driving circuit sets a first output module, a partition control module and a second output module in the gate driving unit. The first output module is used to output the current stage transmission signal; the partition control module is used to control the output of the current stage scan signal; and the second output module is used to output the current stage scan signal. Thus, while ensuring the normal transmission of the stage transmission signal, the output of the current stage scan signal is controlled, thereby realizing partition driving display, which is beneficial to improving the display effect of the display panel. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the gate drive circuit provided in an embodiment of this application;
[0019] Figure 2 for Figure 1 A schematic diagram of the structure of a gate driving unit in the gate driving circuit provided in the image;
[0020] Figure 3 for Figure 2 The first circuit diagram of the gate drive unit provided in the document;
[0021] Figure 4 This is a first driving timing diagram of the gate driving circuit provided in an embodiment of this application;
[0022] Figure 5 for Figure 2 The second circuit diagram of the gate drive unit provided in the diagram;
[0023] Figure 6a This is one of the second driving timing diagrams for the gate driving circuit provided in the embodiments of this application;
[0024] Figure 6b This is a second type of driving timing diagram for a display panel provided in an embodiment of this application;
[0025] Figure 7 for Figure 2 The third circuit diagram of the gate drive unit provided in the document;
[0026] Figure 8 This is a third driving timing diagram of the gate driving circuit provided in the embodiments of this application;
[0027] Figure 9This is a fourth driving timing diagram of the gate driving circuit provided in the embodiments of this application;
[0028] Figure 10 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;
[0029] Figure 11 for Figure 10 The diagram shows the partitioning of the display panel provided. Detailed Implementation
[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0031] This application provides a gate driving circuit and a display panel. The gate driving circuit achieves zone-driven display by setting a zone control module to control the output of the scanning signal at that level, thereby improving the display effect of the display panel. Detailed descriptions are provided below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments. Furthermore, in the description of this application, the term "comprising" means "including but not limited to". The terms "first", "second", "third", etc., are used merely as identifiers to distinguish different objects, not to describe a specific order.
[0032] Please see Figure 1 , Figure 1 This is a schematic diagram of the gate drive circuit provided in an embodiment of this application. Figure 1 As shown, the gate driving circuit provided in this application embodiment includes multiple cascaded gate driving units. Figure 1 Taking the cascaded gate driving unit from the 1st stage to the 3nth stage as an example, the 1st stage to the nth stage, the (n+1)th stage to the 2nth stage, and the (2n+1)th stage to the 3nth stage are divided into three gate driving unit groups 10.
[0033] Among them, the first to the nth stages only output the transmission signal of the current stage in sequence, but do not output the scanning signal of the current stage under the control of the first control signal GON; the (n+1)th to the 2nth stages and the (2n+1)th to the 3nth stages output the transmission signal of the current stage in sequence, and output the scanning signal of the current stage under the control of the first control signal GON.
[0034] Please see Figure 2 , Figure 2 for Figure 1 The diagram shows the structure of a gate driving unit in the gate driving circuit provided. Figure 2As shown, the embodiment of the present application provides a gate driving unit, which comprises an input module 101, a pull-down control module 102, a first output module 103, a partition control module 104, a second output module 105, a pull-down module 106, a first capacitor C1 and a second capacitor C2.
[0035] The input module 101 is electrically connected with a forward scanning signal end U2D, an upper two-stage stage transmission signal end STN(n-2) and a first node Q, and is used for pulling up the potential of the first node Q.
[0036] The pull-down control module 102 is electrically connected with the forward scanning signal end U2D, a lower two-stage clock signal end CK(n+2), a reverse scanning signal end D2U, an upper two-stage clock signal end CK(n-2), a first global signal end Gas1, a lower two-stage stage transmission signal end STN(n+2), a reference low-level signal end VGL, the first node Q, a second node P and a third node K, and is used for controlling the potential of the second node P.
[0037] The first output module 103 is electrically connected with the first node Q, a current-stage clock signal end CK(n) and a current-stage stage transmission signal end STN, and is used for outputting the current-stage stage transmission signal.
[0038] The partition control module 104 is electrically connected with a first control signal end GON, the first node Q and a fourth node S, and is used for controlling the output of the current-stage scanning signal.
[0039] The second output module 105 is electrically connected with the fourth node S, the current-stage clock signal end CK(n) and a current-stage scanning signal end Gout, and is used for outputting the current-stage scanning signal.
[0040] The pull-down module 106 is electrically connected with the first node Q, the second node P, the current-stage stage transmission signal end STN, the current-stage scanning signal end Gout and the reference low-level signal end VGL, and is used for pulling down the potential of the first node Q, the current-stage stage transmission signal end STN and the current-stage scanning signal end Gout.
[0041] One end of the first capacitor C1 is electrically connected with the first node Q, and the other end of the first capacitor C1 is electrically connected with the reference low-level signal end VGL.
[0042] One end of the second capacitor C2 is electrically connected with the second node P, and the other end of the second capacitor C2 is electrically connected with the reference low-level signal end VGL.
[0043] The gate driving circuit provided in this application sets a first output module 103, a partition control module 104, and a second output module 105 in the gate driving unit. The first output module 103 is used to output the current stage transmission signal; the partition control module 104 is used to control the output of the current stage scan signal; and the second output module 105 is used to output the current stage scan signal. Thus, while ensuring the normal transmission of the stage transmission signal, the output of the current stage scan signal is controlled, thereby realizing partition driving display, which is beneficial to improving the display effect of the display panel.
[0044] Please see Figure 3 , Figure 3 for Figure 2 The diagram shows a first type of circuit for the gate drive unit provided in the document. (See diagram for example.) Figure 3 As shown, this application embodiment provides a gate driving unit 100, which includes an input module 101, a pull-down control module 102, a first output module 103, a partition control module 104, a second output module 105, and a pull-down module 106.
[0045] Specifically, the first output module 103 includes a first transistor T1 and a second transistor T2. The first electrode of the first transistor T1 is electrically connected to the clock signal terminal CK(n) of the current stage, and the second electrode of the first transistor T1 is electrically connected to the transmission signal terminal STN of the current stage. The gate of the second transistor T2 is electrically connected to the reference high-level signal terminal VGH. The first electrode of the second transistor T2 is electrically connected to the first node Q, and the second electrode of the second transistor T2 is electrically connected to the gate of the first transistor T1.
[0046] Specifically, the partition control module 104 includes a third transistor T3, the gate of the third transistor T3 is electrically connected to the first control signal terminal GON, the first electrode of the third transistor T3 is electrically connected to the first node Q, and the second electrode of the third transistor T3 is electrically connected to the fourth node S.
[0047] Specifically, the second output module 105 includes a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to the fourth node S, the first electrode of the fifth transistor T5 is electrically connected to the clock signal terminal CK(n) of this stage, and the second electrode of the fifth transistor T5 is electrically connected to the scan signal terminal Gout of this stage.
[0048] One end of the first capacitor C1 is electrically connected to the first node Q, and the other end of the first capacitor C1 is electrically connected to the reference low-level signal terminal VGL; the first capacitor C1 is used to pull down the potential of the first node Q during the non-signal output phase.
[0049] The input module 101 includes a seventh transistor T7. The gate of the seventh transistor T7 is electrically connected to the upper two-stage transmission signal terminal STN(n-2), the first electrode of the seventh transistor T7 is electrically connected to the forward scan signal terminal U2D, and the second electrode of the seventh transistor T7 is electrically connected to the first node Q.
[0050] The pull-down control module 102 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The gate of the eighth transistor T8 is electrically connected to the forward scan signal terminal U2D, the first electrode of the eighth transistor T8 is electrically connected to the next two-stage clock signal terminal CK(n+2), and the second electrode of the eighth transistor T8 is electrically connected to the third node K. The gate of the ninth transistor T9 is electrically connected to the reverse scan signal terminal D2U, the first electrode of the ninth transistor T9 is electrically connected to the previous two-stage clock signal terminal CK(n-2), and the second electrode of the ninth transistor T9 is electrically connected to the third node K. The tenth transistor T10... The gate of the tenth transistor T10 is electrically connected to the third node K; the first electrode of the tenth transistor T10 is electrically connected to the first global signal terminal Gas1; and the second electrode of the tenth transistor T10 is electrically connected to the second node P. The gate of the eleventh transistor T11 is electrically connected to the next two stage transmission signal terminal STN(n+2); the first electrode of the eleventh transistor T11 is electrically connected to the reverse scan signal terminal; and the second electrode of the eleventh transistor T11 is electrically connected to the first node Q. The gate of the twelfth transistor T12 is electrically connected to the first node Q; the first electrode of the twelfth transistor T12 is electrically connected to the second node P; and the second electrode of the twelfth transistor T12 is electrically connected to the reference low-level signal terminal VGL.
[0051] The pull-down module 106 includes a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15. The gates of the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are all electrically connected to the second node P. The first electrode of the thirteenth transistor T13 is electrically connected to the first node Q. The first electrode of the fourteenth transistor T14 is electrically connected to the stage transmission signal terminal STN, and the first electrode of the fifteenth transistor T15 is electrically connected to the stage scan signal terminal Gout. The second electrodes of the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are all electrically connected to the reference low-level signal terminal VGL.
[0052] One end of the second capacitor C2 is electrically connected to the second node P, and the other end of the second capacitor C2 is electrically connected to the reference low-level signal terminal VGL. When the clock signal terminal CK(n) of this stage changes from high level to low level, and since the second node P is high level and the thirteenth transistor T13 is in the open state, the low-level signal output of the clock signal terminal CK(n) of this stage will pull the second node P low to a certain extent. Due to the storage function of the second capacitor C2, the second node P will drop linearly to the low level after a certain delay when the clock signal terminal CK(n) of this stage outputs a low-level signal.
[0053] Please see Figure 4 , Figure 4 This is a first driving timing diagram for the gate driving circuit provided in an embodiment of this application. (See diagram below.) Figure 4 As shown, the first control signal terminal GON corresponding to the gate driving units of stages 1 to 3n receives a high-level signal, and the scanning signal terminal Gout corresponding to the gate driving units of stages 1 to 3n sequentially outputs the scanning signal (G1, G2, G...) of the current stage. n-1 G n... G 2n... G 3n The first control signal terminal GON corresponding to the gate drive units of stages 3n+1 to 4n receives a low-level signal, and the scan signal Gout corresponding to the current stage of the gate drive units of stages 3n+1 to 4n outputs the scan signal (G) of the current stage. 3n+1... G 4n () indicates a low-level signal.
[0054] Please see Figure 5 , Figure 5 for Figure 2 The second circuit diagram of the gate drive unit provided is shown below. Figure 5 As shown, this application embodiment provides a gate driving unit 200. The difference between gate driving unit 200 and gate driving unit 100 is that the partition control module 104 in gate driving unit 200 further includes a fourth transistor T4. The gate of the fourth transistor T4 is electrically connected to the second control signal terminal GOFF, the first electrode of the fourth transistor T4 is electrically connected to the reference low-level signal terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node S. This arrangement is beneficial for timely pulling down the potential of the fourth node S after the third transistor T3 is turned off, preventing erroneous output.
[0055] In this embodiment, the first control signal terminal GON is used to input the first control signal, and the second control signal terminal GOFF is used to input the second control signal. The potentials of the first control signal and the second control signal are opposite. This configuration allows the output of the current scanning signal to be controlled under the control of the first control signal. Furthermore, when the first control signal is low, the second control signal is high, and the fourth transistor T4 is turned on, which can promptly pull down the potential of the fourth node S.
[0056] In the embodiments of this application, the other structures in the gate driving unit 200 are the same as those in the gate driving unit 100, so they will not be described again here.
[0057] Please see Figure 6a and Figure 6b , Figure 6a This is one of the second driving timing diagrams for the gate driving circuit provided in the embodiments of this application; Figure 6b This is a second type of driving timing diagram for a display panel provided in an embodiment of this application. For example... Figure 6a As shown, the first control signal terminal GON corresponding to the gate driving units of stages 1 to n receives a low-level signal and the second control signal terminal GOFF receives a high-level signal. The scan signal (Gout) of the current stage corresponding to the gate driving units of stages 1 to n is output by the scan signal terminal Gout of the current stage. 1... G n The signal is low; the first control signal terminal GON corresponding to the gate drive unit of stage n+1 to stage 4n receives a high-level signal and the second control signal terminal GOFF receives a low-level signal, and the scan signal terminal Gout corresponding to the gate drive unit of stage n+1 to stage 4n sequentially outputs a high-level scan signal (G) for that stage. n+1... G 4n ).
[0058] like Figure 6b As shown, the first control signal terminal GON corresponding to the gate driving units of stages 1 to 3n receives a high-level signal and the second control signal terminal GOFF receives a low-level signal. The scanning signal terminal Gout corresponding to the gate driving units of stages 1 to 3n sequentially outputs a high-level scanning signal (G... 1... G 3n The first control signal terminal GON of the gate driving units from stage 3n+1 to stage 4n receives a low-level signal and the second control signal terminal GOFF receives a high-level signal; the scan signal of the current stage (G) is output from the scan signal terminal Gout of the gate driving units from stage 3n+1 to stage 4n. 3n+1... G 4n () indicates a low-level signal.
[0059] Please see Figure 7 , Figure 7for Figure 2 The diagram shows a third type of circuit for the gate drive unit provided in the document. (See diagram for example.) Figure 7 As shown, this application provides a gate driving unit 300. The difference between the gate driving unit 300 and the gate driving unit 100 / 200 is that the second output module 105 in the gate driving unit 300 further includes a sixth transistor T6. The gate and the first electrode of the sixth transistor T6 are electrically connected to the second global signal terminal Gas2, and the second electrode of the sixth transistor T6 is electrically connected to the local scan signal terminal Gout.
[0060] In the embodiments of this application, the other structures of the display panel 300 are the same as those of the display panels 100 / 200, and therefore will not be described again here.
[0061] Please see Figure 8 , Figure 8 This is a third driving timing diagram for the gate driving circuit provided in an embodiment of this application. (See diagram below.) Figure 8 As shown, the first control signal terminal GON corresponding to the gate driving units of stages 1 to n simultaneously receives a high-level signal and the second control signal terminal GOFF simultaneously receives a low-level signal. The scan signal terminal Gout corresponding to the gate driving units of stages 1 to n simultaneously outputs a high-level scan signal (G... 1... G n ), this level of scanning signal (G 1... G n The output duration is equal to the scan time of one row of pixel units; the first control signal terminal GON corresponding to the gate driving unit from level n+1 to level 4n is sequentially input with a high-level signal and the second control signal terminal GOFF is input with a low-level signal, and the scan signal terminal Gout corresponding to the gate driving unit from level n+1 to level 4n sequentially outputs a high-level scan signal (G) of the current level. n+1... G 4n ).
[0062] Please see Figure 9 , Figure 9 This is a fourth driving timing diagram for the gate driving circuit provided in an embodiment of this application. (See diagram below.) Figure 9 As shown, the driving timing of the gate driving circuit includes a pre-charging stage and an image display stage. In the pre-charging stage t1, the first control signal terminal GON corresponding to the first to nth stage gate driving units simultaneously inputs a high-level signal and the second control signal terminal GOFF inputs a low-level signal. The scanning signal terminal Gout corresponding to the first to nth stage gate driving units simultaneously outputs a high-level scanning signal (Gout) for that stage. 1... G n ), this level of scanning signal (G 1... G n The output duration is equal to the scan time of n rows of pixel units.
[0063] During the image display stage t2, the first control signal terminal GON corresponding to the gate driving units from stage (n+1) to stage 4n sequentially inputs a high-level signal and the second control signal terminal GOFF inputs a low-level signal. The scanning signal terminal Gout corresponding to the gate driving units from stage (n+1) to stage 4n sequentially outputs a high-level scanning signal (G... n+1... G 4n ).
[0064] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 10 As shown, this application embodiment provides a display panel 400, including the gate driving circuits 100 / 200 / 300 as described above. Specifically, the display panel 400 has a display area AA and a non-display area NA, with the non-display area NA surrounding the display area AA;
[0065] The display area AA includes multiple pixel units P, multiple data lines D, and multiple scan lines G. The multiple data lines D and multiple scan lines G are arranged perpendicularly. Each pixel unit P is electrically connected to a data line D and a scan line G respectively. The multiple pixel units P electrically connected to the data lines D form a pixel unit column, and the multiple pixel units P electrically connected to the scan lines G form a pixel unit row. The data lines D are used to input data signals to the pixel units P.
[0066] Please see Figure 11 , Figure 11 for Figure 10 The diagram shows the partitioning of the display panel provided. Figure 11 As shown, the display area AA may include multiple sub-display areas A / B / C / D arranged along the direction closest to the driver chip IC. The number and division of the sub-display areas can be adjusted by those skilled in the art as needed, and this application does not impose any limitations thereon.
[0067] Specifically, the gate driving circuit provided in this application can realize the partitioned driving display of each sub-display area A / B / C / D, and can also perform pre-charging according to different partitions to improve the charging bottleneck, thereby achieving higher resolution.
[0068] In the gate driving circuit and display panel provided in the embodiments of this application, the gate driving circuit sets a first output module 103, a partition control module 104 and a second output module 105 in the gate driving unit. The first output module 103 is used to output the current stage transmission signal; the partition control module 104 is used to control the output of the current stage scan signal; and the second output module 105 is used to output the current stage scan signal. Thus, while ensuring the normal transmission of the transmission signal, the output of the current stage scan signal is controlled, thereby realizing partition driving display, which is beneficial to improving the display effect of the display panel.
[0069] The above provides a detailed description of a gate driving circuit and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A gate drive circuit characterized by comprising: The application relates to a gate drive unit arranged in a multi-stage cascade mode, which comprises an input module, a pull-down control module, a first output module, a partition control module, a second output module and a pull-down module. The input module is electrically connected with a forward scanning signal end, an upper two-stage stage transmission signal end and a first node, and is used for pulling up the potential of the first node. The pull-down control module is electrically connected with the forward scanning signal end, a lower two-stage clock signal end, a reverse scanning signal end, an upper two-stage clock signal end, a first global signal end, a lower two-stage stage transmission signal end, a reference low-level signal end, the first node, a second node and a third node, and is used for controlling the potential of the second node. The first output module is electrically connected with the first node, a current-stage clock signal end and a current-stage stage transmission signal end, and is used for outputting the current-stage stage transmission signal. The partition control module is electrically connected with a first control signal end, the first node and a fourth node, and is used for controlling the output of a current-stage scanning signal on the basis of ensuring the normal downward transmission of a stage transmission signal. The second output module is electrically connected with the fourth node, the current-stage clock signal end and a current-stage scanning signal end, and is used for outputting the current-stage scanning signal. The pull-down module is electrically connected with the first node, the second node, the current-stage stage transmission signal end, the current-stage scanning signal end and the reference low-level signal end, and is used for pulling down the potential of the first node, the current-stage stage transmission signal end and the current-stage scanning signal end.
2. The gate drive circuit according to claim 1, characterized by The first output module comprises a first transistor, the gate of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the current-stage clock signal end, and the second electrode of the first transistor is electrically connected with the current-stage stage transmission signal end.
3. The gate drive circuit according to claim 2, characterized by The first output module further comprises a second transistor, the gate of the second transistor is electrically connected with a reference high-level signal end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the gate of the first transistor.
4. The gate drive circuit according to claim 1, characterized by The partition control module comprises a third transistor, the gate of the third transistor is electrically connected with the first control signal end, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the fourth node.
5. The gate drive circuit according to claim 4, characterized in that The partition control module further comprises a fourth transistor, the gate of the fourth transistor is electrically connected with a second control signal end, the first electrode of the fourth transistor is electrically connected with the reference low-level signal end, and the second electrode of the fourth transistor is electrically connected with the fourth node.
6. The gate drive circuit according to claim 5, characterized by The first control signal end is used for inputting a first control signal, the second control signal end is used for inputting a second control signal, and the potential of the first control signal is opposite to that of the second control signal.
7. The gate drive circuit according to claim 1, characterized by The second output module comprises a fifth transistor, a gate of the fifth transistor is electrically connected with the fourth node, a first electrode of the fifth transistor is electrically connected with the clock signal terminal of the current stage, and a second electrode of the fifth transistor is electrically connected with the scanning signal terminal of the current stage.
8. The gate drive circuit according to claim 7, characterized by The second output module further comprises a sixth transistor, a gate of the sixth transistor and a first electrode of the sixth transistor are electrically connected with the second global signal terminal, and a second electrode of the sixth transistor is electrically connected with the scanning signal terminal of the current stage.
9. The gate drive circuit according to claim 1, characterized by The gate driving unit further comprises a first capacitor, a second capacitor, an input module, a pull-down control module and a pull-down module; One end of the first capacitor is electrically connected with the first node, and the other end of the first capacitor is electrically connected with the reference low voltage signal terminal; One end of the second capacitor is electrically connected with the second node, and the other end of the second capacitor is electrically connected with the reference low voltage signal terminal; The input module comprises a seventh transistor, a gate of the seventh transistor is electrically connected with the up two-stage stage transmission signal terminal, a first electrode of the seventh transistor is electrically connected with the forward scanning signal terminal, and a second electrode of the seventh transistor is electrically connected with the first node; The pull-down control module comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, a gate of the eighth transistor is electrically connected with the forward scanning signal terminal, a first electrode of the eighth transistor is electrically connected with the down two-stage clock signal terminal, and a second electrode of the eighth transistor is electrically connected with the third node; a gate of the ninth transistor is electrically connected with the reverse scanning signal terminal, a first electrode of the ninth transistor is electrically connected with the up two-stage clock signal terminal, and a second electrode of the ninth transistor is electrically connected with the third node; a gate of the tenth transistor is electrically connected with the third node, a first electrode of the tenth transistor is electrically connected with the first global signal terminal, and a second electrode of the tenth transistor is electrically connected with the second node; a gate of the eleventh transistor is electrically connected with the down two-stage stage transmission signal terminal, a first electrode of the eleventh transistor is electrically connected with the reverse scanning signal terminal, and a second electrode of the eleventh transistor is electrically connected with the first node; a gate of the twelfth transistor is electrically connected with the first node, a first electrode of the twelfth transistor is electrically connected with the second node, and a second electrode of the twelfth transistor is electrically connected with the reference low voltage signal terminal; The pull-down module comprises a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, the gate of the thirteenth transistor, the gate of the fourteenth transistor and the gate of the fifteenth transistor are electrically connected with the second node; the first electrode of the thirteenth transistor is electrically connected with the first node; the first electrode of the fourteenth transistor is electrically connected with the level transmission signal terminal of the current stage, and the first electrode of the fifteenth transistor is electrically connected with the scanning signal terminal of the current stage; the second electrode of the thirteenth transistor, the second electrode of the fourteenth transistor and the second electrode of the fifteenth transistor are electrically connected with the reference low voltage signal terminal.
10. A display panel, characterized by, A gate drive circuit comprising any one of claims 1-9.
Citation Information
Patent Citations
GOA circuit
CN107993620A
Display driving circuit and method, display panel and preparation method and device thereof
CN114974114A