Display panel and electronic device

Abstract

The application provides a display panel and an electronic device, comprising a plurality of first sub-pixels and a plurality of second sub-pixels electrically connected to a driving chip through a plurality of first connecting lines and a plurality of second connecting lines respectively, the length of the first connecting lines is greater than the length of the second connecting lines, a plurality of first gate lines electrically connected to the plurality of first sub-pixels and transmitting a plurality of first gate pulses respectively, and a plurality of second gate lines electrically connected to the plurality of second sub-pixels and transmitting a plurality of second gate pulses respectively, each sub-pixel is loaded with a corresponding sub-data signal by a corresponding data line, and the time interval of the gate pulse and the corresponding sub-data signal loaded by the first sub-pixel is greater than the time interval of the gate pulse and the corresponding sub-data signal loaded by the second sub-pixel, so as to effectively balance the optimal charging time length of the far end and the near end and improve the uniformity of the display picture.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to the manufacturing of display device, and specifically to a display panel and an electronic device. BACKGROUND

[0002] As a currently widely used display, liquid crystal display can adopt a three-gate driving architecture to reduce the number of data lines to 1 / 3 of that of a normal driving architecture, increase the number of scan lines to 3 times of that of the normal driving architecture, and reduce the width and charging time of each gate pulse to 1 / 3 of that of the normal driving architecture, considering the cost of a data driving chip. Figure 1 As shown in FIG. 1, especially when displaying a monochrome or mixed color pure color picture, the amplitude of the signal on each data line (each of D1, D2, D3, and Dn) is always in a high-low change state, and the charging time of each row of pixels is insufficient after each gate line (each of G1, G2, G3, and Gn) is turned on to correspond to a row of pixels, which will cause the best charging time of the sub-pixel to be small.

[0003] In the above-mentioned display panel, the gate signal and the data signal generated by the driving chip are generally transmitted from one side of the display panel to the opposite side, which causes the signals at different positions to have different degrees of attenuation, specifically, the degree of attenuation of the signal in the near-end region is much greater than that in the far-end region, resulting in a smaller signal amplitude transmitted to the far-end region, and causing a large difference in color uniformity between the far-end region and the near-end region, which reduces the picture quality of the display panel.

[0004] Therefore, the existing display panel adopting the three-gate driving architecture has the above-mentioned problem of low color uniformity of the picture, which needs to be improved. SUMMARY

[0005] The present application aims to provide a display panel and an electronic device to solve the technical problem of poor color uniformity of a pure color picture in the existing display panel adopting the three-gate driving architecture.

[0006] The present application provides a display panel, comprising a driving chip, a panel main body electrically connected to the driving chip, the panel main body comprising:

[0007] a plurality of sub-pixels, comprising a plurality of first sub-pixels electrically connected to the driving chip through a plurality of first connecting lines, and a plurality of second sub-pixels electrically connected to the driving chip through a plurality of second connecting lines, the length of the first connecting line being greater than the length of the second connecting line;

[0008] a plurality of gate lines, each of the gate lines electrically connected to a corresponding plurality of the sub-pixels to transmit a corresponding gate signal, each of the gate signals comprising a corresponding gate pulse for turning on the corresponding plurality of the sub-pixels, the plurality of the gate lines comprising a plurality of first gate lines electrically connected to the plurality of the first sub-pixels, a plurality of second gate lines electrically connected to the plurality of the second sub-pixels;

[0009] a plurality of data lines, each of the data lines electrically connected to a corresponding plurality of the sub-pixels to transmit a corresponding data signal, the data signal comprising a plurality of sub-data signals respectively corresponding to the plurality of the sub-pixels;

[0010] wherein a time interval in which the gate pulse transmitted by the first gate line overlaps with the corresponding sub-data signal is greater than a time interval in which the gate pulse transmitted by the second gate line overlaps with the corresponding sub-data signal.

[0011] In an embodiment, a time interval between starting points of two gate pulses respectively outputted by two adjacent first gate lines is greater than a time interval between starting points of two gate pulses respectively outputted by two adjacent second gate lines.

[0012] In an embodiment, a pulse width of the gate pulse transmitted by the first gate line is greater than a pulse width of the gate pulse transmitted by the second gate line.

[0013] In an embodiment, the driving chip or the panel body comprises:

[0014] a plurality of gate driving units arranged in cascade, each of the gate driving units electrically connected to a corresponding gate line to transmit a corresponding gate signal;

[0015] a plurality of clock lines, each of the clock lines electrically connected to at least one of the gate driving units to transmit a corresponding clock signal, each of the clock signals comprising a corresponding plurality of clock pulses for generating at least one of the gate pulses;

[0016] wherein the clock pulses of the clock signal corresponding to the first gate line and the clock pulses of the clock signal corresponding to the second gate line are both different for making a time interval in which the gate pulse transmitted by the first gate line overlaps with the corresponding sub-data signal greater than a time interval in which the gate pulse transmitted by the second gate line overlaps with the corresponding sub-data signal.

[0017] In an embodiment, each of the gate pulses is identical to a corresponding one of the clock pulses of the corresponding clock signal.

[0018] In an embodiment, the plurality of gate driving units comprises:

[0019] a plurality of first gate driving units arranged in cascade, each of the first gate driving units being electrically connected to a corresponding first gate line;

[0020] a plurality of second gate driving units arranged in cascade, each of the second gate driving units being electrically connected to a corresponding second gate line;

[0021] wherein a first time interval between starting points of two clock pulses corresponding to two corresponding gate pulses in two clock signals corresponding to two adjacent cascade first gate driving units is greater than a second time interval between starting points of two clock pulses corresponding to two corresponding gate pulses in two clock signals corresponding to two adjacent cascade second gate driving units.

[0022] In an embodiment, the first time interval comprises:

[0023] a first row display time length, equal to a time length during which a plurality of first sub-pixels corresponding to the first row are turned on;

[0024] a first row blanking time length, equal to a time length between an end time at which the plurality of first sub-pixels corresponding to the first row are turned on and a start time at which a plurality of first sub-pixels corresponding to a next first gate driving unit are turned on;

[0025] the second time interval comprises:

[0026] a second row display time length, equal to a time length during which a plurality of second sub-pixels corresponding to the second row are turned on;

[0027] a second row blanking time length, equal to a time length between an end time at which the plurality of second sub-pixels corresponding to the second row are turned on and a start time at which a plurality of second sub-pixels corresponding to a next second gate driving unit are turned on;

[0028] wherein the first row display time length is equal to the second row display time length, and the first row blanking time length is greater than the second row blanking time length.

[0029] In an embodiment, the plurality of gate driving units comprises:

[0030] a plurality of first gate driving units arranged in cascade, each of the first gate driving units being electrically connected to a corresponding first gate line;

[0031] a plurality of second gate driving units arranged in cascade, each of the second gate driving units being electrically connected to a corresponding second gate line;

[0032] The pulse width of the clock pulse corresponding to the corresponding gate pulse in the clock signal corresponding to the first gate driving unit is greater than the pulse width of the clock pulse corresponding to the corresponding gate pulse in the clock signal corresponding to the second gate driving unit.

[0033] In an embodiment, the duty cycle of the clock pulse corresponding to the corresponding gate pulse in the clock signal corresponding to the first gate driving unit is greater than the duty cycle of the clock pulse corresponding to the corresponding gate pulse in the clock signal corresponding to the second gate driving unit.

[0034] The present application also provides an electronic device comprising the display panel as described in any of the above.

[0035] The present application provides a display panel and an electronic device, for a plurality of first sub-pixels located at the "far end" of the display panel and a plurality of second sub-pixels located at the "near end" of the display panel, the time interval during which the gate pulse transmitted by the first gate line overlaps the corresponding sub-data signal is set to be greater than the time interval during which the gate pulse transmitted by the second gate line overlaps the corresponding sub-data signal. It can be considered that the duration during which the first sub-pixel is jointly acted on by the corresponding gate pulse and the corresponding sub-data signal is greater than the duration during which the second sub-pixel is jointly acted on by the corresponding gate pulse and the corresponding sub-data signal, so that under the condition that the data voltages loaded are theoretically equal in size, the optimal charging duration of the far end and the near end can be effectively balanced to improve the display unevenness in the monochrome pure color picture and the color deviation in the mixed color pure color picture. BRIEF DESCRIPTION OF DRAWINGS

[0036] The present application will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings in the following description are only used to explain some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0037] Figure 1 The connection diagram of pixels, gate lines and data lines in the display panel with the three-gate driving architecture provided by the embodiments of the present application.

[0038] Figure 2 The architecture of the display panel provided by the embodiments of the present application and the waveform diagram of the gate signal and the data signal with the existing technical problems.

[0039] Figure 3 The architecture of the display panel provided by the embodiments of the present application and the waveform diagram of the improved gate signal and data signal.

[0040] Figure 4 And Figure 5Two kinds of waveform diagrams of a plurality of gate signals in a display panel provided by the embodiment of the present application.

[0041] Figure 6 The circuit diagram of the gate driving unit provided by the embodiment of the present application.

[0042] Figure 7 And Figure 9 Two kinds of waveform diagrams of a plurality of clock signals in a display panel provided by the embodiment of the present application.

[0043] Figure 8 The specific division mode of the first time interval and the second time interval provided by the embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative work fall within the protection scope of the present application.

[0045] In the description of the present application, the terms "first", "second", and the like are only used for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In addition, it should be noted that the drawings provided are only relatively close structures related to the present application, and some details not closely related to the invention are omitted, the purpose is to simplify the drawings, make the invention points clear at a glance, and not as a limitation on the actual device. Figure 1 The actual device is the same as the drawing, and is not limited.

[0046] In this paper, the phrase "embodiment" means that the specific features, structures or properties described in combination with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment to other embodiments. The person skilled in the art explicitly and implicitly understands that the embodiments described herein can be combined with other embodiments.

[0047] The present application provides a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0048] In an embodiment, as Figure 2 And Figure 3As shown, the display panel 100 comprises a driving chip 10, a panel body 20 electrically connected to the driving chip 10, the panel body 20 comprises: a plurality of sub-pixels 201, a plurality of first sub-pixels 2011 electrically connected to the driving chip 10 through a plurality of first connection lines respectively, a plurality of second sub-pixels 2012 electrically connected to the driving chip 10 through a plurality of second connection lines respectively, the length of the first connection line is greater than the length of the second connection line; a plurality of gate lines 202, each of the gate lines 202 is electrically connected to a corresponding plurality of the sub-pixels 201 to transmit a corresponding gate signal, each of the gate signals comprises a corresponding gate pulse for turning on a corresponding plurality of the sub-pixels 201, the plurality of gate lines 202 comprises a plurality of first gate lines 2021 electrically connected to a plurality of the first sub-pixels 2011, a plurality of second gate lines 2022 electrically connected to a plurality of the second sub-pixels 2012; a plurality of data lines 203, each of the data lines 203 is electrically connected to a corresponding plurality of the sub-pixels 201 to transmit a corresponding data signal, the data signal comprises a plurality of sub-data signals corresponding to a plurality of the sub-pixels 201 respectively; wherein the time interval of the gate pulse (referred to as the first gate pulse) transmitted by the first gate line 2021 and the corresponding sub-data signal overlaps, which is greater than the time interval of the gate pulse (referred to as the second gate pulse) transmitted by the second gate line 2022 and the corresponding sub-data signal overlaps.

[0049] Wherein, the panel body 20 can comprise a display area 01 for displaying a picture and a non-display area 01 for setting a non-transparent period, the non-display area 01 is provided with a plurality of traces electrically connected to a plurality of sub-pixels 201 in the display area 01, the other end of the plurality of traces can be electrically connected with the above-mentioned driving chip 10 and main board 022 in turn, the image signal generated by the main board can generate a plurality of driving signals for driving a plurality of sub-pixels 201 to emit light through the driving chip 10, and the plurality of driving signals can be transmitted to a plurality of sub-pixels 201 through the plurality of traces, the plurality of traces can be arranged in a fan shape 021 to facilitate the connection between the driving chip 10 with smaller size and the panel body 20 with larger size. Further, the display panel 100 can further comprise a gate driving module 204 and a source driving module 101, the source driving module 101 can be integrated in the above-mentioned driving chip 10, the gate driving module 204 can be integrated in the above-mentioned driving chip 10 or arranged in the above-mentioned non-display area 01, hereinafter the latter is taken as an example for description, that is, it can be considered that the gate driving module 204 can also be electrically connected to the above-mentioned driving chip 10 through the corresponding traces to obtain the corresponding signals.

[0050] For ease of description, this example illustrates a configuration where multiple sub-pixels 201 are arranged along both row and column directions, with each gate line 202 electrically connected to a corresponding row of sub-pixels 201 and each data line 203 electrically connected to a corresponding column of sub-pixels 201. The number of source driver modules can be greater than 1. Figure 2 (Taking 4 as an example) Each source driver module can be connected to multiple data lines 203 to transmit corresponding data signals to each data line 203. Multiple sub-data signals within each data signal may or may not have time intervals. If there is a time interval, each sub-data signal can be called a data pulse, and the amplitude of the pulse is equivalent to the data voltage acting on the corresponding sub-pixel 201. If there is no time interval, multiple sub-data signals are connected in series. Specifically, the gate driver module 204 can be connected to multiple gate lines 202 to transmit corresponding gate signals to the multiple gate lines 202 respectively. The gate pulses in different gate signals are in different time periods to sequentially turn on multiple rows of sub-pixels 201. The time period of each sub-data signal and the time period of the corresponding gate pulse should overlap, so that when the corresponding sub-pixel 201 is turned on, the corresponding sub-data signal is also loaded onto the sub-pixel 201, thereby charging the sub-pixel 201. The area R of the overlapping region R between each sub-data signal and the corresponding gate pulse can be defined as the optimal charging time for the sub-pixel 201.

[0051] For ease of description, the portion of the panel body 20 closer to the driver chip 10 is referred to as the "near end," and the portion closer to the driver chip 10 is referred to as the "far end." It should be noted that, since the length of the first connecting line in this embodiment is greater than the length of the second connecting line, meaning the signal attenuation experienced when transmitted to the first sub-pixel 2011 is greater than the attenuation experienced when transmitted to the second sub-pixel 2012, it can be considered that multiple first sub-pixels 2011 are located at the "far end," and multiple second sub-pixels 2012 are located at the "near end."

[0052] Specifically, such as Figure 2As shown, the plurality of sub-pixels 201 can be divided into 3*3 nine areas (A1 to A5) as divided by the dotted lines. For the gate signal, on the one hand, the attenuation degree of the signal obtained by the gate driving module 204 away from the driving chip 10 is increasingly large, and on the other hand, in the direction away from the gate driving module 204, the attenuation degree of the gate signal is increasingly large. Taking the double-sided driving as an example, it can be considered that the sub-pixel 201 at the "remote end" (for example, A1, A2) is more seriously attenuated by the loaded gate pulse p1 than the sub-pixel 201 at the "near end" (for example, A4, A5), and the sub-pixel 201 close to the "middle" (for example, A2, A5) in the horizontal direction is more seriously attenuated by the loaded gate pulse p1 than the sub-pixel 201 close to the "two sides" (for example, A1, A3 and A4) in the horizontal direction (i.e., closer to the gate driving module 204). For the data signal, only the attenuation degree of the data signal in the direction away from the driving chip 10 (i.e., in the direction away from the source driving module) is increasingly large, and it can be considered that the sub-pixel 201 at the "remote end" is more seriously attenuated by the loaded sub-data signal p2 than the sub-pixel 201 at the "near end".

[0053] Therefore, it can be considered that the optimal charging duration of the sub-pixel 201 at the "remote end" and close to the "middle" in the horizontal direction is the smallest, and the optimal charging duration of the sub-pixel 201 at the "near end" and close to the "two sides" in the horizontal direction is the largest. Further, it is found through measurement that the signal attenuation degree of the "near end" is much larger than that of the "remote end", causing the signal attenuation to occur greatly at the "near end", causing the optimal charging of the sub-pixel 201 at the "remote end" to decrease sharply, and causing the picture display to be uneven in the two areas.

[0054] It can be understood that, as Figure 3As shown, in this embodiment, multiple first gate lines 2021 electrically connected to multiple first sub-pixels 2011 (e.g., located in A1, A2) transmit multiple first gate pulses p11 respectively, and multiple second gate lines 2022 electrically connected to multiple second sub-pixels 2012 (e.g., located in A4, A5) transmit multiple second gate pulses p12 respectively. The duration of overlap between the first gate pulse and the corresponding sub-data signal (referred to as the first duration t1) is set to be greater than the duration of overlap between the gate pulse transmitted by the second gate line 2022 and the corresponding sub-data signal. The duration (referred to as the second duration t2) is such that, theoretically, for the same data voltage, the duration of the first gate pulse and the sub-data signal acting together on the first sub-pixel 2011 (i.e., the first duration t1) is greater than the duration of the second gate pulse and the sub-data signal acting together on the second sub-pixel 2012 (i.e., the second duration t2). This allows for effective balancing of the optimal charging duration at near and far ends under theoretically equal data voltages, thereby improving the uneven display in monochrome pure color images and the color shift in mixed pure color images.

[0055] In one embodiment, such as Figure 4 As shown, the time interval between the starting points of the two gate pulses (i.e., the two first gate pulses p111 and p112, respectively contained in the two first gate signals gate11 and gate12) output by two adjacent first gate lines 2021 is greater than the time interval between the starting points of the two gate pulses (i.e., the two second gate pulses p121 and p122, respectively contained in the two second gate signals gate21 and gate22) output by two adjacent second gate lines 2022. It should be noted that, as Figure 2 and Figure 3 As shown, in order to ensure that each sub-data signal can be loaded to the corresponding sub-pixel 201, the starting point of the corresponding gate pulse can be located before the starting point of the corresponding sub-data signal (determined according to the duration of the sub-data signal) to enable the corresponding sub-pixel 201 in advance. In order to ensure that the sub-data signal can be fully loaded to the corresponding sub-pixel 201, the ending point of the corresponding sub-data signal (determined according to the duration of the sub-data signal) can be located after the ending point of the corresponding gate signal.

[0056] Specifically, the "two adjacent first gate lines 2021" in this embodiment can represent two first gate lines 2021 electrically connected to two rows of first sub-pixels 2011 respectively, and the starting points of the corresponding two first gate pulses are different to sequentially turn on the two rows of first sub-pixels 2011. Similarly, the "two adjacent second gate lines 2022" also have different starting points of the corresponding two second gate pulses to sequentially turn on two rows of second sub-pixels 2012. It can be considered that the time interval between the starting points of the two gate pulses corresponding to any two adjacent rows of sub-pixels 201 in the prior art can be equal, and the pulse width of all gate pulses can be equal.

[0057] It can be understood that, due to the time interval between the starting points of the two first gate pulses corresponding to the adjacent two rows of first sub-pixels 2011 in this embodiment being greater than the time interval between the starting points of the two second gate pulses corresponding to the adjacent two rows of second sub-pixels 2012, the starting point of the first gate pulse corresponding to the first sub-pixel 2011 located at the "far end" is equivalent to moving in the positive direction of the time axis compared with the second gate pulse corresponding to the second sub-pixel 2012 located at the "near end". It can be considered that the first gate pulse as a whole moves in the positive direction of the time axis, so that the distance between the starting point of the first gate pulse and the starting point of the corresponding sub-data signal is reduced. If the difference in the pulse width of different gate pulses is not considered, the first gate pulse and the corresponding sub-data signal can have a longer overlapping time interval, so that the first sub-pixel 2011 has a longer optimal charging time compared with the second sub-pixel 2012, thereby effectively balancing the optimal charging time of the far end and the near end to improve the display unevenness in the monochrome pure color picture and the color deviation in the mixed pure color picture.

[0058] Further, compared with the prior art, it can be considered that the total time length of sequentially turning on all rows of sub-pixels 201 in this embodiment does not change. If the time interval between the starting points of any two adjacent gate pulses in the prior art is t0, it can be considered that the time interval between the starting points of the two first gate pulses in this embodiment is t0+△t (△t is greater than 0), and the time interval between the starting points of the two second gate pulses is t0-△t. Further, the number of time intervals of t0+△t can be equal to the number of time intervals of t0-△t, thereby ensuring that the total time length of sequentially turning on all rows of sub-pixels 201 in this embodiment does not change.

[0059] In an embodiment, as Figure 5As shown, the pulse width of the gate pulse transmitted by the first gate line 2021 is greater than the pulse width of the gate pulse transmitted by the second gate line 2022. That is, the pulse width of the first gate pulse corresponding to the first sub-pixel 2011 is greater than the pulse width of the second gate pulse corresponding to the second sub-pixel 2012. It can be understood that, in the embodiment, the pulse width of the first gate pulse is set to be greater, which can be considered as further extending the first gate pulse in the positive direction of the time axis, so that the distance between the end of the first gate pulse and the end of the corresponding sub-data signal is reduced. If the difference in the starting time of different gate pulses is not considered, the first gate pulse and the corresponding sub-data signal can have a longer overlapping time interval, so that the first sub-pixel 2011 has a longer optimal charging time compared with the second sub-pixel 2012, thereby effectively balancing the optimal charging time of the far end and the near end, and improving the display unevenness in the monochrome pure color picture and the color deviation in the mixed pure color picture.

[0060] In an embodiment, in combination with Figure 2 、 Figure 3 and Figure 6 As shown, the driving chip 10 or the panel body 20 includes: a plurality of gate driving units 2041 (included in the above-mentioned gate driving module 204, and here taken as an example that the multi-stage gate driving unit 2041 is arranged in the non-display area 01 of the panel body 20), which are cascaded, and each of the gate driving units 2041 is electrically connected to the corresponding gate line 202 to transmit the corresponding gate signal (output by the corresponding GN terminal); a plurality of clock lines 2042 (included in the above-mentioned gate driving module 204), each of the clock lines 2042 is electrically connected to at least one of the corresponding gate driving units 2041 to transmit the corresponding clock signal (loaded to the corresponding CK terminal), as shown in Figure 7 Each of the clock signals includes a plurality of corresponding clock pulses p3 for generating at least one of the corresponding gate pulses; wherein the clock pulse of the clock signal corresponding to the first gate line 2021 (referred to as the first clock pulse p31) and the clock pulse of the clock signal corresponding to the second gate line 2022 (referred to as the second clock pulse p32) are different, so as to make the time interval of the gate pulse transmitted by the first gate line 2021 and the corresponding sub-data signal overlapping greater than the time interval of the gate pulse transmitted by the second gate line 2022 and the corresponding sub-data signal overlapping.

[0061] In the embodiment, the specific circuit of the gate driving unit 2041 is not limited, Figure 6It is only exemplified that the gate drive unit 2041 is only loaded with one clock signal, in fact, it can be loaded with multiple clock signals, each gate drive unit 2041 is loaded with a corresponding clock signal, and cascaded with the last gate drive unit 2041 to obtain the gate signal of the last stage as the stage transmission signal (loaded to the corresponding G(N-1) end) of the current stage, and the stage transmission signal of the first stage gate drive unit 2041 can be the starting signal directly loaded, and each gate drive unit 2041 generates a corresponding gate signal under the action of the corresponding clock signal and the corresponding stage transmission signal.

[0062] Specifically, as shown in Figure 7 Each of the multiple clock signals ck acting on the multi-stage gate drive unit 2041 can include a plurality of clock pulses arranged in sequence and at intervals, wherein at least one clock pulse is used to control the state (including but not limited to the time period) of the generated gate pulse, based on which, in the embodiment, the first clock pulse (contained in the first clock signal ck1, including ck11 and ck12 acting on the adjacent two stages of the first gate drive circuit) used to generate the first gate pulse and the second clock pulse (contained in the second clock signal ck2, including ck21 and ck22 acting on the adjacent two stages of the first gate drive circuit) used to generate the second gate pulse are different, and the difference can realize the above-mentioned "the time interval of the overlap of the gate pulse transmitted by the first gate line 2021 and the corresponding sub-data signal is greater than the time interval of the overlap of the gate pulse transmitted by the second gate line 2022 and the corresponding sub-data signal", thereby effectively balancing the far-end and near-end optimal charging time, to improve the display unevenness phenomenon in the monochrome pure color picture and the color deviation phenomenon in the mixed color pure color picture.

[0063] It should be noted that the embodiment can include multiple clock signal groups, each clock signal group can include multiple clock signals, and the starting points of the adjacent two clock signals in the same clock signal group can be the same, wherein the clock signals at the same position in each clock signal group can be electrically connected to load the same clock signal, that is, there will be multiple rows of sub-pixels 201 loaded with the same clock signal, but as can be seen from the above analysis, even if loaded with the same clock signal, the gate pulse required by the sub-pixels 201 in different rows is determined by the clock pulses in different time periods of the clock signal, so it can be considered that the different clock pulses (at least one of the time interval of the starting points of the adjacent two clock pulses and the pulse width) in the same clock signal acting on different stages of the gate drive circuit can be set to be different to generate different gate pulses.

[0064] In an embodiment, as shown in Figure 7 Each of the gate pulses is the same as a corresponding clock pulse in the corresponding clock signal. Specifically,Figure 6 This may include multiple transistors (T11, TrQ, TrG, T51 to T54, T32 and T42, T21, T31 and T21) and bootstrap capacitor Cb. For specific connection details, please refer to [reference needed]. Figure 6 ,refer to Figure 6 It can be seen that when T31 is off and T21 is on, the clock signal loaded at the CK terminal can be transmitted to the GN terminal through T21 to form the gate signal. During this period, the clock signal can be considered to include at least one corresponding clock pulse, which can be used as the corresponding gate pulse in the gate signal; that is, the two can be the same. Therefore, by further differentiating the first clock pulse and the second clock pulse based on existing technology, a first gate pulse and a second gate pulse with the above differences can be achieved.

[0065] In one embodiment, such as Figure 3 As shown, the multi-stage gate driving unit 2041 includes: multiple first gate driving units 20411, cascaded together, each first gate driving unit 20411 electrically connected to a corresponding first gate line 2021; and multiple second gate driving units 20412, cascaded together, each second gate driving unit 20412 electrically connected to a corresponding second gate line 2022; wherein, as... Figure 7 As shown, in the two clock signals corresponding to the two adjacent cascaded first gate driving units 20411, the first time interval T1 between the starting points of the two (first) clock pulses p31 corresponding to the two gate pulses is greater than the second time interval T2 between the starting points of the two (second) clock pulses p32 corresponding to the two gate pulses in the two adjacent cascaded second gate driving units 20412.

[0066] As discussed above, each first clock pulse (included in the corresponding first clock signal) is used to generate a first gate pulse, and each second clock pulse (included in the corresponding second clock signal) is used to generate a second gate pulse. Therefore, in this embodiment, by setting the first time interval T1 between the starting points of the first clock pulses corresponding to two adjacent first gate driving units 20411 to be greater than the second time interval T2 between the starting points of the second clock pulses corresponding to two adjacent second gate driving units 20412, it is possible to achieve a time interval between the starting points of two adjacent first gate pulses that is greater than the time interval between the starting points of two adjacent second gate pulses. For example, when there are at least two types of clock signals used for the gate driving unit 2041, the above effect can be achieved by reasonably setting the clock pulse of at least one of the clock signals; for example, when there is only one type of clock signal used for the gate driving unit 2041, the above effect can be achieved by reasonably setting the clock pulse of that one clock signal.

[0067] Specifically, such as Figure 7 As shown, in conjunction with the above discussion, this section takes the example of each gate pulse being the same as the corresponding clock pulse in the corresponding clock signal. That is, each first clock pulse can be set to be consistent with the time period of the first gate pulse it generates, and each second clock pulse can be set to be consistent with the time period of the second gate pulse it generates. In other words, the first time interval T1 can be considered to be equal to t0 + Δt, and the second time interval T2 can be equal to t0 - Δt.

[0068] Furthermore, among the multiple third clock pulses p33 corresponding to the multiple sub-pixels 201 located between the "near end" and the "far end" (referred to as multiple third sub-pixels 201), the third time interval T3 between the starting points of two adjacent third clock pulses ck3 (contained in ck31 and ck32 respectively) can be between the first time interval T1 and the second time interval T2, or it can be equal to the first time interval T1 or the second time interval T2. Figure 7 The example shown is that the third time interval T3 is equal to the first time interval T1.

[0069] In one embodiment, such as Figure 8As shown, the first time interval T1 includes: a first row display duration t11, equal to the duration of the opening of the corresponding plurality of the first sub-pixels 2011; a first row blanking duration t12, equal to the duration between the end time of the opening of the corresponding plurality of the first sub-pixels 2011 and the start time of the opening of the plurality of the first sub-pixels 2011 corresponding to the next stage of the first gate driving unit 20411; the second time interval T2 includes: a second row display duration t21, equal to the duration of the opening of the corresponding plurality of the second sub-pixels 2012; a second row blanking duration t22, equal to the duration between the end time of the opening of the corresponding plurality of the second sub-pixels 2012 and the start time of the opening of the plurality of the second sub-pixels 2012 corresponding to the next stage of the second gate driving unit 20412; wherein the first row display duration t11 is equal to the second row display duration t21, and the first row blanking duration t12 is greater than the second row blanking duration t22.

[0070] Specifically, the plurality of sub-pixels 201 located in the upper half of the display panel 100 are divided into a plurality of first sub-pixels 2011 to be set as "remote", each corresponding to the first time interval T1, and the plurality of sub-pixels 201 located in the lower half of the display panel 100 are divided into a plurality of second sub-pixels 2012 to be set as "remote", each corresponding to the second time interval T2. As discussed above, the row display duration is used to determine the time required for the opening of the corresponding row of sub-pixels 201, and the corresponding row blanking duration is used to determine the time interval between the end time of the opening of the corresponding row of sub-pixels 201 and the start time of the opening of the next row of sub-pixels 201. In this embodiment, the first row display duration t11 is set to be equal to the second row display duration t21, so as to reduce the risk that a certain row or a certain number of rows of sub-pixels 201 cannot be fully opened. In addition, the first row blanking duration t12 is set to be greater than the second row blanking duration t22, so as to achieve that the first time interval T1 is greater than the second time interval T2.

[0071] In an embodiment, as shown in Figure 7 and Figure 9 As shown, the pulse width W1 of the (first) clock pulse corresponding to the corresponding (first) gate pulse in the (first) clock signal corresponding to the first gate driving unit 20411 is greater than the pulse width W2 of the (second) clock pulse corresponding to the corresponding gate pulse in the (second) clock signal corresponding to the second gate driving unit 20412. Similarly, in this embodiment, by setting the pulse width W1 of the first clock pulse to be greater than the pulse width W2 of the second clock pulse, the pulse width of the first gate pulse can be made greater than the pulse width of the second gate pulse.

[0072] Specifically, as shown in Figure 9As shown, in combination with the above discussion, here, taking an example that each gate pulse is equal to a corresponding clock pulse in a corresponding clock signal, for example, the periods of the clock signals are equal, for example, equal to 12H (H is equal to 2.47us, which can be understood as the sum of the row display time length and the row blanking time length in the prior art, that is, the definition of t0 above), the pulse width W1 of the first clock pulse, the pulse width W2 of the second clock pulse, and the pulse width W3 of the third clock pulse corresponding to the plurality of sub-pixels 201 between the "proximal end" and the "distal end" (referred to as a plurality of third sub-pixels 201) can be equal to 6.0H, 5.52H and 5.16H, respectively. Of course, the periods of different clock signals can also be different, which are not limited in the present embodiment, as long as the size relationship of the above pulse widths is met.

[0073] In an embodiment, as shown in Figure 7 and Figure 9 As shown, the duty cycle d1 of the (first) clock pulse in the clock signal corresponding to the corresponding gate pulse corresponding to the first gate drive unit 20411 is greater than the duty cycle d2 of the (second) clock pulse in the clock signal corresponding to the corresponding gate pulse corresponding to the second gate drive unit 20412. Specifically, as shown in Figure 9 The duty cycle d1 of the first clock pulse, the duty cycle d2 of the second clock pulse, and the duty cycle d3 of the third clock pulse corresponding to the plurality of sub-pixels 201 between the "proximal end" and the "distal end" (referred to as a plurality of third sub-pixels 201) can be equal to 50%, 43%, and 46%, respectively. Here, the pulse width W1 of the first clock pulse, the pulse width W3 of the third clock pulse, and the pulse width W2 of the second clock pulse are equal to 6.0H, 5.52H and 5.16H, respectively, which can be calculated based on the same period of the clock signals.

[0074] Wherein, in combination with the above definition of the period of the pulse signal, here, the period of each pulse signal in the present embodiment can also be considered to be equal to k times of the corresponding time interval (including but not limited to the first time interval T1 or the second time interval T2), k is a positive integer greater than 1, here, taking an example that k is equal to 12. It should be noted that, Figure 7The first pulse signal and the third pulse signal can be considered to have a period equal to 12*T1, and the second pulse signal can be considered to have a period equal to 12*T2, and further, considering the difference in duty cycles, the pulse width W1 of the first clock pulse, the pulse width W3 of the third clock pulse, and the pulse width W2 of the second clock pulse can be equal to 50%*12*T1, 46%*12*T1, and 43%*12*T2, respectively, i.e., 6*T1, 5.52*T1, and 5.16*T2, respectively.

[0075] The present application also provides an electronic device comprising the display panel as described in any of the above.

[0076] The present application provides a display panel and an electronic device, for a plurality of first sub-pixels located at a "far end" of the display panel and a plurality of second sub-pixels located at a "near end" of the display panel, by setting a time interval during which the gate pulse transmitted by the first gate line overlaps the corresponding sub-data signal to be greater than a time interval during which the gate pulse transmitted by the second gate line overlaps the corresponding sub-data signal, it can be considered that the first sub-pixels are jointly acted on by the corresponding gate pulse and the corresponding sub-data signal for a longer time than the second sub-pixels are jointly acted on by the corresponding gate pulse and the corresponding sub-data signal, so that under the condition of being loaded with theoretically equal-sized data voltages, the optimal charging time of the far and near ends can be effectively balanced to improve the display unevenness in a monochrome pure color picture and the color deviation in a mixed-color pure color picture.

[0077] The display panel and the electronic device provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper, and the above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof; those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some technical features thereof can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, The panel body includes a driver chip and a panel body electrically connected to the driver chip. The panel body includes: Multiple sub-pixels include multiple first sub-pixels electrically connected to the driving chip via multiple first connection lines, and multiple second sub-pixels electrically connected to the driving chip via multiple second connection lines, wherein the length of the first connection line is greater than the length of the second connection line; Multiple gate lines, each gate line being electrically connected to a corresponding plurality of sub-pixels to transmit a corresponding gate signal, each gate signal including a corresponding gate pulse for turning on the corresponding plurality of sub-pixels, the multiple gate lines including multiple first gate lines electrically connected to a plurality of first sub-pixels and multiple second gate lines electrically connected to a plurality of second sub-pixels; Multiple data lines, each of which is electrically connected between the driver chip and the corresponding multiple sub-pixels, to transmit a corresponding data signal, the data signal including multiple sub-data signals respectively corresponding to the multiple sub-pixels; Wherein, the time interval between the gate pulse transmitted by the first gate line and the corresponding sub-data signal overlapping is greater than the time interval between the gate pulse transmitted by the second gate line and the corresponding sub-data signal overlapping; The time interval between the starting points of the two gate pulses output by the two adjacent first gate lines is greater than the time interval between the starting points of the two gate pulses output by the two adjacent second gate lines.

2. The display panel as described in claim 1, characterized in that, The pulse width of the gate pulse transmitted by the first gate line is greater than the pulse width of the gate pulse transmitted by the second gate line.

3. The display panel as described in claim 1 or 2, characterized in that, The panel body includes: A multi-stage gate driving unit is cascaded, and each gate driving unit is electrically connected to the corresponding gate line to transmit the corresponding gate signal; Multiple clock lines, each of which is electrically connected to at least one corresponding gate driving unit to transmit a corresponding clock signal, each of which includes a plurality of corresponding clock pulses to generate at least one corresponding gate pulse; The clock pulse corresponding to the clock signal of the first gate line and the clock pulse corresponding to the clock signal of the second gate line are different, so that the time interval for the gate pulse transmitted by the first gate line to overlap with the corresponding sub-data signal is greater than the time interval for the gate pulse transmitted by the second gate line to overlap with the corresponding sub-data signal.

4. The display panel as described in claim 3, characterized in that, Each of the gate pulses is the same as a corresponding clock pulse in the corresponding clock signal.

5. The display panel as described in claim 3, characterized in that, The multi-stage gate drive unit includes: A multi-stage first gate driving unit is cascaded, and each first gate driving unit is electrically connected to the corresponding first gate line; A multi-stage second gate driving unit is cascaded, and each second gate driving unit is electrically connected to the corresponding second gate line; Wherein, the first time interval between the start points of the two clock signals corresponding to the two adjacent cascaded first gate driving units, respectively, corresponding to the two clock pulses of the two gate pulses, is greater than the second time interval between the start points of the two clock signals corresponding to the two adjacent cascaded second gate driving units, respectively, corresponding to the two clock pulses of the two gate pulses.

6. The display panel as described in claim 5, characterized in that, The first time interval includes: The display duration of the first row is equal to the duration during which the corresponding multiple first sub-pixels are enabled; The blanking duration of the first row is equal to the duration between the end time of the corresponding multiple first sub-pixels being turned on and the start time of the multiple first sub-pixels being turned on corresponding to the first gate driving unit of the next level. The second time interval includes: The duration displayed in the second row is equal to the duration during which the corresponding multiple second sub-pixels are enabled; The blanking duration of the second row is equal to the duration between the end time of the corresponding multiple second sub-pixels being turned on and the start time of the multiple second sub-pixels being turned on corresponding to the next level second gate driving unit; Wherein, the display duration of the first row is equal to the display duration of the second row, and the blanking duration of the first row is greater than the blanking duration of the second row.

7. The display panel as described in claim 3, characterized in that, The multi-stage gate drive unit includes: A multi-stage first gate driving unit is cascaded, and each first gate driving unit is electrically connected to the corresponding first gate line; A multi-stage second gate driving unit is cascaded, and each second gate driving unit is electrically connected to the corresponding second gate line; Wherein, the pulse width of the clock pulse corresponding to the corresponding gate pulse in the clock signal corresponding to the first gate driving unit is greater than the pulse width of the clock pulse corresponding to the corresponding gate pulse in the clock signal corresponding to the second gate driving unit.

8. The display panel as described in claim 7, characterized in that, The duty cycle of the clock pulse corresponding to the corresponding gate pulse in the clock signal corresponding to the first gate driving unit is greater than the duty cycle of the clock pulse corresponding to the corresponding gate pulse in the clock signal corresponding to the second gate driving unit.

9. An electronic device, characterized in that, Includes the display panel as described in any one of claims 1 to 8.

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