Using temporary parity to generate multiple pass programming of memory cells

Abstract

The present disclosure relates to using temporary parity to generate multiple pass programming of memory cells. Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and first and second user data portions are directed to the first and second blocks. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second blocks are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a second programming pass of the portions of the first and second blocks completing. The temporary parity data is saved in the buffer until a second programming pass of the first and second blocks.

Description

Technical Field

[0001] This disclosure generally relates to writing data into a memory device in multiple passes, and more specifically, to programming memory cells in multiple passes using temporary parity data. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In this example, a method is described. The method includes: receiving one or more write commands containing user data, wherein the one or more write commands are directed to a portion of a memory comprising a first block and a second block, each comprising multiple portions, and wherein a first portion of the user data is directed to the first block and a second portion of the user data is directed to the second block; generating first temporary parity data using the first portion of the user data and the second portion of the user data; storing the first temporary parity data, the first portion of the user data, and the second portion of the user data in a buffer; programming a first portion of the first block with the first portion of the user data, wherein the programming includes a first programming pass and a second programming pass; programming a first portion of the second block with the second portion of the user data, wherein the programming includes a first programming pass and a second programming pass; and invalidating the first portion of the user data in the buffer in response to completion of the second pass of programming the first portion of the first block and the first portion of the second block. The first temporary parity data is held in the buffer until the second pass of programming the first block and the second block is completed.

[0004] In this example, a non-transitory computer-readable storage medium including instructions is described. When executed by a processing device, the instructions cause the processing device to: receive one or more write commands containing user data, wherein the one or more write commands are directed to a portion of a memory comprising a first block and a second block, each comprising multiple portions, and wherein a first portion of the user data is directed to the first block and a second portion of the user data is directed to the second block; generate first temporary parity data using the first portion of the user data and the second portion of the user data; store the first temporary parity data, the first portion of the user data, and the second portion of the user data in a buffer; program a first portion of the first block using the first portion of the user data, wherein the programming includes a first programming pass and a second programming pass; program a first portion of the second block using the second portion of the user data, wherein the programming includes a first programming pass and a second programming pass; and invalidate the first portion and the second portion of the user data in the buffer in response to the completion of the second pass of programming the first portion of the first block and the first portion of the second block. The first temporary parity data is stored in the buffer until the second pass of programming the first block and the second block is completed.

[0005] In this example, a system is described. The system includes: a plurality of memory devices; and a processing device operatively coupled to the plurality of memory devices. The processing device is configured to: receive one or more write commands containing user data, wherein the one or more write commands are directed to a portion of a memory comprising a first block and a second block, each comprising a plurality of portions, and wherein a first portion of the user data is directed to the first block and a second portion of the user data is directed to the second block; generate first temporary parity data using the first portion of the user data and the second portion of the user data; store the first temporary parity data, the first portion of the user data, and the second portion of the user data in a buffer; program a first portion of the first block using the first portion of the user data, wherein the programming includes a first programming pass and a second programming pass; program a first portion of the second block using the second portion of the user data, wherein the programming includes a first programming pass and a second programming pass; and invalidate the first portion of the user data in the buffer in response to completion of the second pass of programming the first portion of the first block and the first portion of the second block. The first temporary parity data is stored in the buffer until the second pass of programming the first block and the second block is completed. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of an instance multi-pass programming system using temporary parity checking, according to some embodiments of the present disclosure.

[0009] Figure 3 This is another block diagram of an instance-multiple-times programming system using temporary parity checks, according to some embodiments of the present disclosure.

[0010] Figure 4 This is another block diagram of an instance-multiple-times programming system using temporary parity checks, according to some embodiments of the present disclosure.

[0011] Figure 5 This is another block diagram of an instance-multiple-times programming system using temporary parity checks, according to some embodiments of the present disclosure.

[0012] Figure 6 This is another block diagram of an instance-multiple-times programming system using temporary parity checks, according to some embodiments of the present disclosure.

[0013] Figure 7 This is another block diagram of an instance-multiple-times programming system using temporary parity checks, according to some embodiments of the present disclosure.

[0014] Figure 8 This is a flowchart of an example method for generating programming of memory cells using temporary parity in multiple passes, according to some embodiments of the present disclosure.

[0015] Figure 9 This is another flowchart of a method for generating instances of programming memory cells using temporary parity in multiple passes, according to some embodiments of the present disclosure.

[0016] Figure 10 This is a block diagram of an example computer system operable in accordance with embodiments of this disclosure. Detailed Implementation

[0017] This disclosure relates to the use of temporary parity generation in multiple passes within a memory subsystem to program memory cells. The memory subsystem may be a storage device, a memory module, or a mixture of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0018] Memory devices can be non-volatile memory devices. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A die in a package may be assigned to one or more channels to communicate with the memory subsystem controller. Each die may consist of one or more planes. Planes may be divided into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane consists of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0019] Depending on the cell type, a cell can store one or more binary information bits and has various logic states related to the number of storage bits. Logic states can be represented by binary values ​​such as "0" and "1" or combinations of such values. Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC can store one information bit and has two logic states.

[0020] In conventional memory systems, defects introduced during manufacturing and operation can hinder proper programming of memory blocks. When attempting to program a memory block containing defects, user data written to the memory block is lost upon programming failure. To preserve data, user data programmed into the memory block is stored in a buffer until successful programming. Additionally, when programming multiple memory blocks and avoiding delays between programming sessions (e.g., starting programming the next memory block while scanning for data integrity checks on the current block), extra buffers are used to store the start of the next block before the current block is complete. For example, a buffer of 10 SLC blocks (8 SLC blocks to cover the current group of 2 QLC blocks and 2 SLC blocks to start the next group of 2 QLC blocks) can be used when programming a consecutive group of 2 QLC blocks to ensure no data is lost due to defects. If the memory block to be programmed is not fully covered, defects in the memory block can cause programming failures and an increased uncorrectable bit error rate (UBER). However, for QLC blocks without defects, a buffer of 4 SLC blocks is redundant. Therefore, it is necessary to weigh the cost of over-deploying UBER against providing full buffer coverage of memory blocks and concurrent buffer coverage of contiguous memory blocks.

[0021] This disclosure addresses the aforementioned and other drawbacks by replacing at least a portion of the user data with a combination of buffered user data and temporary parity data. Temporary parity data occupies less space than user data and allows user data to be cleared from the buffer more quickly, thereby requiring fewer buffer blocks. Because fewer buffer blocks are needed, using temporary parity data reduces the cost of over-deployment. Furthermore, there is a generally higher UBER associated with a smaller buffer size, as the risk of data loss only exists when errors exceed the error correction capability of the temporary parity data.

[0022] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such components.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drivers, universal flash memory (UFS) drivers, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing device.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0026] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, host system 120 uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on volume resistance variations along with a stacked cross-gate format data access array. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without first erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Although a non-volatile memory device, such as a NAND-type memory (e.g., 2D NAND, 3D NAND) and a 3D cross-point array of non-volatile memory cells, is described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled on the command bus by controller 115). The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0032] The memory subsystem controller 115 may include a processing means 117 (processor) configured to execute instructions stored in local memory 119. In the illustrative example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110, and includes handling communication between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem 110).

[0034] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, discard item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0035] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0036] In some embodiments, memory device 130 includes a local media controller 135, which, together with memory subsystem controller 115, operates to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 includes a temporary parity generation component 113 capable of generating temporary parity data during multiple programming passes. In some embodiments, the controller 115 includes at least a portion of the temporary parity generation component 113. For example, the controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the temporary parity generation component 113 is part of the host system 120, an application program, or an operating system.

[0038] The temporary parity generation component 113 can generate temporary parity data during the programming of a memory block and can invalidate user data in a buffer so that the buffer is saved for programming subsequent memory blocks. Further details regarding the operation of the temporary parity generation component 113 are described below.

[0039] Figure 2 This is a block diagram of an instance of a multi-pass programming system 200 that includes a temporary parity generation component 113, using temporary parity generation. The multi-pass programming system 200 includes a buffer 205, a first planar block 210, and a second planar block 215. In some embodiments, the first planar block 210 and the second planar block 215 are not composed of layers, and the block is therefore the smallest independently erasable subdivision. The buffer 205 contains a plurality of blocks, including a programming buffer block A 220, a programming buffer block B 225, a first parity buffer block 230, a second parity buffer block 235, and a third parity buffer block 240. The first planar block 210 has a subdivision including a first planar portion 245, and the second planar block 215 has a subdivision including a second planar portion 250.

[0040] In some embodiments, buffer 205 and its components (programming buffer block A 220, programming buffer block B 225, first parity buffer block 230, second parity buffer block 235, and third parity buffer block 240) are part of the local memory of the memory subsystem, for example... Figure 1 Local memory 119 or Figure 1 The memory device 130. In other embodiments, although described separately, the buffer 205 and its components (programming buffer block A 220, programming buffer block B 225, first parity buffer block 230, second parity buffer block 235 and third parity buffer block 240) are all part of the temporary parity generation component 113.

[0041] The first planar block 210 and the second planar block 215 are blocks on different planes of a memory die. For example, in some embodiments, the first planar block 210 and the second planar block 215, and their respective subdivisions (first planar portion 245 and second planar portion 250) are memory devices (e.g., memory devices). Figure 1 The memory device 130 is a portion thereof. The memory device comprises one or more dies, each of which comprises at least two planes. Throughout this disclosure, a die is defined as a cell of a memory device that independently executes commands and reports its status, and a plane is defined as a subdivision of a die capable of concurrently executing commands. Therefore, as... Figure 2The description indicates that the temporary parity generation component 113 can concurrently program both the second plane portion 250 and the first plane portion 245. Similarly, each plane consists of one or more blocks, each of which consists of one or more pages or word lines. In some embodiments, each block consists of one or more layers, each of which consists of one or more pages or word lines. In embodiments without layer subdivision, a block represents the smallest erasable unit, while in embodiments including layer subdivision, a layer represents the smallest erasable unit. In some embodiments, a page or word line represents the smallest programmable unit of memory.

[0042] The first plane block 210 and the second plane block 215 (and thus their components, including the first plane portion 245 and the second plane portion 250) are composed of QLCs. The first plane portion 245 and the second plane portion 250 are each 1 / 4 of their respective plane blocks, thus storing an equivalent amount of data for the SLC block. Programming buffer block A 220 and programming buffer block B 225 buffer the data stored in the first plane portion 245 and the second plane portion 250, and therefore also store 1 / 4 of the QLC (an equivalent amount of data for the SLC block) and are composed of SLCs. Similarly, the first parity buffer block 230, the second parity buffer block 235, and the third parity buffer block 240 buffer the parity information of the user data stored in the first plane portion 245 and the second plane portion 250 and are also composed of SLCs. The first parity check buffer block 230, the second parity check buffer block 235, and the third parity check buffer block 240 store the same amount of data as each of the first plane portion 245 and the second plane portion 250.

[0043] However, in some embodiments, the first planar block 210 and the second planar block 215 are composed of another cell type (e.g., MLC or TLC), and the number of portions in each of the planar blocks therefore varies based on the cell type. For example, when the first planar block 210 and the second planar block 215 are composed of TLC, there are three planar portions. Similarly, when the first planar block 210 and the second planar block 215 are composed of MLC, there are two planar portions. In these embodiments, programming buffer block A 220, programming buffer block B 225, the first parity buffer block 230, the second parity buffer block 235, and the third parity buffer block 240 are composed of SLC and store an equal amount of data as in each of the planar portions. The number of parity blocks depends on the number of subdivisions of the first planar block 210 and the second planar block 215. For a subdivision number n, there are n-1 parity blocks. For example, when there are four subdivisions of the first plane block 210 and the second plane block 215, there are three parity check blocks: the first parity check buffer block 230, the second parity check buffer block 235 and the third parity check buffer block 240.

[0044] In some embodiments, the temporary parity generation component 113 obtains data from a host device (e.g., Figure 1 The host system 120 receives a write command containing user data including first plane portion data 255 and second plane portion data 260. In such embodiments, the write command also includes logical addresses that, when translated into physical addresses, represent first plane block 210 and second plane block 215.

[0045] The temporary parity generation component 113 programs the first plane portion 245 with the first plane portion data 255 and programs the second plane portion 250 with the second plane portion data 260. The temporary parity generation component 113 also programs programming buffer block A 220 with the first plane portion data 255 and programming buffer block B 225 with the second plane portion data 260. In some embodiments, the temporary parity generation component 113 concurrently programs the first plane portion 245, the second plane portion 250, programming buffer block A 220, and programming buffer block B 225.

[0046] In some embodiments, the temporary parity generation component 113 programs the first plane block 210 and the second plane block 215, and thus its components including the first plane portion 245 and the second plane portion 250, in multiple passes. For example, the temporary parity generation component 113 may program the first plane portion 245 and the second plane portion 250 in two passes, the first pass being called a coarse programming pass and the second pass being called a fine programming pass. The coarse programming pass does not contain all the information needed to read the user data, and the user data is therefore copied elsewhere until the fine programming pass is completed (e.g., in programming buffer block A 220, programming buffer block B 225). In contrast, after the temporary parity generation component 113 performs a fine programming pass on the user data in the first plane portion 245 and the second plane portion 250, the copies of the user data stored in programming buffer block A 220 and programming buffer block B 225 are no longer needed to provide a readable copy of the fine programming pass.

[0047] The temporary parity generation component 113 also uses an XOR operation on the first plane portion data 255 and the second plane portion data 260 to generate parity data 265. In some embodiments, the temporary parity generation component 113 uses an operation other than XOR (e.g., another error correction scheme) to generate parity data 265. In some embodiments, when generating parity data 265 and programming parity data 265 into the first parity buffer block 230, the temporary parity generation component 113 programs programming buffer block A 220 and programming buffer block B 225 with the first plane portion data 255 and the second plane portion data 260, respectively. For example, the temporary parity generation component 113 concurrently programs word lines of the pair between the first plane block 210 and programming buffer block A 220 and the pair between the second plane block 215 and programming buffer block B 225. While still storing user data from programming word lines, the temporary parity generation component 113 also generates parity data on the two word lines of the user data and stores the resulting word lines of the parity data in the first parity buffer block 230.

[0048] In an embodiment where the adaptive buffer allocation component 113 programs the first plane portion 245 and the second plane portion 250 using multi-pass programming, programming buffer blocks A 220 and B 225 provide dual functions: (1) protecting the first plane block 210 and the second plane block 215 from programming block failures; and (2) providing a readable copy of user data during coarse programming passes. However, the first parity buffer block 230 partially protects the first plane block 210 and the second plane block 215 from programming failures. For example, the first plane portion 245 and the second plane portion 250 undergo multi-pass programming, but programming buffer blocks A 220, B 225, and the first parity buffer block 230 do not. Therefore, when the temporary parity generation component 113 stores the first plane portion data 255 and the second plane portion data 260 in the readable programming buffer block A220 and programming buffer block B225, it uses a coarse programming pass to program user data into the first plane portion 245 and the second plane portion 250. The temporary parity generation component 113 also generates parity data 265 from the first plane portion data 255 and the second plane portion data 260 and stores the parity data 265 in the first parity buffer block 230.

[0049] In response to the full programming of the first plane portion 245 and the second plane portion 250 (i.e., completing a fine programming pass for the first plane portion 245 and the second plane portion 250), the temporary parity generation component 113 invalidates or erases programming buffer blocks A 220 and B 225. Therefore, once programming buffer blocks A 220 and B 225 are erased, they provide a readable copy of user data during the coarse programming pass of the first plane portion 245 and the second plane portion 250, but do not protect the contents of the first plane portion 245 and the second plane portion 250 from programming block failures. Because the multi-plane area only accounts for 25% of the fully programmed portion, data may still be lost due to programming block failures of the first plane block 210 or the second plane block 215. However, the first parity buffer 230 contains parity data of the first plane portion 245 and the second plane portion 250 after the programming buffer A 220 and programming buffer B 225 are erased, and can be used to recover data when the programming block fails, thereby reducing the likelihood that the UBER will increase due to invalidating or erasing programming buffer A 220 and programming buffer B 225.

[0050] Figure 3 This is another block diagram of a multi-pass programming system 200 that uses temporary parity generation component 113 to generate instances. A first planar block 210 has a subdivision including a first planar portion 305, and a second planar block 215 has a subdivision including a second planar portion 310.

[0051] In some embodiments, the temporary parity generation component 113 obtains data from a host device (e.g., Figure 1 The host system 120 receives a write command containing user data including first plane portion data 315 and second plane portion data 320. For example, the user data may be part of the write command, which provides data for the first plane portion data 255 and the second plane portion data 260, as described above.

[0052] The temporary parity generation component 113 programs the first plane portion 305 with first plane portion data 315 and programs the second plane portion 310 with second plane portion data 320. The temporary parity generation component 113 also programs programming buffer block A 220 with the first plane portion data 315 and programming buffer block B 225 with the second plane portion data 320. The first plane portion data 315 and the second plane portion data 320 replace buffered data from previous portions stored in programming buffer block A 220 and programming buffer block B 225. In some embodiments, the temporary parity generation component 113 concurrently programs the first plane portion 305, the second plane portion 310, programming buffer block A 220, and programming buffer block B 225.

[0053] The temporary parity generation component 113 generates parity data 325 using an XOR operation performed on the first plane portion data 315 and the second plane portion data 320. In some embodiments, when generating parity data 325 and programming parity data 325 into the second parity buffer block 235, the temporary parity generation component 113 programs programming buffer block A 220 and programming buffer block B 225 with the first plane portion data 315 and the second plane portion data 320, respectively.

[0054] In an embodiment where the adaptive buffer allocation component 113 programs the first plane portion 305 and the second plane portion 310 using multi-pass programming, programming buffer blocks A 220 and B 225 provide dual functions: (1) protecting the first plane block 210 and the second plane block 215 from programming block failures; and (2) providing a readable copy of user data during coarse programming passes for the first plane portion 305 and the second plane portion 310. However, the first parity buffer block 230 partially protects the first plane block 210 and the second plane block 215 from programming failures. Similarly, the second parity buffer block 235 partially protects the first plane portion 305 and the second plane portion 310 from programming failures.

[0055] In response to the full programming of the first plane portion 305 and the second plane portion 310 (i.e., completing a fine programming pass for the first plane portion 305 and the second plane portion 310), the temporary parity generation component 113 invalidates or erases programming buffer block A 220 and programming buffer block B 225. Therefore, once programming buffer block A 220 and programming buffer block B 225 are erased, they provide a readable copy of user data during the coarse programming pass of the first plane portion 305 and the second plane portion 310, but cannot protect the contents of the first plane portion 305 and the second plane portion 310 from programming block failures. Because the multi-plane area only accounts for 50% of the fully programmed portion, data may still be lost due to programming block failures of the first plane block 210 or the second plane block 215. However, after programming buffer block A 220 and programming buffer block B 225 are erased, the first parity buffer block 230 contains Figure 2 The first plane portion 245 and the second plane portion 250 contain parity data, and the second parity buffer block 235 contains parity data of the first plane portion 305 and the second plane portion 310. The first parity buffer block 230 and the second parity buffer block 235 can therefore be used to recover data when the programming block fails, thereby reducing the possibility that UBER will increase due to invalidating or erasing programming buffer block A 220 and programming buffer block B 225.

[0056] Figure 4 This is another block diagram of a multi-pass programming system 200 that uses temporary parity generation component 113 to generate instances. A first planar block 210 has a subdivision including a first planar portion 405, and a second planar block 215 has a subdivision including a second planar portion 410.

[0057] In some embodiments, the temporary parity generation component 113 obtains data from a host device (e.g., Figure 1 The host system 120 receives a write command containing user data including first plane portion data 415 and second plane portion data 420. For example, the user data may be part of the write command, which provides data for the first plane portion data 255 and 315 and the second plane portion data 260 and 320, as described above.

[0058] The temporary parity generation component 113 programs the first plane portion 405 with first plane portion data 415 and programs the second plane portion 410 with second plane portion data 420. The temporary parity generation component 113 also programs programming buffer block A 220 with the first plane portion data 415 and programming buffer block B 225 with the second plane portion data 420. The first plane portion data 415 and the second plane portion data 420 replace buffered data from previous portions stored in programming buffer block A 220 and programming buffer block B 225. In some embodiments, the temporary parity generation component 113 concurrently programs the first plane portion 405, the second plane portion 410, programming buffer block A 220, and programming buffer block B 225.

[0059] The temporary parity generation component 113 also uses an XOR operation on the first plane portion data 415 and the second plane portion data 420 to generate parity data 425. In some embodiments, when generating parity data 425 and programming parity data 425 into the third parity buffer block 240, the temporary parity generation component 113 programs programming buffer block A 220 and programming buffer block B 225 with the first plane portion data 415 and the second plane portion data 420, respectively.

[0060] In an embodiment where the adaptive buffer allocation component 113 programs the first plane portion 405 and the second plane portion 410 using multi-pass programming, programming buffer blocks A220 and B225 provide dual functions: (1) protecting the first plane block 210 and the second plane block 215 from programming block failures; and (2) providing a readable copy of user data during coarse programming passes for the first plane portion 405 and the second plane portion 410. However, the first parity buffer block 230 partially protects the first plane block 210 and the second plane block 215 from programming failures. Similarly, the second parity buffer block 235 partially protects the first plane portion 305 and the second plane portion 310 from programming failures. Similarly, the third parity buffer block 240 partially protects the first plane portion 405 and the second plane portion 410 from programming failures.

[0061] In response to the full programming of the first plane portion 405 and the second plane portion 410 (i.e., completing a fine programming pass for the first plane portion 405 and the second plane portion 410), the temporary parity generation component 113 invalidates or erases programming buffer block A 220 and programming buffer block B 225. Therefore, once programming buffer block A 220 and programming buffer block B 225 are erased, they provide a readable copy of the user data during the coarse programming pass of the first plane portion 405 and the second plane portion 410, but cannot protect the contents of the first plane portion 405 and the second plane portion 410 from programming block failures. Because the multi-plane area only accounts for 75% of the fully programmed portion, data may still be lost due to programming block failures of the first plane block 210 or the second plane block 215. The first parity buffer block 230 contains... Figure 2 The parity check data for the first plane portion 245 and the second plane portion 250. The second parity check buffer block 235 contains... Figure 3 The parity data of the first plane portion 305 and the second plane portion 310 is contained in the third parity buffer block 240. After programming buffer block A 220 and programming buffer block B 225 are erased, the third parity buffer block 240 contains the parity data of the first plane portion 405 and the second plane portion 410. The first parity buffer block 230, the second parity buffer block 235 and the third parity buffer block 240 can therefore be used to recover data in the event of a programming block failure, thereby reducing the likelihood of UBER increasing due to invalidating or erasing programming buffer blocks A 220 and B 225.

[0062] Figure 5 This is another block diagram of a multi-pass programming system 200 that uses temporary parity generation component 113 to generate instances. The first plane block 210 has a subdivision including a first plane portion 505 and the second plane block 215 has a subdivision including a second plane portion 510.

[0063] In some embodiments, the temporary parity generation component 113 obtains data from a host device (e.g., Figure 1 The host system 120 receives a write command containing user data including first plane portion data 515 and second plane portion data 520. For example, the user data may be part of the write command, which provides data for the first plane portion data 255, 315, 415 and the second plane portion data 260, 320 and 420, as described above.

[0064] The temporary parity generation component 113 programs the first plane portion 505 with first plane portion data 515 and programs the second plane portion 510 with second plane portion data 520. The temporary parity generation component 113 also programs programming buffer block A 220 with the first plane portion data 515 and programming buffer block B 225 with the second plane portion data 520. The first plane portion data 515 and the second plane portion data 520 replace buffered data from previous portions stored in programming buffer block A 220 and programming buffer block B 225. In some embodiments, the temporary parity generation component 113 concurrently programs the first plane portion 505, the second plane portion 510, programming buffer block A 220, and programming buffer block B 225.

[0065] In an embodiment where the adaptive buffer allocation component 113 programs the first plane portion 505 and the second plane portion 510 using multi-pass programming, programming buffer block A 220, programming buffer block B 225, first parity buffer block 230, second parity buffer block 235, and third parity buffer block 240 provide dual functions: (1) protecting the first plane block 210 and the second plane block 215 from programming block failures; and (2) providing a readable copy of user data during coarse programming passes for the first plane portion 505 and the second plane portion 510. However, the first parity buffer block 230 partially protects the first plane block 210 and the second plane block 215 from programming failures. Similarly, the second parity buffer block 235 partially protects the first plane portion 305 and the second plane portion 310 from programming failures.

[0066] In response to the full programming of the first plane portion 505 and the second plane portion 510 (i.e., completing a fine programming pass for the first plane portion 505 and the second plane portion 510), the temporary parity generation component 113 scans the first plane block 210 and the second plane block 215 to verify correct programming. In response to the successful verification that the first plane block 210 and the second plane block 215 have been correctly programmed, the temporary parity generation component 113 erases the buffer 205 and thus erases or otherwise invalidates the buffer 205 and thus invalidates the following components: programming buffer block A 220, programming buffer block B 225, first parity buffer block 230, second parity buffer block 235, and third parity buffer block 240.

[0067] However, if programming fails during the programming of the first plane portion 505 and the second plane portion 510, then the first parity buffer block 230 contains Figure 2 The parity check data of the first plane portion 245 and the second plane portion 250, the second parity check buffer block 235 contains Figure 3 The parity check data of the first plane portion 305 and the second plane portion 310, and the third parity check buffer block 240 contains Figure 4 The parity data of the first plane portion 405 and the second plane portion 410 are stored. Similarly, programming buffer block A 220 still stores the first plane portion data 515 and programming buffer block B 225 still stores the second plane portion data 520. The first parity buffer block 230, the second parity buffer block 235, the third parity buffer block 240, programming buffer block A 220, and programming buffer block B 225 can therefore be used to recover data in the event of a programming block failure, thereby reducing the likelihood of UBER increasing due to invalidating or erasing programming buffer blocks A 220 and B 225. Similarly, if the temporary parity generation component 113 detects a programming error while scanning the first plane block 210 and the second plane block 215, then the first parity buffer block 230, the second parity buffer block 235, the third parity buffer block 240, the programming buffer block A 220, and the programming buffer block B 225 can be used to reconstruct the data, thereby reducing the likelihood of an increase in UBER.

[0068] Figure 6 This is another block diagram of a multi-pass programming system 600 containing a temporary parity generation component 113, generated using temporary parity checking. The multi-pass programming system 600 also includes a first parity buffer block 230, a second parity buffer block 235, a first planar portion 245, a first planar portion 305, a top layer 605 of programming buffer block A, a bottom layer 610 of programming buffer block A, a top layer 615 of programming buffer block B, a bottom layer 620 of programming buffer block B, a second planar portion 250, and a second planar portion 310. Although not explicitly stated, the first planar portion 245 and the first planar portion 305 are planar blocks (e.g., Figures 2 to 5 The first planar block 210 is a subdivision. Similarly, the second planar portion 250 and the second planar portion 310 are different planar blocks (e.g., Figures 2 to 5 The second plane block 215) is a subdivision. Additionally, the top layer 605 and bottom layer 610 of programming buffer block A are subdivisions of the programming buffer block (e.g., ...). Figures 2 to 5 The programming buffer block A 220) is a layer. Similarly, the top layer 615 and bottom layer 620 of programming buffer block B are layers of programming buffer blocks (e.g., programming buffer block A 220). Figures 2 to 5 The part of the programming buffer block B 225.

[0069] In some embodiments, although only two layers are described for each programming buffer block (e.g., a pair of top layer 605 and bottom layer 610 of programming buffer block A, and a pair of top layer 615 and bottom layer 620 of programming buffer block B), a memory block may be divided into more than two layers. For the purposes of this disclosure, the term "layer" refers to an independently erasable subdivision of a memory block. In some embodiments, a layer may not be the smallest programmable subdivision of a memory block, and the layer itself may also contain subdivisions, such as word lines. A word line is a subdivision of a layer and therefore also a subdivision of an independently programmable block.

[0070] Temporary parity generation component 113 programs the first plane portions 245 and 305 and the second plane portions 250 and 310 with user data and buffers the data by storing it in the top layer 605 of programming buffer block A, the bottom layer 610 of programming buffer block A, the top layer 615 of programming buffer block B, and the bottom layer 620 of programming buffer block B. Temporary parity generation component 113 also generates parity data from the user data stored in the top layer 605 of programming buffer block A, the bottom layer 610 of programming buffer block A, the top layer 615 of programming buffer block B, and the bottom layer 620 of programming buffer block B, and stores this parity data in the first parity buffer block 230 and the second parity buffer block 235. In one embodiment, temporary parity generation component 113 concurrently programs the word lines of the pair between the first plane portion 245 and the top layer 605 of programming buffer block A, and the pair between the second plane portion 250 and the top layer 615 of programming buffer block B. In this embodiment, each of the pairs of the first plane portion 245 and the top layer 605 of programming buffer block A, and the second plane portion 250 and the top layer 615 of programming buffer block B, is programmed word-by-word. The temporary parity generation component 113 concurrently generates parity data based on the programmed word lines and stores the parity data as word lines in the first parity buffer block 230. This process continues until the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B are fully programmed, at which point the temporary parity generation component 113 continues the process using the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B.

[0071] In response to reaching the full percentage of the multi-plane area indicated by the erase top layer 625, the temporary parity generation component 113 erases or otherwise invalidates the data stored in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B. The full percentage of the multi-plane area indicated by the erase top layer 625 is determined to mean that the user data has been fully programmed (i.e., a fine programming pass has been completed) to the first portion of the first plane portion 245 and the first portion of the second plane portion 250 (the portion buffered by the user data in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B). In some embodiments, each of the programming buffer block layers 605, 610, 615, and 620 is programmed word-for-word and erased layer by layer.

[0072] Since the fine programming pass has been completed, it is no longer necessary to provide a readable copy of the user data buffered in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B during the coarse programming pass of the first plane portion 245 and the second plane portion 250. Furthermore, if a programming block fails, the first parity buffer block 230 stores parity data of the user data stored in the first plane portion 245 and the second plane portion 250, and can therefore be used to recover lost data in the event of a programming block failure, thereby reducing the likelihood of UBER increasing due to invalidating or erasing the top layers 605 of programming buffer block A and the top layer 615 of programming buffer block B.

[0073] The percentage fill of the multi-plane area indicates the progress of the temporary parity generation component 113 in programming the planar block comprising the first plane portions 245 and 305 and the second plane portions 250 and 310. In some embodiments, the percentage fill of the multi-plane area indicates the progress of the temporary parity generation component 113 in performing coarse programming passes on the planar block. For example, when the first plane portions 245 and the second plane portions 250 have undergone coarse programming passes before a certain point, the percentages indicated by erasing top layers 625 and 635 and erasing bottom layer 630 are reached. Because the previous word lines of the first plane portions 245 and the second plane portions 250 concurrently undergo fine programming passes, erasing top layers 625 and 635 and erasing bottom layer 630 also indicate that fine programming passes have been completed for the top and bottom layers of the programming buffer block, respectively. In some embodiments, the percentage of fullness of the multi-plane area indicated by erasing top layers 625 and 635 and erasing bottom layer 630 depends on several variables, including the time it takes for the controller (e.g., memory subsystem controller 115) to perform the operation, the time required to queue future pages into memory, the speed of the controller / controller firmware, the efficiency of the controller / controller firmware, the size of the independently erasable / programmable portion, and similar metrics.

[0074] In response to erasing or otherwise invalidating data stored in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B, the temporary parity generation component 113 allocates the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B to the next portion (e.g., the first plane portion 305 and the second plane portion 310). Additionally, the temporary parity generation component 113 loads a portion of the user data from the next portion into the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B.

[0075] In response to the completion of the coarse programming passes of the first plane portion 245 and the second plane portion 250, the temporary parity generation component 113 concurrently programs the word lines of the pair between the first plane portion 305 and the top layer 605 of the programming buffer block A, and the pair between the second plane portion 310 and the top layer 615 of the programming buffer block B. The temporary parity generation component 113 concurrently generates parity data based on the programmed word lines and stores the generated parity data as word lines in the second parity buffer block 235.

[0076] In response to reaching the full percentage of the multi-plane area indicated by the erase bottom layer 630, the temporary parity generation component 113 erases or otherwise invalidates the data stored in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B. The full percentage of the multi-plane area indicated by the erase bottom layer 630 is determined to mean that the user data has been fully programmed (i.e., a fine programming pass has been completed) to the second portion of the first plane portion 245 and the second plane portion 250 (the portion of user data buffered in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B).

[0077] Since the fine programming pass has been completed, it is no longer necessary to provide a readable copy of the user data buffered in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B during the coarse programming pass of the first plane portion 245 and the second plane portion 250. Furthermore, if a programming block fails, the first parity buffer block 230 stores the parity data of the user data stored in the first plane portion 245 and the second plane portion 250, and can therefore be used to recover lost data in the event of a programming block failure, thereby reducing the likelihood of UBER increasing due to invalidating or erasing the top layers 605 of programming buffer block A and the top layer 615 of programming buffer block B.

[0078] In response to erasing data stored in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B, or otherwise invalidating the data, the temporary parity generation component 113 allocates the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B to the next portion (e.g., the first plane portion 305 and the second plane portion 310). Additionally, the temporary parity generation component 113 loads a portion of the user data from the next portion into the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B.

[0079] The temporary parity generation component 113 continues to program the word lines of the first plane portion 305, the top layer 605 of programming buffer block A, the second plane portion 310, the top layer 615 of programming buffer block B, and the second parity buffer block 235. This process continues until the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B are fully loaded, at which point the temporary parity generation component 113 continues the process using the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B.

[0080] In response to reaching the full percentage of the multi-plane area indicated by the erase top layer 635, the temporary parity generation component 113 erases or otherwise invalidates the data stored in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B. The full percentage of the multi-plane area indicated by the erase top layer 635 is determined to mean that the user data has been fully programmed (i.e., a fine programming pass has been completed) to the first portion of the first plane portion 305 and the first portion of the second plane portion 310 (the portion of user data buffered in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B).

[0081] Since the fine programming pass has been completed, it is no longer necessary to provide a readable copy of the user data buffered in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B during the coarse programming pass of the first plane portion 305 and the second plane portion 310. Furthermore, if a programming block fails, the first parity buffer block 230 stores the parity data of the user data stored in the first plane portion 245 and the second plane portion 250, and the second parity buffer block 235 stores the parity data of the user data stored in the first plane portion 305 and the second plane portion 310. The first parity buffer block 230 and the second parity buffer block 235 can therefore be used to recover lost data in the event of a programming block failure, thereby reducing the likelihood of UBER being affected by invalidating or erasing the top layers 605 of programming buffer block A and the top layer 615 of programming buffer block B.

[0082] In response to erasing data stored in the top layer 605 of programming buffer A and the top layer 615 of programming buffer B, or otherwise invalidating said data, the temporary parity generation component 113 allocates the top layer 605 of programming buffer A and the top layer 615 of programming buffer B to the next portion (e.g., Figure 7 (First plane portion 405 and second plane portion 410). In addition, the temporary parity generation component 113 loads a portion of the user data of the next part into the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B.

[0083] The temporary parity generation component 113 continues to program the word lines of the first plane portion 305, the bottom layer 610 of programming buffer block A, the second plane portion 310, the bottom layer 620 of programming buffer block B, and the second parity buffer block 235. This process continues until the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B are fully loaded.

[0084] Figure 7 This is another block diagram of a multi-pass programming system 600 that uses temporary parity generation component 113. The multi-pass programming system 600 further includes a third parity buffer block 240, first plane portions 405 and 505, and second plane portions 410 and 510.

[0085] Response to completion Figure 6 During the coarse programming passes of the first plane portion 305 and the second plane portion 310, the temporary parity generation component 113 concurrently programs the word lines of the pair between the first plane portion 405 and the top layer 605 of the programming buffer block A, and the pair between the second plane portion 410 and the top layer 615 of the programming buffer block B. The temporary parity generation component 113 concurrently generates parity data based on the programmed word lines and stores the generated parity data as word lines in the third parity buffer block 240.

[0086] In response to reaching the full percentage of the multi-plane area indicated by the erase bottom layer 705, the temporary parity generation component 113 erases or otherwise invalidates the data stored in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B. The full percentage of the multi-plane area indicated by the erase bottom layer 705 is determined to mean that the user data has been fully programmed (i.e., a fine programming pass has been completed) to the second portion of the first plane portion 305 and the second plane portion 310 (the portion of user data buffered in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B).

[0087] Since the fine programming pass has been completed, it is no longer necessary to provide a readable copy of the user data buffered in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B during the coarse programming passes of the first plane portion 305 and the second plane portion 310. Furthermore, if a programming block fails, the first parity buffer block 230 stores the parity data of the user data stored in the first plane portion 245 and the second plane portion 250, and the second parity buffer block 235 stores the parity data of the user data stored in the first plane portion 305 and the second plane portion 310. The first parity buffer block 230 and the second parity buffer block 235 can therefore be used to recover lost data in the event of a programming block failure, thereby reducing the likelihood of UBER being affected by invalidating or erasing the bottom layers 610 and 620 of programming buffer block A and programming buffer block B.

[0088] In response to erasing data stored in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B, or otherwise invalidating the data, the temporary parity generation component 113 allocates the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B to the next portion (e.g., the first plane portion 305 and the second plane portion 310). Additionally, the temporary parity generation component 113 loads a portion of the user data from the next portion into the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B.

[0089] The temporary parity generation component 113 continues to program the word lines of the first plane portion 405, the top layer 605 of programming buffer block A, the second plane portion 410, the top layer 615 of programming buffer block B, and the third parity buffer block 240. This process continues until the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B are fully loaded, at which point the temporary parity generation component 113 continues the process using the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B.

[0090] In response to reaching the full percentage of the multi-plane area indicated by the erase top layer 710, the temporary parity generation component 113 erases or otherwise invalidates the data stored in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B. The full percentage of the multi-plane area indicated by the erase top layer 710 is determined to mean that the user data has been fully programmed (i.e., a fine programming pass has been completed) to the first portion of the first plane portion 405 and the first portion of the second plane portion 410 (the portion of user data buffered in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B).

[0091] Since the fine programming pass has been completed, it is no longer necessary to provide a readable copy of the user data buffered in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B during the coarse programming passes of the first plane portion 305 and the second plane portion 310. Furthermore, if a programming block fails, the first parity buffer block 230 stores the parity data of the user data stored in the first plane portion 245 and the second plane portion 250. The second parity buffer block 235 stores the parity data of the user data stored in the first plane portion 305 and the second plane portion 310. The third parity buffer block 240 stores the parity data of the user data stored in the first plane portion 405 and the second plane portion 410. The first parity buffer block 230, the second parity buffer block 235, and the third parity buffer block 240 can therefore be used to recover lost data when a programming block fails, thereby reducing the likelihood that the UBER will increase due to invalidating or erasing the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B.

[0092] In response to erasing data stored in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B, or otherwise invalidating the data, the temporary parity generation component 113 allocates the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B to the next portion (e.g., the first plane portion 505 and the second plane portion 510). Additionally, the temporary parity generation component 113 loads a portion of the user data from the next portion into the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B.

[0093] In response to the completion of the coarse programming passes of the first plane portion 405 and the second plane portion 410, the temporary parity generation component 113 concurrently programs the word lines of the pair of the first plane portion 505 and the top layer 605 of the programming buffer block A and the pair of the second plane portion 510 and the top layer 615 of the programming buffer block B.

[0094] In response to reaching the full percentage of the multi-plane area indicated by the erase bottom layer 715, the temporary parity generation component 113 erases or otherwise invalidates the data stored in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B. The full percentage of the multi-plane area indicated by the erase bottom layer 715 is determined to mean that the user data has been fully programmed (i.e., a fine programming pass has been completed) to the second portion of the first plane portion 405 and the second plane portion 410 (the portion of user data buffered in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B).

[0095] Since the fine programming iterations have been completed, it is no longer necessary to provide readable copies of the user data buffered in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B during the coarse programming iterations of the first plane portion 405 and the second plane portion 410. Furthermore, if a programming block fails, the first parity buffer block 230 stores the parity data of the user data stored in the first plane portion 245 and the second plane portion 250. The second parity buffer block 235 stores the parity data of the user data stored in the first plane portion 305 and the second plane portion 310. The third parity buffer block 240 stores the parity data of the user data stored in the first plane portion 405 and the second plane portion 410. The first parity buffer block 230, the second parity buffer block 235, and the third parity buffer block 240 can therefore be used to recover lost data when a programming block fails, thereby reducing the likelihood that UBER will increase due to invalidating or erasing the bottom layers 610 of programming buffer block A and 620 of programming buffer block B.

[0096] In response to erasing data stored in the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B, or otherwise invalidating the data, the temporary parity generation component 113 allocates the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B to the next portion (e.g., the first plane portion 505 and the second plane portion 510). Additionally, the temporary parity generation component 113 loads a portion of the user data from the next portion into the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B.

[0097] The temporary parity generation component 113 continues to program the word lines of the first plane portion 505, the top layer 605 of programming buffer block A, the second plane portion 510, and the top layer 615 of programming buffer block B. This process continues until the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B are fully loaded, at which point the temporary parity generation component 113 continues the process using the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B.

[0098] In some embodiments, in response to determining that a memory block is to be programmed after the first plane portion 505 and the second plane portion 510, and in response to reaching the full percentage of the multi-plane area indicated by the erase top layer 720, the temporary parity generation component 113 erases or otherwise invalidates the data stored in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B. The full percentage of the multi-plane area indicated by the erase top layer 720 is determined to mean that the user data has been fully programmed (i.e., a fine programming pass has been completed) to the first portion of the first plane portion 505 and the second plane portion 510 (the portion of the user data buffered in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B).

[0099] Since the fine-grained programming iterations have been completed, it is no longer necessary to buffer user data in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B to prevent data loss when programming the corresponding layers of user data to the first plane portion 505 and the second plane portion 510. Furthermore, if a programming block fails, the first parity buffer block 230 stores parity data of the user data stored in the first plane portion 245 and the second plane portion 250. The second parity buffer block 235 stores parity data of the user data stored in the first plane portion 305 and the second plane portion 310. The third parity buffer block 240 stores parity data of the user data stored in the first plane portion 405 and the second plane portion 410. Therefore, the first parity buffer block 230, the second parity buffer block 235, and the third parity buffer block 240 can be used to recover lost data in the event of a programming block failure, thereby reducing the likelihood of UBER increases.

[0100] In some embodiments, in response to determining that no memory block needs to be programmed after the first plane portion 505 and the second plane portion 510, the temporary parity generation component 113 does not erase the top layer or otherwise invalidate the top layer. In such embodiments, the first parity buffer block 230, the second parity buffer block 235, the third parity buffer block 240, the top layer 605 of programming buffer block A, the bottom layer 610 of programming buffer block A, the top layer 615 of programming buffer block B, and the bottom layer 620 of programming buffer block B can be used to recover lost data in the event of a programming block failure, and may further reduce the likelihood of UBER being increased by invalidating or erasing the top layers 605 and 615 of programming buffer block A and programming buffer block B.

[0101] In response to determining that a memory block needs to be programmed after the first plane portion 505 and the second plane portion 510, and in response to erasing or otherwise invalidating the data stored in the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B, the temporary parity generation component 113 allocates the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B to the next portion (e.g., portions of the next two plane blocks). Additionally, the temporary parity generation component 113 loads a portion of the user data for the next portion into the top layer 605 of programming buffer block A and the top layer 615 of programming buffer block B.

[0102] The temporary parity generation component 113 continues to program the word lines of the first plane portion 505, the bottom layer 610 of programming buffer block A, the second plane portion 510, and the bottom layer 620 of programming buffer block B. This process continues until the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B are fully loaded.

[0103] In response to the full programming of the first plane portion 505 and the second plane portion 510 (i.e., the completion of a fine programming pass), the temporary parity generation component 113 scans the plane blocks to verify correct programming. In response to successful verification that the plane blocks have been correctly programmed, the temporary parity generation component 113 erases the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B, the first parity buffer block 230, the second parity buffer block 235, and the third parity buffer block 240, or otherwise invalidates the bottom layer 610 of programming buffer block A and the bottom layer 620 of programming buffer block B, the first parity buffer block 230, the second parity buffer block 235, and the third parity buffer block 240.

[0104] However, if programming fails during planar block programming, the first parity buffer block 230 contains parity data for the first planar portion 245 and the second planar portion 250. The second parity buffer block 235 contains parity data for the first planar portion 305 and the second planar portion 310. The third parity buffer block 240 contains parity data for the first planar portion 405 and the second planar portion 410. Similarly, the bottom layer 610 of programming buffer block A still stores the user data for the second part of the first planar portion 505, and the bottom layer 620 of programming buffer block B still stores the user data for the second part of the second planar portion 510. The first parity buffer block 230, the second parity buffer block 235, the third parity buffer block 240, the bottom layer 610 of programming buffer block A, and the bottom layer 620 of programming buffer block B can therefore be used to recover lost data in the event of a programming block failure, thereby reducing the likelihood of UBER increases. Similarly, if the temporary parity generation component 113 detects a programming error while scanning the first plane block 210 and the second plane block 215, then the first parity buffer block 230, the second parity buffer block 235, the third parity buffer block 240, the bottom layer 610 of programming buffer block A, and the bottom layer 620 of programming buffer block B can be used to recover lost data, thereby reducing the likelihood of UBER increases.

[0105] Figure 8 This is a flowchart of an example method 800 for programming a memory cell using temporary parity data in multiple passes, according to some embodiments of the present disclosure. Method 800 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 800 is performed by… Figure 1 The temporary parity generation component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0106] At operation 805, the processing device receives a write command for two or more data blocks. For example, the processing device reads a write command from a host device (e.g., ...). Figure 1 The host system 120 receives a write command containing user data and a logical address. The processing device translates the logical address into a physical address and determines the location to write the user data based on the physical address. In response to receiving the write command, the processing device performs operation 810.

[0107] At operation 810, the processing device generates temporary parity data based on the user data of the current portion. For example, the physical address translated from the write command received at operation 805 is associated with two blocks in a separate plane, allowing them to be programmed concurrently (e.g., Figures 2 to 5 The first planar block 210 and the second planar block 215). Each of the two blocks consists of one or more portions. In one embodiment, the processing device performs an XOR operation on the user data of the first planar portion and the user data of the second planar portion to generate temporary parity data.

[0108] At operation 815, the processing device stores a portion of the temporary parity data and user data in a buffer. In some embodiments, the buffer consists of a first programmed buffer block (e.g., Figure 2 The first programming buffer block A 220), the second programming buffer block (e.g. Figure 2 It consists of a programming buffer block B 225 and multiple parity buffer blocks (e.g., a first parity buffer block 230, a second parity buffer block 235, and a third parity buffer block 240). In some embodiments, each of the programming buffer blocks is further composed of layers.

[0109] In some embodiments, the first planar portion and the second planar portion are composed of QLCs. In such embodiments, the buffer is composed of SLCs. In other embodiments, different cell types may be used for the first planar portion, the second planar portion, and / or the buffer.

[0110] At operation 820, the processing device programs user data into corresponding portions of the first and second blocks. In some embodiments, the programming involves multiple passes. For example, the processing device programs the first and second planar portions in two passes (a coarse programming pass and a fine programming pass).

[0111] At operation 825, the processing device erases or otherwise invalidates the buffer layer of user data associated with the first and second plane portions. In some embodiments, the processing device assigns the invalidated layer to the next portion of the first and second planes. In some embodiments, the processing device invalidates the buffer layer in response to completing a second programming pass for the associated first and second plane portions.

[0112] At operation 830, the processing device determines whether the programming of a portion is complete. For example, the processing device determines whether the second programming pass of the first plane portion and the second plane portion has been completed. If the partial programming is complete, the processing device continues to operation 835. If the partial programming is not complete, method 800 returns to operation 820 and programs the next portion of the first plane and the second plane. In some embodiments, although not stated, if the partial programming is not complete, method 800 returns to operation 810 instead (e.g., if the generation of parity data for the portion is also not complete).

[0113] At operation 835, the processing device determines whether block programming is complete. For example, the processing device determines whether the second programming iteration of the first plane block and the second plane block has been completed. If block programming is complete, then method 800 continues to operation 840. If partial programming is incomplete, then method 800 returns to operation 810 and generates temporary parity data for the next portion of the first and second planes.

[0114] At operation 840, the processing device scans for block errors. For example, the processing device scans the first and second plane blocks to verify correct programming. In response to the scan detecting an error, the processing device attempts to correct the errors in the first and second plane blocks using user data and parity data stored in a buffer.

[0115] At operation 845, the processing device invalidates the buffer. For example, the processing device erases or otherwise invalidates the user data and parity data stored in the buffer. In some embodiments, certain layers of the buffer are cleared and allocated to consecutive blocks. In such embodiments, the contents of the buffer corresponding to the buffered user data or parity data of the programming block are invalidated, while the contents of the buffer corresponding to the consecutive block are preserved.

[0116] At operation 850, the processing device moves to the next two memory blocks. For example, the processing device restarts at operation 810 for the next two queued blocks. In some embodiments, when all memory blocks have been programmed, the processing device does not return to operation 810, but waits for the next write command to trigger operation 805.

[0117] Figure 9 This is a flowchart of an example method 900 for programming a memory cell using temporary parity data in multiple passes, according to some embodiments of the present disclosure. Method 900 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 900 is performed by… Figure 1 The temporary parity generation component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0118] At operation 905, the processing device receives a write command for two or more data blocks. For example, the processing device reads a write command from a host device (e.g., ...). Figure 1 The host system 120 receives a write command containing user data and a logical address. The processing unit translates the logical address into a physical address and determines the location to write the user data based on the physical address.

[0119] At operation 910, the processing device generates temporary parity data based on the first and second portions of the user data. For example, the physical address translated from the write command received at operation 905 is associated with two blocks in a separate plane, allowing them to be programmed concurrently (e.g., ...). Figures 2 to 5 The first planar block 210 and the second planar block 215). Each of the two blocks consists of one or more parts. In one embodiment, the processing device performs an XOR operation on the user data of the first planar part (i.e., the first portion of the user data) and the user data of the second planar part (i.e., the first portion of the user data) to generate temporary parity data.

[0120] At operation 915, the processing device stores temporary parity data and the first and second portions of user data in a buffer. In some embodiments, the buffer consists of a first programmed buffer block (e.g., ...). Figure 2 The first programming buffer block A 220), the second programming buffer block (e.g. Figure 2 It consists of a programming buffer block B 225 and multiple parity buffer blocks (e.g., a first parity buffer block 230, a second parity buffer block 235, and a third parity buffer block 240). In some embodiments, each of the programming buffer blocks is further composed of layers.

[0121] In some embodiments, the first planar portion and the second planar portion are composed of QLCs. In such embodiments, the buffer is composed of SLCs. In other embodiments, different cell types may be used for the first planar portion, the second planar portion, and the buffer.

[0122] At operation 920, the processing device programs a first portion of the first block using a first portion of user data. In some embodiments, the programming involves multiple passes. For example, the processing device programs the first planar portion in two passes (a coarse programming pass and a fine programming pass).

[0123] At operation 925, the processing device programs the first portion of the second block using the second portion of the user data. In some embodiments, the programming involves multiple passes. For example, the processing device programs the second planar portion in two passes (a coarse programming pass and a fine programming pass).

[0124] At operation 930, the processing device erases or otherwise invalidates a first portion and a second portion of user data associated with the first and second plane portions, which are stored in a buffer at operation 915. In some embodiments, the processing device assigns an invalidated layer to a next portion of the first and second planes. In some embodiments, the processing device invalidates a buffered layer in response to completing a second programming pass for the associated first and second plane portions.

[0125] Figure 10 This describes an example machine of a computer system 1000, in which a set of instructions for causing a machine to perform any or more of the methods discussed herein are executable. In some embodiments, the computer system 1000 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (The operation of the temporary parity generation component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0126] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0127] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 1018, which communicate with each other via a bus 1030.

[0128] Processing device 1002 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 1002 is configured to execute instructions 1026 for performing the operations and steps discussed herein. Computer system 1000 may further include a network interface device 1008 for communication via network 1020.

[0129] The data storage system 1018 may include a machine-readable storage medium 1024 (also referred to as a computer-readable medium) on which one or more sets of instructions 1026 or software embodying any one or more of the methods or functions described herein are stored. The instructions 1026 may also reside wholly or at least partially within the main memory 1004 and / or the processing device 1002 during execution by the computer system 1000, which also constitute machine-readable storage media. The machine-readable storage medium 1024, the data storage system 1018, and / or the main memory 1004 may correspond to... Figure 1 The memory subsystem 110.

[0130] In one embodiment, instruction 1026 includes instructions for implementing a component corresponding to a temporary parity generation (e.g., Figure 1The temporary parity generation component 113) provides functional instructions. Although the machine-readable storage medium 1024 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions that are executed by a machine and cause the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should accordingly be considered as including (but not limited to) solid-state memory, optical media, and magnetic media.

[0131] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are generally conceived herein as self-consistent sequences of operations that lead to desired results. An operation is an operation that requires the physical manipulation of physical quantities. By way of, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for reasons of convention, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0132] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0133] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specially constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. For example, a computer system or other data processing system (e.g., controller 115) may implement computer implementation methods 800 and 900 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in memory or other non-transitory machine-readable storage media. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0134] The algorithms and displays presented herein do not inherently relate to any particular computer or other device. Various general-purpose systems can be used in conjunction with the teachings herein, or it may be proven convenient to construct more specialized devices to implement the methods. The structures for various such systems will appear as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0135] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0136] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It should be understood that various modifications may be made to the specific exemplary embodiments without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than limiting.

Claims

1. A method for programming memory cells, comprising: receiving one or more write commands including user data, wherein the one or more write commands are directed to a portion of memory including a first block and a second block each including a plurality of portions, and wherein a first portion of the user data is directed to the first block and a second portion of the user data is directed to the second block; generating first temporary parity data by performing a parity operation using the first portion of the user data and the second portion of the user data; storing the first temporary parity data, the first portion of the user data and the second portion of the user data in a buffer; programming a first portion of the first block with the first portion of the user data, wherein the programming includes a first pass programming and a second pass programming; programming a first portion of the second block with the second portion of the user data, wherein the programming includes a first pass programming and a second pass programming; and invalidating the first portion and the second portion of the user data in the buffer in response to completion of the second pass programming of the first portion of the first block and the first portion of the second block, wherein the first temporary parity data is saved in the buffer until completion of the second pass programming of the first block and the second block.

2. The method of claim 1, wherein the first block and the second block are a first type of non-volatile memory elements and wherein the buffer is a second type of non-volatile memory elements.

3. The method of claim 1, wherein a third portion of the user data is directed to the first block and a fourth portion of the user data is directed to the second block, the method further comprising: generating second temporary parity data based on the third portion of the user data and the fourth portion of the user data; storing the second temporary parity data, the third portion of the user data and the fourth portion of the user data in the buffer; programming a second portion of the first block with the third portion of the user data; and programming a second portion of the second block with the fourth portion of the user data.

4. The method of claim 3, wherein the first portion of user data is stored in a first top tier and a first bottom tier of the buffer, and wherein the second portion of user data is stored in a second top tier and a second bottom tier of the buffer, and wherein invalidating the first portion and the second portion of the user data in the buffer includes invalidating the first top tier and the second top tier in response to completion of the first pass programming of the first portion of the first block and the first portion of the second block.

5. The method of claim 3, further comprising: ​ ​ scanning the first block and the second block in response to completion of the second pass programming of the first block and the second block; determining whether the first block and the second block contain defects; and invalidating the first temporary parity data and the second temporary parity data in response to determining that the first block and the second block do not contain defects.

6. The method of claim 3, further comprising: storing temporary pages of the third portion of user data and the fourth portion of user data in a temporary buffer, wherein the temporary pages are pages of the third portion of user data and the fourth portion of user data stored in the temporary buffer prior to completion of the second pass programming of the first portion of the first block and the first portion of the second block.

7. The method of claim 1, wherein the first block and the second block are each planes, together comprising a zone, and wherein the parity operation is an exclusive-OR operation.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receive one or more write commands including user data, wherein the one or more write commands are directed to a portion of a memory including a first block and a second block each comprising a plurality of portions, and wherein a first portion of the user data is directed to the first block and a second portion of the user data is directed to the second block; generate first temporary parity data by performing a parity operation using the first portion of the user data and the second portion of the user data; store the first temporary parity data, the first portion of the user data, and the second portion of the user data in a buffer; program a first portion of the first block with the first portion of the user data, wherein the programming includes a first pass programming and a second pass programming; program a first portion of the second block with the second portion of the user data, wherein the programming includes a first pass programming and a second pass programming; and invalidate the first portion and the second portion of the user data in the buffer in response to completion of the second pass programming of the first portion of the first block and the first portion of the second block, wherein the first temporary parity data is saved in the buffer until completion of the second pass programming of the first block and the second block.

9. The non-transitory computer-readable storage medium of claim 8, wherein the first block and the second block are first type of non-volatile memory elements and wherein the buffer is a second type of non-volatile memory element.

10. The non-transitory computer-readable storage medium of claim 8, wherein a third portion of the user data is directed to the first block and a fourth portion of the user data is directed to the second block, and wherein the processing device further: generating second temporary parity data based on the third portion of the user data and the fourth portion of the user data; storing the second temporary parity data, the third portion of the user data, and the fourth portion of the user data in the buffer; programming a second portion of the first block with the third portion of the user data; and programming a second portion of the second block with the fourth portion of the user data.

11. The non-transitory computer-readable storage medium of claim 10, wherein the first portion of user data is stored in a first top tier and a first bottom tier of the buffer, and wherein the second portion of user data is stored in a second top tier and a second bottom tier of the buffer, and wherein invalidating the first portion and the second portion of the user data in the buffer comprises invalidating the first top tier and the second top tier in response to completion of the first pass programming of the first portion of the first block and the first portion of the second block.

12. The non-transitory computer-readable storage medium of claim 10, wherein the processing device further: scanning the first block and the second block in response to completion of the second pass programming of the first block and the second block; determining whether the first block and the second block contain defects; and invalidating the first temporary parity data and the second temporary parity data in response to determining that the first block and the second block do not contain defects.

13. The non-transitory computer-readable storage medium of claim 10, wherein the processing device further: stores temporary pages of the third portion of user data and the fourth portion of user data in a temporary buffer, wherein the temporary pages are pages of the third portion of user data and the fourth portion of user data stored in the temporary buffer prior to completion of the second pass programming of the first portion of the first block and the first portion of the second block.

14. The non-transitory computer-readable storage medium of claim 8, wherein the first block and the second block are each planes, together comprising a zone, and wherein the parity operation is an exclusive-OR operation.

15. A memory sub-system, comprising: a plurality of memory devices; and a processing device, operably coupled with the plurality of memory devices, to: receive one or more write commands including user data, wherein the one or more write commands are directed to a portion of memory including a first block and a second block each comprising a plurality of portions, and wherein a first portion of the user data is directed to the first block and a second portion of the user data is directed to the second block, and wherein the first block and the second block are first type of non-volatile memory elements; generate first temporary parity data by performing a parity operation using the first portion of the user data and the second portion of the user data; storing the first temporary parity data, the first portion of the user data, and the second portion of the user data in a buffer, wherein the buffer is a second type of non-volatile memory element; programming a first portion of the first block with the first portion of the user data, wherein the programming includes a first pass programming and a second pass programming; programming a first portion of the second block with the second portion of the user data, wherein the programming includes a first pass programming and a second pass programming; and invalidating the first and second portions of the user data in the buffer in response to completion of the second pass programming of the first portion of the first block and the first portion of the second block, wherein the first temporary parity data is saved in the buffer until completion of the second pass programming of the first block and the second block.

16. The memory sub-system of claim 15, wherein a third portion of the user data is directed to the first block and a fourth portion of the user data is directed to the second block, and wherein the processing device further: generating second temporary parity data based on the third portion of the user data and the fourth portion of the user data; storing the second temporary parity data, the third portion of the user data, and the fourth portion of the user data in the buffer; programming a second portion of the first block with the third portion of the user data; and programming a second portion of the second block with the fourth portion of the user data.

17. The memory sub-system of claim 16, wherein the first portion of user data is stored in a first top tier and a first bottom tier of the buffer, and wherein the second portion of user data is stored in a second top tier and a second bottom tier of the buffer, and wherein invalidating the first and second portions of the user data in the buffer includes invalidating the first top tier and the second top tier in response to completion of the first pass programming of the first portion of the first block and the first portion of the second block.

18. The memory sub-system of claim 16, wherein the processing device further: scanning the first block and the second block in response to completion of the second pass programming of the first block and the second block; determining whether the first block and the second block contain defects; and invalidating the first temporary parity data and the second temporary parity data in response to determining that the first block and the second block do not contain defects.

19. The memory sub-system of claim 16, wherein the processing device further: storing the third portion of user data and the temporary pages of the fourth portion of user data in a temporary buffer, wherein the temporary pages are pages of the third portion of user data and the fourth portion of user data stored in the temporary buffer prior to completion of the second pass programming of the first portion of the first block and the first portion of the second block.

20. The memory sub-system of claim 15, wherein the first block and the second block are each planes, together constituting a zone, and wherein the parity operation is an exclusive-OR operation.

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