Sensing displacement for improved overlay error metrology

Abstract

A method for semiconductor metrology includes depositing a first thin film layer on a semiconductor substrate and depositing a second thin film layer overlying the first thin film layer. The first thin film layer and the second thin film layer are patterned to define a plurality of overlay targets, the plurality of overlay targets comprising: first target features formed in the first thin film layer having respective first locations separated by a first nominal distance; and second target features formed in the second thin film layer having respective second locations separated by a second nominal distance different from the first nominal distance. An image of the semiconductor substrate is processed to measure respective displacements between the first target location and the second target location in each of the overlay targets, and both an actual overlay error between the patterning of the first thin film layer and the second thin film layer and a measurement error of an imaging assembly are estimated.

Description

Technical Field

[0001] The present invention relates generally to the fabrication of semiconductor devices, and in particular to methods and target features for semiconductor circuit metrology. Background Art

[0002] Semiconductor circuits are typically manufactured using photolithographic methods. In photolithography, a thin layer of a photosensitive polymer (photoresist) is deposited on a semiconductor substrate and patterned using optical or other radiation so that portions of the substrate are covered by the photoresist. The photoresist is patterned by a scanner that projects an image of a mask onto the photoresist, typically using ultraviolet radiation. After patterning, the substrate is modified by methods such as etching and ion bombardment to change the material properties and / or morphology of the substrate, while portions of the substrate covered by the photoresist are not affected.

[0003] Semiconductor circuit metrology is used to measure the properties of patterned photoresists, such as the topography and position of patterned features. The accurate position of the patterned features of the photoresist relative to the previous process layer is critical to achieving a high yield in the photolithography process. Any error in the registration (mismatch) of the patterned photoresist relative to the underlying process layer is called the "overlay error". As an example, in a typical semiconductor circuit with a minimum line width of 10nm to 14nm (the so-called 10-nm design rule), the maximum allowable overlay error is 2nm to 3nm. In leading-edge semiconductor circuits, line widths are shrinking to 5nm, and the maximum allowable overlay error is also decreasing.

[0004] Overlay error is often measured using optical overlay metrology equipment (often referred to as optical overlay metrology tools) because optical radiation in visible and infrared wavelengths can penetrate photoresist layers and through dielectric layers beneath the photoresist. In addition, infrared wavelengths can penetrate semiconductor substrates (e.g., silicon), enabling through-substrate metrology.

[0005] Optical overlay metrology tools such as the Archer 3D from KLA (Milpitas, CA) TM series of tools) to perform scribe lines (lines separating adjacent dies) on the semiconductor substrate and / or overlay targets within the die (e.g., KLA's AIM TM The method uses an image analysis algorithm to locate the center of symmetry of the target feature in the process layer and the center of symmetry of the target feature in the patterned photoresist layer. The overlay error is calculated based on the displacement between the centers of symmetry of the target features in the two layers.

[0006] Alternatively, the overlay error may be measured in a scatterometry mode. In this measurement mode, a scatterometry image of periodic target features of the overlay target is captured from the exit pupil of the objective of the metrology tool. The scatterometry image, which indicates the angular distribution of the optical radiation scattered from the target features, is processed to measure the overlay error.

[0007] As used in this specification and claims, the terms "optical ray," "optical radiation," "light," and "radiation beam" generally refer to any and all visible, infrared, and ultraviolet radiation. Summary of the invention

[0008] Embodiments of the invention described below provide improved methods and targeted features for semiconductor circuit metrology.

[0009] Therefore, according to an embodiment of the present invention, a method for semiconductor metrology is provided. The method includes depositing a first thin film layer on a semiconductor substrate and depositing a second thin film layer overlying the first thin film layer. The first thin film layer and the second thin film layer are patterned to define a plurality of superimposed targets, the plurality of superimposed targets including: first target features formed in the first thin film layer with respective first positions separated by a first nominal distance; and second target features formed in the second thin film layer with respective second positions separated by a second nominal distance different from the first nominal distance. Each second target feature overlies a respective first target feature to define a respective one of the superimposed targets. The method further includes capturing at least one image of the semiconductor substrate on which the superimposed target has been formed using an imaging assembly, and processing the at least one image to measure respective displacements between the first target position and the second target position in each of the superimposed targets. Based on the measured displacements and the first nominal distance and the second nominal distance, both an actual superimposed error between the patterning of the first thin film layer and the second thin film layer and a measurement error of the imaging assembly are estimated.

[0010] In some embodiments, patterning the first and second film layers includes patterning a matrix of fields and defining a plurality of overlay targets in each of the fields, and capturing an image includes capturing at least one image of the plurality of overlay targets in at least one of the fields.

[0011] In a further embodiment, the first nominal distance and the second nominal distance are selected such that, for each stacking target, the respective displacement between the first position and the second position corresponds to a respective nominal displacement. Additionally or alternatively, estimating both the actual stacking error and the measured error comprises, for a set of the stacking targets, comparing the measured displacement with respective modeled displacements, each modeled displacement comprising a sum of a displacement calculated from a scanner model and the respective nominal displacement for a given stacking target.

[0012] In yet further embodiments, the scanner model includes coefficients defining displacements between patterns formed in the first and second thin film layers by a photolithography process.

[0013] In some embodiments, estimating the measurement error includes finding a linear coefficient between the corresponding nominal displacements and the measured displacements on the set of the superimposed targets. Additionally or alternatively, finding the linear coefficient includes applying a regression method between the corresponding measured displacements and the modeled displacements to estimate the coefficients of the scanner model and the linear coefficients.

[0014] In further embodiments, estimating the actual stacking error includes applying the linear coefficient to the measured displacement.

[0015] In yet further embodiments, estimating the actual overlay error and the measured error includes finding coefficients of a scanner model, and patterning the first film layer and the second film layer includes selecting respective nominal displacements of the overlay target that are at least partially orthogonal to the scanner model. Additionally or alternatively, selecting the respective nominal displacements includes calculating a projection of the nominal displacement onto the scanner model, and selecting the respective nominal displacements such that the projection does not exceed a predefined limit.

[0016] In some embodiments, selecting the respective nominal displacements includes calculating an orthogonal nominal displacement at the location of each superposition target for use in selecting the respective nominal displacements for the superposition targets.

[0017] According to an embodiment of the present invention, an optical metrology apparatus is also provided. The apparatus includes a semiconductor substrate having a first thin film layer deposited thereon and a second thin film layer overlying the first thin film layer. The first thin film layer and the second thin film layer are patterned to define a plurality of superimposed targets, the plurality of superimposed targets including: first target features formed in the first thin film layer with respective first positions separated by a first nominal distance; and second target features formed in the second thin film layer with respective second positions separated by a second nominal distance different from the first nominal distance. Each second target feature overlies a respective first target feature to define a respective one of the superimposed targets. The apparatus further includes an imaging assembly configured to capture at least one image of the semiconductor substrate on which the superimposed targets have been formed. A controller is configured to process the at least one image to measure respective displacements between the first target position and the second target position in each of the superimposed targets and estimate both an actual superimposed error between the patterning of the first thin film layer and the second thin film layer and a measurement error of the imaging assembly based on the measured displacements and the first nominal distance and the second nominal distance.

[0018] Will be combined with Figure 1 The present invention will be more fully understood from the following detailed description of embodiments of the present invention, in which: BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic side view of an optical metrology apparatus for measuring overlay error on a semiconductor substrate according to an embodiment of the present invention;

[0020] Figure 2 According to an embodiment of the present invention Figure 1 A schematic top view of a semiconductor substrate showing an overlying target on the substrate;

[0021] Figure 3A According to an embodiment of the present invention Figure 1 A schematic top view of a single field of a semiconductor substrate of FIG. 1 showing superimposed objects;

[0022] Figure 3B is a schematic top view of two superimposed targets according to an embodiment of the present invention;

[0023] Figure 4 is a flow chart schematically illustrating a method for estimating linear coefficients of correctable terms of a scanner model and stacking error measurements according to an embodiment of the present invention; and

[0024] Figure 5 and 6is a flow chart schematically illustrating an alternative method for selecting an overlay target according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Overview

[0026] Overlay targets for overlay metrology are typically used for precise and accurate measurement of overlay errors between successive patterned layers on a semiconductor substrate. These layers may include, for example, a process layer and a photoresist layer (photoresist), or, in post-etch applications, two process layers, or, as in some multiple patterning applications, one process layer. Thus, although some example embodiments are described below with reference to a process layer and a photoresist layer, the principles of these embodiments may be applied to a first process layer and a second process layer with appropriate modifications. In some multiple patterning applications, the first process layer and the second process layer may include the same material.

[0027] In the manufacturing process of semiconductor circuits, measured overlay errors are often used to calculate and provide feedback to scanners used to print features of the circuits in the photolithography process. As will be described in further detail below, the feedback is given in the form of coefficients of a given scanner model (called "correctable terms"). This model describes errors in the positioning and orientation of the semiconductor substrate in the scanner (wafer model), as well as optical and mechanical pattern placement errors between the scanner's mask and the substrate (field model). Alternatively or in addition, the measured overlay errors can be used to "dispose" the semiconductor substrate, i.e., determine whether the displacement of the photoresist pattern across the semiconductor substrate relative to the previous process layer is within predefined limits, so that processing of the substrate can continue to the next step, or whether the patterned substrate must be returned for repeated processing.

[0028] However, the accuracy of the correctable term may be affected by the inaccuracy of the metrology equipment used to measure the overlay error (e.g., measurement errors in the imaging assembly of the metrology equipment). For example, the measured displacement between the centers of symmetry of target features in a process layer as measured by the metrology equipment and specified by Meas_Displ may have a linear relationship with the actual displacement specified by Actual_Displ, but may have a linear coefficient that deviates from the ideal value of 1. The linear relationship can be written as the equation Meas_Displ = α * Actual_Displ + β. In this equation, α is the linear coefficient and β is the offset, which is generally negligible in practical applications. Having a linear coefficient α different from 1 may significantly distort the measured value of the overlay error. These distortions may then send erroneous feedback to the scanner in the form of inaccurate correctable terms and may even lead to incorrect decisions about the handling of the patterned semiconductor substrate. Although in the embodiments described below, a linear error model is used to estimate the error introduced by the metrology equipment, a higher-order error model, such as a quadratic or other function model, may also be used instead.

[0029] The embodiments of the invention described herein solve the above-mentioned overlay error metrology problem by estimating both the actual overlay error between the patterning of the first film layer and the second film layer and the measured error of the imaging assembly. To this end, for example, the disclosed embodiments provide a method for extracting a linear coefficient between the measured error and the actual overlay error.

[0030] In the description below, each overlay target in a pair of continuous thin film layers on a semiconductor substrate consists of one or more first target features formed in the first thin film layer at a first position and a second target feature formed in the second thin film layer at a second position. (The term "continuous" refers to the deposition order of the first thin film layer and the second thin film layer on the substrate but does not imply direct continuity, that is, there may be one or more additional layers between the first and second layers mentioned here.) In metrology systems known in the art, the nominal displacement (also called "offset") between the first position and the second position is zero. For such zero displacement or zero offset targets, the overlay error as measured by an ideal metrology system is zero. This nominal displacement is implemented in the design of masks used in lithography processes. However, in practice, due to misalignment and other manufacturing errors, the actual displacement between positions is non-zero.

[0031] However, in an embodiment of the present invention, the nominal displacements between corresponding positions of target features in at least some of the stacking targets are intentionally set to known non-zero values. Therefore, even under ideal measurement conditions, the actual displacements will vary from target to target, and the actual displacements between the first set of target features and the second set of target features are given by the stacking errors due to the process plus the intentional (nominal) displacements between the positions. Therefore, the measured displacements (i.e., the displacements between the first set of target features and the second set of target features of the stacking target as measured by the metrology equipment) are equal to the sum of the actual displacements between these features and any errors introduced by the metrology equipment. In this embodiment, the intentionally varying displacements between the positions of the target features are used to estimate the measurement error and thus derive a more accurate measure of the actual stacking error.

[0032] To produce a set of superposition targets that can be used in this manner, a first film layer and a second film layer are deposited on a semiconductor surface, wherein the second film layer overlies the first film layer. In some multiple patterning applications (e.g., "lithography-frozen lithography-etching" (LFLE)), the first layer and the second layer include the same film material. The first film layer and the second film layer are patterned to define a plurality of superposition targets, the plurality of superposition targets including first target features and second target features in the first film layer and the second film layer, respectively, having corresponding first and second positions. The first target features are separated by a first nominal distance, and the second positions are separated by a second nominal distance different from the first nominal distance. Each second target feature overlies a corresponding first target feature to define one of the superposition targets, but due to the different nominal distances between the positions, the superposition targets have different nominal displacements. (The term "overlying" is used in the context of this specification and claims according to its simple meaning: one of the target features is disposed on another, but is not limited to precise alignment or overlap of features.)

[0033] An imaging assembly in a metrology tool captures one or more images of a semiconductor substrate on which an overlay target has been formed. The image or images are processed to measure respective displacements between a first target position and a second target position for each of the overlay targets. As previously described, these displacements reflect both actual displacements between patterns in the thin film layers due to process errors and measurement errors of the imaging assembly. Based on these measured displacements and known variations in nominal displacements (due to different nominal distances in the first and second layers), both the measurement errors of the imaging assembly and the actual overlay error between the patterning of the first and second thin film layers can be estimated. By modeling the measurement errors (e.g., by finding linear coefficients), the actual overlay error can be derived with improved accuracy.

[0034] In the embodiments described below, the positions of target features are determined by predefined geometrical properties of these features, such as their respective centers of symmetry. Alternatively, other properties of target features may be used to determine their positions.

[0035] Although the described embodiments relate to imaging overlay error metrology, the principles of the invention may be similarly applied to additional overlay error metrology methods. Furthermore, although the described embodiments relate to patterning by a scanner, the principles of the invention may be similarly applied to patterns produced by alternative or more complex patterning methods.

[0036] System Description

[0037] Figure 11 is a schematic side view of an optical metrology apparatus 10 for measuring displacement between two patterned thin film layers on a semiconductor substrate 12 according to an embodiment of the present invention. This apparatus is shown by way of example for the sake of specificity and clarity; and the principles of the present invention may be similarly applied using other types of metrology tools known in the art.

[0038] The optical metrology apparatus 10 includes an imaging assembly 14, an illumination assembly 16, a controller 18, and a stage 20 on which the substrate 12 is mounted. The imaging assembly 14 includes an objective lens 22, a cube beam splitter 24, and an imaging lens 26. The imaging assembly 14 further includes a sensor 28, which includes, for example, a complementary metal oxide semiconductor (CMOS) image sensor having a two-dimensional pixel array 30.

[0039] Illumination assembly 16 includes a light source 32 that emits optical radiation and a lens 34. Stage 20 is located near objective lens 22 and includes an actuator controlled by controller 18 that can move the stage linearly in x, y, and z directions (referenced to Cartesian coordinates 36), as well as rotate the stage about the z-axis. Cartesian coordinates 36 are shown in this and subsequent figures to clarify the orientation of these figures relative to apparatus 10.

[0040] In the depicted embodiment, the first thin film layer 38 and the second thin film layer 40 have been deposited on the semiconductor substrate 12 and patterned in a photolithography process, as shown in the following figure. In this embodiment, the first layer 38 is a process layer, and the second layer 40 is a photoresist layer deposited on the process layer. Alternatively, both layers 38 and 40 can be process layers, including layers comprising the same material.

[0041] To measure the displacement between the pattern in the upper layer 40 of the substrate 12 and the pattern in the underlying layer 38, a superimposed target including target features (hereinafter referred to as Figure 2 and 3A 3B) has been formed by a photolithographic process in layers 38 and 40. Substrate 12 is positioned on stage 20 so that the combined optics of lens 22 and lens 26 images the substrate onto sensor 28 (ie, the substrate and sensor are on optically conjugate planes).

[0042] Controller 18 receives images from sensor 28 and adjusts the position and orientation of stage 20. Controller 18 typically includes a programmable processor programmed in software and / or firmware to perform the functions described herein, along with appropriate digital and / or analog interfaces for connecting to other elements of apparatus 10. Alternatively or in addition, controller 18 includes hardwired and / or programmable hardware logic circuitry that implements at least some of the functions of the controller. Although controller 18 may be Figure 1, but for simplicity, as a single, monolithic functional block, in practice, the controller may include a plurality of interconnected control units with appropriate interfaces for receiving and outputting the signals illustrated in the figures and described in the text. Program instructions implementing, for example, the methods described herein may be transmitted via or stored on a carrier medium. The carrier medium may include a storage medium such as a read-only memory, a random access memory, a magnetic or optical disk, a non-volatile memory, a solid-state memory, a magnetic tape, and the like.

[0043] To capture an image of an overlay target on semiconductor substrate 12, light source 32 projects a beam of optical radiation to lens 34, which further projects the beam to cubic beam splitter 24. Beam splitter 24 reflects the beam into objective 22, which projects the beam onto substrate 12. Radiation impinging on substrate 12 is scattered back to objective 22 and passes onto beam splitter 24, is transmitted to lens 26, and is focused onto sensor 28. Controller 18 reads out the image captured by sensor 28 and processes the image to identify corresponding positions of features of the overlay target in layer 40 and underlying layer 38 on substrate 12. Controller 18 measures the displacement between these two patterned layers based on the displacement between the corresponding positions of the target features.

[0044] Alternatively, apparatus 10 may be configured to measure displacement in a scatterometry mode. For this mode, lens 26 is modified and / or moved to image the exit pupil (not shown) of objective 22 onto sensor array 28. This scatterometry image indicates the angular distribution of optical radiation scattered from the target feature, and in this case, controller 18 is configured to process the angular distribution to measure displacement.

[0045] Figure 2 is a schematic top view (from the z direction) of a semiconductor substrate 12 showing superimposed targets 112 , 114 on the substrate in accordance with an embodiment of the present invention.

[0046] In a photolithography process, a matrix 100 of M fields 103 has been exposed on a substrate 12. (In the embodiment shown, the number of fields M is 32, but in alternative embodiments, the number of fields may be less than or greater than 32.) In a successive exposure step of the photolithography process, a scanner projects an image of a reticle onto the field 103 to expose a die 102 along with a plurality of overlay targets 112 and 114, as will be described in further detail below. (In alternative embodiments, more than one die 102 may be exposed within a field 103.) To illustrate Figure 2 To distinguish between fields 103 in 103 and die 102, field 103a is marked with cross-hatching, and die 102a (not in field 103a) is marked with reverse cross-hatching. Die 102 is separated by scribe lines 104 and contains active areas 106 (circumscribed by the scribe lines) including circuit elements 108.

[0047] In an example embodiment, semiconductor substrate 12, also commonly referred to as a wafer or semiconductor wafer, typically has a diameter of 300 mm. Each die 102 is typically square, for example, with dimensions of 20 mm x 20 mm, but other sizes and shapes may be used instead. Scribe lines 104 typically have a width of about 100 μm.

[0048] The thin film layer (eg Figure 1 8 and 9) are patterned to define N offset overlay targets 112 (N ≥ 2) within each field 103, with non-zero nominal displacements between the centers of symmetry of the target features in layers 38 and 40, as further described below. Alternatively, the nominal displacements as well as the measured displacements may be defined between other geometrical properties of the target features. The thin film layer may also be patterned to define additional default overlay targets 114 with zero nominal displacements within each field 103. Although Figure 2 An offset target 112 within die 102 is illustrated in , and a default overlay target 114 is shown in scribe line 104 , but each type of overlay target may alternatively be located in any position in field 103 .

[0049] To define scanner correctable terms, as described below, two two-dimensional Cartesian coordinate systems are used to define each point within each field 103: a wafer coordinate axis 120 and a field coordinate axis 122, wherein their respective x- and y-axes are aligned with the x- and y-axes of the Cartesian coordinates 36. The wafer coordinate axis 120 is referenced to the wafer (i.e., to the semiconductor substrate 12), wherein its coordinate axes are labeled x and y. W and W , where W refers to "wafer". Each field 103 has its respective field coordinate axis 122 located identically in each respective field, where the coordinate axis is labeled x F and F , where F refers to "field". (For clarity, only one set of field coordinate axes 122 is shown.) Thus, the position of a given point in field 103 can be represented by four coordinates (x W ,y W ,x F ,y F ) description, where x W and W refers to the chip coordinate axis 120 and x F and F refers to the field coordinate axis 122 (of the particular field in which the point is located).

[0050] The field 103 is labeled by j, where j=1, 2, ..., M, and the offset target 112 is labeled by i, where i=1, 2, ..., N, and the coordinates of the nominal displacement target within the semiconductor substrate 12 can be written as (x W i,j ,yW i,j ,x F i ,y F i ). The field coordinate (x ) associated with the field coordinate axis 122 F i ,y F i ) has only one index (i) because the field coordinate axis is repeated in each field 103.

[0051] Figure 3A is a schematic top view of a single field 103 of a semiconductor substrate 12 showing an offset overlay target 112 in accordance with an embodiment of the present invention.

[0052] Each offset overlay target 112 includes a first set of target features formed in a first thin film layer 38 and a second set of target features formed in a second thin film layer 40. These two sets of target features are formed by a scanner that has exposed a corresponding photoresist layer through a first mask (in a corresponding photolithography process step) for forming the first set of target features in layer 38 and similarly has exposed layer 40 through a second mask for forming the second set of target features. The first mask has been designed and manufactured to form the first target features spaced a first nominal distance apart using a highly accurate manufacturing method (e.g., electron beam writing). Similarly, the second mask has been designed and manufactured to form the second target features spaced a second nominal distance apart, wherein the second nominal distance is different from the first predefined nominal distance. Each second target feature overlies a corresponding first target feature and defines a corresponding offset target 112.

[0053] The first nominal distance and the second nominal distance have been selected so that each offset superposition target 112 including the first target feature and the second target feature has a nominal displacement of ΔX and ΔY in the respective x-direction and y-direction between the centers of symmetry of the first set of target features and the second set of target features. In the depicted embodiment, the nominal displacements ΔX and ΔY are equal and Figure 3A 1 and 1 , as indicated by a numerical label within each target 112. (Alternatively, unequal nominal displacements ΔX and ΔY may be chosen, in which case each target 112 would be characterized by two displacement maps.) Thus, for offset overlay target 112a, the nominal displacements of the second set of target features relative to the first set of target features are ΔX = +8 nm and ΔY = +8 nm (i.e., 8 nm in both positive axis directions), while for offset target 112b, the nominal displacements are ΔX = -5 nm and ΔY = -5 nm (i.e., 5 nm in the negative axis direction).

[0054] Although in the present embodiment the offset overlay target 112 has a nominal displacement in both the x-direction and the y-direction, the same principles can be applied with appropriate modifications to a unidirectional overlay target having an offset in only one direction.

[0055] Generally speaking, with a corresponding nominal displacement ΔX i and ΔY i N offset overlay targets i are formed in field 103, where i=1, 2, ..., N,. In the following description, N is taken to be 15, but other numbers of targets less than and greater than 15 may be formed. Advantageously, the nominal displacement of target 112 is of the same order of magnitude as the expected overlay error in the lithography process under test.

[0056] The N offset overlay targets can be similar or different. An example of a similar target is a box-in-box target, where the outer box of the target is formed in the process layer and the inner box is formed in the photoresist layer. An example of a different target is a box-in-box target, where for some targets, the outer box is in the process layer and the inner box is in the photoresist layer, while for other targets, the inner box is in the process layer and the outer box is in the photoresist layer. This approach can also be applied to other target designs, such as AIM targets.

[0057] Figure 3B is a schematic top view of an assembly of two overlay targets 162 and 164 according to an embodiment of the present invention. These targets are composed of first target features 142 and 144 in layer 38 and second target features 152 and 154 in layer 40 to form two box-in-box overlay targets 162 and 164 on semiconductor substrate 12. As used in overlay error metrology and in this embodiment to illustrate the displacement of overlay targets, the target features of the box-in-box overlay target include two nominally concentric squares (one square inside the other square) aligned along the x-axis and the y-axis. The outer square typically has dimensions of 20 μm×20 μm and the inner square has dimensions of 10 μm×10 μm, but other dimensions may be used alternatively. The center of each square in both the x-direction and the y-direction is the center of symmetry of the square, which is used here to define the position of the target features. For clarity, the depicted embodiment shows the displacement of the target features (squares) only in the x-direction, where the centers of the target features are aligned with each other in the y-direction.

[0058] Two first target features 142 and 144, comprising two squares, are formed in first film layer 38. Center lines 146 and 148 mark the centers of first target features 142 and 144, respectively, in the x-direction. First target features 142 and 144 are separated by a first nominal distance of 1.000010 mm in the x-direction, shown as the distance between center lines 146 and 148. Two second target features 152 and 154 (two squares) are formed in second film layer 40. Center lines 156 and 158 mark the centers of second target features 152 and 154, respectively, in the x-direction. Second target features 152 and 154 are separated by a second nominal distance of 1.000000 mm in the x-direction, shown as the distance between center lines 156 and 158. (For clarity, the difference between the two nominal distances is shown highly exaggerated.)

[0059] Assuming that there are no errors in the photolithography process in which target features 142, 144, 152, and 154 are formed in the respective thin film layers on semiconductor substrate 12, the target features are aligned in the x-direction such that center lines 148 and 158 of respective target features 144 and 154 are aligned on top of each other, thereby forming overlay target 164. Thus, the nominal displacement of overlay target 164 is zero (similar to, for example) Figure 2 10 nm (0.000010 mm) in the x-direction, as shown by the separation of the corresponding center lines 146 and 156 on the semiconductor substrate 12. Thus, the overlay target 162 is similar to the offset overlay target 112.

[0060] Although the target features are aligned in the depicted embodiment so that the nominal displacement of overlay target 164 is zero, different alignment schemes may be implemented to accordingly change the nominal displacements of overlay targets 162 and 164. When overlay errors occur, the actual displacement will differ from the nominal displacement.

[0061] Nominal displacement in the y-direction (or nominal displacement in both the x-direction and the y-direction) can be implemented in a similar manner in box and box overlay targets, as well as other types of overlay targets, such as the AIM, AIMid (AIM in-die), rAIM (Robust-AIM Moiré), and SCOL (Scattering Measurement Overlay) targets provided by KLA.

[0062] Measurement and analysis

[0063] 1. Scanner Model

[0064] The scanner model is used to describe the overlay error caused by the misalignment of the semiconductor substrate 12 in the scanner, as well as the error generated in the scanner when projecting the image of the mask onto the substrate and other errors with similar system behavior. For example, the scanner model can describe the corresponding x-direction and y-direction on the wafer (i.e., on the semiconductor substrate 12) through Model_OVLX(x W y W , x F ,y F ) and Model_OVLY(x W ,y W ,x F ,y F ) at point (x W ,y W ,x F ,y F ) due to the scanner stacking error:

[0065] Model_OVLX(x W ,y W , x F ,y F )=

[0066] OffX+ScalX*x W +WRotX*y W +MagX*x F +FRotX*y F

[0067] and

[0068] Model_OVLY(x W ,y W , x F ,y F )=

[0069] OffY+WrotY*x W +ScalY*y W +FRotY*x F +MagY*y F ,

[0070] where OVL is the overlay error. The scanner correctable term multiplied by the appropriate coordinates gives the pattern placement error due to various errors within the scanner as follows:

[0071] OffX = pattern placement error due to fixed misalignment of the wafer (semiconductor substrate 12) in the x-direction;

[0072] OffY = pattern placement error due to fixed misalignment of the wafer in the y direction;

[0073] ScalX = pattern placement error in the x-direction due to scaling error in wafer movement, i.e., error due to the wafer moving within the scanner by a distance that differs from the expected distance by a constant factor;

[0074] ScalY = pattern placement error in the y direction due to scaling error of wafer movement;

[0075] WRotX = pattern placement error in the x-direction due to wafer rotation, i.e., angular error due to wafer placement within the scanner;

[0076] WRotY = pattern placement error in the y direction due to wafer rotation;

[0077] MagX = pattern placement error in the x direction due to the optical magnification error of the scanner;

[0078] MagY = pattern placement error in the y direction due to the optical magnification error of the scanner;

[0079] FRotX = pattern placement error in the x-direction due to unintended rotation of the scanner field; and

[0080] FRotY = pattern placement error in the y direction due to unintended rotation of the scanner field.

[0081] These scanner correctable terms are estimated from the measured overlay errors by fitting the measured overlay errors to the overlay errors according to the scanner model, typically through a fitting process such as linear regression. The correctable terms are then fed back to the scanner for use in correcting linear and rotational positioning errors of the wafer within the scanner for subsequent exposures, as well as correcting errors in projecting the scanner reticle onto the field 103.

[0082] Scanner models that include higher order terms in wafer and / or field coordinates may be used in alternative embodiments.

[0083] 2. Linear error in superposition error measurement

[0084] As explained above, the measured displacement Meas_Displ has a linear relationship with the actual displacement Actual_Displ, but the linear coefficient may deviate from the ideal value of 1. This relationship can be written as the equation Meas_Displ = α * Actual_Displ + β with a non-unity linear coefficient α. The offset β is assumed to be negligible and will be ignored from subsequent calculations.

[0085] If not characterized and corrected, linear errors in the overlay error metrology can lead to incorrect scanner correctable terms and thus can lead to insufficient scanner correction or possibly even to an increase in pattern placement errors due to the scanner. Furthermore, it can lead to incorrect handling of the patterned substrate 12.

[0086] 3. Use offset stacking targets to eliminate linear errors

[0087] Figure 4 2 is a flow chart 200 schematically illustrating a method for estimating linear coefficients of correctable terms for a scanner model and stacking error measurements according to an embodiment of the present invention. The method is presented below as being related to displacements in the x-direction. The same method can also be applied to displacements in the y-direction.

[0088] The method starts in a start step 202. In a displacement selection step 204, N nominal displacements ΔX are selected. i (x F i ,y F i ). (The specific method used for displacement selection is in Figure 5 and 6 ) In the target forming step 206, the offset superposition target 112 is formed in each field 103 of the semiconductor substrate 12 ( Figure 3A ). In a displacement measurement step 208, the displacement between the corresponding centers of symmetry of the target features in layers 38 and 40 is measured for each target 112 in each field 103 using the optical metrology apparatus 10. The measured M×N displacements in the x-direction are given by Meas_DisplX(x W i，j ,y W i，j , x F i ,y F i ) specifies, where i=1, 2, ..., N and j=1, 2, ..., M.

[0089] In a scanner model selection step 210, a scanner model is selected for calculation, such as the model described above. In a modeled displacement error step 212, the modeled superposition error in the original scanner model is modified to account for the different nominal displacements of the target 112. Thus, the modeled displacement is the sum of the superposition errors due to the nominal displacements of the scanner and the target 112, and it also takes into account the linear coefficient α x Using the notation introduced above, the modeled displacement of the i-th offset target 112 in the j-th field 103 is written as:

[0090] Model_DisplX(xW i，j ,yW i，j , x F i ,y F i )=

[0091] α x *[OffX+ScalX*x W i，j +WRotX*y w i，j +MagX*x F i +FRotX*y F i

[0092] +ΔX i (x F i ,y F i )].

[0093] Since the position of the offset target 112 is defined by the mask used in the scanner during the photolithography process, ΔX i Depends only on the field coordinates (x F ,y F ).

[0094] In the calculation step 214, by modeling the displacement Model_DisplX(x W i，j ,y W i，j , x F i ,y F i ) and the displacement Meas_DisplX(x W i，j ,y W i，j , x F i ,y F i ) are used to estimate the scanner correctable terms OffX, ScalX, WRotX, MagX, FRotX and the linear coefficient α x Since the model includes products of variables, it is necessary to apply higher-order regression rather than linear regression. The purpose of the regression method is to minimize the effect of possible random or higher-order metrological errors on the estimated scanner correctable terms and linear coefficients. Regression is performed to find the solution that minimizes the sum S given by x The set of values ​​of the correctable terms and linear coefficients of :

[0095]

[0096] Alternatively, substitute in estimating a single linear coefficient α x When all fields 103 are included, α may be performed based on one or more subsets of fields 103. x , where each subset includes one or more fields (not shown in flowchart 200). Further alternatively, the displacement may be averaged over all fields and terms related to the wafer model may be omitted. By estimating α for multiple subsets of the fields 103 across the semiconductor substrate 12 x , to obtain α across the substrate x to reflect the potential measurement deviation across the substrate and the linear coefficient α of the overlay error metric x To estimate α on a subset of the field 103 x , calculate the above sum S for each subset separately x , where S is modified accordingly x The method ends in an end step 216 .

[0097] As an alternative to nonlinear regression, other computational methods known in the art for fitting measurements to a model may be used. These methods may include, for example, nonlinear changes in variables, which may allow the application of linear regression.

[0098] 4. Selection of offset overlay target

[0099] Figure 5 and 6 Flowcharts 300 and 400 respectively schematically illustrate two alternative methods for selecting an offset overlay target 112 according to embodiments of the present invention.

[0100] If the magnitudes of the N offset overlay targets 112 and their positions lie in the linear space of the scanner model (i.e., if the combination of the nominal displacements of the N targets and the target positions can be fully described by the scanner model), then the offset overlay targets will only modify the estimate of the scanner correctable terms but not by Figure 4 The method described in produces a linear coefficient α x and α y Therefore, the scanner correctable term will contain the error due to the nominal displacement and the error due to the linear coefficient α x and α y Therefore, the magnitude of the displacement of the center of symmetry in target 112 and the position of the target should be within Figure 4The displacement vector φ is selected in the displacement selection step 204 (and implemented in the target formation step 206) so that it is at least partially orthogonal to the scanner model used in the calculation. The term "partially orthogonal" is used here to mean that the displacement vector has a component orthogonal to the scanner model. Since the position of the target 112 depends on the field coordinate (x F ,y F ), so only the field coordinate dependent part of the scanner model is used to determine orthogonality.

[0101] For almost any randomly chosen set of displacements ΔX i (x F i ,y F i )(i=1,2,...N), the above requirement can be met (for the linear scanner model) as long as N is large enough to give statistically significant measurements. However, for numerical considerations, systematic methods (such as those described below) Figure 5 and 6 ) is advantageous.

[0102] Flowchart 300( Figure 5 ) shows an iterative method for determining and improving the orthogonality of the offset stacking target 112 and the scanner model. The method starts at start step 301. In selection step 302, N nominal displacements ΔX are selected. i (x F i ,y F i ). In the projection step 304, by i (x F i ,y F i ) and MagX*x F i +FRotX*y F i The linear regression between the estimated scanner field correction term MagX and FRotX is used to calculate the ΔX on the scanner field model i (x F i ,y F i )'s projection MagX*x F i +FRotX*y F i , where i = 1, 2, ..., N. In the projection magnitude step 306, the relative magnitude Proj of the projection x Calculated as

[0103]

[0104] In the first comparison step 308, Proj x With the predetermined restrictions. If Proj x If the predetermined limit is exceeded, then in an adjustment step 310, the nominal displacement ΔX is adjusted by randomly selecting the magnitude and / or position of the nominal displacement target or by systematically iterating over the vectors from a linear basis of a larger linear space (including the linear space spanned by the model's vectors as a subspace). i (x F i ,y F i ) to make another selection. Iterate the loop of the projection step 304, the projection value step 306, the first comparison step 308 and the adjustment step 310 until Proj x reaches a value below a predefined limit.

[0105] Once the nominal displacement ΔX is determined i (x F i ,y F i ) makes Proj x does not exceed a predetermined limit, that is, in the second comparison step 312 the nominal displacement ΔX i (x F i ,y F i ) is compared with the expected magnitude of the overlay error in the lithography process. If the magnitude of the nominal displacement is significantly different from the expected range of overlay error values ​​in the lithography process under consideration, then ΔX i (x F i ,y F i ) are multiplied by a common constant in a scaling step 314 to bring the magnitude of the nominal displacement into the expected range. The loop of steps 312 and 314 is iterated until the magnitude of the nominal displacement is satisfactory, and the process ends at an end step 316. The nominal displacement ΔX obtained by the method is i (x F i ,y F i ) in the photolithography step (e.g., step 206 ( Figure 4 )) is used to form target 112.

[0106] Flowchart 400( Figure 6 ) shows a direct method for selecting an offset stacking target 112 that is orthogonal to the scanner field model (ie, has a zero projection on the scanner field model). The method begins at start step 402. Similar to steps 302 and 304 ( Figure 5 ), in the selection step 404, N nominal displacements ΔX are selected i (x F i ,y F i ). In the projection step 406, by i (x F i ,y F i ) and MagX*x F i +FRotX*y F i The linear regression between the estimated scanner field correction term MagX and FRotX is used to calculate ΔX i (x F i ,y F i ) projection MagX*x on the scanner field model F i +FRotX*y F i , where i = 1, 2, ..., N. In the orthogonal nominal displacement component calculation step 408, ΔX i (x F i ,y F i ) component ΔX i ORTHO (x F i ,y F i )(i.e., orthogonal to the scanner field model MagX*x F i +FRotX*y F i The component ΔX i (x F i ,y F i )) is calculated as ΔX i ORTHO (x F i ,y F i )=ΔX i (x F i ,y F i )-MagX*x F i +FRotX*y Fi , where i=1,2,…,N.

[0107] Similar to steps 312 and 314 ( Figure 5 ), in the comparison step 410, the orthogonal nominal displacement component ΔX is compared i ORTHO (x F i ,y F i ) and the expected magnitude of the overlay error in the lithography process under consideration. If necessary, the orthogonal nominal displacement components are multiplied by a common constant in a scaling step 412 until ΔX is reached. i ORTHO (x F i ,y F i ) is the desired magnitude of the nominal displacement component of ). The method ends in an end step 414. The orthogonal nominal displacement ΔX obtained by the method i ORTHO (x F i ,y F i ) in the photolithography step (e.g., step 206 ( Figure 4 )) is used to form target 112.

[0108] Similarly, for a high-dimensional scanner model (ie, for a nonlinear model), the selected displacement ΔX i (x F i ,y F i ) should not lie in the high-dimensional plane defined by the scanner model. For example, for the quadratic scanning model, the high-dimensional plane consists of five vectors and In this case, for N>5, almost any vector ΔX i (x F i ,y F i ) will satisfy the requirement of sufficient orthogonality.

[0109] It will be understood that the above embodiments are cited as examples, and the present invention is not limited to what has been specifically illustrated and described above. Specifically, the scope of the present invention includes combinations and sub-combinations of the various features described above, as well as changes and modifications thereof that will occur to those skilled in the art when reading the foregoing description and that are not disclosed in the prior art.

Claims

1. A method for semiconductor metrology, comprising: Depositing a first thin film layer on a semiconductor substrate and depositing a second thin film layer overlying the first thin film layer; The first thin film layer and the second thin film layer are patterned to define a plurality of superimposed targets, the plurality of superimposed targets comprising: first target features formed in the first film layer at respective first locations separated by a first nominal distance; and second target features formed in the second film layer having respective second locations separated by a second nominal distance different than the first nominal distance, each second target feature overlying a respective first target feature to define a respective one of the superimposed targets; capturing, using an imaging assembly, at least one image of the semiconductor substrate on which the overlay target has been formed; processing the at least one image to measure a displacement between the respective first position and the second position in each of the superimposed objects; and Based on the measured displacement and the first and second nominal distances, both an actual overlay error between the patterning of the first and second film layers and a measured error of the imaging assembly are estimated.

2. The method of claim 1 , wherein patterning the first thin film layer and the second thin film layer comprises patterning a field matrix and defining a plurality of the superimposed targets in each of the fields, and capturing an image comprises capturing the at least one image of the plurality of superimposed targets in at least one of the fields. 3 . The method of claim 1 , wherein the first nominal distance and the second nominal distance are selected such that, for each of the superposition targets, a respective displacement between the first position and the second position corresponds to a respective nominal displacement.

4. The method of claim 3 , wherein estimating both the actual overlay error and the measured error comprises, for a set of the overlay targets, comparing the measured displacements with corresponding modeled displacements, each of the modeled displacements comprising a sum of a displacement calculated from a scanner model and the corresponding nominal displacement for a given overlay target. 5 . The method of claim 4 , wherein the scanner model includes coefficients defining displacements between patterns formed in the first and second thin film layers by a photolithography process. 6 . The method of claim 5 , wherein estimating the measurement error comprises finding a linear coefficient between the corresponding nominal displacements and the measured displacements on the set of the stacked targets.

7. The method of claim 6, wherein finding the linear coefficients comprises applying a regression method between the respective measured displacements and the modeled displacements to estimate the coefficients of the scanner model and the linear coefficients.

8. The method of claim 6, wherein estimating the actual stacking error comprises: The linear coefficient is applied to the measured displacement.

9. The method of claim 3, wherein estimating the actual overlay error and the measured error comprises finding coefficients of a scanner model, and wherein patterning the first film layer and the second film layer comprises selecting respective nominal displacements of the overlay target that are at least partially orthogonal to the scanner model.

10. The method of claim 9, wherein selecting the respective nominal displacements comprises calculating a projection of the nominal displacements onto the scanner phantom; and selecting the respective nominal displacements such that the projections do not exceed a predefined limit.

11. The method of claim 9, wherein selecting the respective nominal displacements comprises calculating an orthogonal nominal displacement at the location of each of the overlay targets for selecting the respective nominal displacements of the overlay targets.

12. An optical metrology device, comprising: A semiconductor substrate having a first thin film layer deposited thereon and a second thin film layer overlying the first thin film layer, wherein the first thin film layer and the second thin film layer are patterned to define a plurality of overlay targets, the plurality of overlay targets comprising: first target features formed in the first film layer at respective first locations separated by a first nominal distance; and second target features formed in the second film layer having respective second locations separated by a second nominal distance different than the first nominal distance, each second target feature overlying a respective first target feature to define a respective one of the superimposed targets; an imaging assembly configured to capture at least one image of the semiconductor substrate on which the overlay target has been formed; and A controller is configured to process the at least one image to measure a displacement between the respective first position and the second position in each of the overlay targets and to estimate both an actual overlay error between the patterning of the first film layer and the second film layer and a measured error of the imaging assembly based on the measured displacement and the first nominal distance and the second nominal distance.

13. The apparatus of claim 12, wherein the first thin film layer and the second thin film layer are patterned to form a field matrix and define a plurality of the superimposed targets in each of the fields, and the imaging assembly is configured to capture at least one image of the plurality of superimposed targets in at least one of the fields.

14. The apparatus of claim 12, wherein the first nominal distance and the second nominal distance are selected such that, for each of the superposition targets, a respective displacement between the first position and the second position corresponds to a respective nominal displacement.

15. An apparatus according to claim 14, wherein the controller is configured to compare the measured displacement with corresponding modeled displacements for a set of the superposition targets, each of the modeled displacements comprising a sum of a displacement calculated from a scanner model and the corresponding nominal displacement for a given superposition target.

16. The apparatus of claim 15, wherein the scanner model includes coefficients defining displacements between patterns formed in the first and second thin film layers by a photolithography process.

17. The apparatus of claim 16, wherein estimating the measurement error comprises finding a linear coefficient between the corresponding nominal displacements and the measured displacements on the set of the stacked targets.

18. The apparatus of claim 17, wherein finding the linear coefficients comprises applying a regression method between respective the measured displacements and the modeled displacements to estimate the coefficients of the scanner model and the linear coefficients.

19. The apparatus of claim 17, wherein estimating the actual stacking error comprises: The linear coefficient is applied to the measured displacement.

20. The apparatus of claim 14, wherein estimating the actual stacking error and the measured error comprises: Coefficients of a scanner model are found, and wherein the corresponding nominal displacement of the superposition target is at least partially orthogonal to the scanner model.

Images