Improved targets for diffraction-based overlay error metrology

Abstract

A method for semiconductor metrology includes depositing first and second overlying film layers on a semiconductor substrate and patterning the layers to define overlay targets. The targets include a first grating pattern in the first layer including at least a first linear grating oriented in a first direction and at least a second linear grating oriented in a second direction perpendicular to the first direction, and a second grating pattern in the second layer including at least a third linear grating identical to the first linear grating and a fourth linear grating identical to the second linear grating. The second grating pattern has a nominal offset relative to the first grating pattern of first and second displacements in the first and second directions, respectively. Scatterometry images of the substrate are captured and processed to estimate overlay error between patterning of the first and second layers.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application 63 / 283,429, filed November 27, 2021, which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present invention relates generally to the fabrication of semiconductor devices, and in particular, the present invention relates to methods and target features for semiconductor circuit metrology. BACKGROUND

[0004] Semiconductor circuits are typically fabricated using photolithographic methods. In photolithography, a thin layer of a light-sensitive polymer (photoresist) is deposited on a semiconductor substrate and patterned using optical or other radiation to cover portions of the substrate with photoresist. The photoresist is patterned by a scanner projecting an image of a reticle onto the photoresist, typically using ultraviolet radiation. After patterning, the substrate is modified by methods such as etching and ion bombardment to change the material properties and / or topography of the substrate, while the portions of the substrate covered by photoresist are unaffected.

[0005] Semiconductor circuit metrology is used to measure properties of the patterned photoresist, such as the topography and position of the patterned features. The accurate position of the patterned features of the photoresist relative to the previous process layer is critical to achieving high yield of the photolithographic process. Any error in the registration of the patterned photoresist relative to the underlying process layer (misregistration) refers to “overlay error”. As an example, in a typical semiconductor circuit with a minimum line width of 10 nm to 14 nm (so-called 10-nm design rules), the maximum allowable overlay error is 2 nm to 3 nm. In a leading-edge semiconductor circuit, the line width shrinks to 5 nm, and the maximum allowable overlay error decreases with it.

[0006] Overlay error is typically measured using optical overlay metrology equipment (often referred to as optical overlay metrology tools), because optical radiation in the visible and infrared wavelengths is able to penetrate the photoresist layer as well as the dielectric layers under the photoresist. In addition, infrared wavelengths are able to penetrate the semiconductor substrate (e.g., silicon) to enable through-substrate metrology. Overlay error is measured using overlay targets located in scribe lines (lines separating adjacent dies) of the semiconductor substrate and / or within the dies.

[0007] Commonly used overlay metrology tools fall into two categories: scatterometry tools and imaging tools. Scatterometry tools (such as the ATL100 TMThe instrument captures a diffraction (scattering measurement) image of the periodic target features of the superimposed target from the exit pupil of the objective lens. The processing instructions then analyze the scattering measurement image of the angular distribution of optical radiation scattered from the target features to measure the superimposition error.

[0008] Imaging tools (such as KLA's Archer from Milpitas, California) TM A series of tools) to capture images of overlaid targets, such as KLA's AIM. TM Overlaying targets. Image analysis algorithms are applied to the acquired image to locate the center of symmetry of target features in the process layer and the center of symmetry of the target structure in the photoresist layer. Overlay error is calculated based on the displacement between the centers of symmetry of the target features in the two layers.

[0009] The terms “optical radiation” and “light” (as used in this description and claims) generally refer to any or all of visible light, infrared light, and ultraviolet light. Summary of the Invention

[0010] The embodiments of the invention described below provide improved designs for stacked targets, particularly for scattering measurements, and methods and systems for metrology using such stacked targets.

[0011] Therefore, according to embodiments of the present invention, a method for semiconductor metrology is provided. The method includes depositing a first film layer on a semiconductor substrate and depositing a second film layer overlying the first film layer, and patterning the first and second film layers to define an overlay target. The overlay target includes a first grating pattern formed in the first film layer and including at least a first linear grating oriented in a first direction and at least a second linear grating oriented in a second direction perpendicular to the first direction. The overlay target further includes a second grating pattern formed in the second film layer and including at least a third linear grating identical to the first linear grating and a fourth linear grating identical to the second linear grating, the second grating pattern having a nominal offset relative to the first grating pattern by predetermined first and second displacements in the first and second directions. The method further includes using an imaging assembly to capture a scattering measurement image of the semiconductor substrate on which the overlay target is formed and processing the image to estimate an overlay error between the patterning of the first and second film layers.

[0012] In some embodiments, the first grating pattern further includes fifth and sixth linear gratings oriented in the first and second directions, respectively, and the second grating pattern further includes seventh and eighth linear gratings oriented in the first and second directions, respectively, and the third and fourth linear gratings are offset in positive directions relative to the first and second linear gratings by the predetermined first and second displacements, while the seventh and eighth linear gratings are offset in negative directions relative to the fifth and sixth linear gratings by the predetermined first and second displacements.

[0013] In the disclosed embodiments, the first and second displacements have equal magnitudes.

[0014] Additionally or alternatively, each of the linear gratings includes at least two parallel bars in each of the linear gratings, the bars having a pre-defined spacing therebetween, and the first linear grating and the second linear grating are separated by a distance equal to the pre-defined spacing between the bars.

[0015] In some embodiments, the first and second grating patterns have dimensions in a plane of the semiconductor substrate no larger than 10 pm x 10 pm. Alternatively, the first and second grating patterns have dimensions in the plane of the semiconductor substrate no larger than 5 pm x 5 pm.

[0016] In additional embodiments, the first film layer includes a process layer, and the second film layer includes a photoresist layer. Alternatively, each of the first and second film layers includes a process layer.

[0017] In some embodiments, capturing the scatterometry image includes focusing optical radiation scattered from the overlay target at an exit pupil of an objective lens, and imaging the exit pupil onto an image sensor. Additionally or alternatively, processing the image includes comparing two or more diffraction orders in the image to estimate the overlay error.

[0018] According to embodiments of the present application, there is also provided a mask set for patterning a semiconductor wafer. The mask set includes a first photolithography mask configured for patterning a first film layer on the semiconductor wafer, the first photolithography mask including: a first grating pattern including at least a first linear grating oriented in a first direction and at least a second linear grating oriented in a second direction perpendicular to the first direction. The mask set further includes a second photolithography mask configured for patterning a second film layer overlying the first film layer on the semiconductor wafer. The second photolithography mask includes a second grating pattern formed on the second film layer and including at least a third linear grating identical to the first linear grating and a fourth linear grating identical to the second linear grating, the second grating pattern having a nominal offset relative to the first grating pattern by a predetermined first and second displacement in the first and second directions, respectively.

[0019] The present application will be more fully understood from the following detailed description of embodiments thereof, taken together with the drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a schematic side view of a scatterometry overlay metrology apparatus for measuring overlay errors on a semiconductor wafer according to embodiments of the present application;

[0021] Figure 2 is a schematic front view of an overlay target for scatterometry according to embodiments of the present application;

[0022] Figure 3A and 3B is a schematic front view of a mask set including two photolithography masks according to embodiments of the present application; and

[0023] Figure 4 is a flowchart schematically illustrating a method for measuring overlay errors on a semiconductor wafer according to embodiments of the present application. DETAILED DESCRIPTION

[0024] Overlay targets are commonly used for accurate and precise measurement of overlay errors between successive patterned film layers on a semiconductor substrate. These layers can include, for example, process layers and photoresist layers, or, in post-etch applications, two process layers. Thus, although some example embodiments are described below with reference to process layers and photoresist layers, the principles of these embodiments can be applied to a first process layer and a second process layer with appropriate modifications.

[0025] In standard scatterometry overlay metrology, the overlay target includes linear gratings formed of parallel equispaced bars oriented in two orthogonal directions in the plane of the semiconductor wafer, with several sets of identical overlay gratings in a photoresist layer and a process layer. The gratings in the photoresist layer are offset by a predetermined nominal displacement of the value f0from the gratings in the process layer by a suitable shift of mask features in the lithography process, which is less than the grating pitch. The displacement of each linear grating is in a direction orthogonal to the grating bars. For each grating direction, some of the displacements are in the positive direction, while others are in the negative direction. These displacements break the symmetry between the gratings in the two layers and thus between the +1 and -1 diffraction orders, and overlay errors can be extracted from the diffraction signal. The sign of the displacement refers to a coordinate axis chosen arbitrarily, where the positive and negative directions of the axis can be chosen arbitrarily. Similarly, the choice of the sign of the diffraction order is arbitrary.

[0026] A common design of scatterometry overlay targets includes a square with four cells positioned as a square of four quadrants. A typical size of such a target is 20 μm x 20 μm with four 5 μm x 5 μm cells. Each cell includes a linear grating in the process layer (process grating), and the same linear grating in the photoresist layer (photoresist grating) overlying the process grating. In two of the cells, the bars of the linear gratings are oriented in the y direction, and the photoresist grating is offset in the x direction from the process grating; while in the other two cells, the bars are oriented in the x direction, and the photoresist grating is offset in the y direction from the process grating by a displacement f0, and in the fourth cell of the photoresist.

[0027] For such scatterometry overlay targets with such dimensions, the optical crosstalk in the form of diffraction between the ends of the bars of a grating pair in one cell and the orthogonally oriented grating pair in the adjacent cell is negligible. However, as the target size is reduced (e.g., in targets designed to be inserted in device areas), the total required size of the target shrinks to 5 μm x 5 μm or even smaller. For such small targets, the optical crosstalk between a grating pair and its orthogonally adjacent one can induce a significant error in the measurement results.

[0028] The embodiments described below solve the problem of optical crosstalk in small scatterometry targets by offsetting each of the gratings in the photoresist layer relative to the gratings in the process layer in both directions perpendicular and parallel to the grating bars. Thus, the ends of the bars are displaced along the long dimension of the bars. Therefore, by properly choosing the direction and sign of the displacement of each grating, the bar ends have the same offset as the long edges of the adjacent grating bars. In addition, the distance between the bar ends and the adjacent grating is designed to have the same pitch as the pitch of the adjacent grating bars. Thus, the bar ends add part of a bar to the adjacent grating and will contribute to the scatterometry signal in a beneficial manner rather than introducing an error.

[0029] In the disclosed examples, a method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and depositing a second film layer overlying the first film layer, and patterning the first and second film layers to define an overlay target. The overlay target includes a first grating pattern formed in the first film layer and including at least a first linear grating oriented in a first direction and at least a second linear grating oriented in a second direction perpendicular to the first direction. The overlay target further includes a second grating pattern formed in the second film layer and including at least a third linear grating identical to the first linear grating and a fourth linear grating identical to the second linear grating. The second grating pattern has a nominal offset in the first and second directions, respectively, of a predetermined first and second displacement relative to the first grating pattern. (In this description and claims, the term "nominal" refers to the dimensions and patterns that would be printed in an ideal lithography process according to the design of a mask used to pattern both film layers.)

[0030] The method further includes using the imaging assembly to capture a scatterometry image of the semiconductor substrate on which the overlay target has been formed, and processing the image to estimate overlay error between the patterning of the first and second film layers. Deviation of the scatterometry image from an image that would be obtained from an ideal process indicates deviation of actual offsets between grating patterns in the target from nominal offsets.

[0031] Figure 1 is a schematic side view of a scatterometry overlay metrology apparatus 10 for measuring overlay error on a semiconductor wafer 12 according to an embodiment of the present invention. The apparatus 10 is shown by way of example to illustrate the use of the overlay targets described herein. Alternatively, such targets can be used in other kinds of scatterometry systems.

[0032] The scatterometry overlay metrology apparatus 10 includes an imaging assembly 14, an illumination assembly 16, a controller 18, and a stage 20 on which the wafer 12 is mounted. The imaging assembly 14 includes an objective lens 22 having an exit pupil 23, a cube beam splitter 24, and an imaging lens 26. The imaging assembly 14 further includes a two-dimensional sensor array 28, including for example a complementary metal-oxide-semiconductor (CMOS) detector having a two-dimensional array of pixels 30. The imaging lens 26 images the exit pupil 23 onto the sensor array 28.

[0033] The illumination assembly 16 includes a light source 32 that emits optical radiation and a lens 34. The stage 20 is located near the objective lens 22 and includes actuators controlled by the controller 18 that can linearly move the stage in x, y, and z directions (with reference to a Cartesian coordinate system 36), as well as rotate the stage about the z axis.

[0034] In the depicted embodiment, a first film layer 38 has been deposited on the semiconductor wafer 12 and patterned in a lithography process. In a subsequent process step, a second film layer 40, including photoresist, has been deposited on the first film layer 38. In this embodiment, the first film layer 38 is referred to as a "process layer," and the second film layer 40 is referred to as a "photoresist layer." In alternative embodiments (e.g., post-etch applications), both the first and second film layers can comprise process layers. The layers 38 and 40 include patterns formed by a lithography process in which semiconductor circuitry is formed in the wafer 12 that includes target features of a scatterometry overlay target, such as Figure 2 the overlay target shown in FIG. 1 and described below.

[0035] The controller 18 is coupled to the sensor array 28 and the stage 20. The controller 18 typically includes a programmable processor programmed with software and / or firmware to perform the functions described herein, along with suitable digital and / or analog interfaces for connection to the other elements of the apparatus 10. Alternatively or additionally, the controller 18 includes hard-wired and / or programmable hardware logic circuitry that performs at least some of the functions of the controller. Although the controller 18 is shown in FIG. 1 as a single monolithic functional block for simplicity, in practice the controller can include multiple interconnected control units with suitable interfaces for receiving and outputting the signals illustrated in the figures and described in the text. Figure 1

[0036] To capture a scatterometry image of the scatterometry overlay target in the film layers 38 and 40, the wafer 12 is positioned on the stage 20 so that the target is in the field of view (FOV) of the objective lens 22. The light source 32 projects a beam of coherent optical radiation to the lens 34, which further projects the beam to the cube beam splitter 24. The beam splitter 24 reflects the beam into the objective lens 22, which projects the beam onto the wafer 12. The radiation that is illuminated on the wafer 12 scatters back to the objective lens 22, where the angular distribution of the scattered radiation forms a scatterometry image in the exit pupil 23. The scatterometry image is imaged by the lens 26 onto the sensor array 28. The controller 18 reads the image and processes the image to measure overlay error.

[0037] Figure 2 An overlay target 100 for scatterometry of overlay error according to an embodiment of the present application is shown. Cartesian coordinates 36 are also shown in this figure to clarify the orientation of the overlay target 100 relative to the apparatus 10, and to facilitate description of the target.

[0038] From the z-direction in this figure, the target 100 includes four cells 102, 104, 106, and 108. Each cell includes a pattern formed in a photoresist layer 40 (e.g., the second film layer 40 in FIG. 1) on a process layer 38 (e.g., the first film layer 38 in FIG. 1). The process layer 38 is a layer of material that is used in the fabrication of semiconductor circuitry, such as a layer of silicon dioxide or a layer of photoresist. The photoresist layer 40 is a layer of photoresist that is used in a lithography process to form a pattern in the process layer 38. Figure 1 ​linear gratings in FIG. 1 1 1, which overlay the same linear gratings formed in underlying process layer 38, have a nominal offset in both the x and y directions. In the depicted example, each linear grating includes two parallel bars, with the gratings and bar labels as follows:

[0039] Table 1 : Grating and bar labels within a cell

[0040]

[0041] The first grating pattern of layer 38 and the second grating pattern of layer 40 are further detailed below.

[0042] Although for simplicity, Figure 2 While each of the linear gratings in FIG. 1 1 1 includes only two bars, in practice, each of the gratings formed in layers 38 and 40 typically includes a larger number of bars.

[0043] The two linear gratings within a cell are parallel to each other. Thus, for example, linear gratings 140 and 142 of cell 102 are parallel to each other. In the depicted example, the gratings in cells 102 and 106 are oriented in the y direction, and the gratings in cells 104 and 108 are oriented in the x direction. In all four cells, the bars in the photoresist layer and process layer have the same nominal bar width (critical dimension, CD) W and bar-to-bar spacing S.

[0044] Target 100 includes a first grating pattern in layer 38 and a second grating pattern in layer 40. In aggregate (Table 1 ), linear gratings 142, 146, 150, and 154, which include bars 1 12a / b, 1 16a / b, 120a / b, and 124a / b, respectively, make up the first grating pattern, while linear gratings 140, 144, 148, and 152, which include bars 1 10a / b, 1 14a / b, 1 18a / b, and 122a / b, respectively, make up the second grating pattern. The second grating pattern has a nominal offset relative to the first grating pattern, defined by a displacement in both the x and y directions, as explained in further detail below. Although Figure 2 The grating patterns shown in FIG. 1 1 1 include four linear gratings in each of layers 38 and 40, but in alternative embodiments, overlay targets with these kinds of nominal offsets can include a fewer number of gratings, e.g., two gratings or a larger number of gratings. Furthermore, although Figure 2 The grating patterns shown in FIG. 1 1 1 have, for convenience, the same geometry (including width, spacing, and offset) in both the x and y directions, but in alternative embodiments, the dimensions in the x and y dimensions can be different.

[0045] Two aspects of the target 100 are useful in mitigating the negative effects of optical cross-talk and improving scatterometry images for computing overlay error: 1) a selected pitch between adjacent cells, and 2) a nominal offset between the bars in layers 38 and 40, including a displacement in each of the two x and y directions.

[0046] As previously described, the nominal offset in this description refers to an offset designed in the lithography process, where the offset is implemented by a suitable displacement of features in a lithography mask used to produce the bars. The actual offset of the bars in layer 40 relative to the bars in layer 38 is the sum of the nominal offset and the overlay error. The nominal offset is used to break the symmetry between the +1 and -1 diffraction orders of the scatterometry signal and thus enable the controller 18 to process the scatterometry images to estimate the overlay error between layers 38 and 40.

[0047] For example, with reference to cells 102 and 104, the nominal pitch between the ends of bars 116a and 116b in layer 38 of cell 104 and the adjacent bar 112b in layer 38 of cell 102 is designed to have the same nominal pitch S as between bars 112a and 112b. Similarly, with reference to cells 102 and 108, the nominal pitch between the ends of bars 112a and 112b in layer 38 of cell 102 and the adjacent bar 124b in layer 38 of cell 108 is designed to have the same nominal pitch S as between bars 124a and 124b. Similar pitches are applied between the other two pairs of cells (cells 106 and 108 and cells 104 and 106).

[0048] With further reference to cell 102, the nominal offset between bars 110a and 110b in layer 40 relative to bars 112a and 112b in layer 38 includes a displacement -f0 in the y direction and a displacement -f0 in the x direction. The displacement f0 is typically a fraction of the bar width W. Here, the negative direction of the displacement indicates that the displacement is in the negative direction of the coordinate axis of the Cartesian coordinate 36. (The direction of the "positive" and "negative" directions of the coordinate axis has been arbitrarily chosen.)

[0049] In cell 108, bars 122a and 122b have a nominal offset relative to respective bars 124a and 124b, which includes a displacement -f0 in the y direction and a displacement +f0 in the x direction.

[0050] The nominal offset of cell 106 includes a displacement in the opposite direction relative to cell 102, i.e., bars 118a and 118b are displaced +f0 in the positive direction of both the x and y axes relative to respective bars 120a and 120b.

[0051] Finally, the nominal shift of the cell 104 comprises a displacement in opposite direction relative to the cell 108, meaning that the bars 114a and 114b are displaced in the y-direction by +f0 and in the x-direction by -f0 relative to the respective bars 116a and 116b.

[0052] Combining the pitch between the cells with the (two-dimensional) nominal shift of the grating pattern has the effect that the ends of the bars in each cell have a structure similar to the long sides of the bars in the neighboring cell. For example, the layer structure and the pitch in the region 126 encompassing the ends of the bars 116a and 114a in the cell 104 and the long-side facing regions of the bars 112b and 110b in the cell 102 is identical to the layer structure and the pitch in the region 128 encompassing the bars 112a and 112b and the bars 110a and 110b in the cell 102. Thus, the structure in the region 126 contributes to the scatterometry image formed by the bars 110a / b and 112a / b in the cell 102. Similarly by the ends of the bars 116b and 114b in the region 130.

[0053] In the overlay target 100, each of the cells 102, 104, 106 and 108 comprises two bars. As previously mentioned, in an alternative overlay target, the cells can comprise a larger number of bars, for example three, four, five or more bars. A larger number of bars increases the diffraction efficiency of the target 100 and thus improves the quality of the scatterometry image imaged onto the sensor array 28 Figure 1 ) but at the cost of a larger target size.

[0054] The pitch (period) P of the grating given by P = W + S is chosen such that the first diffraction orders (+1 and -1) of the light diffracted from the target 100 are imaged within the exit pupil 23 of the objective 22 Figure 1 ). Depending on the numerical aperture (NA) of the objective 22 and the spectrum of the coherent optical radiation emitted by the light source 32, the pitch P can be chosen to be, for example, 500 nm, with a bar width W = 250 nm and a bar pitch S = 250 nm. Alternatively, the pitch P can be larger, for example 700 nm or 800 nm, corresponding to a grating with equal bar width and pitch of W = 350 nm or 400 nm and S = 350 nm or 400 nm, respectively. In alternative examples, unequal pitches and pitches can be chosen.

[0055] Depending on the number of bars within a cell and the pitch P of the bars, the overlay target according to embodiments of the application can have outer dimensions in the plane of the substrate 20 of less than 10 pm x 10 pm. By appropriate choice of grating pitch, bar width and number of bars, the overlay target can be made as small as 5 pm x 5 pm and still give good performance in the scatterometry measurement of overlay errors, or even as low as 2 pm x 2 pm or smaller when finer design rules are implemented.

[0056] Figure 3A and 3B is a schematic front view of a set of masks including lithography masks 180 and 182 that can be used to produce an overlay target 100 according to embodiments of the present application. (In practice, such masks typically include a larger set of device features, but for simplicity, Figure 3A and 3B only overlay target features are shown.)

[0057] Lithography mask 180 includes openings (e.g., openings 184a and 184b) in an opaque background 181 that define a first grating pattern on process layer 38 during a lithography process. For example, openings 184a and 184b define bars 124a and 124b, Figure 2 respectively. Lithography mask 182 includes openings (e.g., openings 186a and 186b) in an opaque background 183 that define a second grating pattern on photoresist layer 40. For example, openings 186a and 186b define bars 122a and 122b, Figure 2 respectively. The openings of mask 182 are shifted relative to the openings of mask 180 in both the x and y directions to produce a desired nominal offset between the first and second grating patterns.

[0058] Alternatively, instead of uniform grating bars, each opening can include a set of multiple closely spaced parallel openings such that the corresponding multi-line printed on semiconductor substrate 12 conforms to the design rules of the lithography process. The set of multi-lines defines bars in the overlay target because the individual lines are typically not resolvable by imaging assembly 14 of apparatus 10.

[0059] Figure 4 is a flowchart 200 that schematically illustrates the manufacture of an overlay target (e.g., target 100) and the use of the target to measure overlay error according to embodiments of the present application.

[0060] In a first deposition step 202, a first film layer (e.g., process layer 38, as shown in Figure 1 ) is deposited on semiconductor substrate 20. In a first patterning step 204, a first grating pattern is patterned in the first layer (e.g., by a lithography process using a first mask followed by etching). In a second deposition step 206, a second film layer (e.g., photoresist layer 40) is deposited on the first layer. In a second patterning step 208, a second grating pattern is patterned in the second layer (e.g., using a second lithography mask) with a pre-defined offset in the x and y directions for each grating of the grating pattern. The first and second grating patterns together constitute an overlay target.

[0061] After patterning the first and second film layers in this manner, a scatterometry image is captured (e.g., by imaging assembly 14 of apparatus 10) in scatterometry image capture step 210. In overlay error estimation step 212, controller 18 of apparatus 10 processes the scatterometry image to estimate the overlay error between layers 38 and 40.

[0062] It should be appreciated that the foregoing examples have been presented by way of example only, and that the application is not limited to the particulars described above. Rather, the scope of the present application includes combinations and sub-combinations of the various features described above, as well as variations and modifications thereof that occur to those skilled in the art upon reading the foregoing description, which are not disclosed in the prior art.

Claims

1. A method for semiconductor metrology, comprising: depositing a first film layer on a semiconductor substrate and depositing a second film layer overlying the first film layer; patternizing the first and second film layers to define an overlay target, the overlay target comprising: a first grating pattern formed in the first film layer and comprising at least a first linear grating oriented in a first direction and at least a second linear grating oriented in a second direction perpendicular to the first direction; and a second grating pattern formed in the second film layer and comprising at least a third linear grating identical to the first linear grating and a fourth linear grating identical to the second linear grating, the third linear grating having a nominal offset relative to the first linear grating by a predetermined first displacement and a second displacement in a negative direction of the first direction and a negative direction of the second direction, respectively; and the fourth linear grating having the nominal offset relative to the second linear grating by a predetermined third displacement and a predetermined fourth displacement in a positive direction of the first direction and the negative direction of the second direction, respectively; acquiring a scatterometry image of the semiconductor substrate on which the overlay target has been formed using an imaging assembly; and processing the scatterometry image to estimate an overlay error between the patterization of the first and second film layers, wherein each of the linear gratings comprises at least two parallel bars in each of the linear gratings with a pre-defined spacing between the bars, and wherein the first linear grating and the second linear grating are separated by a distance equal to the pre-defined spacing between the bars.

2. The method of claim 1, wherein the first grating pattern further comprises a fifth linear grating and a sixth linear grating oriented in the first direction and the second direction, respectively, and the second grating pattern further comprises a seventh linear grating and an eighth linear grating oriented in the first direction and the second direction, respectively, and wherein the seventh linear grating is offset relative to the fifth linear grating by a predetermined fifth displacement in the positive direction of the first direction, and the seventh linear grating is offset relative to the fifth linear grating by a predetermined sixth displacement in the positive direction of the second direction, and the eighth linear grating is offset relative to the sixth linear grating by a predetermined seventh displacement in the negative direction of the first direction, and the eighth linear grating is offset relative to the sixth linear grating by a predetermined eighth displacement in the positive direction of the second direction.

3. The method of claim 1, wherein the first displacement, the second displacement, the third displacement, and the fourth displacement have equal values.

4. The method of claim 1, wherein the first grating pattern and the second grating pattern have a size in a plane of the semiconductor substrate no greater than 10 pm x 10 pm.

5. The method of claim 4, wherein the first grating pattern and the second grating pattern have a size in the plane of the semiconductor substrate no greater than 5 pm x 5 pm.

6. The method of claim 1, wherein the first film layer comprises a process layer and the second film layer comprises a photoresist layer.

7. The method of claim 1, wherein each of the first film layer and the second film layer comprises a process layer.

8. The method of claim 1, wherein retrieving the scatterometry image comprises: focusing optical radiation scattered from the overlay target at an exit pupil of the objective; and imaging the exit pupil onto an image sensor.

9. The method of claim 8, wherein processing the scatterometry image comprises: comparing two or more diffraction orders in the scatterometry image to estimate the overlay error.

10. The method of claim 2, wherein the first displacement, the second displacement, the third displacement, the fourth displacement, the fifth displacement, the sixth displacement, the seventh displacement, and the eighth displacement have equal values.

11. A mask set for patterning a semiconductor wafer, the mask set comprising: a first lithography mask configured for patterning a first film layer on the semiconductor wafer, the first lithography mask comprising a first grating pattern, the first grating pattern comprising at least a first linear grating oriented in a first direction and at least a second linear grating oriented in a second direction perpendicular to the first direction; and a second lithography mask configured for patterning a second film layer overlying the first film layer on the semiconductor wafer, the second lithography mask comprising a second grating pattern, the second grating pattern formed on the second film layer and comprising at least a third linear grating identical to the first linear grating and a fourth linear grating identical to the second linear grating, the third linear grating having a nominal offset of a predetermined first displacement and a second displacement relative to the first linear grating in a negative direction of the first direction and a negative direction of the second direction, respectively; and the fourth linear grating having the nominal offset of a predetermined third displacement and a predetermined fourth displacement relative to the second linear grating in a positive direction of the first direction and the negative direction of the second direction, respectively, wherein each of the linear gratings comprises at least two parallel bars in each of the linear gratings with a pre-defined spacing between the bars, and wherein the first linear grating and the second linear grating are separated by a distance equal to the pre-defined spacing between the bars.

12. The mask set of claim 11, wherein the first grating pattern further comprises a fifth linear grating and a sixth linear grating oriented in the first direction and the second direction, respectively, and the second grating pattern further comprises a seventh linear grating and an eighth linear grating oriented in the first direction and the second direction, respectively, and wherein the seventh linear grating is offset from the fifth linear grating by a predetermined fifth displacement in the positive direction of the first direction and the seventh linear grating is offset from the fifth linear grating by a predetermined sixth displacement in the positive direction of the second direction, and the eighth linear grating is offset from the sixth linear grating by a predetermined seventh displacement in the negative direction of the first direction and the eighth linear grating is offset from the sixth linear grating by a predetermined eighth displacement in the positive direction of the second direction.

13. The mask set of claim 11, wherein the first displacement, the second displacement, the third displacement, and the fourth displacement have equal values.

14. The mask set of claim 11, wherein the first grating pattern and the second grating pattern have a size in a plane of the semiconductor substrate that is no greater than 10 pm x 10 pm.

15. The mask set of claim 14, wherein the first grating pattern and the second grating pattern have a size in the plane of the semiconductor substrate that is no greater than 5 pm x 5 pm.

16. The mask set of claim 12, wherein the first displacement, the second displacement, the third displacement, the fourth displacement, the fifth displacement, the sixth displacement, the seventh displacement, and the eighth displacement have equal values.

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