Doherty amplifier and its output network, design method of Doherty amplifier

Abstract

An embodiment of the present application provides an output network for a Doherty amplifier. The output network includes: a combining node, a main output network connected between the output end of the main amplifier of the Doherty amplifier and the combining node, a secondary output network connected between the output end of the secondary amplifier of the Doherty amplifier and the combining node, and a combining matching network connected between the combining node and the RF output end of the Doherty amplifier. The secondary output network includes a first sub-network and a second sub-network connected in series. The first sub-network and the main output network have the same circuit topology and each includes at least an inductor and a capacitor, and the second sub-network includes at least an inductor. The combining matching network is configured such that the node impedance at the combining node is a complex impedance, and the main output network and the secondary output network are configured such that the node impedance is matched to the target load impedance of the main amplifier and the secondary amplifier.

Description

Technical Field

[0001] The present application relates to the field of wireless communication, and more particularly, to an output network for a Doherty amplifier, a Doherty amplifier including the output network, and a method for designing a Doherty amplifier. Background Art

[0002] With the development of wireless communication technology, the communication bandwidth required by wireless communication systems is constantly increasing, and the modulation signals adopted by wireless communication systems are also becoming more and more complex. In order to meet the requirements for the bandwidth, efficiency, volume, etc. of wireless communication systems, in the radio frequency front-end system of wireless communication networks, higher and higher requirements are put forward for the efficiency, back-off power range, operating bandwidth, size, etc. of power amplifiers (PAs).

[0003] In related technologies, Doherty amplifiers can be used in the radio frequency front-end of wireless communication systems (including base stations, broadcasts, and mobile terminals, etc.) to improve the efficiency of wireless communication systems. However, due to the continuous increase in the number of radio frequency link units (including power amplifiers and antennas, etc.) included in the radio frequency front-end system, and the fact that Doherty amplifiers use more components and have a larger circuit size, it is difficult to meet the design requirements of miniaturized amplifiers. In addition, since the load modulation of Doherty amplifiers is achieved by quarter-wavelength transmission lines, this structure results in a narrow operating bandwidth and a small back-off power range with high efficiency for Doherty amplifiers. Therefore, it is difficult for wireless communication systems to meet the increasingly high requirements in terms of bandwidth, efficiency, volume, etc. through traditional Doherty amplifiers. Currently, there are some methods to increase the bandwidth by improving the load modulation network of Doherty amplifiers, but this often increases the size of Doherty amplifiers, making it difficult to achieve a good balance among the efficiency, bandwidth, back-off power range, and circuit size of the amplifiers. Summary of the Invention

[0004] In view of this, the present application provides an output network for a Doherty amplifier, a Doherty amplifier including the output network, and a method for designing a Doherty amplifier to alleviate, mitigate, or even eliminate the above problems.

[0005] Embodiments of the present application provide an output network for a Doherty amplifier. The Doherty amplifier includes a main amplifier and a auxiliary amplifier. The output network includes: a combining node, a main output network connected between the output end of the main amplifier and the combining node, a auxiliary output network connected between the output end of the auxiliary amplifier and the combining node, and a combining matching network connected between the combining node and the RF output end of the Doherty amplifier. Wherein the auxiliary output network includes a first sub-network and a second sub-network connected in series. The first sub-network and the main output network have the same circuit topology and each includes at least an inductor and a capacitor. And the second sub-network includes at least an inductor. Wherein the combining matching network is configured such that the node impedance at the combining node is a complex impedance. The main output network and the auxiliary output network are configured such that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier.

[0006] According to some embodiments of the present application, the main output network is equivalent to a first transmission line in the operating frequency band, and the auxiliary output network is equivalent to a second transmission line in the operating frequency band. The electrical angle θ of the first transmission line M and the electrical angle θ of the second transmission line A satisfy: 70° < θ M < 90°, and 135° < θ A < 180°.

[0007] According to some embodiments of the present application, the output network is configured such that the output current I of the main amplifier M and the output current I of the auxiliary amplifier A satisfy: the amplitude of I M is not greater than the amplitude of I A , and the phase difference between I M and I A is less than 90°.

[0008] According to some embodiments of the present application, both the first sub-network and the main output network include a first capacitor, a second capacitor and a first inductor. One end of the first capacitor and one end of the first inductor are both connected to the output end of the main amplifier or the auxiliary amplifier. The other end of the first capacitor is grounded. The other end of the first inductor is connected to one end of the second capacitor. The other end of the second capacitor is grounded.

[0009] According to some embodiments of the present application, both the first sub-network and the main output network further include a third capacitor. One end of the third capacitor is connected to the output end of the main amplifier or the auxiliary amplifier. The other end of the third capacitor is grounded.

[0010] According to some embodiments of the present application, the first sub-network and the main output network both further include a second inductor. One end of the second inductor is connected to the output end of the main amplifier or the auxiliary amplifier, and the other end of the second inductor is grounded.

[0011] According to some embodiments of the present application, the second sub-network includes a third inductor and a fourth capacitor. One end of the third inductor is connected to the output end of the first sub-network, the other end of the third inductor is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded.

[0012] According to some embodiments of the present application, the combining matching network includes a fourth inductor, a fifth inductor, a sixth inductor, a fifth capacitor, and a sixth capacitor. One end of the fourth inductor is connected to the combining node, the other end of the fourth inductor is connected to both one end of the fifth capacitor and one end of the fifth inductor. The other end of the fifth capacitor is grounded. The other end of the fifth inductor is connected to both one end of the sixth capacitor and one end of the sixth inductor. The other end of the sixth capacitor is grounded. The other end of the sixth inductor is connected to a DC voltage terminal, and the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the sixth inductor, the fifth inductor, the fourth inductor, the main output network, and the auxiliary output network.

[0013] According to some embodiments of the present application, the combining matching network includes a third transmission line, a fourth transmission line, a fifth transmission line, a sixth transmission line, and a seventh capacitor. One end of the third transmission line is connected to the combining node, the other end of the third transmission line is connected to both one end of the fourth transmission line and one end of the fifth transmission line. The other end of the fourth transmission line is connected to the DC voltage terminal and one end of the seventh capacitor. The other end of the seventh capacitor is grounded. The other end of the fifth transmission line is connected to one end of the sixth transmission line, and the other end of the sixth transmission line is floating. The DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the fourth transmission line, the third transmission line, the main output network, and the auxiliary output network.

[0014] According to some embodiments of the present application, the combining and matching network includes a seventh inductor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a seventh transmission line, and an eighth transmission line. One end of the seventh inductor is connected to the combined node, and the other end of the seventh inductor is connected to one end of the eighth capacitor and one end of the seventh transmission line. The other end of the eighth capacitor is grounded. The other end of the seventh transmission line is connected to one end of the ninth capacitor and one end of the eighth transmission line. The other end of the ninth capacitor is grounded. The other end of the eighth transmission line is connected to a DC voltage terminal. One end of the tenth capacitor is connected to the DC voltage terminal, and the other end of the tenth capacitor is grounded. The DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the eighth transmission line, the seventh transmission line, the seventh inductor, the main output network, and the auxiliary output network.

[0015] According to some embodiments of the present application, at least one of the first to tenth capacitors can be implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device.

[0016] According to some embodiments of the present application, at least one of the first to seventh inductors can be implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device, a bonding wire, a microstrip line, a metal winding, a transmission line.

[0017] According to some embodiments of the present application, at least one of the third to eighth transmission lines can be implemented in at least one of the following forms: a microstrip line, a strip line, a coplanar waveguide, a substrate integrated waveguide.

[0018] Another embodiment of the present application provides a Doherty amplifier, including: a main amplifier; an auxiliary amplifier; and an output network according to any one of the foregoing embodiments, wherein the output network is configured to receive a first amplified signal output by the main amplifier and a second amplified signal output by the auxiliary amplifier, so that the first amplified signal and the second amplified signal are combined at the combined node to be provided to the RF output terminal of the Doherty amplifier.

[0019] Another embodiment of the present application provides a method for designing a Doherty amplifier, the Doherty amplifier including a main amplifier, a auxiliary amplifier, and an output network, wherein the method includes: setting target performance indicators of the Doherty amplifier, the target performance indicators at least including the operating frequency, saturation power, and dynamic range of the Doherty amplifier; selecting transistors for the main amplifier and the auxiliary amplifier according to the target performance indicators; determining first, second, and third target impedances based on load-pull testing or simulation analysis, wherein the first target impedance is the load impedance that maximizes the efficiency of the main amplifier when the Doherty amplifier is in the back-off power state, the second target impedance is the load impedance that maximizes the efficiency of the main amplifier when the output power of the main amplifier reaches the saturation power, and the third target impedance is the load impedance that maximizes the efficiency of the auxiliary amplifier when the output power of the auxiliary amplifier reaches the saturation power; determining the circuit topologies and component parameters of each sub-network in the auxiliary output network and the main output network, and determining the circuit topology and component parameters of the combining matching network based on the first, second, and third target impedances.

[0020] In an output network for a Doherty amplifier according to some embodiments of the present application, a main output network, an auxiliary output network, and a combining matching network are provided, wherein the auxiliary output network includes a first sub-network and a second sub-network connected in series, wherein the combining matching network is configured such that the node impedance at the combining node is a complex impedance, and the main output network and the auxiliary output network are configured such that the node impedance is matched to the target load impedances of the main amplifier and the auxiliary amplifier, so that the Doherty amplifier can operate efficiently from low power to high power. On the other hand, the first sub-network and the main output network have the same circuit topology and both include at least an inductor and a capacitor, and the second sub-network includes at least an inductor, which helps to simplify the structure of the output network of the Doherty amplifier and the corresponding design process.

[0021] These and other aspects of the present application will be apparent and will be elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In the following description of exemplary embodiments in conjunction with the drawings, more details, features, and advantages of the technical solution of the present application are disclosed. In the drawings:

[0023] Figure 1 Schematically shows an exemplary schematic diagram of a Doherty amplifier in the related art;

[0024] Figure 2Schematically shows an exemplary schematic diagram of an output network for a Doherty amplifier according to some embodiments of the present application;

[0025] Figure 3 Schematically shows according to some embodiments of the present application Figure 2 Exemplary schematic diagram of the output network in [the text] achieving load modulation at low power;

[0026] Figure 4 Schematically shows according to some embodiments of the present application Figure 2 Exemplary schematic diagram of the output network in [the text] achieving load modulation at high power;

[0027] Figure 5 Schematically shows an exemplary circuit topology diagram of a first sub-network and a main output network according to some embodiments of the present application;

[0028] Figure 6 Schematically shows an exemplary circuit topology diagram of a second sub-network according to some embodiments of the present application;

[0029] Figure 7 Schematically shows an exemplary circuit topology diagram of a combining matching network according to some embodiments of the present application;

[0030] Figure 8 Schematically shows an exemplary schematic diagram of a Doherty amplifier according to some embodiments of the present application;

[0031] Figure 9 Schematically shows a schematic diagram of a package structure included in a Doherty amplifier according to some embodiments of the present application;

[0032] Figure 10 Schematically shows a schematic diagram of a package structure included in a Doherty amplifier according to some other embodiments of the present application;

[0033] Figure 11 Schematically shows a schematic diagram of a package structure included in a Doherty amplifier according to still some other embodiments of the present application;

[0034] Figure 12 Schematically shows a schematic diagram of various implementation manners of an inductor according to some embodiments of the present application;

[0035] Figure 13 Schematically shows a schematic diagram of the structure of a Doherty amplifier according to some embodiments of the present application;

[0036] Figure 14 Schematically shows a flowchart of a method for designing a Doherty amplifier according to some embodiments of the present application;

[0037] Figure 15Schematically shows a performance example diagram of a Doherty amplifier according to some embodiments of the present application;

[0038] Figure 16 Schematically shows a performance example diagram of a Doherty amplifier according to some embodiments of the present application. Detailed implementation

[0039] Several embodiments of the present application will be described in more detail below with reference to the accompanying drawings so that those skilled in the art can implement the technical solutions of the present application. The technical solutions of the present application can be embodied in many different forms and purposes, and should not be limited to the embodiments described herein. These embodiments are provided to make the technical solutions of the present application clear and complete, but the embodiments do not limit the protection scope of the present application.

[0040] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present application belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of the present specification, and will not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0041] Figure 1 Schematically shows an exemplary schematic diagram of a Doherty amplifier in the related art. As Figure 1 shown, the Doherty amplifier includes two amplifiers (a main amplifier and a sub - amplifier). The main amplifier and the sub - amplifier are respectively connected to two output ports of a power divider (not shown). The RF output ports of the main amplifier and the sub - amplifier are connected to a power combining network composed of capacitors and inductors. Among them, C dsM and C dsA are respectively the parasitic capacitances of the transistors corresponding to the main amplifier and the sub - amplifier themselves. C addM and C M -C dsA are lumped capacitance elements, L M is a lumped inductance element. The two - port network formed by these capacitance and inductance elements can be equivalent to a transmission line with a characteristic impedance of Z M and an electrical length of 90° (i.e., a quarter - wavelength transmission line) in the operating frequency band. In the related art, the main amplifier operates in class B or class AB, and the sub - amplifier operates in class C. As the input power increases, the current output after the sub - amplifier is turned on will affect the load R LIt generates a modulation effect, and then dynamically modulates the respective loads of the two amplifiers (this process is also known as "dynamic load modulation"). The two amplifiers do not work alternately. Instead, the main amplifier works all the time, and the auxiliary amplifier starts to work when the input power reaches the set peak value. The quarter-wave transmission line in the output path of the main amplifier can play a role in phase compensation, making the output signals in the output path of the main amplifier and the output path of the auxiliary amplifier have the same phase at the combining point.

[0042] With the continuous development of communication technologies, multiple-input multiple-output (MIMO) systems have been increasingly widely used. The radio frequency front-end system of an MIMO system includes multiple (for example, dozens or even hundreds) of radio frequency link units, which poses higher and higher requirements for the miniaturized design of power amplifiers in the radio frequency link units. However, the traditional solutions have high complexity, use many components, and large circuit sizes, making it difficult to meet the design requirements of miniaturized amplifiers.

[0043] On the other hand, the increase in circuit components brings more problems to the integrated design of power amplifiers. Not only does the design difficulty increase, the overall circuit size increases, and the chip cost increases, but also the circuit loss becomes larger and the efficiency of the power amplifier decreases, which makes it more difficult to design an efficient, energy-saving, and low-cost system.

[0044] In addition, with the continuous iteration of communication systems, the communication bandwidth has doubled. For example, in the 5G scenario, the communication bandwidth has reached 500 MHz or even higher, which poses a high challenge to the operating bandwidth of power amplifiers. In Figure 1 it, the load modulation of the Doherty amplifier is achieved by a quarter-wave transmission line, and this structure has only a narrow operating bandwidth (usually less than 200 MHz), so this architecture far cannot meet the requirements of today's system for broadband operation.

[0045] Figure 2 Schematically shows an exemplary schematic diagram of an output network 200 for a Doherty amplifier according to some embodiments of the present application. As Figure 2 shown, the output network 200 includes: a combining node 230, a main output network 210 connected between the output end of the main amplifier of the Doherty amplifier and the combining node 230, a secondary output network 220 connected between the output end of the secondary amplifier of the Doherty amplifier and the combining node 230, and a combining matching network 240 connected between the combining node 230 and the radio frequency output end of the Doherty amplifier.

[0046] Exemplarily, the auxiliary output network 220 includes a first sub-network 221 and a second sub-network 222 connected in series. The first sub-network 221 and the main output network 210 have the same circuit topology and each includes at least an inductor and a capacitor. The second sub-network 222 includes at least an inductor. The combining matching network 240 is configured such that the node impedance at the combining node 230 is a complex impedance Z combine , the main output network 210 and the auxiliary output network 220 are configured such that the node impedance is matched to the target load impedance of the main amplifier and the auxiliary amplifier. Exemplarily, the second sub-network 222 may include only one inductor, one end of which is connected to the output end of the first sub-network 221 and the other end of which is connected to the combining node 230. Alternatively, the second sub-network 222 may include an inductor and a capacitor (e.g., an LC circuit).

[0047] As Figure 2 shown, Z combine is the equivalent impedance seen from the combining node 230 towards the combining matching network 240, which can be regarded as the ratio of the voltage U TC at the combining node 230 to the current I TC flowing into the combining matching network 240 in some cases. The combining matching network 240 may include appropriate types and quantities of circuit devices as long as these circuit devices make the node impedance at the combining node 230 a complex impedance Z combine . Exemplarily, the combining matching network 240 may include an LC circuit, which transforms the load (e.g., Figure 1 the R L ) at the RF output end of the Doherty amplifier into a complex impedance Z combine , that is, makes the node impedance at the combining node 230 a complex impedance Z combine .

[0048] It should be noted that in this application, the statement "A and B have the same circuit topology" indicates that A and B include the same types and quantities of circuit elements (devices, components), and the connection relationships between these circuit elements in A and B are also the same. Exemplarily, the first sub-network 221 and the main output network 210 with the same circuit topology may both include an LC circuit or an LLC circuit. Additionally, although the first sub-network 221 and the main output network 210 have the same circuit topology, this does not mean that the element parameters of the first sub-network 221 and the main output network 210 are also the same. For example, they may both include an LC circuit, but the corresponding inductance values and capacitance values in the LC circuits may be different.

[0049] In Figure 2In the illustrated embodiment, the first sub-network 221 and the second sub-network 222 form the auxiliary output network 220, but this does not exclude the case where the auxiliary output network 220 includes other components (and the same applies to the main output network 210). For example, in other embodiments, the main output network 210 may further include other circuit devices, such as capacitors for isolating direct current; similarly, the auxiliary output network 220 may also include other circuit devices, such as capacitors for isolating direct current. Additionally or alternatively, the auxiliary output network 220 may further include other sub-networks, such as one or more third sub-networks (whose circuit topology may be the same as that of the second sub-network 222).

[0050] In addition, the combination node 230 indicates the common connection point of the main output network 210, the auxiliary output network 220, and the combining matching network 240. Exemplarily, the combination node 230 may be the electrical common connection point of the main output network 210, the auxiliary output network 220, and the combining matching network 240. The combination node 230 may also be the electrical node at the output end of the main output network 210, or the electrical node at the output end of the auxiliary output network 220. Even the combination node 230 may be the electrical node at the input end of the combining matching network 240.

[0051] Specifically, the impedance matching process of the output network 200 will be elucidated below in conjunction with Figure 3 and Figure 4 to clarify the impedance matching process of the output network 200.

[0052] As Figure 3 shown, at low power, the auxiliary amplifier is not turned on, so it can be equivalently regarded as an open circuit state. At this time, the branch where the auxiliary output network 320 is located (hereinafter simply referred to as the auxiliary path) provides the auxiliary path impedance Z off at the combination node 330, which is connected in parallel with the node impedance Z combine to one end of the branch where the main output network 310 is located (hereinafter simply referred to as the main path). At the back-off power, the main output network 310 can convert the parallel impedance Z off of the auxiliary path impedance Z combine and the node impedance Z off / / Z combine into the target load impedance of the main amplifier at the back-off power ( Figure 3 the Z goal, BO in). For the main amplifier or the auxiliary amplifier (usually implemented as a transistor), its target load impedance indicates the optimal power matching impedance of the amplifier at a specific power level, that is, the load impedance that can make the amplifier reach the highest efficiency value at a specific power level. The target load impedance depends on the parameters of the amplifier itself and the actual power level, and it can be obtained through theoretical calculation or simulation analysis, or by experimental measurement methods (such as load-pull testing). The main output network 310 converts the parallel impedance Zoff / / Z combine Convert to the target load impedance Z of the main amplifier at the back-off power goal, BO , which can enable the main amplifier to still work efficiently at the back-off power.

[0053] As Figure 4 shown, at high power, the auxiliary amplifier is turned on, and the current flowing through the auxiliary path is I T2 , and the current flowing through the main path is I T1 . According to Kirchhoff's voltage law and Kirchhoff's current law, the combined equivalent impedance of the main path at this time can be obtained as (1 + I T2 / I T1 )*Z combine , and the combined equivalent impedance of the auxiliary path is (1 + I T1 / I T2 )*Z combine . Therefore, the current I T2 can dynamically modulate the combined equivalent impedance of the main path and the combined equivalent impedance of the auxiliary path. At the saturation power, the main output network 410 can convert the combined equivalent impedance of the main path (1 + I T2 / I T1 )*Z combine to the target load impedance of the main amplifier at the saturation power ( Figure 4 Z in goal, M ). The auxiliary output network 420 (including the first sub-network 421 and the second sub-network 422) can convert the combined equivalent impedance of the auxiliary path (1 + I T1 / I T2 )*Z combine to the target load impedance of the auxiliary amplifier at the saturation power ( Figure 4 Z in goal, A ). By respectively converting the combined equivalent impedance of the main path and the combined equivalent impedance of the auxiliary path into the corresponding target load impedances of the main amplifier and the auxiliary amplifier at the saturation power, the main amplifier and the auxiliary amplifier can both work efficiently at the saturation power.

[0054] The "combined equivalent impedance" mentioned here refers to the equivalent impedance seen looking towards the combining node (i.e., the combining node 430) on a certain path. Exemplarily, as Figure 4 shown, the combined equivalent impedance of the main path is the ratio of the voltage U T1 at the output end of the main path to the current I T1 in the main path, and the combined equivalent impedance of the auxiliary path is the ratio of the voltage U T2 at the output end of the auxiliary path to the current I T2 in the auxiliary path.

[0055] In the present application, the main amplifier and the auxiliary amplifier may include and are not limited to, for example, power transistors based on VDMOS, LDMOS or GaN, and different transistor technologies provide different performance advantages in terms of output power, gain and performance. For example, the type of transistor can be selected according to requirements such as frequency, bandwidth, cost, etc. According to some embodiments of the present application, the main amplifier and the auxiliary amplifier may be the same type of power transistors (such as GaN-based power transistors), and the parameters and sizes of the transistors used as the main amplifier and the transistors used as the auxiliary amplifier may be exactly the same. In other embodiments, the transistors used as the main amplifier and the transistors used as the auxiliary amplifier differ in at least one of the aspects of transistor type, parameters and size. According to another embodiment of the present application, the main amplifier or the auxiliary amplifier may include a plurality of transistors. The specific implementation of the main amplifier and the auxiliary amplifier is not specifically limited herein.

[0056] By using a Doherty amplifier Figure 2 The output network 200 shown can combine the node impedance Z at the node 230 at different power levels. combine The target load impedance of the main amplifier and the auxiliary amplifier of the Doherty amplifier is matched, so that the main amplifier can still work efficiently at the back-off power, and the main amplifier and the auxiliary amplifier can work efficiently at the saturation power, that is, the Doherty amplifier can work efficiently at different power levels. On the other hand, the first sub-network 221 and the main output network 210 have the same circuit topology and both include at least an inductor and a capacitor, and the second sub-network 222 includes at least an inductor, which helps to simplify the structure of the output network of the Doherty amplifier and the corresponding design process. In addition, as will be further described below, by reasonably setting the circuit topology and component parameters of each sub-network in the main output network 210 and the auxiliary output network 220, the Doherty amplifier can have a larger working bandwidth and a deeper back-off power (i.e., a larger back-off power range) while working efficiently.

[0057] In some embodiments, the main output network can be equivalent to the first transmission line TL1 in the working frequency band, the auxiliary output network can be equivalent to the second transmission line TL2 in the working frequency band, and the electrical angle θ of the first transmission line TL1 M and the electrical angle θ of the second transmission line TL2 A Satisfies: 70°<θ M <90°, and 135°<θ A <180°. The above range can be achieved by appropriately selecting the circuit topology and component parameters of the main output network and the auxiliary output network. Figure 2Taking the output network 200 shown as an example, specifically, by selecting the circuit topologies and component parameters of the main output network 210, the first sub-network 221, and the second sub-network 222, the transmission lines (the first transmission line TL1 and the second transmission line TL2) equivalent to the main output network 210 and the auxiliary output network 220 in the operating frequency band have corresponding characteristic impedances and electrical lengths, and the electrical angle θ of the first transmission line TL1 M and the electrical angle θ of the second transmission line TL2 A meet the above range. The above range helps the Doherty amplifier to have a large operating bandwidth and a deeper back-off power while operating at high efficiency.

[0058] In some embodiments, the output network may be configured such that the output current I of the main amplifier M and the output current I of the auxiliary amplifier A meet: The amplitude of I M is not greater than the amplitude of I A , and the phase difference between I M and I A is less than 90°, that is, the result of subtracting the phase of I A from the phase of I M is less than 90°. Similar to the above description, by appropriately selecting the circuit topologies and component parameters of the main output network and the auxiliary output network, the above constraints on I M and I A can be achieved, which also helps the Doherty amplifier to have a large operating bandwidth and a deeper back-off power while operating at high efficiency.

[0059] Figure 5 Schematically shows an exemplary circuit topology diagram of the first sub-network and the main output network according to some embodiments of the present application.

[0060] As Figure 5 shown, in some embodiments, the first sub-network and the main output network may have a circuit topology 510, that is, they both include a first capacitor C1, a second capacitor C2, and a first inductor L1. One end of the first capacitor C1 and one end of the first inductor L1 are both connected to the output end of the main amplifier or the auxiliary amplifier (that is, one end of the first capacitor C1 and one end of the first inductor L1 in the main output network are both connected to the output end of the main amplifier, while one end of the first capacitor C1 and one end of the first inductor L1 in the first sub-network are both connected to the output end of the auxiliary amplifier). The other end of the first capacitor C1 is grounded, and the other end of the first inductor L1 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded.

[0061] In some embodiments, the first sub-network and the main output network may have a circuit topology 520, that is, compared with the circuit topology 510, they both further include a third capacitor C3. One end of the third capacitor C3 is connected to the output end of the main amplifier or the auxiliary amplifier (that is, one end of the third capacitor C3 in the main output network is connected to the output end of the main amplifier, and one end of the third capacitor C3 in the first sub-network is connected to the output end of the auxiliary amplifier), and the other end of the third capacitor C3 is grounded.

[0062] In some embodiments, the first sub-network and the main output network may have a circuit topology 530, that is, compared with the circuit topology 510, they both further include a second inductor L2. One end of the second inductor L2 is connected to the output end of the main amplifier or the auxiliary amplifier (that is, one end of the second inductor L2 in the main output network is connected to the output end of the main amplifier, and one end of the second inductor L2 in the first sub-network is connected to the output end of the auxiliary amplifier), and the other end of the second inductor L2 is grounded.

[0063] Figure 6 An exemplary circuit topology diagram of a second sub-network according to some embodiments of the present application is schematically shown. As Figure 6 shown, in some embodiments, the second sub-network may have a circuit topology 610, that is, the second sub-network includes a third inductor L3. One end of the third inductor L3 is connected to the output end of the first sub-network, and the other end of the third inductor L3 is connected to the combined node. In other embodiments, the second sub-network may have a circuit topology 620, that is, compared with the circuit topology 610, the second sub-network further includes a fourth capacitor C4. As shown in the circuit topology 620, one end of the third inductor L3 is connected to the output end of the first sub-network, and the other end of the third inductor L3 is connected to one end of the fourth capacitor C4 (the other end of the third inductor L3 is also connected to the combined node), and the other end of the fourth capacitor C4 is grounded.

[0064] It should be noted that although Figure 6 the circuit topology 620 of the second sub-network shown in includes an LC circuit composed of a third inductor L3 and a fourth capacitor C4, those skilled in the art should understand that the second sub-network may further include other circuit devices, such as a capacitor for isolating direct current. Similarly, although not shown in the Figure 5 respective circuit topologies of, those skilled in the art should understand that Figure 5 at least one of the circuit topologies 510, 520, and 530 shown in may include other circuit devices, such as a capacitor for isolating direct current.

[0065] Figure 7Schematically shows an exemplary circuit topology diagram of a combining matching network according to some embodiments of the present application.

[0066] As Figure 7 shown, in some embodiments, the combining matching network may have a circuit topology 710, that is, the combining matching network includes a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a fifth capacitor C5, and a sixth capacitor C6. One end of the fourth inductor L4 is connected to the combined node, and the other end of the fourth inductor L4 is connected to both one end of the fifth capacitor C5 and one end of the fifth inductor L5. The other end of the fifth capacitor C5 is grounded, and the other end of the fifth inductor L5 is connected to both one end of the sixth capacitor C6 and one end of the sixth inductor L6. The other end of the sixth capacitor C6 is grounded, and the other end of the sixth inductor L6 is connected to a DC voltage terminal, and the DC voltage terminal is configured to provide a DC bias voltage V to the main amplifier and the auxiliary amplifier via the sixth inductor L6, the fifth inductor L5, the fourth inductor L4, the main output network, and the auxiliary output network DD .

[0067] In some embodiments, the combining matching network may have a circuit topology 720, that is, the combining matching network includes a third transmission line TL3, a fourth transmission line TL4, a fifth transmission line TL5, a sixth transmission line TL6, and a seventh capacitor C7. One end of the third transmission line TL3 is connected to the combined node, and the other end of the third transmission line TL3 is connected to both one end of the fourth transmission line TL4 and one end of the fifth transmission line TL5. The other end of the fourth transmission line TL4 is connected to the DC voltage terminal and one end of the seventh capacitor C7. The other end of the seventh capacitor C7 is grounded, the other end of the fifth transmission line TL5 is connected to one end of the sixth transmission line TL6, and the other end of the sixth transmission line TL6 is floating. The DC voltage terminal is configured to provide a DC bias voltage V to the main amplifier and the auxiliary amplifier via the fourth transmission line TL4, the third transmission line TL3, the main output network, and the auxiliary output network DD .

[0068] In some embodiments, the combining matching network may have a circuit topology 730, that is, the combining matching network includes a seventh inductor L7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C 10, the seventh transmission line TL7 and the eighth transmission line TL8. One end of the seventh inductor L7 is connected to the combined node. The other end of the seventh inductor L7 is connected to one end of the eighth capacitor C8 and one end of the seventh transmission line TL7. The other end of the eighth capacitor C8 is grounded. The other end of the seventh transmission line TL7 is connected to one end of the ninth capacitor C9 and one end of the eighth transmission line TL8. The other end of the ninth capacitor C9 is grounded. The other end of the eighth transmission line TL8 is connected to the DC voltage terminal. One end of the tenth capacitor C 10 is connected to the DC voltage terminal. The other end of the tenth capacitor C 10 is grounded. The DC voltage terminal is configured to provide a DC bias voltage V DD to the main amplifier and the auxiliary amplifier via the eighth transmission line TL8, the seventh transmission line TL7, the seventh inductor L7, the main output network, and the auxiliary output network.

[0069] It should be noted that, although not shown in each circuit topology of Figure 7 , those skilled in the art should understand that Figure 7 at least one of the circuit topologies 710, 720, and 730 shown may include other circuit devices, such as capacitors for DC isolation. With such capacitors for DC isolation, the DC signal from the DC voltage terminal will not be transmitted to the RF output terminal of the Doherty amplifier, thereby protecting sensitive RF components (loads) from the influence of direct current.

[0070] In addition, in the embodiments described above with respect to Figure 5 and Figure 6 , although the relevant bias circuits for providing the DC bias voltage V DD to the main amplifier and the auxiliary amplifier are not disclosed, this is merely illustrative. Those skilled in the art should understand that relevant bias circuits can be set in these embodiments according to actual applications. The number of relevant bias circuits and their positions in the Doherty amplifier circuit can be flexibly adjusted. Exemplarily, when the configuration parameters of the main amplifier and the auxiliary amplifier of the Doherty amplifier are different (for example, when they are not the same type of transistor), corresponding DC bias circuits can be set for the main amplifier and the auxiliary amplifier respectively. Exemplarily, corresponding DC bias circuits can be set in the main output network to provide DC bias for the main amplifier, and corresponding DC bias circuits can be set in the first sub-network or the second sub-network to provide DC bias for the auxiliary amplifier. Alternatively, corresponding DC bias circuits can be set in the combining matching network to provide DC bias for the main amplifier and the auxiliary amplifier (for example, see the circuit topologies 710, 720, and 730 described above).

[0071] In some embodiments, at least one of the first to tenth capacitors may be implemented in at least one of the following forms: PCB surface-mounted components, integrated circuit devices.

[0072] In some embodiments, at least one of the first to seventh inductors may be implemented in at least one of the following forms: PCB surface-mounted components, integrated circuit devices, bonding wires, microstrip lines, metal windings, transmission lines.

[0073] In some embodiments, at least one of the third to eighth transmission lines may be implemented in at least one of the following forms: microstrip lines, striplines, coplanar waveguides, substrate integrated waveguides.

[0074] The microstrip line is a planar transmission line most commonly used in current hybrid microwave integrated circuits and monolithic microwave integrated circuits. It is a strip-shaped conductor (signal line) separated from the ground layer by a dielectric. The microstrip line can be implemented in various forms such as PCB microstrip lines and integrated circuit microstrip lines. The factors affecting the characteristic impedance of the microstrip line include the thickness, width, distance from the ground layer, and dielectric constant of the dielectric. The length of the microstrip line can correspond to the electrical angle of the microstrip line. Exemplarily, at least one of the third to eighth transmission lines can be implemented using a microstrip line. Correspondingly, the length, width, and other dimensional parameters of the microstrip line can be configured based on the characteristic impedance and electrical angle of the corresponding transmission line among the third to eighth transmission lines. By using a microstrip line to implement the corresponding transmission line among the third to eighth transmission lines, a transmission line that meets the characteristic parameter requirements can be obtained, thereby enabling the Doherty amplifier to have a smaller circuit size, higher operating efficiency, larger operating bandwidth, and deeper back-off power (i.e., a larger back-off power range). In particular, the microstrip line can be implemented by selecting a substrate with a high dielectric constant to further reduce the size of the relevant circuit.

[0075] The stripline is a high-frequency transmission wire placed between dielectrics between two parallel ground planes (or power planes). The stripline has the advantages of small volume, light weight, wide bandwidth, high quality factor, simple process, and low cost, and is suitable for making high-performance (wide bandwidth, high quality factor, high isolation) passive components. The coplanar waveguide (CPW) is formed by fabricating a center conductor strip on one surface of a dielectric substrate and fabricating conductor planes on both sides adjacent to the center conductor strip. In the millimeter-wave band, the coplanar waveguide has lower losses than microstrip lines and stripline circuits. The substrate integrated waveguide (SIW) uses metal vias to realize the field propagation mode of the waveguide on the dielectric substrate and has the advantages of low differential loss, low radiation, and high quality factor. In some embodiments, at least one of the third to eighth transmission lines may be composed of only one of a stripline, a coplanar waveguide, or a substrate integrated waveguide.

[0076] Another embodiment of the present application provides a Doherty amplifier, comprising: a main amplifier; a sub-amplifier; and an output network according to any one of the foregoing embodiments, wherein the output network is configured to receive a first amplified signal output by the main amplifier and a second amplified signal output by the sub-amplifier, such that the first amplified signal and the second amplified signal are combined at the combining node and provided to the RF output terminal of the Doherty amplifier. Since the Doherty amplifier includes an output network according to the foregoing embodiments of the present application, the Doherty amplifier has the advantages brought by the corresponding output network. The following will be further described in conjunction with Figure 8 to further describe such a Doherty amplifier.

[0077] As Figure 8 shown, the RF input signal is respectively connected to the main amplifier and the sub-amplifier after passing through a power divider (these amplifiers can be single-stage transistors or cascaded multi-stage transistors), and the input sides of the main amplifier and the sub-amplifier further include input matching networks (i.e., Figure 8 the input matching network 1 and the input matching network 2 shown) and phase shifter networks (i.e., Figure 8 the phase shifter 1 and the phase shifter 2 shown), wherein the phase shifter network can be provided only on the auxiliary path or only on the main path (for example, only provided on the auxiliary path). The output sides of the main amplifier and the sub-amplifier are an output network according to any one of the foregoing embodiments of the present application, and the output network includes a main output network 810 and a sub-output network 820. The sub-output network 820 includes a first sub-network 821 and a second sub-network 822 connected in series. The combining matching network 840 is configured such that the node impedance at the combining node 830 is a complex impedance, and the main output network 810 and the sub-output network 820 are configured such that the node impedance is matched to the target load impedance of the main amplifier and the sub-amplifier. Exemplarily, the (drain) DC bias voltage can be fed through the DC bias circuits in the main output network 810 and the first sub-network 821 (or the combining matching network 840).

[0078] The main output network 810 and the first sub-network 821 can have any one of the circuit topologies described above with respect to Figure 5 description, the second sub-network 822 can have the circuit topology described above with respect to Figure 6 description, and the combining matching network 840 can have any one of the circuit topologies described above with respect to Figure 7 description. By selecting the circuit topologies and component parameters of the main output network 810, the first sub-network 821, and the second sub-network 822, the transmission lines equivalent to the main output network 810 and the sub-output network 820 in the operating frequency band can have corresponding characteristic impedances, electrical lengths, and electrical angles, so that the Doherty amplifier has a large operating bandwidth and a deep back-off power while operating at high efficiency.

[0079] It should be noted that although Figure 8 the Doherty amplifier shown in

[0080] Figure 9 merely includes one auxiliary amplifier, those skilled in the art should understand that the Doherty amplifier disclosed in the present application may include more auxiliary amplifiers (for example, two auxiliary amplifiers). Based on the foregoing embodiments of the present application, the multiple auxiliary output networks on the multiple auxiliary paths corresponding to these auxiliary amplifiers may all adopt the circuit structures disclosed in the foregoing embodiments of the present application. Figure 9 FIG. schematically shows a schematic diagram of a package structure included in a Doherty amplifier according to some embodiments of the present application. As Figure 5 shown, the Doherty amplifier includes a package carrier 900 (which may adopt an LGA structure or a QFN structure). The package carrier 900 includes: a metal pad 901 (the main purpose is to carry circuit components and provide a heat dissipation and grounding loop); a main amplifier circuit chip 902, whose output terminal is connected to a pad 907 through a group of bonding wires 906 (the parasitic equivalent inductance can be controlled by adjusting the number, spacing, height, and length of the bonding wires); an auxiliary amplifier circuit chip 903, similar to the main amplifier circuit chip 902, whose output terminal is also connected to a pad through a group of bonding wires 908; an output matching unit chip 904. Among them, the circuit topologies of the main output network and the first sub-network are similar to the circuit topology 510 described above (but do not include the first capacitor C1), and the second sub-network adopts the circuit topology 600 described above. Among them, the bonding wire 906 is used to implement the first inductor L1 in the main output network. As can be seen from Figure 6 Figure 9 it, since there is no need for parasitic capacitors C dsM and C dsA ​(i.e., the first capacitor C1), the output ends of the main amplifier circuit chip 902 and the auxiliary amplifier circuit chip 903 can be directly connected to the bonding wires 906 and 908. The bonding wires 908 and 910 are respectively used to implement the first inductor L1 in the first sub-network and the third inductor L3 in the second sub-network (L1 can be equal to L3). The capacitor 909 is used to implement the second capacitor C2 in the first sub-network. The capacitor 911 is used to implement the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network. That is, the capacitor 911 can be regarded as the parallel capacitance (C2 + C4) of the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network. The output matching unit chip 904 is connected to the package output pin through the bonding wire 912. In addition, the input ends of the main amplifier circuit chip 902 and the auxiliary amplifier circuit chip 903 are electrically connected to the pads 916 and 917 on the input circuit chip 915 through bonding wires or other means, and are connected to the input matching circuit. The specific implementation form of the input matching circuit in this application is not limited.

[0081] Figure 10 Schematically shows a schematic diagram of a package structure included in a Doherty amplifier according to other embodiments of the present application. As Figure 10 shown, the Doherty amplifier includes a package carrier 1000 (which can adopt an LGA structure or a QFN structure). The package carrier 1000 includes: a metal pad 1001 (the main purpose is to carry circuit elements and provide a heat dissipation and grounding loop); a main amplifier circuit chip 1002, whose output end is connected to the pad 1006 through a group of bonding wires 1005. Here, the height and length of the bonding wire 1005 are controlled to be as small as possible, so that its parasitic inductance characteristics can be ignored; an auxiliary amplifier circuit chip 1003, similar to the main amplifier circuit chip 1002, whose output end is also connected to the pad through a group of bonding wires; an output matching unit chip 1004, where the main output network and the first sub-network adopt the circuit topology 520 described above regarding Figure 5 description, and the second sub-network adopts the circuit topology 600 described above regarding Figure 6 description. Among them, the first capacitor C1 in the main output network and the first sub-network can be the parasitic capacitances C dsM and C dsA, the capacitor 1007 is used to implement the third capacitor C3 in the main output network. The bonding wire 1008 (whose parasitic equivalent inductance can be controlled by adjusting the number, spacing, height, and length of the bonding wires) is used to implement the first inductor L1 in the main output network. The capacitors 1011 and 1012 are respectively used to implement the third capacitor C3 and the second capacitor C2 in the first sub-network. The bonding wires 1009 and 1010 are respectively used to implement the first inductor L1 in the first sub-network and the third inductor L3 in the second sub-network. The capacitor 1013 is used to implement the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network, that is, the capacitor 1013 can be regarded as the parallel capacitance (C2 + C4) of the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network. The output matching unit chip 1004 is connected to the package output pin through the bonding wire 1014; in addition, the input ends of the main amplifier circuit chip 1002 and the auxiliary amplifier circuit chip 1003 are electrically connected to the pads 1017 and 1018 on the input circuit chip 1016 through bonding wires or other means, and are connected to the input matching circuit. The specific implementation form of the input matching circuit in this application is not limited.

[0082] Figure 11 Schematically shows a schematic diagram of a package structure included in a Doherty amplifier according to some further embodiments of the present application. As Figure 11 shown, the Doherty amplifier includes a package carrier 1100 (which can adopt an LGA structure or a QFN structure). The package carrier 1100 includes: a metal pad 1101 (whose main purpose is to carry circuit elements and provide a heat dissipation and grounding loop); a main amplifier circuit chip 1102, whose output end is connected to the pad 1107 through a group of bonding wires 1106 (whose parasitic equivalent inductance can be controlled by adjusting the number, spacing, height, and length of the bonding wires); an auxiliary amplifier circuit chip 1103, similar to the main amplifier circuit chip 1102, whose output end is also connected to the pad through a group of bonding wires 1108; an output matching unit chip 1104. The circuit topologies of the main output network and the first sub-network are similar to the circuit topology 530 described above Figure 5 (but not including the first capacitor C1), and the second sub-network adopts the circuit topology 600 described above Figure 6 . Among them, the bonding wire 1106 is used to implement the first inductor L1 in the main output network. From Figure 11 it can be seen that since the parasitic capacitances C dsM and C dsA(i.e., the first capacitor C1), the output terminals of the main amplifier circuit chip 1102 and the auxiliary amplifier circuit chip 1103 can be directly connected to the bonding wires 1106 and 1108. The bonding wires 1108 and 1110 are respectively used to implement the first inductor L1 in the first sub-network and the third inductor L3 in the second sub-network (L1 can be equal to L3). The capacitor 1109 is used to implement the second capacitor C2 in the first sub-network. The capacitor 1111 is used to implement the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network. That is, the capacitor 1111 can be regarded as the parallel capacitance (C2 + C4) of the second capacitor C2 in the main output network and the fourth capacitor C4 in the second sub-network. The output matching unit chip 1104 is connected to the package output pin through the bonding wire 1112. In addition, the input terminals of the main amplifier circuit chip 1102 and the auxiliary amplifier circuit chip 1103 are electrically connected to the pads 1116 and 1117 on the input circuit chip 1115 through bonding wires or other means, and are connected to the input matching circuit. The specific implementation form of the input matching circuit in this application is not limited.

[0083] In addition, as Figure 11 shown, the output terminal of the main amplifier circuit chip 1102 is also connected to the package pin 1119 through the bonding wire 1118, and the output terminal of the auxiliary amplifier circuit chip 1103 is connected to the package pin 1121 through the bonding wire 1120. By adjusting the number, spacing, height, length, etc. of the bonding wires 1118 and 1120, their parasitic equivalent inductance can be controlled to implement the second inductor L2 in the main output network and the second inductor L2 in the first sub-network. The package pins 1119 and 1121 can be directly or indirectly connected to the ground through an external circuit.

[0084] Figure 12 Schematically shows a schematic diagram of various implementation methods of inductors according to some embodiments of the present application. As Figure 12 shown, in the output matching unit chips 1200 and 1210 (which can be used to implement any of the output matching unit chips described above regarding Figures 9 - 11 ), in addition to being implemented by the parasitic inductance of the bonding wire, the inductor can also be implemented in the form of a metal wire or a transmission line. Figure 12 The left side shows an example where the first inductor L1 in the main output network is implemented by the metal winding 1204 (the first inductor L1 in the first sub-network and the third inductor L3 in the second sub-network are still implemented by the bonding wires 1205 and 1207). By adjusting the length, line width, and winding form (such as spacing and length) of the metal winding, its equivalent inductance can be adjusted. Figure 12On the right side, an example is shown where all inductors (the first inductor L1 in the main output network, the first inductor L1 in the first sub-network, and the third inductor L3 in the second sub-network) are implemented by metal windings (1214, 1215, and 1217).

[0085] Figure 13 Schematically shows a structural diagram of a Doherty amplifier according to some embodiments of the present application. As Figure 13 shown, the Doherty amplifier includes a circuit carrier 1300, and the circuit carrier 1300 includes: a package structure 1301 (which can be Figures 9 - 11 any of the package structures shown), which is mainly composed of an input circuit 1303a, transistor amplifiers 1303, 1304, and an output circuit 1302. The output circuit 1302 is connected to a pin 1306 through a bonding wire 1305 and connected to a peripheral PCB circuit to implement the circuit topology 730 described above regarding Figure 7 where 1305 is the seventh inductor L7, 1308 is the eighth capacitor C8, 1307 is the seventh transmission line TL7, 1309 is the ninth capacitor C9, the other end of the ninth capacitor C9 is connected to a pad and connected to ground through a via 1310, 1311 is the eighth transmission line TL8, 1312 is the tenth capacitor C 10 , 1313 is a filter capacitor, 1316 is a blocking capacitor, 1315 is an external DC voltage port, which can provide a drain voltage for the transistor through 1311 (the eighth transmission line TL8) and 1307 (the seventh transmission line TL7), and 1317 is an SMA connector (which provides a radio frequency output port of the Doherty amplifier). The input end 1320 is connected to a corresponding connector through a transmission line 1319 (which provides a radio frequency input port of the Doherty amplifier). Additionally, multiple DC ports marked by 1318 can provide the required DC bias voltages (such as gate voltage and DC voltage of the drive circuit) for the package structure 1301.

[0086] Another embodiment of the present application provides a method for designing a Doherty amplifier, and the Doherty amplifier includes a main amplifier, a auxiliary amplifier, and an output network 200 described above regarding Figure 2 description. Figure 14 Schematically shows a flowchart 1400 of a method for designing a Doherty amplifier according to some embodiments of the present application. As Figure 14 shown, the method includes the following steps:

[0087] In step 1410, set the target performance metrics of the Doherty amplifier, where the target performance metrics at least include the operating frequency, saturation power, and dynamic range of the Doherty amplifier; in step 1420, according to the target performance metrics, select transistors for the main amplifier and the auxiliary amplifier. The selection of transistors can consider various design requirements, such as power, cost, size, etc., and can refer to the descriptions of different types of transistors above. This application does not limit this; in step 1430, based on load-pull testing or simulation analysis, determine the first, second, and third target impedances, where the first target impedance is the load impedance that maximizes the efficiency of the main amplifier when the Doherty amplifier is in the back-off power state, the second target impedance is the load impedance that maximizes the efficiency of the main amplifier when the output power of the main amplifier reaches the saturation power, and the third target impedance is the load impedance that maximizes the efficiency of the auxiliary amplifier when the output power of the auxiliary amplifier reaches the saturation power; in step 1440, based on the first, second, and third target impedances, determine the circuit topologies and component parameters of each sub-network in the auxiliary output network and the main output network, and determine the circuit topology and component parameters of the combining and matching network.

[0088] Using the method for designing a Doherty amplifier proposed in the embodiments of this application, a Doherty amplifier with a more compact structure, a simplified circuit structure, and a simplified design process can be obtained. In addition, this Doherty amplifier can also achieve efficient operation in the range from low power to high power, and has a deeper back-off power and a wider operating bandwidth.

[0089] The following gives a parameter design example of the output circuit 1302 obtained using the above design method (in the output network corresponding to the output circuit 1302, the main output network and the first sub-network of the auxiliary output network adopt the circuit topology 510 described above regarding Figure 13 The second sub-network of the auxiliary output network adopts the circuit topology 600 described above regarding Figure 5 ): Figure 6 :

[0090] The Doherty amplifier corresponding to the output network can be applied to a 5G mobile communication system (3.5 GHz band, 32T transmitter array, base station amplifier). The main amplifier is a transistor based on gallium nitride (GaN) semiconductor technology with a total gate width of 4.8 mm, its saturation power is 50 W, and the parasitic capacitance C dsM is 2 pF (here C dsM is the first capacitor in the main output network); the auxiliary amplifier is a transistor based on gallium nitride (GaN) semiconductor technology with a total gate width of 8.4 mm, its saturation power is 85 W, and the parasitic capacitance C dsA is 3 pF (here C dsAFor the first capacitor in the first sub-network); The other component parameters of each sub-network in the output network 1100 are as follows:

[0091] L1 = 0.926 nH (where L1 is the first inductor in the main output network);

[0092] C M = 2.03 pF (where C M is the second capacitor in the main output network);

[0093] L A = 0.358 nH (where L A is the first inductor in the first sub-network and the third inductor in the second sub-network);

[0094] C1 = 5.74 pF (where C1 is the second capacitor in the first sub-network);

[0095] C2 = 2.87 pF (where C2 is the fourth capacitor in the second sub-network);

[0096] Z combine = 2.31 - j2.49.

[0097] Among them, the radio frequency characteristics of the main output network in the 3.5 GHz frequency band can be equivalent to a transmission line with an electrical length of 86°, and the radio frequency characteristics of the auxiliary output network in the 3.5 GHz frequency band can be equivalent to a transmission line with an electrical length of 161°.

[0098] Figure 15 and Figure 16 Schematically shows a performance example diagram of a Doherty amplifier according to some embodiments of the present application. As Figure 15 shown, for the Doherty amplifier according to some embodiments of the present application and the traditional Doherty amplifier, the amplifier DC - RF conversion efficiency varying with the output power is respectively shown as curves 1510 and 1520. It can be seen that in the low output power state, the efficiency of the Doherty amplifier according to some embodiments of the present application is much higher than the traditional scheme. As Figure 16 shown, for the Doherty amplifier according to some embodiments of the present application and the traditional Doherty amplifier, the small signal gains of the amplifiers are respectively shown as curves 1610 and 1620. It can be seen that the bandwidth of the Doherty amplifier according to some embodiments of the present application is much larger than that of the traditional Doherty amplifier (more than twice the bandwidth of the traditional Doherty amplifier).

[0099] It will be understood that although the terms first, second, third, etc. may be used herein to describe various devices, elements, components or parts, these devices, elements, components or parts should not be limited by these terms. These terms are only used to distinguish one device, element, component or part from another. "Connection" as referred to herein includes "direct connection" or "indirect connection".

[0100] Although the present application has been described in connection with some embodiments, it is not intended to be limited to the specific forms set forth herein. On the contrary, the scope of the present application is only limited by the appended claims. Additionally, although individual features may be included in different claims, these may possibly be advantageously combined, and including in different claims does not imply that a combination of features is not feasible and / or advantageous. The order of features in the claims does not imply that the features must work in any specific order. Further, in the claims, the word "comprising" does not exclude other elements, and the term "a" or "an" does not exclude a plurality. The reference numerals in the claims are provided only as illustrative examples and should not be construed as limiting the scope of the claims in any way.

Claims

1. An output network for a Doherty amplifier, the Doherty amplifier including a main amplifier and a auxiliary amplifier, the output network comprising: A combined node, a main output network connected between the output end of the main amplifier and the combined node, a secondary output network connected between the output end of the secondary amplifier and the combined node, and a combining matching network connected between the combined node and the radio frequency output end of the Doherty amplifier wherein the secondary output network includes a first sub-network and a second sub-network connected in series, the first sub-network and the main output network have the same circuit topology and both include at least an inductor and a capacitor, and the second sub-network includes at least an inductor wherein the combining matching network is configured such that the node impedance at the combined node is a complex impedance, and the main output network and the secondary output network are configured such that the node impedance is matched to the target load impedance of the main amplifier and the secondary amplifier Wherein the main output network is equivalent to a first transmission line in the operating frequency band, the auxiliary output network is equivalent to a second transmission line in the operating frequency band, and the electrical angle θ of the first transmission line M and the electrical angle θ of the second transmission line A satisfy: 70° < θ M < 90°, and 135° < θ A < 180°.

2. The output network according to claim 1, wherein the output network is configured such that the output current I of the main amplifier M and the output current I of the auxiliary amplifier A satisfy: The magnitude of I M is not greater than the magnitude of I A , and the phase difference between I M and I A is less than 90°.

3. The output network according to claim 1, wherein both the first sub-network and the main output network include a first capacitor, a second capacitor and a first inductor. One end of the first capacitor and one end of the first inductor are both connected to the output end of the main amplifier or the secondary amplifier. The other end of the first capacitor is grounded. The other end of the first inductor is connected to one end of the second capacitor. The other end of the second capacitor is grounded 4. The output network according to claim 3, wherein at least one of the first capacitor and the second capacitor is implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device 5. The output network according to claim 3, wherein the first inductor is implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device, a bonding wire, a microstrip line, a metal winding, a transmission line 6. The output network according to claim 6, wherein both the first sub-network and the main output network further include a third capacitor. One end of the third capacitor is connected to the output end of the main amplifier or the secondary amplifier. The other end of the third capacitor is grounded 7. The output network according to claim 6, wherein at least one of the first capacitor, the second capacitor and the third capacitor is implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device 8. The output network according to claim 3, wherein both the first sub-network and the main output network further include a second inductor. One end of the second inductor is connected to the output end of the main amplifier or the secondary amplifier. The other end of the second inductor is grounded 9. The output network according to claim 8, wherein at least one of the first capacitor and the second capacitor is implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device 10. The output network according to claim 8, wherein at least one of the first inductor and the second inductor is implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device, a bonding wire, a microstrip line, a metal winding, a transmission line 11. The output network according to claim 1, wherein the second sub-network includes a third inductor and a fourth capacitor. One end of the third inductor is connected to the output end of the first sub-network, the other end of the third inductor is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded.

12. The output network according to claim 11, wherein the fourth capacitor is implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device.

13. The output network according to claim 11, wherein the third inductor is implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device, a bonding wire, a microstrip line, a metal winding, a transmission line.

14. The output network according to claim 1, wherein the combining matching network includes a fourth inductor, a fifth inductor, a sixth inductor, a fifth capacitor, and a sixth capacitor. One end of the fourth inductor is connected to the combined node, the other end of the fourth inductor is connected to one end of the fifth capacitor and one end of the fifth inductor. The other end of the fifth capacitor is grounded, the other end of the fifth inductor is connected to one end of the sixth capacitor and one end of the sixth inductor. The other end of the sixth capacitor is grounded, and the other end of the sixth inductor is connected to a DC voltage terminal. The DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the sixth inductor, the fifth inductor, the fourth inductor, the main output network, and the auxiliary output network.

15. The output network according to claim 14, wherein at least one of the fifth capacitor and the sixth capacitor is implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device.

16. The output network according to claim 14, wherein at least one of the fourth inductor, the fifth inductor, and the sixth inductor is implemented in at least one of the following forms: a PCB surface mount component, an integrated circuit device, a bonding wire, a microstrip line, a metal winding, a transmission line.

17. The output network according to claim 1, wherein the combining matching network includes a third transmission line, a fourth transmission line, a fifth transmission line, a sixth transmission line, and a seventh capacitor. One end of the third transmission line is connected to the combined node, the other end of the third transmission line is connected to one end of the fourth transmission line and one end of the fifth transmission line. The other end of the fourth transmission line is connected to the DC voltage terminal and one end of the seventh capacitor. The other end of the seventh capacitor is grounded, the other end of the fifth transmission line is connected to one end of the sixth transmission line, and the other end of the sixth transmission line is floating. The DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the fourth transmission line, the third transmission line, the main output network, and the auxiliary output network.

18. The output network according to claim 17, wherein the seventh capacitor is implemented in at least one of the following forms: a PCB surface-mounted component, an integrated circuit device.

19. The output network according to claim 17, wherein at least one of the third transmission line, the fourth transmission line, the fifth transmission line, and the sixth transmission line is implemented in at least one of the following forms: a microstrip line, a stripline, a coplanar waveguide, a substrate integrated waveguide.

20. The output network according to claim 1, wherein the combining and matching network includes a seventh inductor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a seventh transmission line, and an eighth transmission line. One end of the seventh inductor is connected to the combined node, and the other end of the seventh inductor is connected to one end of the eighth capacitor and one end of the seventh transmission line. The other end of the eighth capacitor is grounded. The other end of the seventh transmission line is connected to one end of the ninth capacitor and one end of the eighth transmission line. The other end of the ninth capacitor is grounded. The other end of the eighth transmission line is connected to a DC voltage terminal. One end of the tenth capacitor is connected to the DC voltage terminal, and the other end of the tenth capacitor is grounded. The DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the eighth transmission line, the seventh transmission line, the seventh inductor, the main output network, and the auxiliary output network.

21. The output network according to claim 20, wherein at least one of the eighth capacitor, the ninth capacitor, and the tenth capacitor is implemented in at least one of the following forms: a PCB surface-mounted component, an integrated circuit device.

22. The output network according to claim 20, wherein the seventh inductor is implemented in at least one of the following forms: a PCB surface-mounted component, an integrated circuit device, a bonding wire, a microstrip line, a metal wire winding, a transmission line.

23. The output network according to claim 20, wherein at least one of the seventh transmission line and the eighth transmission line is implemented in at least one of the following forms: a microstrip line, a stripline, a coplanar waveguide, a substrate integrated waveguide.

24. A Doherty amplifier, comprising: a main amplifier; an auxiliary amplifier; and the output network according to any one of claims 1-23, wherein the output network is configured to receive a first amplified signal output by the main amplifier and a second amplified signal output by the auxiliary amplifier, such that the first amplified signal and the second amplified signal are combined at the combined node and provided to the RF output terminal of the Doherty amplifier.

25. A method for designing a Doherty amplifier, the Doherty amplifier comprising a main amplifier, an auxiliary amplifier, and an output network as claimed in claim 1, wherein the method comprises: setting target performance indicators of the Doherty amplifier, the target performance indicators at least including the operating frequency, saturation power, and dynamic range of the Doherty amplifier; Select transistors for the main amplifier and the auxiliary amplifier according to the target performance indicators; Based on load-pull testing or simulation analysis, determine the first, second, and third target impedances, where the first target impedance is the load impedance that maximizes the efficiency of the main amplifier when the Doherty amplifier is in the back-off power state, the second target impedance is the load impedance that maximizes the efficiency of the main amplifier when the output power of the main amplifier reaches the saturation power, and the third target impedance is the load impedance that maximizes the efficiency of the auxiliary amplifier when the output power of the auxiliary amplifier reaches the saturation power; Based on the first, second, and third target impedances, determine the circuit topologies and component parameters of each sub-network in the auxiliary output network and the main output network, and determine the circuit topology and component parameters of the combining and matching network.

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