A gallium nitride power transistor and a method for manufacturing a gallium nitride power transistor

Abstract

The present invention relates to a gallium nitride power transistor (100) comprising: a gallium nitride buffer layer (110) comprising a top surface and a bottom surface, the gallium nitride buffer layer comprising a first region (101), a second region (102) and a third region (103) at the top surface; an aluminum gallium nitride barrier layer (112) deposited at the top surface of the gallium nitride buffer layer; an emitter contact formed at the interface of the gallium nitride buffer layer at the first region of the aluminum gallium nitride buffer layer; a first p-doped gallium nitride layer (113) deposited at the aluminum gallium nitride barrier layer over the second region of the gallium nitride buffer layer, the first p-doped gallium nitride layer forming a gate contact of the gallium nitride power transistor; and a second p-doped gallium nitride layer (114) deposited over the third region of the gallium nitride buffer layer, the second p-doped gallium nitride layer forming a collector contact of the gallium nitride power transistor.

Description

Technical Field

[0001] This invention relates to the field of gallium nitride (GaN) technology for power device applications. Specifically, this invention relates to a GaN power transistor and a method for manufacturing such a GaN power transistor, particularly a GaN power field-effect transistor (FET) with conductivity modulation enhancement effect. Background Technology

[0002] Over the past 15 to 20 years, the semiconductor industry has made significant efforts to develop gallium nitride (GaN) technology to replace traditional silicon-based field-effect transistors (FETs). The use of wide-bandgap materials has provided unprecedented possibilities for performance improvements at both the device and system levels. Today, enhancement-mode GaN power FETs are becoming a reality, with several major semiconductor manufacturers already launching products on the market. The most mature GaN device concept used by the vast majority of players is the pGaN normally-off concept.

[0003] In traditional pGaN power MOSFETs, a single AlGaN barrier with a certain thickness and aluminum (Al) content is used to define the electrical characteristics of a two-dimensional electron gas (2DEG). This approach has several drawbacks: 1) The threshold voltage (VTH) and 2DEG characteristics cannot be controlled independently; 2) This method is highly sensitive to surface effects (i.e., dynamic effects); 3) This method is highly sensitive to gate module details (i.e., Schottky and Ohmke); 4) This method exhibits reduced current capability, meaning that performance must be traded off due to reliability issues; 5) Very low VTH is typically achieved, for example, between approximately 1 and 1.5V; 6) Stray conduction can be problematic; 7) This method is highly sensitive to parasitics and voltage and current overshoot. Summary of the Invention

[0004] The purpose of this invention is to provide a solution for GaN power transistors that does not have the aforementioned drawbacks.

[0005] Specifically, one object of the present invention is to provide a novel device concept for GaN-based power transistors that are novel, industrially relevant, and offer significant advantages over conventional devices.

[0006] This objective is achieved through the features of the independent claim. Other implementations are apparent from the dependent claims, the description, and the drawings.

[0007] This novel device concept for GaN-based power transistors is based on GaN field-effect power transistors exhibiting a conductivity modulation enhancement effect. The structure of the novel GaN power transistor that causes this conductivity modulation enhancement effect is described below.

[0008] The basic idea of ​​this invention is to realize a novel device concept for GaN-based power transistors. This device is the first disclosed IGBT-like power device for GaN technology. Due to minority carrier injection at the p-GaN collector, the device can operate under conduction modulation, thus significantly reducing the resistance in the on-state. The device employs a pGaN gate concept, which allows for the rapid depletion of minority carriers accumulated during the on-conductance state. Therefore, compared to conventional silicon IGBTs, this device exhibits fast turn-off. Utilizing this concept, tail current suppression can be achieved, thus enabling faster turn-off at V... CEON With E OFF A better trade-off can be achieved between these. This is the concept of lateral devices. Therefore, by increasing the length of the lateral drift region, lateral breakdown can be easily increased.

[0009] In this invention, insulated-gate bipolar transistors (IGBTs) and GaN IGBT-based transistor-like devices are described. The IGBT approach is an industry standard used exclusively for silicon technology. Now, approximately 30 years after its invention, the bipolar-MOS (BiMOS) controlled switch, known as the insulated-gate bipolar transistor (IGBT), is the preferred device for most power electronic converters, with power ratings ranging from several kilowatts to over 1 GW. IGBTs are characterized by their ability to handle both high current and high voltage simultaneously. IGBTs combine the simple gate drive characteristics of power MOSFETs with the high current and low saturation voltage capabilities of bipolar transistors. IGBTs integrate an isolated-gate FET for input control and a bipolar power transistor as a switch in a single device. The main characteristics of IGBT silicon transistors can be summarized as follows: combining high efficiency and fast switching; high input impedance due to the insulated-gate structure; conductance modulation in the on-state due to minority carrier injection at the p-type collector; V CON With E OFF The trade-offs are: due to the smaller carrier recombination time and tail current, switching is slower compared to MOSFETs. In higher blocking voltage rated devices, IGBTs are characterized by a significantly lower forward voltage drop compared to conventional MOSFETs, although the absence of a diode Vf in the IGBT's output BJT causes MOSFETs to exhibit a lower forward voltage at lower current densities.

[0010] The GaN-based power transistor proposed in this invention combines the advantages of IGBT devices and GaN technology.

[0011] To describe the invention in detail, the following terms, abbreviations, and symbols will be used:

[0012] GaN (Gallium Nitride)

[0013] FET (Field Effect Transistor)

[0014] pGaN p-doped GaN

[0015] AlGaN (AlGaN Gallium Nitride)

[0016] 2DEG two-dimensional electron gas

[0017] V TH Threshold voltage

[0018] In this invention, two methods for manufacturing metal / pGaN interfaces are described: the Ohmic interface method and the Schottky interface method.

[0019] In the ohmic interface method, the interface between the metal gate and the pGaN surface is almost ideal. This translates to a large DC current, which sustains device operation under on-state conditions, but also complicates the driving strategy and significantly increases drive losses.

[0020] In the Schottky interface method, a reverse-biased Schottky diode is inserted in series with a pn-pGaN / AlGaN diode. This allows for a significant reduction in DC gate current. In the Schottky interface method, the pGaN node is isolated from the gate terminal via the reverse-biased Schottky diode.

[0021] According to a first aspect, the present invention relates to a gallium nitride (GaN) power transistor, comprising: a gallium nitride buffer layer including a top surface and a bottom surface opposite to the top surface, the GaN buffer layer including a first region, a second region, and a third region on the top surface; an aluminum gallium nitride (AGaN) barrier layer deposited on the top surface of the GaN buffer layer; an emitter contact formed above the first region of the AGaN buffer layer at an interface with the GaN buffer layer; a first p-type doped gallium nitride layer deposited above the second region of the GaN buffer layer on the AGaN barrier layer, the first p-type doped gallium nitride layer forming a gate contact of the GaN power transistor; and a second p-type doped gallium nitride layer deposited above the third region of the GaN buffer layer, the second p-type doped gallium nitride layer forming a collector contact of the GaN power transistor.

[0022] This GaN power transistor offers a technological advantage: tail current can be almost completely eliminated due to the transistor's specific gate structure. Specifically, the pGaN gate region, i.e., the second region as described above, allows for the rapid depletion of holes injected into the drift region during the on-state conduction cycle. Furthermore, the switching speed of the device can be controlled by appropriately selecting the off-state voltage applied to the gate electrode.

[0023] A further advantage of this GaN power transistor is that, due to the injection of minority carriers from the p-GaN collector, the device allows operation under conductance modulation. Therefore, a significant reduction in on-state resistance can be achieved.

[0024] This device employs a pGaN gate concept, which allows for the rapid depletion of minority carriers accumulated during the conduction phase of the on-state, thus enabling faster off-state switching compared to conventional silicon IGBTs.

[0025] GaN power transistors can suppress tail current. Therefore, it is possible to achieve this at V. CEON With E OFF Achieving a better balance between them.

[0026] GaN power transistors follow the concept of lateral devices. Therefore, by increasing the length of the lateral drift region, lateral breakdown can be easily increased.

[0027] In an exemplary implementation of a gallium nitride power transistor, the emitter contact is formed by a two-dimensional electron gas generated at the interface between the aluminum gallium nitride barrier layer and the gallium nitride buffer layer.

[0028] This provides the advantage of improving the electrical performance of the emitter contact.

[0029] In an exemplary implementation of a gallium nitride power transistor, a collector contact is formed at the interface between the second p-type doped gallium nitride layer and the gallium nitride buffer layer.

[0030] This provides the advantage that pn diodes can be formed from a pGaN layer (collector) and a 2DEG formed at the AlGaN-GaN interface. The pn diode is used to implement the IGBT structure that provides the aforementioned advantages for the first aspect.

[0031] In an exemplary implementation of a gallium nitride power transistor, a second p-type doped gallium nitride layer is deposited at an aluminum nitride barrier layer within a recess in the aluminum gallium nitride barrier layer, the recess being partially recessed into the aluminum gallium nitride barrier layer.

[0032] This corresponds to a third possible embodiment of a gallium nitride power transistor, which will be discussed below. Figure 3Further description. Therefore, GaN power transistors can have flexible designs regarding the etching of the aluminum gallium nitride barrier layer.

[0033] In an exemplary implementation of a gallium nitride power transistor, a second p-type doped gallium nitride layer is deposited at a gallium nitride buffer layer within a recess in an aluminum gallium nitride barrier layer, the recess extending downward into the gallium nitride buffer layer.

[0034] This corresponds to a first possible embodiment of a gallium nitride power transistor, which will be discussed below. Figure 1 Further description. Therefore, gallium nitride power transistors can have flexible designs regarding the etching of the aluminum gallium nitride barrier layer.

[0035] In an exemplary implementation of a gallium nitride power transistor, a second p-type doped gallium nitride layer is deposited at a gallium nitride buffer layer within a recess in an aluminum gallium nitride barrier layer, the recess extending into and recessing into the gallium nitride buffer layer.

[0036] This corresponds to a second possible embodiment of a gallium nitride power transistor, which will be discussed below. Figure 2 Further description. Therefore, GaN power transistors can have flexible designs regarding the etching of the aluminum gallium nitride barrier layer and the gallium nitride buffer layer.

[0037] In an exemplary implementation of a gallium nitride (GaN) power transistor, the GaN power transistor includes a metal layer deposited at a first p-type doped gallium nitride layer, wherein the interface between the metal layer and the first p-type doped gallium nitride layer forms a Schottky interface or an ohmic interface.

[0038] This provides GaN power transistors with the technical advantage of flexible design regarding gate contacts.

[0039] The Ohmic interface method has the following advantages: (i) the pGaN node is neatly connected to the gate metal terminal, so the device is not prone to VTH instability; (ii) good reliability: gate breakage is caused by thermal runaway when a large DC current flows through the gate; (iii) a large number of holes injected from the gate improve the dynamic effect.

[0040] The Schottky interface method offers the following advantages: (i) the pGaN node is decoupled from the gate terminal by a reverse-biased Schottky diode; (ii) at the expense of V TH (iii) Low DC current means that dynamic effect optimization is more difficult due to the smaller number of holes in the injection buffer; (iv) Gate module breaks down via TDDB mechanism (such as oxide in Si-MOS devices); (v) Dynamic effects, gate reliability and V TH The interaction between stability factors is difficult.

[0041] In an exemplary implementation of a gallium nitride power transistor, the GaN power transistor includes a series circuit of a lateral power p-gallium nitride high electron mobility transistor with a pn diode, wherein the anode of the pn diode forms a collector contact.

[0042] Gallium nitride power transistors are specifically formed as non-insulated gate bipolar transistors (NIGBTs).

[0043] In an exemplary implementation of a gallium nitride power transistor, the pn diode is formed by the interface between a second p-type doped GaN layer and an aluminum gallium nitride barrier layer and a gallium nitride buffer layer; or the pn diode is formed by a second p-type doped gallium nitride layer and a gallium nitride buffer layer.

[0044] This provides a technological advantage, namely that IGBT-based structures can be designed efficiently in conjunction with the advantages mentioned above in the first aspect.

[0045] In an exemplary implementation of a gallium nitride power transistor, a pn diode is formed between a second p-type doped gallium nitride layer and a partially or completely recessed aluminum gallium nitride barrier layer.

[0046] This provides the technical advantage of being able to design different embodiments based on the IGBT structure. This offers flexibility to suit individual design requirements.

[0047] In an exemplary implementation of a gallium nitride power transistor, in the case of a fully recessed aluminum gallium nitride barrier layer, the second p-type doped gallium nitride layer is in direct contact with a GaN channel formed at the top surface of the gallium nitride buffer layer.

[0048] This provides the advantage that the electrical characteristics of such IGBT-based devices can be improved.

[0049] In an exemplary implementation of a GaN power transistor, the semiconductor doping of the second p-type doped gallium nitride layer differs from that of the first p-type doped GaN layer.

[0050] This provides the technical advantage that the first p-type doped gallium nitride layer and the second p-type doped gallium nitride layer can be formed in different process steps, thereby improving design flexibility.

[0051] In an exemplary implementation of a gallium nitride power transistor, the gallium nitride power transistor includes: a first metal layer deposited on a first p-type doped gallium nitride layer; and a second metal layer deposited on a second p-type doped gallium nitride layer, wherein the metal of the first metal layer is different from the metal of the second metal layer.

[0052] This provides the technical advantage that the metal of the gate contact can be different from that of the collector contact. Therefore, the gate and collector contacts can be manufactured in different process steps, which increases design flexibility.

[0053] In an exemplary implementation of a GaN power transistor, the thickness of the second p-type doped gallium nitride layer differs from the thickness of the first p-type doped GaN layer.

[0054] This provides the technical advantages of having different pGaN layers for the gate contact and the collector contact. Therefore, the gate and collector contacts can be formed in different process steps, thus increasing design flexibility.

[0055] In an exemplary implementation of a GaN power transistor, the depletion of minority carriers from the first p-type doped gallium nitride layer occurs faster with respect to a negative gate voltage applied to the gate contact of the gallium nitride power transistor during the off-state than with respect to a zero gate voltage applied to the gate contact during the off-state.

[0056] By exhausting the minority carrier wave more quickly, the switching speed of the device can be increased. This means that the speed of the device can be controlled by changing the gate voltage applied to the gate electrode during the device's off-state.

[0057] In an exemplary implementation of a gallium nitride power transistor, the aluminum gallium nitride barrier layer and the gallium nitride buffer layer include additional p-type injection in the region below the emitter contact and the gate contact.

[0058] This provides a technical advantage that can improve the electrical performance of the emitter contact.

[0059] According to a second aspect, the present invention relates to a method for manufacturing a gallium nitride (GaN) power transistor, the method comprising: forming a gallium nitride buffer layer including a top surface and a bottom surface opposite to the top surface, the GaN buffer layer including a first region, a second region, and a third region at the top surface; depositing an aluminum gallium nitride (AGaN) barrier layer on the top surface of the GaN buffer layer; depositing a first p-type doped gallium nitride layer on the AGaN barrier layer above the second region of the GaN buffer layer, the first p-type doped gallium nitride layer forming a gate contact of the GaN power transistor; depositing a second p-type doped gallium nitride layer on the third region of the GaN buffer layer, the second p-type doped gallium nitride layer forming a collector contact of the GaN power transistor; and forming an emitter contact at the interface between the AGaN barrier layer and the GaN buffer layer above the first region of the GaN buffer layer.

[0060] This approach offers the same advantages as the corresponding device in the first aspect.

[0061] Specifically, this method offers the advantage of enabling the production of novel GaN power transistors, for which tail current can be almost completely eliminated due to the specific gate structure. The pGaN gate region, i.e., the second region as described above, allows for the rapid depletion of holes injected into the drift region during the on-state conduction cycle. Furthermore, the switching speed of the device can be controlled by appropriately selecting the off-state voltage applied to the gate electrode.

[0062] In an exemplary implementation of the method, the method includes: depositing and constructing a first hard mask layer on an aluminum gallium nitride (AGaN) barrier layer to define a third region of a GaN buffer layer; trench etching the AGaN barrier layer in the third region of the GaN buffer layer; removing the first hard mask layer; depositing a p-type doped GaN layer on the AGaN barrier layer and the GaN buffer layer exposed by the trench etching of the AGaN barrier layer; depositing and constructing a second hard mask layer on the p-type doped GaN layer to define a second region and a third region of the GaN buffer layer; and etching. A p-type doped gallium nitride layer is formed outside the second and third regions of the gallium nitride buffer layer to form a first p-type doped gallium nitride layer and a second p-type doped gallium nitride layer; a second hard mask layer is removed; a first metal layer is formed over the first region of the gallium nitride buffer layer exposed by etching the p-type doped gallium nitride layer; a second metal layer is formed over the first p-type doped gallium nitride layer, and a third metal layer is formed over the second p-type doped gallium nitride layer; and a passivation layer is formed at the aluminum gallium nitride barrier layer between the first metal layer and the second p-type doped gallium nitride layer.

[0063] This approach offers the advantage of high design flexibility. These steps can also be performed in a different order than described above.

[0064] The above method corresponds to the following about Figure 7 The first method flow is described.

[0065] The first metal layer (emitter) can be formed in process steps prior to the formation of the second and third metal layers (gate and collector).

[0066] Alternatively, the first metal layer (emitter) can be formed in a method step after the formation of the second and third metal layers (gate and collector).

[0067] In an exemplary implementation of the method, the metal of the second metal layer is different from the metal of the third metal layer.

[0068] This provides the advantage that the second and third metal layers can be formed in different process steps.

[0069] For example, when two metal layers are formed in different method steps, the metal of the second metal layer may be different from the metal of the third metal layer. Or, for example, when two metal layers are formed in a single method step, the metal of the second metal layer may be the same as the metal of the third metal layer.

[0070] In an exemplary implementation of the method, the method includes: depositing and constructing a first hard mask layer on an aluminum gallium nitride (AGaN) barrier layer to define a third region of a GaN buffer layer; trench etching the AGaN barrier layer in the third region of the GaN buffer layer; removing the first hard mask layer; depositing a p-type doped GaN layer on the AGaN barrier layer and the GaN buffer layer exposed by the trench etching of the AGaN barrier layer; forming a metal layer on the p-type doped GaN layer; and depositing and constructing a second hard mask layer on the metal layer to define the GaN buffer layer. The second and third regions of the buffer layer; etching a metal layer and a p-type doped gallium nitride layer outside the second and third regions of the gallium nitride buffer layer to form a first p-type doped gallium nitride layer with a second metal contact and a second p-type doped gallium nitride layer with a third metal contact; removing the second hard mask layer; forming a first metal layer over the first region of the gallium nitride buffer layer exposed by etching the p-type doped gallium nitride layer; and forming a passivation layer at the aluminum gallium nitride barrier layer between the first metal layer and the second p-type doped gallium nitride layer.

[0071] This approach offers the advantage of high design flexibility. These steps can also be performed in a different order than described above.

[0072] This method corresponds to the following about Figure 8 The second method flow is described.

[0073] In an exemplary implementation of the method, the method includes: depositing a p-type doped gallium nitride (GaN) layer on an aluminum gallium nitride (AGaN) barrier layer; depositing and constructing a first hard mask layer on the p-type doped GaN layer to define a second region of a GaN buffer layer; etching the p-type doped GaN layer outside the second region of the GaN buffer layer to form a first p-type doped GaN layer; depositing and constructing a second hard mask layer on the first p-type doped GaN layer and the AGaN barrier layer exposed by etching the p-type doped GaN layer to define a third region of the GaN buffer layer; trench etching the AGaN barrier layer in the third region of the GaN buffer layer; depositing a second p-type doped GaN layer on the GaN buffer layer exposed by trench etching the AGaN barrier layer; forming a first metal layer over the first region of the GaN buffer layer removed from the second hard mask layer; forming a second metal layer over the first p-type doped GaN removed from the second hard mask layer; and forming a third metal layer over the second p-type doped GaN layer.

[0074] This approach offers the advantage of high design flexibility. These steps can also be performed in a different order than described above.

[0075] This corresponds to the following about Figure 9 The third method flow is described.

[0076] The first metal layer (emitter) can be formed in process steps prior to the formation of the second and third metal layers (gate and collector).

[0077] Alternatively, the first metal layer (emitter) can be formed in a method step after the formation of the second and third metal layers (gate and collector).

[0078] In an exemplary implementation of the method, the metal of the second metal layer is different from the metal of the third metal layer.

[0079] This provides the advantage that the two metal layers can be formed at different method steps of the method.

[0080] For example, when two metal layers are formed in different method steps, the metal of the second metal layer may be different from the metal of the third metal layer. Or, for example, when two metal layers are formed in a single method step, the metal of the second metal layer may be the same as the metal of the third metal layer.

[0081] As an alternative to the above, the metal can be deposited before pGaN etching, and the etching steps can be performed simultaneously on both the metal and pGaN layers, similar to the method described above. Specifically, after the first pGaN deposition and etching, a second pGaN can be deposited. Then, a window can be opened in the passivation covering the first pGaN layer, and a common metal layer can be deposited for both pGaN1 and pGaN2. Finally, metal etching can be performed. Attached Figure Description

[0082] Other embodiments of the present invention will be described in conjunction with the following drawings, in which...

[0083] Figure 1 A schematic cross-section of the novel GaN power transistor 100 according to the first embodiment is shown;

[0084] Figure 2 A schematic cross-section of the novel GaN power transistor 200 according to the second embodiment is shown;

[0085] Figure 3 A schematic cross-section of a novel GaN power transistor 300 according to a third embodiment is shown;

[0086] Figure 4 A schematic cross-section of a novel GaN power transistor 400 according to a fourth embodiment is shown;

[0087] Figure 5 The performance graph of the novel GaN power transistor relative to a conventional pGaN Schottky HEMT of similar size is shown in the example output characteristics 500.

[0088] Figure 6 An exemplary simulation of the on-off switching of a novel GaN power transistor based on the voltage applied to the gate electrode is shown, along with a current-voltage diagram.

[0089] Figure 7 An example method flow 700 for manufacturing a novel GaN power transistor according to a first embodiment is shown;

[0090] Figure 8 An example method flow 800 for manufacturing a novel GaN power transistor according to a second embodiment is shown;

[0091] Figure 9 An example method flow 900 for producing novel GaN power transistors according to a third embodiment is shown. Detailed Implementation

[0092] In the following detailed description, reference is made to the accompanying drawings, which form a part of this specification, illustrating specific aspects of the invention that can be practiced. It should be understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0093] It should be understood that the annotations relating to the described methods also apply to the devices or systems corresponding to the execution of the methods, and vice versa. For example, if specific method steps are described, the corresponding devices may include units for performing the described method steps, even if such units are not illustrated or described in detail in the figures. Furthermore, it should be understood that, unless otherwise explicitly stated, features of the various exemplary aspects described herein can be combined with each other.

[0094] The power transistors described herein can be used in the production of integrated circuits and / or power semiconductors, and can be manufactured using various technologies. For example, the semiconductor devices can be used in logic integrated circuits, analog integrated circuits, mixed-signal integrated circuits, optical circuits, memory circuits, and / or integrated passive devices.

[0095] Figure 1A schematic cross-section of a novel GaN power transistor 100 according to a first embodiment is shown. The GaN power transistor 100 is a novel GaN field-effect power transistor with a conductivity modulation enhancement effect. The structure of the novel GaN power transistor 100 that causes this conductivity modulation enhancement effect is described below.

[0096] This first embodiment represents a device concept for achieving complete AlGaN removal without etching the GaN channel, as described below.

[0097] GaN power transistor 100 includes gallium nitride buffer layer 110, which includes a top surface 110a and a bottom surface 110b opposite to the top surface 110a.

[0098] The gallium nitride buffer layer 110 includes a first region 101, a second region 102, and a third region 103 on the top surface 110a.

[0099] An aluminum gallium nitride (AlGaN) barrier layer 112 is deposited on the top surface 110a of the GaN buffer layer 110.

[0100] The emitter contact E is formed at the interface between the aluminum gallium nitride barrier layer 112 and the gallium nitride buffer layer 110 above the first region 101 of the gallium nitride buffer layer 110.

[0101] The GaN power transistor 100 includes a first p-type doped gallium nitride layer 113 deposited over a second region 102 of a gallium nitride buffer layer 110 at an aluminum gallium nitride barrier layer 112. The first p-type doped gallium nitride layer 113 forms the gate contact G of the gallium nitride power transistor 100.

[0102] The GaN power transistor 100 includes a second p-type doped gallium nitride layer 114, which is deposited over a third region 103 of the GaN buffer layer 110. The second p-type doped gallium nitride layer 114 forms the collector contact C of the gallium nitride power transistor 100.

[0103] The aluminum gallium nitride barrier layer 112 can be a thin AlGaN barrier deposited on the GaN buffer layer 110 to generate a strong two-dimensional electron gas (2DEG) at the AlGaN / GaN interface.

[0104] The first p-type doped GaN layer 113 may be composed of magnesium as a p-type dopant. For example, the p-type dopant may be defined below the gate metal contact G, which is only in the gate region, i.e., the second region 102. The first p-type doped GaN layer 113 depletes the 2DEG in the gate region 102 and enables the fabrication of an enhancement-mode (normally off) GaN power transistor 100.

[0105] The emitter contact E is formed by a two-dimensional electron gas generated at the interface between the aluminum gallium nitride barrier layer 112 and the gallium nitride buffer layer 110.

[0106] The collector contact C is formed at the interface between the second p-type doped gallium nitride layer 114 and the gallium nitride buffer layer 110.

[0107] The length of the first p-type doped gallium nitride layer 113 is denoted as L. GATE The length of the drift layer, i.e., the distance between the first p-type doped GaN layer 113 and the second p-type doped GaN layer 114, is denoted as L. DRIFT .

[0108] The GaN buffer layer 110 can be implemented as a GaN C-doped (carbon-doped) buffer layer. A GaN channel UID (unintentional doping) can be formed on top of the GaN buffer layer 110. The GaN channel UID 111 represents the channel of the GaN power transistor 100.

[0109] In this first embodiment of the GaN power transistor 100, a second p-type doped gallium nitride layer 114 is deposited at a gallium nitride buffer layer 110 within a recess 119 of the aluminum gallium nitride barrier layer 112. The recess 119 extends downward into the gallium nitride buffer layer 110.

[0110] The gallium nitride power transistor 100 includes a metal layer 117 deposited on a first p-type doped gallium nitride layer 113. A Schottky interface or an ohmic interface may be formed at the interface between the metal layer 117 and the first p-type doped gallium nitride layer 113.

[0111] Gallium nitride power transistor 100 may include a series circuit of a lateral power p-gallium nitride high electron mobility transistor with a pn diode, wherein the anode of the pn diode forms the collector contact C.

[0112] A pn diode can be formed at the interface between a second p-type doped gallium nitride layer 114, an aluminum gallium nitride barrier layer 112, and a gallium nitride buffer layer 110. Alternatively, a pn diode can be formed by a second p-type doped gallium nitride layer 114 and a gallium nitride buffer layer 110.

[0113] A pn diode can be formed between a second p-type doped gallium nitride layer 114 and a partially or fully recessed aluminum gallium nitride barrier layer 112.

[0114] In such Figure 1 In the case of the fully recessed aluminum gallium nitride barrier layer 112 shown in the first embodiment, the second p-type doped gallium nitride layer 114 is in direct contact with the gallium nitride channel 111 formed at the top surface 110a of the gallium nitride buffer layer 110.

[0115] In one exemplary implementation, the semiconductor doping of the second p-type doped gallium nitride layer 114 may be different from the semiconductor doping of the first p-type doped gallium nitride layer 113.

[0116] Figure 1 The gallium nitride power transistor 100 shown includes: a first metal layer 117 deposited on a first p-type doped gallium nitride layer 113; and a second metal layer 116 deposited on a second p-type doped gallium nitride layer 114. The metal of the first metal layer 117 may be different from the metal of the second metal layer 116.

[0117] Figure 1 The gallium nitride power transistor 100 shown includes a third metal layer 115, which is deposited at the emitter contact E.

[0118] The thickness of the second p-type doped gallium nitride layer 114 may be different from the thickness of the first p-type doped gallium nitride layer 113.

[0119] exist Figure 1 In the gallium nitride power transistor 100 shown, the depletion of minority carriers from the first p-type doped gallium nitride layer 113 results in a negative gate voltage applied to the gate contact of the gallium nitride power transistor during the off-state compared to a zero gate voltage applied to the gate contact during the off-state. This performance is as follows: Figure 6 As shown.

[0120] The switching speed of a device can be increased by depleting the minority carriers more quickly. This means that the device speed can be controlled by changing the gate voltage applied to the gate electrode during the device's off-state. In this way, minority carriers are depleted directly from the gate, avoiding the significantly slower normal generation-recombination process.

[0121] In this GaN power transistor 100, several parameters can be used to customize the electrical characteristics of the power device. Specifically, the following parameters can be defined:

[0122] -Gate length L G Defined as the pGaN gate region, i.e., the second region 102 ( Figure 1 Only one such second region 102 is shown in the image;

[0123] P-type doping in the pGaN gate region, i.e., the first p-type doped GaN layer 113;

[0124] -pGaN collector region P-type doping, i.e. second p-type doped GaN layer 114;

[0125] -Metal / semiconductor interface between the metal gate G and the pGaN region: Ohm-to-Schottky;

[0126] -AlGaN barrier layer 112: thickness and Al content [%];

[0127] - Passivation thickness 118 and passivation material composition (dielectric constant);

[0128] -Amount of recess 119 in AlGaN barrier layer 112: partial, complete, with GaN over-etching;

[0129] -Horizontal extension of the access area: L access

[0130] For the metal gate G, collector contact C, and emitter contact E, the following metals or combinations thereof can be used: for example, Ti, Al, TiN, W, Au, Ni, W.

[0131] For example, the length L of the first p-type doped gallium nitride layer 113 GATE It can extend from 0.3um to 5um (micrometer).

[0132] For example, the length L of the drift layer DRIFT The distance between the first p-type doped GaN layer 113 and the second p-type doped GaN layer 114 can be extended from 1µm to 30µm (micrometers).

[0133] For example, the thickness of the AlGaN barrier layer 112 can be extended from 10 nm to 30 nm.

[0134] For example, the Al content in the AlGaN barrier layer 112 can reach 15% to 25%.

[0135] For example, the pGaN thickness in the second region 102 can be extended from 50 nm to 200 nm.

[0136] For example, the pGaN thickness in the third region 103 can be extended from 50 nm to 500 nm.

[0137] The pGaN doping in the second region 102 can be based on Mg with a doping concentration of 1e18cm-3 to 5e19cm-3.

[0138] The pGaN doping in the third region 103 can be based on Mg with a doping concentration of 1e18cm-3 to 5e19cm-3.

[0139] Figure 2A schematic cross-section of a novel GaN power transistor 200 according to a second embodiment is shown. The GaN power transistor 200 is a novel GaN field-effect power transistor with a conductivity modulation enhancement effect. The structure of the novel GaN power transistor 200 that causes this conductivity modulation enhancement effect is described below.

[0140] This second embodiment represents a device concept that achieves complete AlGaN removal and partial GaN channel over-etching as described below.

[0141] The second embodiment of the GaN power transistor 200 has a structure similar to that of... Figure 1 The structure of the GaN power transistor 100 according to the first embodiment.

[0142] This means that the GaN power transistor 200 includes a gallium nitride buffer layer 110, which includes a top surface 110a and a bottom surface 110b opposite to the top surface 110a.

[0143] The gallium nitride buffer layer 110 includes a first region 101, a second region 102, and a third region 103 on the top surface 110a.

[0144] An aluminum gallium nitride (AlGaN) barrier layer 112 is deposited on the top surface 110a of the gallium nitride buffer layer 110.

[0145] The emitter contact E is formed at the interface between the aluminum gallium nitride barrier layer 112 and the gallium nitride buffer layer 110 above the first region 101 of the gallium nitride buffer layer 110.

[0146] The GaN power transistor 100 includes a first p-type doped gallium nitride layer 113, which is deposited on an aluminum gallium nitride barrier layer 112 above a second region 102 of a gallium nitride buffer layer 110. The first p-type doped gallium nitride layer 113 forms the gate contact G of the gallium nitride power transistor 100.

[0147] The gallium nitride power transistor 100 includes a second p-type doped gallium nitride layer 114, which is deposited over a third region 103 of the gallium nitride buffer layer 110. The second p-type doped gallium nitride layer 114 forms the collector contact C of the gallium nitride power transistor 100.

[0148] In a second embodiment of the gallium nitride power transistor 200, a second p-type doped gallium nitride layer 114 is deposited at the gallium nitride buffer layer 110 within the recess 119 of the aluminum gallium nitride barrier layer 112. Figure 1 The difference in the first embodiment is that the recess 119 extends into and is recessed into the gallium nitride buffer layer 110.

[0149] This means that the AlGaN barrier layer 112 is completely removed, and the GaN channel 111, which is part of a segment on the GaN buffer layer 110, is partially over-etched, as shown from... Figure 2 This can be seen in the image. In one example, the over-etching can even extend down to the GaN buffer layer 110.

[0150] In this GaN power transistor 200, several parameters can be used to customize the electrical characteristics of the power device. Specifically, the above references can be defined. Figure 1 The same related parameters as described.

[0151] Figure 3 A schematic cross-section of a novel GaN power transistor 300 according to a third embodiment is shown. The GaN power transistor 300 is a novel GaN field-effect power transistor with a conductivity modulation enhancement effect. The structure of this novel GaN power transistor 300 that causes this conductivity modulation enhancement effect is described below.

[0152] This third embodiment illustrates a device concept for partially over-etched AlGaN, as described below.

[0153] The structure of the third embodiment of the GaN power transistor 300 is similar to that according to the... Figure 1 The structure of the GaN power transistor 100 in the first embodiment described above is similar to that according to the... Figure 2 The structure of the GaN power transistor 200 in the second embodiment described above.

[0154] This means that the GaN power transistor 300 includes a gallium nitride buffer layer 110, which includes a top surface 110a and a bottom surface 110b opposite to the top surface 110a.

[0155] The gallium nitride buffer layer 110 includes a first region 101, a second region 102, and a third region 103 on the top surface 110a.

[0156] An aluminum gallium nitride (AlGaN) barrier layer 112 is deposited on the top surface 110a of the GaN buffer layer 110.

[0157] The emitter contact E is formed above the first region 101 of the gallium nitride buffer layer 110 at the interface between the aluminum gallium nitride barrier layer 112 and the gallium nitride buffer layer 110.

[0158] The GaN power transistor 100 includes a first p-type doped gallium nitride layer 113 deposited over a second region 102 of a gallium nitride buffer layer 110 at an aluminum gallium nitride barrier layer 112. The first p-type doped gallium nitride layer 113 forms the gate contact G of the gallium nitride power transistor 100.

[0159] The GaN power transistor 100 includes a second p-type doped gallium nitride layer 114 deposited over a third region 103 of the gallium nitride buffer layer 110. The second p-type doped gallium nitride layer 114 forms the collector contact C of the gallium nitride power transistor 100.

[0160] In a third embodiment of the GaN power transistor 300, a second p-type doped gallium nitride layer 114 is deposited at the aluminum nitride barrier layer 112 within a recess 119 of the aluminum gallium nitride barrier layer 112. Figure 1 The difference in the first embodiment is that the recess 119 is partially recessed into the aluminum gallium nitride barrier layer 112, rather than completely removing the AlGaN barrier layer 112.

[0161] In this GaN power transistor 300, several parameters can be used to customize the electrical characteristics of the power device. Specifically, parameters related to... Figure 1 The same related parameters as those mentioned above.

[0162] Figure 4 A schematic cross-section of a novel gallium nitride power transistor 400 according to a fourth embodiment is shown. The GaN power transistor 400 is a novel GaN field-effect power transistor with a conductivity modulation enhancement effect. The structure of this novel GaN power transistor 400 that causes this conductivity modulation enhancement effect is described below.

[0163] This fourth embodiment illustrates a device concept for implementing additional p-type implantation to increase electrical properties and suppress possible latch-up effects, as described below.

[0164] The structure of this third embodiment of the GaN power transistor 300 is similar to that according to the... Figures 1 to 3 Any one of the GaN power transistors 100, 200, and 300 described in the first, second, and third embodiments above.

[0165] The difference from the first, second, and third embodiments is that the aluminum gallium nitride barrier layer 112 and the gallium nitride buffer layer 110 include additional p-type implants in the regions below the emitter and gate contacts. This additional p-type implant increases the base voltage (BV) and suppresses potential latch-up effects.

[0166] Figure 5 The illustration shows a performance graph of the example output characteristics 500 of the novel GaN power transistor compared to a conventional pGaN Schottky HEMT with comparable dimensions.

[0167] Figure 5 The above information is shown in the figure. Figures 1 to 4The description compares the output characteristics of the newly disclosed device concept 501 with those of a conventional pGaN Schottky HEMT 502 with comparable dimensions.

[0168] It can be observed that the typical knee voltage of IGBT-type GaN devices is visible at low collector-emitter voltages. Compared to the conventional GaN HEMT 502, the newly disclosed device (GaN IGBT) 501 exhibits a lower on-state current at low collector-emitter voltages. However, due to channel conductance modulation, a significant improvement in on-state conductivity can be observed at higher collector-emitter voltages.

[0169] Figure 6 An exemplary simulation of the on-off switching of a novel GaN power transistor based on the voltage applied to the gate electrode is shown, along with a current-voltage diagram.

[0170] First Figure 601 shows the current (amperes) on the collector-emitter voltage (volts) applied to the gate electrode at a zero-volt gate voltage. Second Figure 602 shows the current (amperes) on the collector-emitter voltage (volts) applied to the gate electrode at a negative 5-volt gate voltage.

[0171] Figure 6 This demonstrates one of the major advantages of the disclosed device concept. While in conventional silicon-based IGBTs, the tail current generated by the slow recombination effect of a few carriers in the drift region strongly affects the switching speed and performance of the device, in the newly proposed device concept, the tail current can be almost completely eliminated due to the specific gate structure implemented.

[0172] In particular, the pGaN gate region allows for the rapid depletion of holes injected into the drift region during conduction in the on-state. Furthermore, the switching speed of the device can be controlled by appropriately selecting the off-state voltage applied to the gate electrode.

[0173] Figure 6 Specifically, when a negative gate voltage (in this example of -5V) is applied to the gate electrode, holes can be depleted from the drift region more quickly during the off-state, thus making the device's on-off transition period faster. In this way, the device speed can be electrically controlled by varying the voltage applied to the gate electrode during the off-state.

[0174] Figure 7 An example method flow 700 for manufacturing a novel GaN power transistor according to a first embodiment is shown.

[0175] The main methods and steps can be summarized as follows:

[0176] a) The initial epitaxial stack includes a GaN buffer 110, an AlGaN barrier 112, and a GaN layer p-type doped 701;

[0177] b) Sacrifice passivation deposition and structure. This passivation layer is used as a mask layer 710 for the subsequent trench etching process step. The next step is AlGaN barrier 112 trench etching (complete, partial, or even over-etched, as described above). Figures 1 to 3 (As stated above). The hard mask 710 was subsequently removed;

[0178] c) pGaN 701 is regrown on the cover wafer;

[0179] d) Deposition and construction of hard mask 711 for defining the gate and collector regions;

[0180] e) etch pGaN 701, stop on AlGaN barrier layer 112, and then remove hard mask 711;

[0181] f) Contact formation (gate G, emitter E, and collector C) and final device passivation 118.

[0182] Figure 8 An example method flow 800 for manufacturing a novel GaN power transistor according to a second embodiment is shown.

[0183] As Figure 7 The alternative to method flow 700 shown is... Figure 8 The method flow 800 shown above represents the same as the above regarding Figure 7 The method flow 700 is described with minor variations. Specifically, the metal 810 for the gate (G) contact and collector (C) contact is deposited just after the pGaN 701 is regrown and before the pGaN 701 is etched. Then, after hard mask deposition and construction, the metal layer 810 and the pGaN layer 701 are simultaneously recessed to define the gate and collector regions.

[0184] Figure 9 An example method flow 900 for producing novel GaN power transistors according to a third embodiment is shown.

[0185] Figure 9 It indicates Figure 7 and 8 Another illustrative alternative to the method flows 700 and 800 shown is method flow 900. Regarding... Figure 7 or Figure 8The main difference between the method flows 700 and 800 shown is that the pGaN regions 113 and 114 for the gate G and for the collector C are formed in two different steps of the method. This allows for independent tuning of the geometry and doping of the two regions, and provides greater freedom for final device optimization and electrical characteristic customization.

[0186] In summary, method flows 700, 800, and 900 can be described using methods for manufacturing gallium nitride power transistors 100, 200, 300, and 400. These methods include the following steps:

[0187] A gallium nitride buffer layer 110 is formed, which includes a top surface 110a and a bottom surface 110b opposite to the top surface 110a. The gallium nitride buffer layer 110 includes a first region 101, a second region 102, and a third region 103 on the top surface 110a, for example, as described above regarding... Figures 1 to 3 The above;

[0188] An aluminum gallium nitride barrier layer 112 is deposited on the top surface 110a of the gallium nitride buffer layer 110;

[0189] A first p-type doped gallium nitride layer 113 is deposited above the second region 102 of the gallium nitride buffer layer 110 at the aluminum gallium nitride barrier layer 112, and the first p-type doped gallium nitride layer 113 forms the gate contact of the gallium nitride power transistor 100.

[0190] A second p-type doped gallium nitride layer 114 is deposited above the third region 103 of the gallium nitride buffer layer 110, and the second p-type doped gallium nitride layer 114 forms the collector contacts of the gallium nitride power transistors 100, 200, and 300; and

[0191] An emitter contact is formed at the interface between the gallium nitride barrier layer 112 and the gallium nitride buffer layer 110 above the first region 101 of the gallium nitride buffer layer 110.

[0192] for Figure 7 The method flow 700 shown above may include the following method steps:

[0193] A first hard mask layer 710 is deposited and constructed at the aluminum gallium nitride barrier layer 112 (see method step b) to define a third region 103 of the gallium nitride buffer layer 110, for example, as described above regarding Figures 1 to 3 The above;

[0194] A gallium aluminum nitride barrier layer 112 is trench-etched at the third region 103 of the gallium nitride buffer layer 110 (see method step c), for example, as described above regarding Figures 1 to 3 The above;

[0195] Remove the first hard mask layer 710;

[0196] A p-type doped gallium nitride layer 701 is deposited on the gallium nitride barrier layer 112 and the gallium nitride buffer layer 110 exposed by trench etching of the aluminum gallium nitride barrier layer 112 (see method step c).

[0197] A second hard mask layer 711 is deposited and constructed on the p-type doped gallium nitride layer 701 (see method step d) to define the second region 102 and the third region 103 of the gallium nitride buffer layer 110;

[0198] The p-type doped gallium nitride layer 701 is etched outside the second region 102 and the third region 103 of the gallium nitride buffer layer 110 (see method step e) to form the first p-type doped gallium nitride layer 113 and the second p-type doped gallium nitride layer 114.

[0199] Remove the second hard mask layer 711 (see method step f);

[0200] A first metal layer 115 is formed over the first region 101 of the gallium nitride buffer layer 110 exposed by etching the p-type doped gallium nitride layer 701 (see method step f);

[0201] A second metal layer 117 is formed over the first p-type doped gallium nitride layer 113 (see method step f), and a third metal layer 116 is formed over the second p-type doped gallium nitride layer 114; and

[0202] A passivation layer 118 is formed at the aluminum gallium nitride barrier layer 112 between the first metal layer 115 and the second p-type doped gallium nitride layer 114 (see method step f).

[0203] For example, when two metal layers 117 and 116 are formed in different method steps, the metal of the second metal layer 117 may be different from the metal of the third metal layer 116. Alternatively, for example, when two metal layers 117 and 116 are formed in a single method step, the metal of the second metal layer 117 may be the same as the metal of the third metal layer 116.

[0204] The first metal layer 115 (emitter) can be formed in a method step prior to the formation of the second metal layer 117 and the third metal layer 116 (gate and collector).

[0205] Alternatively, the first metal layer 115 (emitter) can be formed in a method step after the formation of the second metal layer 117 and the third metal layer 116 (gate and collector).

[0206] for Figure 8 The method flow 800 shown above may include the following method steps:

[0207] A first hard mask layer 710 (see method step b) is deposited and constructed on the aluminum gallium nitride barrier layer 112 to define a third region 103 of the gallium nitride buffer layer 110.

[0208] A gallium aluminum nitride barrier layer 112 is trench-etched at the third region 103 of the gallium nitride buffer layer 110 (see method step b);

[0209] Remove the first hard mask layer 710 (see method step c);

[0210] A p-type doped gallium nitride layer 701 is deposited on the gallium nitride barrier layer 112 and the gallium nitride buffer layer 110 exposed by trench etching of the aluminum gallium nitride barrier layer 112 (see method step c).

[0211] A metal layer 810 is formed at the p-type doped gallium nitride layer 701 (see method step e);

[0212] A second hard mask layer 711 is deposited and constructed at the metal layer 810 (see method step d) to define the second region 102 and the third region 103 of the gallium nitride buffer layer 110;

[0213] Etch metal layer 810 (see method step f) and p-type doped gallium nitride layer 701 outside the second region 102 and the third region 103 of gallium nitride buffer layer 110 to form a first p-type doped gallium nitride layer 113 having a second metal contact 117 and a second p-type doped gallium nitride layer 114 having a third metal contact 116.

[0214] Remove the second hard mask layer 711 (see method step g);

[0215] A first metal layer 115 is formed over the first region 101 of the gallium nitride buffer layer 110 exposed by etching the p-type doped gallium nitride layer 701 (see method step g); and

[0216] A passivation layer 118 is formed at the aluminum gallium nitride barrier layer 112 between the first metal layer 115 and the second p-type doped gallium nitride layer 114 (see method step g).

[0217] for Figure 9 The method flow 900 shown above may include the following method steps:

[0218] A p-type doped gallium nitride layer 701 is deposited on the aluminum gallium nitride barrier layer 112 (see method step a);

[0219] A first hard mask layer 910 is deposited and constructed at the p-type doped gallium nitride layer 701 (see method step a) to define a second region 102 of the gallium nitride buffer layer 110;

[0220] A p-type doped gallium nitride layer 701 is etched outside the second region 102 of the gallium nitride buffer layer 110 (see method step b) to form a first p-type doped gallium nitride layer 113;

[0221] A second hard mask layer 911 is deposited and constructed at the first p-type doped gallium nitride layer 102 and the aluminum gallium nitride barrier layer 112 exposed by etching the p-type doped gallium nitride layer 701 (see method step c) to define a third region 103 of the gallium nitride buffer layer 110.

[0222] A gallium aluminum nitride barrier layer 112 is trench-etched at the third region 103 of the gallium nitride buffer layer 110 (see method step d);

[0223] A second p-type doped gallium nitride layer 114 is deposited on the gallium nitride buffer layer 110 exposed by trench etching of the aluminum gallium nitride barrier layer 112 (see method step e);

[0224] A first metal layer 115 is formed over the first region 101 of the gallium nitride buffer layer 110 removed from the second hard mask layer 911 (see method step f);

[0225] A second metal layer 117 is formed over the first p-type doped gallium nitride layer 113 removed from the second hard mask layer 911 (see method step f); and

[0226] A third metal layer 116 is formed above the second p-type doped gallium nitride layer 114 (see method step f).

[0227] For example, when two metal layers 117 and 116 are formed in different method steps, the metal of the second metal layer 117 may be different from the metal of the third metal layer 116. Alternatively, for example, when two metal layers 117 and 116 are formed in a single method step, the metal of the second metal layer 117 may be the same as the metal of the third metal layer 116.

[0228] The first metal layer 115 (emitter) can be formed in a method step prior to the formation of the second metal layer 117 and the third metal layer 116 (gate and collector).

[0229] Alternatively, the first metal layer 115 (emitter) can be formed in a method step after the formation of the second metal layer 117 and the third metal layer 116 (gate and collector).

[0230] As an alternative to the above method, the metal can be deposited before pGaN etching, and the etching step can be performed on both the metal and the pGaN layer simultaneously, similar to the methods of claims 18 and 20. Specifically, after the first pGaN deposition and etching, a second pGaN can be deposited, and then a window can be opened in the passivation covering the first pGaN layer, allowing a common metal layer to be deposited for both pGaN1 and pGaN2. Finally, metal etching can be performed.

[0231] While certain features or aspects of the invention may have been disclosed in combination with only one of several implementations, such features or aspects may be combined with one or more features or aspects of other implementations, provided that they are necessary or advantageous for any given or particular application. Furthermore, to a certain extent, the terms “comprising,” “having,” “possessing,” or other variations of these words are used in the detailed description or claims; such terms are similar to the term “comprising” and both indicate inclusion. Similarly, the terms “exemplary” and “for example” are used only as examples and not as best or most preferred. The terms “coupled” and “connected,” as well as their derivatives, may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical contact or electrical contact, or whether they are not in direct contact with each other.

[0232] While specific aspects have been illustrated and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may replace the specific aspects shown and described without departing from the scope of the invention. This application is intended to cover any modifications or alterations to the specific aspects discussed herein.

[0233] Although the elements in the above claims are listed in a specific order using corresponding labels, these elements are not necessarily limited to being implemented in that specific order unless the description of the claims otherwise implies a specific order for implementing some or all of these elements.

[0234] Based on the above guidance, many alternatives, modifications, and variations will be apparent to those skilled in the art. Of course, those skilled in the art will readily recognize that numerous other applications of the invention exist besides those described herein. Although the invention has been described in conjunction with one or more specific embodiments, those skilled in the art will recognize that many changes can be made to the invention without departing from its scope. Therefore, it should be understood that the invention can be practiced in ways other than those specifically described herein, as long as it remains within the scope of the appended claims and their equivalents.

Claims

1. A gallium nitride power transistor (100), characterized in that, include: Gallium nitride buffer layer (110), the gallium nitride buffer layer (110) includes a top surface (110a) and a bottom surface (110b) opposite to the top surface (110a), the gallium nitride buffer layer (110) includes a first region (101), a second region (102) and a third region (103) at the top surface (110a). An aluminum gallium nitride barrier layer (112) is deposited on the top surface (110a) of the gallium nitride buffer layer (110); Emitter contact, which is formed at the interface between the aluminum gallium nitride barrier layer (112) and the gallium nitride buffer layer (110) above the first region (101) of the gallium nitride buffer layer (110); A first p-type doped gallium nitride layer (113) is deposited on the aluminum gallium nitride barrier layer (112) above the second region (102) of the gallium nitride buffer layer (110), and the first p-type doped gallium nitride layer (113) forms the gate contact of the gallium nitride power transistor (100); A second p-type doped gallium nitride layer (114) is deposited over the third region (103) of the gallium nitride buffer layer (110), and the second p-type doped gallium nitride layer (114) forms the collector contact of the gallium nitride power transistor (100); The second p-type doped gallium nitride layer (114) is deposited in the recess of the aluminum gallium nitride barrier layer (112) at the aluminum gallium nitride barrier layer (112), the recess being partially recessed into the aluminum gallium nitride barrier layer (112).

2. The gallium nitride power transistor (100) according to claim 1, characterized in that, The emitter contact is formed by a two-dimensional electron gas generated at the interface between the aluminum gallium nitride barrier layer (112) and the gallium nitride buffer layer (110).

3. The gallium nitride power transistor (100) according to claim 1 or 2, characterized in that, Includes a metal layer (117) deposited on the first p-type doped gallium nitride layer (113), wherein the interface between the metal layer (117) and the first p-type doped gallium nitride layer (113) forms a Schottky interface or an ohmic interface.

4. The gallium nitride power transistor (100) according to claim 3, characterized in that, A series circuit comprising a lateral power p-gallium nitride high electron mobility transistor with a pn diode, wherein the anode of the pn diode forms the collector contact.

5. The gallium nitride power transistor (100) according to claim 4, characterized in that, The pn diode is formed by the interface between the second p-type doped gallium nitride layer (114), the aluminum gallium nitride barrier layer (112), and the gallium nitride buffer layer (110).

6. The gallium nitride power transistor (100) according to claim 4 or 5, characterized in that, The pn diode is formed between the second p-type doped gallium nitride layer (114) and the partially recessed aluminum gallium nitride barrier layer (112).

7. The gallium nitride power transistor (100) according to claim 6, characterized in that, In the case of a fully recessed aluminum gallium nitride barrier layer (112), the second p-type doped gallium nitride layer (114) is in direct contact with the gallium nitride channel (111) formed at the top surface (110a) of the gallium nitride buffer layer (110).

8. The gallium nitride power transistor (100) according to any one of claims 1, 2, 4, 5 or 7, characterized in that, The semiconductor doping of the second p-type doped gallium nitride layer (114) is different from that of the first p-type doped gallium nitride layer (113).

9. The gallium nitride power transistor (100) according to any one of claims 1, 2, 4, 5 or 7, characterized in that, include: A first metal layer (117) is deposited on the first p-type doped gallium nitride layer (113); A second metal layer (116) is deposited on top of the second p-type doped gallium nitride layer (114). The metal of the first metal layer (117) is different from the metal of the second metal layer (116).

10. The gallium nitride power transistor (100) according to any one of claims 1, 2, 4, 5 or 7, characterized in that, The thickness of the second p-type doped gallium nitride layer (114) is different from the thickness of the first p-type doped gallium nitride layer (113).

11. The gallium nitride power transistor (100) according to any one of claims 1, 2, 4, 5 or 7, characterized in that, The depletion of minority carriers from the first p-type doped gallium nitride layer (113) results in a negative gate voltage applied to the gate contact of the gallium nitride power transistor during the off state than a zero gate voltage applied to the gate contact during the off state.

12. The gallium nitride power transistor (100) according to any one of claims 1, 2, 4, 5 or 7, characterized in that, The aluminum gallium nitride barrier layer (112) and the gallium nitride buffer layer (110) include additional p-type implantation in the region below the emitter contact and the gate contact.

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