Packaging structure, packaging method and radio frequency module

Abstract

This application provides a packaging structure, packaging method, and radio frequency module, relating to the field of semiconductor chip packaging technology, and improves the sealing performance of the packaging structure. The packaging structure includes: a cover plate; an outer wall stacked on one side of the cover plate, the orthographic projection of the outer wall onto the cover plate being a closed annular region; a wafer stacked on the side of the outer wall opposite to the cover plate, the cover plate, outer wall, and wafer forming a cavity structure, electronic devices disposed on the surface of the wafer near the cover plate, the electronic devices being located within the cavity structure, the wafer including a first through-hole; and a wiring layer filling the first through-hole, thereby forming a closed cavity structure through the complete cover plate, outer wall, wafer, and wiring layer, making the electronic devices located within the cavity structure less susceptible to contamination, thus improving the sealing performance and reliability of the packaging structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip packaging technology, specifically to a packaging structure, packaging method, and radio frequency module. Background Technology

[0002] With the rapid development of 5G mobile communication technology, acoustic filters have been widely used in the mobile communication field due to their advantages of high performance and small size. The packaging of acoustic filters must ensure that the interdigital transducers (IDTs) within them do not come into contact with other materials to avoid affecting the normal operation of the acoustic filter. However, current packaging structures and methods suffer from problems such as susceptibility to contamination, complex manufacturing processes, and poor packaging reliability.

[0003] Therefore, improving the sealing performance and reliability of the packaging has become an urgent problem to be solved. Summary of the Invention

[0004] To address the aforementioned technical problems, this application is proposed. Embodiments of this application provide a packaging structure, a packaging method, and a radio frequency module.

[0005] In a first aspect, one embodiment of this application provides a packaging structure, which includes: a cover plate; an outer wall stacked on one side of the cover plate, the orthographic projection of the outer wall on the cover plate being a closed annular region; a wafer stacked on the side of the outer wall opposite to the cover plate, the cover plate, the outer wall and the wafer forming a cavity structure, an electronic device being disposed on the surface of the wafer near the cover plate, the electronic device being located within the cavity structure, the wafer including a first through-hole; and a wiring layer filling the first through-hole.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, the orthographic projection of the first through hole onto the cover plate lies between the annular region and the orthographic projection of the electronic device onto the cover plate.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, the packaging structure further includes: electrodes stacked on the side of the wafer near the cover plate, in contact with the wiring layer, and the electrodes located within the cavity structure;

[0008] Preferably, the orthographic projection of the electrode on the cover plate is located between the annular region and the orthographic projection of the electronic device on the cover plate;

[0009] Preferably, the orthographic projection of the electrode on the cover plate covers the orthographic projection of the first through hole on the cover plate;

[0010] Preferably, the packaging structure further includes: bumps, stacked on the side of the wiring layer away from the cover plate, and in contact with the wiring layer;

[0011] Preferably, the wiring layer extends to the surface of the wafer opposite to the cover plate.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the packaging structure further includes: a passivation layer stacked on the side of the wiring layer away from the cover plate, wherein the orthographic projection of the wafer on the cover plate is located within the orthographic projection range of the passivation layer on the cover plate, or the orthographic projection of the passivation layer on the cover plate coincides with the orthographic projection of the wafer on the cover plate.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the passivation layer includes a second via that exposes the bump;

[0014] Preferably, the edge of the wafer's orthographic projection onto the cover plate is located between the inner and outer edges of the annular region.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the orthographic projection of the exterior wall onto the cover plate is located within the orthographic projection range of the passivation layer onto the cover plate.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the cover plate is made of glass.

[0017] Secondly, one embodiment of this application provides a packaging method, which includes: providing a wafer; fabricating a plurality of outer walls on one side of the wafer, wherein the orthographic projection of the outer walls on the wafer is a closed annular region; providing a cover plate and bonding the cover plate to the side of the wafer with the outer walls, so that the cover plate, the outer walls and the wafer form a cavity structure; cutting the cover plate in units of the outer walls to obtain a plurality of packaging structures; wherein an electronic device is disposed on the surface of the wafer near the cover plate, the electronic device is located in the cavity structure, and the wafer includes a first through hole, the first through hole being filled with a wiring layer.

[0018] In conjunction with the second aspect, in some implementations of the second aspect, after providing a cover plate and bonding the cover plate to the side of the wafer with an outer wall, the packaging method further includes: preparing a passivation layer on the side of the wiring layer opposite to the cover plate, and forming a second via within the passivation layer, wherein the orthographic projection of the wiring layer on the cover plate covers the orthographic projection of the second via on the cover plate, and the orthographic projection of the wafer on the cover plate is located within the orthographic projection range of the passivation layer on the cover plate, or the orthographic projection of the passivation layer on the cover plate coincides with the orthographic projection of the wafer on the cover plate; and preparing bumps within the second via, such that the bumps fill and protrude from the second via.

[0019] Thirdly, one embodiment of this application provides a radio frequency module, including the packaging structure mentioned in any of the above embodiments.

[0020] The packaging structure provided in this application includes: a cover plate; an outer wall stacked on one side of the cover plate, the orthographic projection of the outer wall on the cover plate being a closed annular region; a wafer stacked on the side of the outer wall away from the cover plate, the cover plate, the outer wall, and the wafer forming a cavity structure, an electronic device being disposed on the surface of the wafer near the cover plate, the electronic device being located within the cavity structure, and the wafer including a first through-hole; and a wiring layer filling the first through-hole, thereby forming a closed cavity structure through the complete cover plate, outer wall, wafer, and wiring layer, making the electronic device located within the cavity structure less susceptible to contamination, thereby improving the sealing and reliability of the packaging structure. Attached Figure Description

[0021] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0022] Figure 1 The diagram shown is a schematic diagram of the packaging structure provided in an embodiment of this application.

[0023] Figure 2 The diagram shown is a schematic diagram of the packaging structure provided in another embodiment of this application.

[0024] Figure 3 The diagram shown is a flowchart of an embodiment of the encapsulation method provided in this application.

[0025] Figure 4 The diagram shown is a flowchart of a packaging method provided in another embodiment of this application.

[0026] Figures 5a to 5g The image shown is of this application. Figure 1 The diagram shows the process structure of the encapsulation structure.

[0027] Figure 6 The diagram shown is a flowchart of a packaging method provided in another embodiment of this application.

[0028] Figures 7a to 7e The image shown is of this application. Figure 2 The diagram shows the process structure of the encapsulation structure.

[0029] Figure 8 The diagram shown is a structural schematic of a radio frequency module provided in an embodiment of this application.

[0030] Reference numerals: Package structure 100; Cover plate 110; Outer wall 120; Wafer 130; Electronic device 140; Wiring layer 150; Electrode 160; Bump 170; Passivation layer 181; Cavity structure 0; RF module 10. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented even without certain specific details. In some instances, methods and means well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0033] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0034] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0035] Figure 1 The diagram shown is a schematic representation of the packaging structure provided in one embodiment of this application. Figure 1 As shown, one embodiment of this application provides a packaging structure 100, which includes: a cover plate 110; an outer wall 120 stacked on one side of the cover plate 110, the orthographic projection of the outer wall 120 on the cover plate 110 being a closed annular region; a wafer 130 stacked on the side of the outer wall 120 facing away from the cover plate 110, the cover plate 110, the outer wall 120 and the wafer 130 forming a cavity structure O, an electronic device 140 being disposed on the surface of the wafer 130 near the cover plate 110, the electronic device 140 being located within the cavity structure O, the wafer 130 including a first through-hole; and a wiring layer 150 filling the first through-hole.

[0036] Specifically, the packaging structure 100 can be an acoustic filter, and the electronic device 140 can be an interdigital transducer. The outer wall 120 can be an insulating layer, such as an organic dry film.

[0037] In one embodiment of the related technology, the wiring layer is led out through through-holes in the cover plate. However, making through-holes in the cover plate can easily lead to cracks in the cover plate, greatly increasing the risk of contaminating electronic devices and resulting in poor sealing and reliability.

[0038] In this embodiment, the wiring layer 150 is led out through the first through hole on the wafer 130, thereby ensuring the integrity of the cover plate 110. The complete cover plate 110, outer wall 120, wafer 130 and wiring layer 150 form a closed cavity structure O, making the electronic device 140 located in the cavity structure O less susceptible to contamination, thereby improving the sealing and reliability of the packaging structure 100.

[0039] refer to Figure 1 In the encapsulation structure 100 provided in this application embodiment, the orthographic projection of the first through hole on the cover plate 110 is located between the annular region and the orthographic projection of the electronic device 140 on the cover plate 110.

[0040] This application embodiment provides the projected positional relationship between the first through hole and the outer wall 120 and the electronic device 140. Since the wiring layer 150 fills the first through hole, it also provides the projected positional relationship between the wiring layer 150 and the outer wall 120 and the electronic device 140, thereby achieving the purpose of leading out the wiring layer 150 through the first through hole to ensure the integrity of the cover plate 110.

[0041] refer to Figure 1 In the packaging structure 100 provided in this application embodiment, the packaging structure 100 further includes: an electrode 160, which is stacked on the side of the wafer 130 near the cover plate 110 and in contact with the wiring layer 150. The electrode 160 is located within the cavity structure O. By setting the electrode 160 and having it in contact with the wiring layer 150, this application embodiment forms an important link in the electrical connection between the packaging structure 100 and the external circuit board.

[0042] Preferably, the orthographic projection of electrode 160 on cover plate 110 is located between the annular region and the orthographic projection of electronic device 140 on cover plate 110, thereby making electrode 160 contact with wiring layer 150.

[0043] Preferably, the orthographic projection of electrode 160 on cover plate 110 covers the orthographic projection of the first through hole on cover plate 110. As described above, the first through hole is filled with wiring layer 150, and the orthographic projection of electrode 160 on cover plate 110 covers the orthographic projection of the first through hole on cover plate 110. This ensures that the orthographic projection of electrode 160 on cover plate 110 covers the orthographic projection of wiring layer 150 in the first through hole on cover plate 110, thereby ensuring that electrode 160 and wiring layer 150 are in full contact, avoiding partial contact that could affect the reliability of the electrical connection and thus affect signal transmission.

[0044] Preferably, the packaging structure 100 further includes: a bump 170, which is stacked on the side of the wiring layer 150 away from the cover plate 110 and in contact with the wiring layer 150.

[0045] Specifically, the shape of the bump 170 can be hemispherical, spherical, elliptical, or cuboid. The shape of the bump 170 can be set according to actual needs, which will not be elaborated further here. Additionally, the material of the bump 170 can be metal, such as nickel-palladium-gold, nickel-gold, or tin-silver solder balls. The bump 170 is used to connect to external devices, such as external circuit boards, so that the package structure 100 transmits signals to and receives signals from the external device through the bump 170.

[0046] Preferably, the wiring layer 150 extends to the surface of the wafer 130 opposite to the cover plate 110, thereby increasing the coverage of the wiring layer 150, providing more options for the placement of the bumps 170, and improving the flexibility of the bump placement.

[0047] In another embodiment of the related technology, the wiring layer is led out from the side of the wafer and spans at least the packaging layer, electrode 160, passivation layer and wafer. This results in a long wiring layer, which increases the signal transmission time and causes adverse consequences such as delayed response.

[0048] In this embodiment, the wiring layer 150 passes directly through the wafer 130 via the first via, with one end contacting the bump 170 and the other end contacting the electrode 160. The wiring layer 150 provided in this embodiment only spans the wafer 130, greatly shortening its length and thus reducing signal transmission time, which is beneficial for rapid response.

[0049] refer to Figure 1 In the packaging structure 100 provided in this application embodiment, the packaging structure 100 further includes a passivation layer 181, which is stacked on the side of the wiring layer 150 facing away from the cover plate 110. The orthogonal projection of the wafer 130 on the cover plate 110 is located within the orthogonal projection range of the passivation layer 181 on the cover plate 110, thereby sealing all sides of the wafer 130 through the cover plate 110 and the passivation layer 181. For the electronic device 140, based on the closed cavity structure O formed by the cover plate 110, outer wall 120, wafer 130 and wiring layer 150, the passivation layer 181 is added as a protective barrier, thereby making the cover plate 110, outer wall 120, wafer 130 and wiring layer 150 less susceptible to water and oxygen corrosion from the external environment, and the electronic device 140 less susceptible to water and oxygen corrosion and less susceptible to contamination. Therefore, the embodiments of this application further improve the sealing performance and reliability of the packaging structure 100.

[0050] refer to Figure 1In the packaging structure 100 provided in this application embodiment, the passivation layer 181 includes a second via, which exposes a bump 170. This application embodiment provides the relative positional relationship between the passivation layer 181 and the bump 170, with the bump 170 passing through the second via of the passivation layer 181 and contacting the wiring layer 150.

[0051] Preferably, the edge of the orthographic projection of the wafer 130 on the cover plate 110 is located between the inner and outer edges of the annular region, so that the passivation layer 181 can completely cover the wafer 130 during the preparation of the passivation layer 181, thereby ensuring the sealing of the package structure 100.

[0052] refer to Figure 1 In the encapsulation structure 100 provided in this application embodiment, the orthographic projection of the outer wall 120 on the cover plate 110 is located within the orthographic projection range of the passivation layer 181 on the cover plate 110. This seals all sides of the outer wall 120 through the cover plate 110 and the passivation layer 181, making the electronic device 140 less susceptible to water and oxygen corrosion and less prone to contamination. Therefore, this application embodiment further improves the sealing performance and reliability of the encapsulation structure 100.

[0053] In another embodiment of this application, reference is made to Figure 2 , Figure 2 The diagram shown is a schematic representation of a packaging structure provided in another embodiment of this application. In the packaging structure 100 provided in this embodiment, the packaging structure 100 further includes a passivation layer 181, stacked on the side of the wiring layer 150 facing away from the cover plate 110. The orthogonal projection of the passivation layer 181 on the cover plate 110 coincides with the orthogonal projection of the wafer 130 on the cover plate 110, thereby making the wafer 130 less susceptible to corrosion by water and oxygen in the external environment, and thus making the electronic device 140 less susceptible to water and oxygen corrosion and less prone to contamination. Therefore, this embodiment further improves the sealing performance and reliability of the packaging structure 100.

[0054] refer to Figure 2 In the packaging structure 100 provided in this application embodiment, the passivation layer 181 includes a second via, which exposes a bump 170. This application embodiment provides the relative positional relationship between the passivation layer 181 and the bump 170, with the bump 170 passing through the second via of the passivation layer 181 and contacting the wiring layer 150.

[0055] refer to Figure 2 In the encapsulation structure 100 provided in this application embodiment, the orthographic projection of the outer wall 120 on the cover plate 110 is located within the orthographic projection range of the passivation layer 181 on the cover plate 110.

[0056] In this embodiment, based on the use of a closed cavity structure O to surround the electronic device 140, a passivation layer 181 is added as a protective barrier, thereby further improving the sealing performance and reliability of the packaging structure 100.

[0057] In the encapsulation structure 100 provided in this application embodiment, the cover plate 110 is made of glass. It is understood that glass has good environmental resistance and mechanical stability, resulting in less warping during the manufacturing process. This avoids the problems associated with cover plates 110 made of other materials, such as the release of organic matter at high temperatures and easy collapse that could contaminate the electronic device 140. Therefore, the glass cover plate 110 provided in this application embodiment improves the sealing performance, reliability, and stability of the encapsulation structure 100.

[0058] The above describes in detail the specific contents of the packaging structure 100 provided in this application. Based on the same inventive concept, this application also provides a corresponding packaging method. The specific steps of the packaging method are described below.

[0059] Figure 3 The diagram shown is a schematic flowchart of a packaging method provided in an embodiment of this application. Figure 3 As shown, the encapsulation method provided in this application embodiment includes the following steps:

[0060] Step S31, provide wafer 130.

[0061] In step S32, a plurality of outer walls 120 are fabricated on one side of wafer 130. The orthographic projection of the outer wall 120 on wafer 130 is a closed annular region.

[0062] Step S33: Provide a cover plate 110 and bond the cover plate 110 to one side of the wafer 130 with an outer wall 120, so that the cover plate 110, the outer wall 120 and the wafer 130 form a cavity structure O.

[0063] In step S34, the cover plate 110 is cut into units of the outer wall 120 to obtain multiple encapsulation structures 100.

[0064] Among them, an electronic device 140 is disposed on the side surface of the wafer 130 near the cover plate 110. The electronic device 140 is located in the cavity structure O. The wafer 130 includes a first through hole, and the first through hole is filled with a wiring layer 150.

[0065] Figure 4 The diagram shown is a flowchart illustrating a packaging method provided in another embodiment of this application. Figure 4 As shown, after providing the cover plate 110 and bonding the cover plate 110 to one side of the wafer 130 having the outer wall 120, the packaging method further includes the following steps:

[0066] In step S41, a passivation layer 181 is prepared on the side of the wiring layer 150 facing away from the cover plate 110, and a second via is formed within the passivation layer 181. The orthogonal projection of the wafer 130 onto the cover plate 110 lies within the orthogonal projection range of the passivation layer 181 onto the cover plate 110, and the orthogonal projection of the wiring layer 150 onto the cover plate 110 covers the orthogonal projection of the second via onto the cover plate 110.

[0067] Step S42: Prepare a bump 170 in the second through hole, so that the bump 170 fills and protrudes from the second through hole.

[0068] Figures 5a to 5g The image shown is of this application. Figure 1 The diagram shows the process structure of the packaging structure, combined with... Figure 3 , 4 The flowchart of the encapsulation method shown is as follows: Figures 5a to 5g Detailed description Figure 1 The packaging method corresponding to the packaging structure 100 shown.

[0069] like Figure 5a As shown in steps S31 to S33, a wafer 130 is first provided; then an electronic device 140 and at least two electrodes 160 are formed on one side of the wafer 130, and a plurality of outer walls 120 are fabricated on the same side; then a cover plate 110 is provided, and the cover plate 110 is bonded to the side of the wafer 130 with the outer walls 120, so that the cover plate 110, the outer walls 120 and the wafer 130 form a cavity structure O.

[0070] As described above, the outer wall 120 can be an insulating layer. In the preparation process of the outer wall 120, a complete insulating layer is first prepared, and then the insulating layer is exposed and developed to form an opening that exposes the electronic device 140 and the electrode 160, thus forming the outer wall 120.

[0071] In this embodiment, a vacuum molding process is used to bond the cover plate 110 to the wafer 130.

[0072] like Figure 5b As shown, using the cover plate 110 as a carrier plate, the back side of the wafer 130 with the outer wall 120 is thinned so that the thickness of the wafer 130 meets the preset thickness threshold condition.

[0073] During the thinning process, the back side of the wafer 130 with the outer wall 120 is first ground and cleaned so that the thickness of the wafer 130 meets the preset thickness threshold condition; then the residual stress on the back side of the wafer 130 in the previous step is removed by etching or chemical mechanical polishing.

[0074] In this embodiment, the cover plate 110 serves two purposes: firstly, it forms a closed cavity structure O to seal the electronic device 140 within it; secondly, it is reused as a carrier plate for thinning the wafer 130, thus eliminating the need for an additional carrier plate. Therefore, this embodiment simplifies the packaging process, saves packaging materials, and reduces production costs.

[0075] like Figure 5c As shown, the back side of wafer 130 with outer wall 120 is etched to form a first via. The first via exposes electrode 160, and the etching method can be deep reactive ion etching.

[0076] Furthermore, after etching, the wafers 130 originally stacked between adjacent outer walls 120 are etched away to facilitate the subsequent preparation of the passivation layer 181 and the cutting of the cover plate 110.

[0077] like Figure 5d As shown, a seed layer is deposited on the exposed electrode 160, and metal is formed sequentially through sputtering, coating, photolithography, development, electroplating, resist removal, and etching processes to fill the first via and extend the metal to the surface of the wafer 130 opposite to the cover plate 110, thereby forming a wiring layer 150. The seed layer can be made of titanium or copper.

[0078] like Figure 5e As shown in step S41, a passivation layer 181 is prepared on the side of the wiring layer 150 facing away from the cover plate 110, and a second via is formed within the passivation layer 181. The orthogonal projection of the wafer 130 onto the cover plate 110 lies within the orthogonal projection range of the passivation layer 181 onto the cover plate 110, and the orthogonal projection of the wiring layer 150 onto the cover plate 110 covers the orthogonal projection of the second via onto the cover plate 110.

[0079] Specifically, the passivation layer 181 can be made of polymer organic materials, such as PI adhesive, to protect the cover plate 110, the outer wall 120, the wafer 130 and the wiring layer 150 from water and oxygen corrosion in the external environment.

[0080] like Figure 5f As shown in step S42, a bump 170 is prepared in the second through hole, so that the bump 170 fills and protrudes from the second through hole.

[0081] like Figure 5g As shown in step S34, the cover plate 110 is cut into units of the outer wall 120 to obtain multiple encapsulation structures 100.

[0082] The packaging method provided in this application embodiment leads out the wiring layer 150 through the first through hole on the wafer 130, thereby ensuring the integrity of the cover plate 110. The complete cover plate 110, outer wall 120, wafer 130 and wiring layer 150 form a closed cavity structure O, making the electronic device 140 located in the cavity structure O less susceptible to contamination. Furthermore, the passivation layer 181 completely covers the outer wall 120, wafer 130 and wiring layer 150, thereby making the packaging structure 100 have good sealing performance, reliability and stability.

[0083] This application also provides another encapsulation method. Figure 6 The diagram shown is a flowchart illustrating a packaging method provided in another embodiment of this application. Figure 6 As shown, after providing the cover plate 110 and bonding the cover plate 110 to one side of the wafer 130 having the outer wall 120, the packaging method further includes the following steps:

[0084] In step S61, a passivation layer 181 is prepared on the side of the wiring layer 150 facing away from the cover plate 110, and a second via is formed in the passivation layer 181. The orthogonal projection of the passivation layer 181 onto the cover plate 110 coincides with the orthogonal projection of the wafer 130 onto the cover plate 110, and the orthogonal projection of the wiring layer 150 onto the cover plate 110 covers the orthogonal projection of the second via onto the cover plate 110.

[0085] Step S62: Prepare a bump 170 in the second through hole, so that the bump 170 fills and protrudes from the second through hole.

[0086] Figures 7a to 7e The image shown is of this application. Figure 2 The diagram shows the process structure of the packaging structure, combined with... Figure 3 , 6 The flowchart of the encapsulation method shown is as follows: Figures 7a to 7e Detailed description Figure 2 The packaging method corresponding to the packaging structure 100 shown.

[0087] like Figure 7a As shown in step S31, a wafer 130 is first provided; then one side of the wafer 130 is etched to form a blind via; then metal is electroplated into the blind via to fill it; then, as in step S32, an electronic device 140 and at least two electrodes 160 are formed on the same side of the wafer 130, and a plurality of outer walls 120 are fabricated on the same side; then, as in step S33, a cover plate 110 is provided, and the cover plate 110 is bonded to the side of the wafer 130 with the outer walls 120, so that the cover plate 110, the outer walls 120 and the wafer 130 form a cavity structure O.

[0088] like Figure 7bAs shown, using cover plate 110 as a carrier, the back side of wafer 130 with outer wall 120 is thinned to expose metal on the back side of wafer 130 with outer wall 120. Specifically, TSV back-side copper exposure process is used to thin wafer 130.

[0089] like Figure 7c As shown, on the back side of the wafer 130 with the outer wall 120, metal is formed sequentially through sputtering, coating, photolithography, development, electroplating, resist removal and etching processes, so that the metal exposed after thinning extends to the surface of the wafer 130 away from the cover plate 110, thereby forming a wiring layer 150.

[0090] like Figure 7d As shown in step S61, a passivation layer 181 is prepared on the side of the wiring layer 150 facing away from the cover plate 110, and a second via is formed in the passivation layer 181. The orthogonal projection of the passivation layer 181 onto the cover plate 110 coincides with the orthogonal projection of the wafer 130 onto the cover plate 110, and the orthogonal projection of the wiring layer 150 onto the cover plate 110 covers the orthogonal projection of the second via onto the cover plate 110.

[0091] Specifically, the passivation layer 181 can be made of polymer organic materials, such as PI adhesive, to protect the cover plate 110, the outer wall 120, the wafer 130 and the wiring layer 150 from water and oxygen corrosion in the external environment.

[0092] like Figure 7e As shown in step S62, a bump 170 is prepared in the second through hole, so that the bump 170 fills and protrudes from the second through hole. Then, as shown in step S34, the cover plate 110 is cut in units of the outer wall 120 to obtain multiple encapsulation structures 100.

[0093] The packaging method provided in this application embodiment leads out the wiring layer 150 through the first through hole on the wafer 130, thereby ensuring the integrity of the cover plate 110. Thus, the complete cover plate 110, outer wall 120, wafer 130 and wiring layer 150 form a closed cavity structure O, making the electronic device 140 located in the cavity structure O less susceptible to contamination. Furthermore, this application embodiment adopts a method of first forming blind vias and then bonding the cover plate 110 to the side of the wafer 130 with the outer wall 120. This method has a mature process route and is simple and easy to implement.

[0094] Both packaging methods described above involve first forming a closed cavity structure O using a complete cover plate 110, outer wall 120, wafer 130, and wiring layer 150, with the electronic device 140 located within this cavity structure O. Then, the cover plate 110 is cut to obtain multiple package structures 100. It is important to emphasize that both packaging methods enclose and protect the electronic device 140 before cutting the cover plate 110, thus preventing contamination of the electronic device 140 during the cutting process and improving the reliability of the package structure 100. Furthermore, both packaging methods are suitable for mass production with high production efficiency.

[0095] Understandably, in describing Figure 6 When describing the encapsulation method, only its relationship with... Figure 4 The different encapsulation methods shown Figure 6 The encapsulation method shown is the same as Figure 4 The similarities between the encapsulation methods shown will not be repeated here.

[0096] Figure 8 The diagram shown is a structural schematic of a radio frequency module provided in an embodiment of this application. Figure 8 As shown, one embodiment of this application provides a radio frequency module 10, including the packaging structure 100 mentioned in any of the above embodiments. Its technical principle and effects are similar, and will not be repeated here. Furthermore, the radio frequency module 10 may include at least two of the following devices: a radio frequency switch, a filter, a duplexer, and a power amplifier.

[0097] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0098] It should also be noted that in this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered equivalent solutions to this application. Although several exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A packaging structure, characterized in that, include: Cover plate; The outer wall is stacked on one side of the cover plate, and the orthographic projection of the outer wall on the cover plate is a closed annular area; A wafer is stacked on the side of the outer wall away from the cover plate. The cover plate, the outer wall, and the wafer form a cavity structure. Electronic devices are disposed on the surface of the wafer near the cover plate. The electronic devices are located within the cavity structure. The wafer includes a first through-hole. Wiring layer, filling the first via; An electrode is stacked on the side of the wafer closest to the cover plate, in contact with the wiring layer, and the electrode is located within the cavity structure; A passivation layer is stacked on the side of the wiring layer opposite to the cover plate, wherein the orthographic projection of the wafer on the cover plate is located within the orthographic projection range of the passivation layer on the cover plate, or the orthographic projection of the passivation layer on the cover plate coincides with the orthographic projection of the wafer on the cover plate. The edge of the wafer's orthographic projection onto the cover plate is located between the inner and outer edges of the annular region; The orthographic projection of the electrode on the cover plate covers the orthographic projection of the first through hole on the cover plate; The cover plate is made of glass; There is a gap between the electrode and the cover plate.

2. The packaging structure according to claim 1, characterized in that, The orthographic projection of the first through hole on the cover plate lies between the annular region and the orthographic projection of the electronic device on the cover plate.

3. The packaging structure according to claim 1, characterized in that, The orthographic projection of the electrode on the cover plate lies between the orthographic projection of the annular region and the orthographic projection of the electronic device on the cover plate.

4. The packaging structure according to claim 1, characterized in that, Also includes: The protrusions are stacked on the side of the wiring layer opposite to the cover plate and are in contact with the wiring layer.

5. The packaging structure according to claim 4, characterized in that, The wiring layer extends to the surface of the wafer opposite to the cover plate.

6. The packaging structure according to claim 4, characterized in that, The passivation layer includes a second via that exposes the bump.

7. The packaging structure according to claim 1, characterized in that, The orthographic projection of the outer wall onto the cover plate lies within the orthographic projection range of the passivation layer onto the cover plate.

8. A packaging method, characterized in that, include: Provide wafers; Electronic devices and at least two electrodes are formed on one side of the wafer, and multiple outer walls are fabricated on the same side, wherein the orthographic projection of the outer walls on the wafer is a closed annular region; A cover plate is provided and the cover plate is bonded to one side of the wafer having the outer wall, such that the cover plate, the outer wall and the wafer form a cavity structure; The cover plate is cut into units based on the outer wall to obtain multiple encapsulation structures; The electronic device is located within the cavity structure, and the wafer includes a first through-hole filled with a wiring layer. A passivation layer is prepared on the side of the wiring layer opposite to the cover plate, and a second via is formed in the passivation layer, wherein the orthographic projection of the wiring layer on the cover plate covers the orthographic projection of the second via on the cover plate, the orthographic projection of the wafer on the cover plate is located within the orthographic projection range of the passivation layer on the cover plate, or the orthographic projection of the passivation layer on the cover plate coincides with the orthographic projection of the wafer on the cover plate; A bump is prepared inside the second through hole, such that the bump fills and protrudes from the second through hole; The orthographic projection of the electrode on the cover plate covers the orthographic projection of the first through hole on the cover plate; The cover plate is made of glass; There is a gap between the electrode and the cover plate.

9. A radio frequency module, characterized in that, Includes the packaging structure as described in any one of claims 1 to 7 above.

Images