Programmable linear feedback shift register system and method

Abstract

Various techniques are provided to implement a programmable linear feedback shift register (LFSR) circuit. In one example, the LFSR circuit includes a state storage element. Each state storage element is configured to store a state signal. The LFSR circuit also includes a programmable logic level circuit, each of which is configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide an output signal. Each programmable logic level circuit is connected to at least one other programmable logic level circuit. The LFSR circuit also includes a pipeline element. Each pipeline element is configured to selectively connect at least two programmable logic level circuits. The LFSR circuit also includes a set of delay balancing elements. Related systems and methods are provided.

Description

Technical Field

[0001] The present invention relates generally to programmable logic devices, and more particularly to programmable linear feedback shift register systems and methods. Background Art

[0002] A programmable logic device (PLD) (e.g., a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a field programmable system on a chip (FPSC), or other types of programmable devices) can be configured with various user designs to implement desired functions. Typically, the user design is synthesized and mapped into configurable resources available in a particular PLD, which configurable resources include, as non-limiting examples, programmable logic gates, lookup tables (LUTs), embedded hardware, interconnects, and / or other types of resources. The physical layout and routing for the synthesized and mapped user design can then be determined to generate configuration data for the particular PLD. The generated configuration data is loaded into a configuration memory of the PLD to implement the programmable logic gates, LUTs, embedded hardware, interconnects, and / or other types of configurable resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A block diagram of a PLD according to an embodiment of the present disclosure is shown.

[0004] Figure 2 A block diagram showing logic blocks of a PLD according to an embodiment of the present disclosure is shown.

[0005] Figure 3 The design process of a PLD according to an embodiment of the present disclosure is shown.

[0006] Figure 4 A block diagram of a linear feedback shift register circuit having a type 1 topology according to an embodiment of the present disclosure is shown.

[0007] Figure 5 A block diagram of a linear feedback shift register circuit having a type 2 topology according to an embodiment of the present disclosure is shown.

[0008] Figure 6 A block diagram of an example output conversion logic circuit for converting from a type 1 LFSR output to a type 2 LFSR output according to an embodiment of the present disclosure is shown.

[0009] Figure 7 A block diagram of a linear feedback shift register circuit with pipeline elements and latency balancing elements according to an embodiment of the present disclosure is shown.

[0010] Figure 8A block diagram of a linear feedback shift register circuit with separate feedforward logic and feedback logic according to an embodiment of the present disclosure is shown.

[0011] Fig. 9 A block diagram of a linear feedback shift register circuit with pipeline elements and delay balancing elements according to an embodiment of the present disclosure is shown.

[0012] Fig.10 A block diagram of a linear feedback shift register circuit with separate feedforward logic and feedback logic according to an embodiment of the present disclosure is shown.

[0013] Fig.11 A block diagram of a linear feedback shift register circuit with pipeline elements and delay balancing elements according to an embodiment of the present disclosure is shown.

[0014] Fig.12 A block diagram of a linear feedback shift register circuit with separate feedforward logic and feedback logic according to an embodiment of the present disclosure is shown.

[0015] Fig.13 A flow chart of an example process for operating a linear feedback shift register according to an embodiment of the present disclosure is shown.

[0016] Fig.14 A block diagram of a three-tap series linear feedback shift register circuit with type 1 topology is shown.

[0017] Fig.15 A block diagram of a three-tap series linear feedback shift register circuit with type 2 topology is shown.

[0018] Fig.16 A block diagram of a three-tap series linear feedback shift register circuit with type 2 topology is shown.

[0019] Fig.17 A block diagram of a three-tap series linear feedback shift register circuit with type 1 topology is shown.

[0020] Fig.18 A block diagram of a three-tap series linear feedback shift register circuit with type 1 topology is shown.

[0021] Fig.19 A block diagram of a three-tap series linear feedback shift register circuit with type 2 topology is shown.

[0022] Embodiments of the present disclosure and their advantages may be best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements shown in one or more of the accompanying drawings. DETAILED DESCRIPTION

[0023] According to various embodiments set forth herein, techniques are provided for implementing a linear feedback shift register (LFSR) circuit arrangement within a configurable / programmable logic component, such as a component of a programmable logic device (PLD). For example, in some embodiments, a PLD includes a plurality of programmable logic blocks (PLBs), memory blocks, digital signal processing blocks, input / output blocks, and / or other components that can be interconnected in various ways to achieve a desired circuit design and / or functionality. A circuit design can be represented at least in part by a netlist that can describe the components in the design and the connections between the components. For example, a user design can be converted into and / or represented by a netlist that includes a set of PLD components (e.g., configured for logic, arithmetic, clocking, and / or other hardware functions) and associated interconnections available in the PLD. The netlist can be used to place components for the design and / or route connections (e.g., utilizing routing resources of the PLD) for a particular PLD (e.g., using a simulation of the desired circuit design constructed from the netlist). Typically, a PLD (e.g., FPGA) structure includes various routing structures and an array of similarly arranged logic cells arranged within programmable function blocks (e.g., PFBs and / or PLBs). The goal of designing a particular type of PLD is typically to maximize functionality while minimizing the area, power, and delay of the structure.

[0024] Although various embodiments are discussed and improvements are proposed herein with reference to the field of PLD utilization (e.g., including FPGAs), various embodiments discussed herein may be implemented in other types of hardware and / or software. As non-limiting examples, the LFSR / LFSR architecture described herein may be implemented using an application specific integrated circuit (ASIC), a system on a chip, a general purpose logic circuit, a processor (e.g., a configurable processor, a digital signal processor), generally any programmable resource of any programmable circuit or device, or any combination thereof. As an example, various embodiments may be used in a customized built-in register transfer level (RTL) logic that may be implemented in a general purpose integrated circuit (IC) and / or implemented as a dedicated block of its own type (e.g., as an independent resource in a programmable structure). When implemented in a PLD, in RTL logic for a custom IC, and / or otherwise, embodiments of the present design may achieve significant improvements in performance (e.g., timing performance) and space utilization. Therefore, embodiments of the present disclosure should not be considered to be generally limited to PLD implementations.

[0025] LFSR circuits can be used in a variety of applications, such as applications in communication systems. In some aspects, LFSR circuits can be used to facilitate high-speed operation, such as in the gigahertz range. As non-limiting examples, LFSR circuits can be used for pseudo-random number generation / checking (e.g., pseudo-random binary sequence (PRBS) generation / checking), scrambling / descrambling, and error detection (e.g., checksum calculations for cyclic redundancy checks (CRCs), forward error correction (FEC), etc.).

[0026] LFSR circuits can be characterized using LFSR architecture / topology types, generator polynomials (e.g., also referred to as characteristic polynomials or feedback polynomials), and / or data input polynomials. In an embodiment, the LFSR circuit may have a type 1 architecture or a type 2 architecture. In a type 1 architecture, combinational logic may be provided outside the path formed by the state storage element. In one aspect, the type 1 architecture may be referred to as an external logic LFSR architecture or a Fibonacci architecture. In a type 2 architecture, combinational logic may be provided consistent with the path formed by the state storage element. In one aspect, the type 2 architecture may be referred to as an internal logic LFSR architecture or a Galois architecture.

[0027] In some embodiments, the LFSR circuit includes a state storage element (e.g., also referred to as a register), a programmable multiplier, a programmable combiner, and associated programmable routing resources, which are used to selectively connect the state storage element, the programmable multiplier, and / or the programmable combiner. In one aspect, such a LFSR circuit can be referred to as a programmable LFSR circuit (e.g., in contrast to a fixed LFSR circuit). Each programmable multiplier, each programmable combiner, and associated programmable routing resources can be selectively programmed (e.g., selectively enabled or disabled) depending on the combinational logic (e.g., application) to be implemented using the LFSR circuit. For a given LFSR circuit, each state storage element can be a memory cell for storing (e.g., buffering) a state signal of the LFSR circuit. Each state signal can be one bit. In some cases, the current state of the LFSR circuit can be indicated by a state signal stored in the state storage element of the LFSR circuit. As a non-limiting example, each state storage element can be implemented by a flip-flop (e.g., a D-type flip-flop). In some cases, each combiner can implement a bitwise operation, such as an exclusive or (XOR) operation or an exclusive or not (XNOR) operation.

[0028] In some embodiments, a programmable multi-mode LFSR circuit allows the LFSR architecture type, generator polynomial, and / or data input polynomial to be programmable (e.g., on the fly) based on the desired application. A particular application may be deemed more suitable for implementation using a type 1 architecture or a type 2 architecture (e.g., type 1 for PRBS and self-synchronizing scramblers, type 2 for CRC and FEC, etc.). In some aspects, as an alternative or in addition to allowing the LFSR architecture type to be programmable, a programmable LFSR circuit having a type 1 LFSR architecture and a programmable output conversion logic circuit may be programmed and connected to each other such that the programmable output conversion logic circuit receives a type 1 output from the LFSR circuit and converts the type 1 output to a type 2 output. In some cases, such a conversion may be performed rather than implementing a type 2 LFSR circuit to directly generate a type 2 output because, in various cases, a type 1 LFSR circuit may be associated with a smaller chip area (e.g., smaller utilization of standard cell area and / or fewer components) and / or better timing performance than a corresponding type 2 LFSR circuit. In this regard, in this case, through this conversion, a Type 1 LFSR architecture can be implemented to take advantage of its use of smaller area (e.g., fewer components) and better timing performance while providing a Type 2 LFSR output where appropriate for a given application. For example, the equivalence between various aspects of the Type 1 LFSR architecture and the Type 2 LFSR architecture is as follows: Figures 14 to 19 is described.

[0029] In some embodiments, the programmable LFSR circuit can allow programming of parallel implementations, wherein the LFSR circuit can provide multiple outputs per time unit (e.g., clock cycle), thus facilitating higher data rates. As an example, in some cases, the parallel programmable LFSR circuit architecture can allow data rates of tens or hundreds of gigabits per second as needed. Thus, the parallel implementation can facilitate meeting the desired throughput. In some cases, parallelization can achieve high data rates while using standard cells that are typically associated with lower clock rates, compared to high-speed serial architectures that typically require components that can operate at higher clock rates.

[0030] In some aspects, in order to allow timing closure of the LFSR circuit with parallelization, a pipeline stage can be provided. By adding a pipeline stage, delay balancing can be applied to the input and / or output of the LFSR circuit, so that inputs for processing can be received and outputs can be provided in desired time units (e.g., clock cycles). The pipeline stage can be considered to separate / split the sequential combination paths of the LFSR circuit into a set of combinational stages. Each set of combinational stages can be associated with a corresponding delay balancing circuit device. In some cases, such pipeline stages and delay balancing can be implemented using storage elements such as flip-flops to provide appropriate signal buffering.

[0031] In some aspects, a given LFSR circuit can be split into a feedforward logic portion without a feedback loop, and a feedback logic portion. The feedforward logic portion can implement the calculation of the output of the LFSR circuit. The feedback logic portion can implement matrix multiplication associated with the state transition of the LFSR circuit. Pipeline stages (and associated delay balance) can be provided in the feedforward logic portion to allow timing closure. The throughput reduction associated with pipeline stages can be avoided by taking the feedback logic out of the pipeline path.

[0032] In some embodiments, programmable multimode LFSR circuits can be provided as independent resources in a programmable structure. With such resources, subsystems requiring LFSR functions can be built using dedicated circuit devices rather than general logic to facilitate higher operating speeds and lower power consumption. Programmable LFSR circuits can be used in high-speed communications and selectively adjusted through their programmability to achieve higher performance and bandwidth as needed, such as to adapt to emerging standards and / or evolving customer needs. Various embodiments can provide programmable LFSR circuits for applications (e.g., real-time applications) or simulations at higher speeds and allow operation at data rates specified for, for example, 10G Ethernet, 25G Ethernet, etc.

[0033] Such multimode LFSR circuits can provide support for a variety of existing and emerging standards, designs and applications as needed. In one case, programmable LFSR circuits can be advantageous for multi-protocol serializers / deserializers (SERDES). In this regard, LFSR circuits can be used to support various standards (e.g., SERDES) for serial data communications, such as IEEE802.3, PCIe, and JESD204C, which specify fixed LFSR circuits for specific applications. This programmability / flexibility can allow less stringent / more general LFSR specifications and / or their extensions in the standard for high-speed communications to be described. For example, users of the standard can develop more efficient error correction capabilities for a given communication channel, based on the optimal spectrum signal characteristics of a specific scrambler, etc.

[0034] Now referring to the accompanying drawings, Figure 1A block diagram of a PLD 100 according to an embodiment of the present disclosure is shown. In various embodiments, the PLD 100 may be implemented as, for example, a stand-alone device, or may be embedded within a system on a chip (SOC), other logic devices, and / or (multiple) other integrated circuits. The PLD 100 (e.g., a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a field programmable system on a chip (FPSC), or other types of programmable devices) generally includes an input / output (I / O) block 102 and a logic block 104 (e.g., also referred to as a programmable logic block (PLB), a programmable function unit (PFU), or a programmable logic unit (PLC)). In some cases, the PLD 100 may generally be any type of programmable device (e.g., a programmable integrated circuit) with a distributed configuration, which may involve loading configuration data through pins, transferring to appropriate locations in a related structure, and configuring configuration memory cells. The PLBs may also be referred to as logic blocks, programmable function units (PFUs), or programmable logic units (PLCs). In one aspect, the PLBs 104 may collectively form an integrated circuit (IC) core or a logic core of the PLD 100. I / O block 102 provides I / O functionality (e.g., supports one or more I / O and / or memory interface standards) for PLD 100, while PLB 104 provides logic functionality (e.g., LUT-based logic) for PLD 100. Additional I / O functionality may be provided by serializer / deserializer (SERDES) block 150 and physical coding sublayer (PCS) block 152. PLD 100 may also include hard intellectual property core (IP) block 160 to provide additional functionality (e.g., substantially predetermined functionality provided in hardware that may be configured with less programming than PLB 104).

[0035] PLD 100 may suitably include memory blocks 106 (e.g., blocks of erasable programmable read-only memory (EEPROM), block static RAM (SRAM), and / or flash memory), clock-related circuitry 108 (e.g., clock sources, phase-locked loop (PLL) circuits, delay-locked loop (DLL) circuits, and / or feeder interconnects), and / or various routing resources 180 (e.g., interconnects and appropriate switching circuits to provide paths for routing signals throughout PLD 100, such as for clock signals, data signals, control signals, etc.). In general, the various elements of PLD 100 may be used to perform their intended functions for a desired application, as will be appreciated by those skilled in the art.

[0036] For example, certain ones of I / O blocks 102 may be used to program memory 106 or to transfer information (e.g., various types of user data and / or control signals) to / from PLD 100. Other ones of I / O blocks 102 include a first programming port (which may represent a central processing unit (CPU) port, a peripheral data port, a serial peripheral interface (SPI) interface, and / or a sysCONFIG programming port) and / or a second programming port, such as a Joint Test Action Group (JTAG) port (e.g., by adopting a standard such as the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 or 1532 standards). In various embodiments, I / O block 102 may be included to receive configuration data and commands (e.g., via one or more connections) to configure PLD 100 for its intended use, and to appropriately support serial or parallel device configuration and information transfer with SERDES block 150, PCS block 152, hard IP block 160, and / or PLB 104. In another example, routing resources 180 may be used to route connections between components, such as connections between I / O nodes of logic block 104. In some embodiments, such routing resources may include programmable elements (e.g., nodes where multiple routing resources intersect) that may be used to selectively form signal paths for specific connections between components of PLD 100.

[0037] It should be understood that the number and location of the various elements are not limiting and may depend on the desired application. For example, various elements may not be required for the desired application or design specification (e.g., for the type of programmable device selected). In addition, it should be understood that for clarity, these elements are shown in block form, and the various elements will generally be distributed throughout the PLD 100, such as in and between the PLBs 104, the hard IP blocks 160, and the routing resources 180 to perform their conventional functions (e.g., storing configuration data that configures the PLD 100 or providing interconnect structures within the PLD 100). For example, the routing resources 180 may be used for internal connections within each PLB 104 and / or between different PLBs 104. It should also be understood that the various embodiments disclosed herein are not limited to programmable logic devices, such as the PLD 100, but may be applied to various other types of programmable devices, as understood by those skilled in the art.

[0038] External system 130 may be used to create a desired user configuration or design for PLD 100, and to generate corresponding configuration data to program (e.g., configure) PLD 100. For example, to configure PLD 100, system 130 may provide such configuration data to one or more of I / O block 102, PLB 104, SERDES block 150, and / or other portions of PLD 100. In this regard, external system 130 may include link 140 that connects to a programming port (e.g., SPI, JTAG) of PLD 100 to facilitate the transfer of configuration data from external system 130 to PLD 100. As a result, I / O block 102, PLB 104, various routing resources 180, and any other appropriate components of PLD 100 may be configured to operate according to a user-specified application.

[0039] In the illustrated embodiment, the system 130 is implemented as a computer system. In this regard, the system 130 includes, for example, one or more processors 132, which may be configured to execute instructions, such as software instructions, provided in one or more memories 134 and / or stored in a non-transitory form in one or more non-transitory machine-readable media 136 (e.g., the media may be internal or external to the system 130). For example, in some embodiments, the system 130 may run PLD configuration software, such as Lattice Diamond systemPlanner software available from Lattice Semiconductor Corporation, to allow a user to create a desired configuration and generate corresponding configuration data to program the PLD 100. In this regard, in some cases, the system 130 and / or other external / remote systems may be used to factory program or remotely program (e.g., remotely update) one or more PLDs, such as the PLD 100 (e.g., over a network).

[0040] Alternatively or additionally, the configuration data may be stored on PLD 100 (e.g., in a memory located within PLD 100) and / or on a separate / discrete memory of a system including PLD 100 and the separate / discrete memory (e.g., a system in which PLD 100 operates). In some embodiments, memory 106 of PLD 100 may include non-volatile memory (e.g., flash memory) that is used to store configuration data generated and provided to memory 106 by external system 130. During configuration of PLD 100, non-volatile memory may provide configuration data via configuration paths and associated data lines to configure various portions of PLD 100 (e.g., I / O blocks 102, PLBs 104, SERDES blocks 150, routing resources 180, and / or other portions). In some cases, the configuration data may be stored in a non-volatile memory external to PLD 100 (e.g., on an external hard drive such as memory 134 in system 130). During configuration, configuration data may be provided (eg, loaded) into PLD 100 from external non-volatile memory to configure PLD 100 .

[0041] For example, system 130 also includes a user interface 135 (e.g., a screen or display) for displaying information to a user, and one or more user input devices 137 (e.g., a keyboard, mouse, trackball, touch screen, and / or other devices) for receiving user commands or design inputs to prepare a desired configuration of PLD 100. In some embodiments, for example, user interface 135 may be adapted to display a netlist, component placement, connection routing, hardware description language (HDL) code, and / or other final and / or intermediate representations of a desired circuit design.

[0042] Figure 2 1 shows a block diagram of a logic block 104 of a PLD 100 according to an embodiment of the present disclosure. As discussed, the PLD 100 includes a plurality of logic blocks 104, which include various components for providing logic and arithmetic functions. Figure 2In the example embodiment shown, logic block 104 includes a plurality of logic cells 200 that may be interconnected internally within logic block 104 and / or externally using routing resources 180. For example, each logic cell 200 may include various components such as a lookup table (LUT) 202, mode logic circuitry 204, registers 206 (e.g., flip-flops or latches), and various programmable multiplexers (e.g., programmable multiplexers 212 and 214) to select desired signal paths for and / or between logic cells 200. In this example, LUT 202 accepts four inputs 220A-220D, making it a four-input LUT (which may be abbreviated as "4-LUT" or "LUT4") that may be programmed via configuration data for PLD 100 to implement any suitable logic operation with four or fewer inputs. Mode logic 204 may include various logic elements and / or additional inputs, such as input 220E, to support functionality for various modes of logic unit 200 (e.g., including various processing and / or functional modes). In other examples, LUT 202 may be any other suitable size with any other suitable number of inputs for a particular implementation of a PLD. In some embodiments, LUTs of different sizes may be provided for different logic blocks 104 and / or different logic units 200.

[0043] In some embodiments, output signal 222 from LUT 202 and / or mode logic 204 may be passed through register 206 to provide output signal 233 of logic cell 200. In various embodiments, output signal 223 from LUT 202 and / or mode logic 204 may be passed directly to output 223, as shown. Depending on the configuration of multiplexers 210-214 and / or mode logic 204, output signal 222 may be temporarily stored (e.g., latched) in register 206 according to control signal 230. In some embodiments, configuration data for PLD 100 may configure output 223 and / or 233 of logic cell 200 to be provided as one or more inputs of another logic cell 200 (e.g., in another logic block or the same logic block) in a hierarchical or cascade arrangement (e.g., including multiple levels) to configure logic and / or other operations that cannot be implemented in a single logic cell 200 (e.g., operations that have too many inputs to be implemented by a single LUT 202). Furthermore, logic unit 200 may be implemented with multiple outputs and / or interconnects to facilitate selectable modes of operation.

[0044] Mode logic circuit 204 may be used in some configurations of PLD 100 to efficiently implement arithmetic operations such as adders, subtractors, comparators, counters, or other operations, to efficiently form some extended logic operations (e.g., higher order LUTs operating on multi-bit data), to efficiently implement relatively small RAMs, and / or to allow selection between logic, arithmetic, extended logic, and / or other selectable modes of operation. In this regard, mode logic circuits 204 across multiple logic cells 202 may be linked together to pass carry signals 205 and carry signals 207, and / or other signals (e.g., output signals 222) between adjacent logic cells 202. Figure 2 In the example of , carry signal 205 may be passed directly to mode logic circuit 204, for example, or may be passed to mode circuit 204 by configuring one or more programmable multiplexers. In some cases, mode logic circuit 204 may be linked across multiple logic blocks 104.

[0045] Figure 2 The illustrated logic unit 200 is merely an example, and the logic unit 200 according to different embodiments may include different combinations and arrangements of PLD components. Figure 2 Logic block 104 is shown with eight logic cells 200, but logic block 102 according to other embodiments may include fewer logic cells 200 or more logic cells 200. Each logic cell 200 of logic block 104 may be used to implement a portion of a user design implemented by PLD 100. In this regard, PLD 100 may include many logic blocks 104, each of which may include logic cells 200 and / or other components that are used to collectively implement a user design.

[0046] Figure 3 FIG. 3 shows a design process 300 for a PLD according to an embodiment of the present disclosure. For example, Figure 3 The process may be performed by system 130 running Lattice Diamond software to configure PLD 100. In some embodiments, Figure 3 The various files and information referenced in may be stored, for example, in one or more databases and / or other data structures in memory 134, machine-readable media 136, and / or other storage devices.

[0047] In operation 310, system 130 receives a user design that specifies desired functionality for PLD 100. For example, a user may interact with system 130 (e.g., via user input device 137 and hardware description language (HDL) code representing the design) to identify various features of the user design (e.g., high-level logic operations, hardware configurations, I / O and / or SERDES operations, and / or other features). In some embodiments, the user design may be provided in an RTL description (e.g., a gate-level description). System 130 may perform one or more rule checks to confirm that the user design describes a valid configuration of PLD 100. For example, system 130 may appropriately reject invalid configurations and / or request that the user provide new design information.

[0048] In operation 320, system 130 synthesizes the design to create a netlist (e.g., a synthesized RTL description) that identifies an abstract logic implementation of the user design as a plurality of logic components (e.g., also referred to as a netlist component). In some embodiments, the netlist may be stored in a local general purpose database (NGD) file in an electronic design interchange format (EDIF).

[0049] In some embodiments, synthesizing the design into a netlist in operation 320 may involve converting (e.g., translating) a high-level description of logic operations, hardware configurations, and / or other features in the user design into a set of PLD components (e.g., logic blocks 104, logic cells 200, and other components of PLD 100 that are configured to implement the logic, arithmetic, or other hardware functions of the user design) and their associated interconnections or signals. Depending on the embodiment, the converted user design may be represented as a netlist.

[0050] In some embodiments, synthesizing the design into a netlist in operation 320 may also involve performing an optimization process on the user design (e.g., the user design converted / translated into a set of PLD components and their associated interconnections or signals) to reduce propagation delays, consumption of PLD resources and routing resources, and / or otherwise optimize the performance of the PLD when the PLD is configured to implement the user design. In some cases, the combinational logic associated with the LFSR circuit device may be optimized to reduce the number of components (e.g., multipliers, combiners), remove redundant components / computations, etc. During the optimization process, the combinational paths of the LFSR circuit device may be traversed at a desired clock speed. Depending on the embodiment, the optimization process may be performed on a netlist representing the converted / translated user design. Depending on the embodiment, the optimization process may represent the optimized user design in a netlist (e.g., to produce an optimized netlist).

[0051] In some embodiments, the optimization process may include optimizing routing connections identified in the user design. For example, the optimization process may include detecting connections with timing errors in the user design, and swapping and / or adjusting PLD resources that implement invalid connections and / or other connections to reduce the number of PLD components and / or routing resources used to implement the connections, and / or to reduce propagation delays associated with the connections. In some cases, routing distances may be determined based on timing.

[0052] In operation 330, system 130 performs a mapping process that identifies components of PLD 100 that can be used to implement the user design. In this regard, system 130 may map the optimized netlist (e.g., stored in operation 320 as a result of the optimization process) to various types of components (e.g., logic blocks 104, logic cells 200, embedded hardware, and / or other portions of PLD 100) provided by PLD 100 and their associated signals (e.g., in a logical manner, but without having yet to specify placement or routing). In some embodiments, the mapping may be performed on one or more previously stored NGD files, with the mapping results being stored as physical design files (e.g., also referred to as NCD files). In some embodiments, the mapping process may be performed as part of the synthesis process in operation 320 to produce a netlist that is mapped to the PLD components.

[0053] In operation 340, system 130 performs a placement process to assign the mapped netlist components to specific physical components residing at specific physical locations of PLD 100 (e.g., to specific logic cells 200, logic blocks 104, clock-related circuitry 108, routing resources 180, and / or other physical components of PLD 100), and thereby determine the layout of PLD 100. In some embodiments, placement may be performed in memory on data retrieved from one or more previously stored NCD files and / or on one or more previously stored NCD files, with the placement results stored as another physical design file (e.g., in memory 134 and / or machine-readable medium 136).

[0054] In operation 350, system 130 performs a routing process to route connections between components of PLD 100 based on the placement layout determined in operation 340 (e.g., using routing resources 180), thereby implementing physical interconnections between the placed components. In some embodiments, routing may be performed in memory on data retrieved from one or more previously stored NCD files and / or on one or more previously stored NCD files, where the routing results are stored as another physical design file (e.g., in memory 134 and / or machine-readable medium 136).

[0055] In various embodiments, routing the connections in operation 350 may also involve performing an optimization process on the user design to reduce propagation delays, consumption of PLD resources and / or routing resources, and / or otherwise optimize performance of the PLD when the PLD is configured to implement the user design. In some embodiments, the optimization process may be performed on a physical design file representing the converted / translated user design, and the optimization process may represent the optimized user design in the physical design file (e.g., to produce an optimized physical design file).

[0056] Changes to routing may be propagated back to previous operations, such as synthesis, mapping, and / or placement, to further optimize various aspects of the user's design.

[0057] Thus, after operation 350, one or more physical design files may be provided that specify the user design after it has been synthesized (e.g., translated and optimized), mapped, placed, and routed (e.g., further optimized) for PLD 100 (e.g., by combining the results of corresponding previous operations). In operation 360, system 130 generates configuration data for the synthesized, mapped, placed, and routed user design. In operation 370, system 130 configures / programs PLD 100 with the configuration data by, for example, loading a configuration data bitstream into PLD 100 via connection 140.

[0058] Figure 4 FIG. 4 is a block diagram of an LFSR circuit 400 according to an embodiment of the present disclosure. In one embodiment, the LFSR circuit 400 provides a parallel implementation of a serial LFSR circuit, such as Fig.14 The example three-tap serial LFSR described above is shown in FIG. 4. Such a parallel implementation can be obtained by expanding and replicating the logic of the serial LFSR representation. In this regard, the LFSR circuit 400 provides a parallel 4-bit LFSR circuit that provides four output signals y for each time unit (e.g., each clock cycle). type1 (n), y type1 (n+1), y type1 (n+2) and y type1 (n+3). Such an output signal may be referred to as a primary output of the LFSR circuit 400. The output signal may be provided to a downstream system or subsystem depending on the application. For example, if the LFSR circuit 400 is programmed to implement a pseudo-random sequence generator, each of the output signals may be a bit of the pseudo-random sequence and provided (e.g., sent) to a security-related key generator that generates a key based on the pseudo-random sequence.

[0059] LFSR circuit 400 includes state storage elements 405, 410 and 415 and programmable logic stage circuits 420A-D (e.g., also referred to as programmable combinational logic stage circuits). Each state storage element may be a memory cell for storing (e.g., buffering) a state signal of LFSR circuit 400. As a non-limiting example, each state storage element may be implemented by a flip-flop (e.g., a D-type flip-flop). Programmable logic stage circuit 420A includes programmable multipliers 425A-C (also referred to as multipliers) and programmable combiners 430A-C (also referred to as combiners). In one aspect, programmable multipliers may be referred to as programmable taps. Programmable logic stage circuit 420B includes programmable multipliers 435A-C and programmable combiners 440A-C. Programmable logic stage circuit 420C includes programmable multipliers 445A-C and programmable combiners 450A-C. Programmable logic stage circuit 420D includes programmable multipliers 455A-C and programmable combiners 460A-C. Combiners 430A-C, 440A-C, 450A-C, and 460A-C may be collectively referred to as combiner circuits of programmable logic level circuits 420A, 420B, 420C, and 420D, respectively. In some cases, each combiner may implement a bitwise operation, such as an XOR operation or an XNOR operation.

[0060] Each programmable multiplier, each programmable combiner, and the associated programmable routing between the programmable multipliers, programmable combiners and storage elements 405, 410, and 415 can be selectively programmed (e.g., selectively enabled or disabled) depending on the application to be implemented by the LFSR 400 circuit. In some cases, the application to be implemented by the LFSR circuit 400 can be characterized by a generator polynomial. Multipliers 425A, 435A, 445A, and 455A can be enabled by setting coefficient c0 to a non-zero value and disabled by setting coefficient c0 to zero. Multipliers 425B, 435B, 445B, and 455B can be enabled by setting coefficient c1 to a non-zero value and disabled by setting coefficient c1 to zero. Multipliers 425C, 435C, 445C, and 455C can be enabled by setting coefficient c2 to a non-zero value and disabled by setting coefficient c2 to zero. In one aspect, coefficients c0, c1, and c2 may be binary coefficients having a value of 1 for enabling and a value of 0 for disabling.Programmable routing resources may also be enabled or disabled based on the values ​​of corresponding coefficients c0, c1, and c2.

[0061] As an example, if coefficient c1 is zero and coefficients c0 and c2 are non-zero, programmable routing resources from storage element 405 to multiplier 435B, from multiplier 435B to combiner 440C, from storage element 410 to multiplier 425B, from multiplier 425B to combiner 430C, from combiner 430A to multiplier 445B, from multiplier 445B to combiner 450C, etc. may be disabled. In this example, multipliers 425C, 435C, 445C, and 455C may be routed directly to combiners 430B, 440B, 450B, and 460B, respectively, because combiners 430C, 440C, 450C, and 460C are disabled, respectively. Other programmable routing resources may be enabled or disabled appropriately based on coefficient c1 being zero and coefficients c0 and c2 being non-zero.

[0062] Each state storage element in state storage elements 405, 410 and 415 has an input terminal and an output terminal. The output terminal of state storage element 405 is selectively connected to programmable logic gate circuit 420A (e.g., via multiplier 425A), 420B (e.g., via multiplier 425B) and 420C (e.g., via multiplier 425C). The output terminal of storage element 410 is selectively connected to programmable logic gate circuit 420A (e.g., at multiplier 425B) and 420B (e.g., at multiplier 435C). The output terminal of state storage element 415 is selectively connected to programmable logic gate circuit 420A (e.g., at multiplier 425C). The input terminal of storage element 405 is selectively connected to programmable logic gate circuit 420D (e.g., at combiner 460A). The input terminal of storage element 410 is selectively connected to programmable logic gate circuit 420C (e.g., at combiner 450A). The input terminal of the storage element 415 is selectively connected to the programmable logic gate circuit 420B (e.g., via the combiner 440A). In this regard, the feedback path / loop of the parallel LFSR 400 can be selectively programmed so that the input terminals of the storage elements 405, 410 and 415 selectively receive feedback signals from the programmable logic gate circuits 420B, 420C and 420D. The state storage elements 405, 410 and 415 receive the state signals f0(n+4), f1(n+4) and f2(n+4) respectively via the corresponding feedback paths.

[0063] For the programmable logic gate circuit 420A, multipliers 425A, 425B and 425C are selectively connected to the state storage elements 405, 410 and 415, respectively. Multiplier 425A is selectively connected to combiner 430B. Each of multipliers 425B and multiplier 425C is selectively connected to combiner 430C. Combiner 430B is selectively connected to combiner 430A. Combiner 430A is selectively connected to the programmable input terminal of the programmable logic gate circuit 420A to selectively receive the input signal x(n). Note that for some applications (e.g., such as when the LFSR circuit 400 is used to implement a pseudo-random bit sequence), the input signal x(n) may be optional or may not exist. Multipliers 425A, 425B and 425C selectively receive state signals f0(n), f1(n) and f2(n). Combiner 430C selectively receives c2f2(n) and c1f1(n) as inputs and generates / provides outputs based on these inputs. Combiner 430B selectively receives c0f0(n) and the output of combiner 430C as inputs and generates / provides outputs based on these inputs. Combiner 430A generates and provides output signal y based on input signal x(n) and the output of combiner 430B. type1 (n).

[0064] For the programmable logic gate circuit 420B, the multiplier 435A is selectively connected to the combiner 430A of the programmable logic stage circuit 420A, the multiplier 435B is selectively connected to the state storage element 405, and the multiplier 435C is selectively connected to the state storage element 410. The multiplier 435A is selectively connected to the combiner 440B. Each of the multipliers 435B and the multiplier 435C is selectively connected to the combiner 440C. The combiner 440C is selectively connected to the combiner 440B. The combiner 440B is selectively connected to the combiner 440A. The combiner 440A is selectively connected to the programmable input terminal of the programmable logic gate circuit 420B to selectively receive the input signal x(n+1). The multipliers 435A, 435B and 435C selectively receive the state signals f0(n+1), f1(n+1) and f2(n+1). Combiner 440C selectively receives c2f2(n+1) and c1f1(n+1) as inputs and generates / provides outputs based on these inputs. Combiner 440B selectively receives c0f0(n+1) and the output of combiner 440C as inputs and generates / provides outputs based on these inputs. Combiner 440A generates and provides output signal y based on input signal x(n+1) and the output of combiner 440B. type1 (n+1).

[0065] For programmable logic gate circuit 420C, multiplier 445A is selectively connected to combiner 440A of programmable logic stage circuit 420B, multiplier 445B is selectively connected to combiner 430A of programmable logic stage circuit 420A, and multiplier 445C is selectively connected to state storage element 405. Multiplier 445A is selectively connected to combiner 450B. Each of multipliers 445B and multiplier 445C is selectively connected to combiner 450C. Combiner 450C is selectively connected to combiner 450B. Combiner 450B is selectively connected to combiner 450A. Combiner 450A is selectively connected to a programmable input terminal of programmable logic gate circuit 420C to selectively receive input signal x(n+2). Multipliers 445A, 445B, and 445C selectively receive state signals f0(n+2), f1(n+2), and f2(n+2). Combiner 450C selectively receives c2f2(n+2) and c1f1(n+2) as inputs and generates / provides outputs based on these inputs. Combiner 450B selectively receives c 0f0 Combiner 450A generates and provides an output signal y based on the input signal x(n+2) and the output of combiner 450B. type1 (n+2).

[0066] For programmable logic gate circuit 420D, multiplier 455A is selectively connected to combiner 450A of programmable logic stage circuit 420C, multiplier 455B is selectively connected to combiner 440A of programmable logic stage circuit 420B, and multiplier 455C is selectively connected to combiner 430A of programmable logic stage circuit 420A. Multiplier 455A is selectively connected to combiner 460B. Each of multipliers 455B and multiplier 455C is selectively connected to combiner 460C. Combiner 460B is selectively connected to combiner 460A. Combiner 460A is selectively connected to a programmable input terminal of programmable logic gate circuit 420D to selectively receive input signal x(n+3). Multipliers 455A, 455B, and 455C selectively receive state signals f0(n+3), f1(n+3), and f2(n+3). Combiner 460C selectively receives c2f2(n+3) and c1f1(n+3) as inputs and generates / provides outputs based on these inputs. Combiner 460B selectively receives c0f0(n+3) and the output of combiner 460C as inputs and generates / provides outputs based on these inputs. Combiner 460A generates and provides output signal y based on input signal x(n+3) and the output of combiner 460B.type1 (n+3).

[0067] The state vector (e.g., also referred to as a current state vector) associated with the i-th programmable logic gate circuit (for 0≤i≤3) (where programmable logic gate circuit 420A is designated as the 0th programmable logic gate circuit, programmable logic gate circuit 420B is designated as the first programmable logic gate circuit, and so on) may be provided as:

[0068]

[0069] It can also be expressed as [f0(n+i) f1(n+i) f2(n+i)] T =[f0 f1 f2] T (n+i).

[0070] The next state vector associated with the i-th programmable logic gate circuit may be provided as:

[0071]

[0072] in is the input vector, and is the next-state matrix (eg, also called a state transition matrix).

[0073] The output equation associated with the programmable logic gate circuit 420A (eg, also referred to as the main output equation) is provided by the following equation:

[0074]

[0075] In this regard, the LFSR circuit 400 can be characterized by its next state vector (e.g., next state formula group) and its output formula. The next state vector and output formula describe the state and main output of the LFSR circuit 400 after the operation (e.g., shift operation) of the function of the current state vector, the input vector and the next state matrix. The next state matrix has only one non-trivial row, which represents the generator polynomial of the LFSR circuit 400. The other positions of the state transfer matrix are filled with 1 on the diagonal and filled with 0 in other places. In other words, the state transfer matrix is ​​a sparse matrix.

[0076] The LFSR circuit 400 (which provides a parallel implementation equivalent to a four-bit shift operation) includes appropriate hardware (e.g., multipliers, combiners, and associated routing) to multiply the state transfer matrix by itself four times. The matrix obtained by multiplying the state transfer matrix (e.g., a sparse state transfer matrix) by itself multiple times generally becomes filled and no longer sparse. Through parallel implementation, the LFSR circuit 400 does not program the 4×4 coefficients of the matrix obtained by multiplying the state transfer matrix by itself four times (e.g., for a serial LFSR circuit implementation), but instead implements the matrix multiplication by programming only a generator polynomial with four coefficients, thereby reducing programming complexity (e.g., relative to the case of a serial LFSR circuit). More generally, for a parallel implementation equivalent to an N-bit shift operation, the next state matrix is ​​multiplied by itself N times. Through parallel implementation, the parallel LFSR architecture can implement the matrix multiplication by programming only a generator polynomial with N coefficients, thereby reducing programming complexity, rather than programming the N×N coefficients of the matrix obtained by multiplying the state transfer matrix by itself N times.

[0077] Notice, Figure 4 (and subsequent figures) illustrate a non-limiting example of a programmable routing resource for selectively connecting various components (e.g., state storage elements, multipliers, combiners). In this regard, various arrows represent the programmable routing resource and the direction of associated data flow (e.g., one bit of data flow). As an example, although in Figure 4 In FIG. 4 , combiner 440A is shown as being selectively connected to multipliers 445A and 455B via partially overlapping programmed routing resources, but the overlap in programmed routing resources may be different than Figure 4 440A to multiplier 445A, or the programmable routing resources for selectively routing combiner 440A to multiplier 455A do not overlap (e.g., are completely separate) with the programmable routing resources for selectively routing combiner 440A to multiplier 455B. Figure 4 LFSR circuit 400 is shown for four bits, but LFSR circuits associated with more or less than four bits may be implemented. For example, LFSR circuit 400 may be part of a larger programmable structure that has been specifically programmed to implement LFSR circuit 400.

[0078] Figure 5 1 shows a block diagram of an LFSR circuit 500 having a type 2 architecture. The LFSR circuit 500 may provide a parallel implementation of a serial type 2 LFSR circuit, such as Fig.15 An example three-tap serial LFSR circuit is described. Figure 5 As shown, the straightforward implementation / programming of a Type 2 LFSR architecture is generally similar to that of a Type 1 LFSR architecture (such as Figure 41 and 2. The LFSR circuit 500 has a higher complexity than the related implementation / programming of the LFSR circuit 500 shown in FIG. 1 . In this regard, the combiner is provided to be consistent with the path formed by the state storage element. In addition, in addition to the coefficients c0, c1 and c2 associated with the programmable generator polynomial, the LFSR circuit 500 also has coefficients d0, d1 and d2 associated with the programmable data input polynomial.

[0079] In one aspect, the coefficients c0, c1, and c2 associated with the generator polynomial and / or the coefficients d0, d1, and d2 associated with the data input polynomial can be dynamically reprogrammed. This reprogrammability can be referred to as real-time programmability and can be desirable or required in some applications. On the other hand, during real-time operation of the associated LFSR, the coefficients remain constant (e.g., cannot be reprogrammed). In some cases, when the coefficients are not real-time programmable, the coefficients can be reprogrammed while the LFSR is idle (e.g., for different use cases).

[0080] As described above, in various embodiments, a type 1 LFSR architecture may be associated with a smaller chip area (e.g., standard cell area) and / or better timing performance. Thus, in some embodiments, rather than implementing a type 2 LFSR architecture to directly generate a type 2 output, a type 1 LFSR architecture may be implemented and, if desired for a desired application, the type 1 LFSR architecture may be selectively connected to output conversion logic to convert the type 1 output to a type 2 output. For example, the equivalence between various aspects of the type 1 LFSR architecture and the type 2 LFSR architecture is as follows: Figures 14 to 19 to describe.

[0081] Figure 6 A block diagram of an example output conversion logic circuit 600 for converting from a type 1 LFSR output to a type 2 LFSR output according to an embodiment of the present disclosure is shown. However, not all of the components described are required, and one or more embodiments may include additional components not shown in the figure. The arrangement and type of components may be varied without departing from the spirit or scope of the claims described herein. Additional components, different components, and / or fewer components may be provided. In one embodiment, the output conversion logic circuit 600 may be selectively programmed (e.g., enabled or disabled) based on whether a type 2 output is desired.

[0082] The output conversion logic circuit 600 selectively receives the type 1 output y of the type 1 LFSR circuit. type1 (n), y type1 (n+1), y type1 (n+2) and y type1(n+3). For explanation purposes, in some embodiments, the output conversion logic circuit 600 selectively receives the type 1 output y from the LFSR circuit 400 type1 (n), y type1 (n+1), y type1 (n+2) and y type1 (n+3) and generate Figure 5 The type 2 output y of the LFSR circuit 500 type2 (n), y type2 (n+1), y type2 (n+2) and y type2 (n+3), although the output conversion logic circuit 600 may be selectively coupled to, for example, Figures 7 to 12 The type 1 LFSR circuit described herein may be selectively coupled to any type 1 LFSR circuit in general (e.g., by adjusting the components and connections of the LFSR circuit and / or output switching logic circuit 600 to accommodate the appropriate number of inputs and / or outputs). In this regard, the output switching logic circuit 600 provides 4-bit parallel output switching logic corresponding to the 4-bit outputs of the LFSR circuits 400 and 500.

[0083] Output conversion logic circuit 600 includes state storage elements 605, 610, 615, and 620; multipliers 625A-D, 630A-D, and 635A-D; and combiners 640A-D. State storage elements 605, 610, 615, and 620 are selectively connected to a type 1 LFSR circuit (e.g., LFSR circuit 400) to selectively receive output y type1 (n), y type1 (n+1), y type1 (n+2) and y type1 (n+3). Multiplier 625A is selectively connected to state storage element 610. Multiplier 630A is selectively connected to state storage element 615. Multiplier 635A is selectively connected to the type 1 LFSR circuit to selectively receive output signal y type1 (n). Multiplier 625B is selectively connected to state storage element 620. Multiplier 630B is selectively connected to the type 1 LFSR circuit to selectively receive output signal y tpe1 (n). The multiplier 635B is selectively connected to the type 1 LFSR circuit to selectively receive the output signal y type1 (n+1). The multiplier 625C is selectively connected to the type 1 LFSR circuit to selectively receive the output signal y type1 (n). The multiplier 630C is selectively connected to the type 1 LFSR circuit to selectively receive the output signal y type1(n+1). The multiplier 635C is selectively connected to the type 1 LFSR circuit to selectively receive the output signal y type1 (n+2). The multiplier 625D is selectively connected to the type 1 LFSR circuit to selectively receive the output signal y type1 (n+1). The multiplier 630D is selectively connected to the type 1 LFSR circuit to selectively receive the output signal y type1 (n+2). The multiplier 635D is selectively connected to the type 1 LFSR circuit to selectively receive the output signal y type1 (n+3).

[0084] Combiner 640A is selectively connected to multipliers 625A, 630A, and 635A, and generates output y based on the outputs of multipliers 625A, 630A, and 635A. type2 (n). The combiner 640B is selectively connected to the multipliers 625B, 630B, and 635B, and generates an output y based on the outputs of the multipliers 625B, 630B, and 635B. type2 The combiner 640C is selectively connected to the multipliers 625C, 630C, and 635C, and generates an output y based on the outputs of the multipliers 625C, 630C, and 635C. type2 The combiner 640D is selectively connected to the multipliers 625D, 630D, and 635D, and generates an output y based on the outputs of the multipliers 625D, 630D, and 635D. type2 (n+3). Note that the right output tap (e.g., eight right-pointing arrows) may be optional. These Type 1 outputs (with or without buffering at state storage elements 605, 610, 615, and 620) may be provided downstream to other processing circuitry.

[0085] like Figure 6 As shown, the output conversion logic circuit 600 does not have a feedback loop. In some cases, the output conversion logic circuit 600 can be pipelined (e.g., highly pipelined) by construction. The depth of the logic of the output conversion logic circuit 600 depends on the number of taps rather than the degree of parallelization. In various embodiments, such logic can be suitable for implementation in high-speed circuits, and as shown, the output conversion logic circuit 600 can be implemented in high-speed circuits. Such logic is in contrast to, for example, Figure 4 The LFSR circuit 400 and Figure 5 The logic associated with LFSR circuit 500 generally depends on both the number of taps and the degree of parallelization. Therefore, the logic associated with LFSR circuits 400 and 500 may not be well suited for implementation in high speed circuits, particularly for type 2 LFSR architectures.

[0086] In some embodiments, pipeline stages may be used to allow for timing closure of LFSR circuits with a high degree of parallelism operating at high clock rates, such as clock rates above 1 GHz. Figure 7 FIG. 7 is a block diagram of an LFSR circuit 700 according to an embodiment. The LFSR circuit 700 includes Figure 4 LFSR 400 is provided with pipeline elements 705, 710 and 715 and delay balancing elements 720A, 720B, 725A and 725B. Each state storage element and pipeline element can be a memory unit for storing (e.g., buffering) a state signal of the LFSR circuit 700. Each delay balancing element can be a memory unit for storing (e.g., buffering) an input signal or an output signal of the LFSR circuit 700. As a non-limiting example, each state storage element, pipeline element and delay balancing element can be implemented by a trigger (e.g., a D-type trigger). In one aspect, the LFSR circuit 700 can be referred to as a 4-bit pipeline parallel LFSR circuit.

[0087] Pipeline element 705 is selectively connected to combiner 440A, multiplier 445A, multiplier 455B, and state storage element 415. Pipeline element 710 is selectively connected to combiner 430A, multiplier 445B, and multiplier 455C. Pipeline element 715 is selectively connected to storage element 405 and multiplier 445C. Pipeline elements 705, 710, and 715 may be collectively provided and referred to as pipeline stages between a first set of logic stages (e.g., also referred to as bit levels or simply as levels) before a pipeline stage and a second set of logic stages after a pipeline stage. In this regard, pipeline elements 705, 710, and 715 are inserted after two logic stages. The first group of stages includes programmable logic stage circuits 420A and 420B and is coupled to input signals x(n) and x(n+1); state signals f0(n), f1(n), f2(n), f0(n+1), f1(n+1), and f2(n+1); and output signals y type1 (n) and y type1 The second group of stages includes programmable logic stage circuits 420C and 420D, and is associated with input signals x(n+2) and x(n+3); state signals f0(n+3), f1(n+3), f2(n+3), f0(n+4), f1(n+4), and f2(n+4); and output signals y type1 (n+;) and y type1 In one aspect, the LFSR circuit 700 can be considered to provide a sequential combinatorial path formed by sequential elements / connections and partitioned into a set of stages by pipeline stages.

[0088] Delay balancing elements 720A, 720B, 725A, and 725B are provided to balance the operation time units (e.g., clock cycles) associated with the first group of logic stages and the second group of logic stages due to the insertion of pipeline elements 705, 710, and 715. Output signals y associated with the first group of stages (e.g., a group of stages before the pipeline stage) type1 (n) and y type1 (n+1) are pipelined (e.g., delayed, buffered) so that these output signals are output by the LFSR circuit 700 at the output signals y associated with the second set of stages (e.g., a set of stages after the pipeline stage). type1 (n+2) and y type The input signals x(n+2) and x(n+3) associated with the second set of stages are pipelined such that these inputs are provided for processing (e.g., by combiners 450A and 460A) in the same time units (e.g., the same clock cycles) as the input signals x(n) and x(n+1) associated with the first set of stages.

[0089] In this regard, Figure 7 As shown, the output signal y associated with the first group of stages type1 (n) and y type1 (n+1) are pipelined by delay balancing elements 720A and 720B respectively. By applying this pipeline to the output signal y type1 (n) and y type1 (n+1), output signal y type1 (n) and y type1 (n+1) can be used with the output signal y after the pipeline stage type1 (n+2) and y type1 (n+3) identical time units are output from the LFSR circuit 700. At this point, the delay balancing elements 720A and 720B are applied to the output signal y respectively. type1 (n) and y type1 The pipeline balance of (n+1) is applied to the output signal y by pipeline elements 705, 710 and 715. type1 (n+2) and y type1 Without the pipeline performed by the delay balancing elements 720A and 720B, the output signal y type1 (n) and y type1 (n+1) can be obtained by LFSR circuit 700 in comparison with the output signal y type1 (n+2) and y type1 The output is (n+3) time units earlier (eg, one clock cycle earlier).

[0090] The input signals x(n+2) and x(n+3) associated with the second group of stages are pipelined by delay balancing elements 725A and 725B, respectively. By applying such pipelines to the input signals x(n+2) and x(n+3), the input signals x(n+2) and x(n+3) can be provided to combiners 435C and 435D, respectively, at the same time unit that the input signals x(n) and x(n+1) are provided to combiners 435A and 435B, respectively. In this regard, the pipelines applied to the input signals x(n+2) and x(n+3) align the input signals x(n+2) and x(n+3) with the signals delayed by pipeline elements 705, 710, and 715. In the absence of pipelining by delay balancing elements 725A and 725B, input signals x(n+2) and x(n+3) arrive earlier in time (e.g., one clock cycle earlier) than signals (e.g., signals f0(n+2), f1(n+2), and f2(n+2)) that are provided as inputs to pipeline elements 705, 710, and 715 and delayed by pipeline elements 705, 710, and 715).

[0091] Figure 8 FIG. 8 shows an LFSR circuit 800 according to an embodiment of the present disclosure. The LFSR circuit 800 includes Figure 4 The LFSR circuit 400 and Figure 7 The various programmable components and programmable routing resources shown in the LFSR circuit 700. In this regard, Figure 4 and Figure 7 The preceding description generally applies to Figure 8 , where examples and other descriptions of the differences are provided. In some cases, because the pipeline stages in the LFSR circuit 700 are in the path of the feedback loop in the LFSR circuit 700, the transition from the current state to the next state may require two time units (e.g., two clock cycles) instead of one time unit. In one aspect, the LFSR circuit 800 can be referred to as a 4-bit pipelined parallel LFSR circuit.

[0092] In some cases, the pipeline elements 705, 710, and 715 of the LFSR circuit 700 may be associated with a reduction in throughput (e.g., compared to an architecture without the pipeline elements 705, 710, and 715). The reduction in throughput associated with the LFSR circuit 700 may be mitigated / avoided by removing the feedback logic from the pipeline path (e.g., if required by the application). In this regard, the combinational logic of the LFSR circuit 800 is separated into a pipeline feedforward logic portion 805 and a feedback logic portion 810. As described with respect to Figure 4 and Figure 7As described above with respect to the LFSR circuits 400 and 700 of the present invention, the LFSR circuit 800 includes state storage elements 405, 410 and 415, multipliers 425A-C, 435A-C, 445A-C and 455A-C, combiners 430A-C, 440A-C, 450A-C and 460A-C, pipeline elements 705, 710 and 715, and delay balancing elements 720A, 720B, 725A and 725B. Figure 4 and Figure 7 In addition to the various programmable components described for LFSR circuits 400 and 700 , LFSR circuit 800 also includes multipliers 815A-D, 820A-D, and 825A-D, and combiners 830 , 835 , 840 , and 845 , which form a feedback logic portion 810 of the LFSR circuit 800 .

[0093] exist Figure 8 In FIG. 4 , combiners 435D, 440D, and 445D are not selectively connected to storage elements 405, 410, and 415, respectively. Figure 7 , so removed Figure 7 820C and 825D. Multipliers 815B, 820B and 825B are selectively connected to combiner 830. Combiner 830 is selectively connected to multipliers 815B, 820C and 825D. Multipliers 815B, 820B and 825B are selectively connected to combiner 835. Combiner 835 is selectively connected to multipliers 815C and 820D and state storage element 415. Multipliers 815C, 820C, and 825C are selectively connected to combiner 840. Combiner 840 is selectively connected to multiplier 815D and state storage element 415.

[0094] like Figure 8 As shown, the logic of the feedback logic portion 810 has similar complexity to the logic of the feedforward logic portion 805. The feedforward logic portion 805 is based in part on the next state matrix and the main output vector of the LFSR circuit 800 (e.g., the main output signal y type1 (n), y type1 (n+1), y type1 (n+2) and y type1(n+3) formation). In this way, the feedforward logic portion 805 can be referred to as an output logic circuit. In some cases, the feedforward logic portion 805 can be referred to as providing a critical path because it provides a path / portion associated with generating a main output signal. In one aspect, separating the LFSR logic into the feedforward logic portion 805 and the feedback logic portion 810 can separate the critical path (e.g., of the feedforward logic portion 805) from the remaining LFSR logic. At this point, the output signals at time units n+1, n+2, etc. up to n+N (e.g., for the 4-bit case in the LFSR circuit 800, N=3) are retained. The logic architecture can calculate the value at n+1 as a function of the value at n, the value at n+2 as a function of the value at n+1, and so on. Such calculations involve the original next state matrix of each stage, and the N-fold matrix multiplication is implemented by the combination of N stages. Because the output signals are involved, the degrees of freedom of the logic synthesis tool (such as the degrees of freedom of duplicating logic, combining logic, reconstructing logic, etc.) may generally be more limited. In some cases, pipeline stage(s) may be used to reduce the critical path to allow logic optimization that reduces the critical path from N to N / P, where P is the number of pipeline stages. Input and output delays may be inserted so that the inputs and outputs of all stages arrive at the appropriate time units (e.g., appropriate clock cycles).

[0095] In contrast, the feedback logic section 810 does not need to retain the generation of the main output signal y type1 (n), y type1 (n+1), y type1 (n+2) and y type1 (n+3) nodes (e.g., the feedback logic portion 810 does not involve output signals). Since the output signals do not need to be preserved, the logic synthesis tool can have more freedom to optimize the logic of the feedback logic portion 810 (e.g., such optimization is Figure 8). In this regard, the feedback logic portion 810 involves internal state calculations, in which the next state matrix is ​​multiplied multiple times by itself. In the case where the coefficients are not reprogrammed in real time, this matrix multiplication is not on the critical path. Therefore, in some cases, the matrix multiplication circuit device (e.g., multipliers and combiners) can be implemented with small and / or slow transistors or logic gates that are generally associated with low power consumption (e.g., compared to larger and / or faster transistors / gates). This matrix multiplication performed by the feedback logic portion 810 can be considered non-time critical, and can be pre-calculated for the case where the coefficients (e.g., c2, c1, c0) are not programmable in real time. In some cases, only the final stage is considered on the critical path, in which the resulting matrix is ​​multiplied with the real-time state and the input vector. The length of the critical path can be at most N, and can be reduced to logN by using the optimization of the RTL synthesis tool (e.g., similar to the reduction as a fast N-bit adder). In this way, the LFSR circuit 800 can allow the calculation of the time-critical next state vector to be optimized by utilizing synthesis techniques.

[0096] The pipeline stages of the feedforward logic portion 805 generally do not affect the operation of the feedback logic portion 810. In one aspect, pipeline stages may be inserted into the feedback logic portion 810. In some cases, delay balancing elements are not inserted into the feedback logic portion 810 (e.g., even though pipeline stages are inserted into the feedback logic portion 810). The number of pipeline stages in the feedforward logic portion 805 may be different than the number of pipeline stages in the feedback logic portion 810. As an example, the number of pipeline stages in the feedback logic portion 810 may be the same as or less than the number of pipeline stages in the feedforward logic portion 805. In some cases, any pipeline element in the feedforward logic portion 805 affects the latency associated with the feedforward logic portion 805 without affecting the throughput, while any pipeline element in the feedback logic portion 810 may affect both latency and throughput. In some cases, the logic of the feedback logic portion 810 may be optimized to the extent that timing can be met even without any pipeline stages (e.g., in situations such as Figure 8 810 shown in the feedback logic section).

[0097] Fig. 9 A block diagram of an LFSR circuit 900 according to an embodiment of the present disclosure is shown. The LFSR circuit 900 includes a state storage circuit device 905, a set of programmable logic stage circuits 910, a set of programmable logic stage circuits 925, a pipeline circuit device 940, a delay balance circuit device 945, and a delay balance circuit device 950. The set of programmable logic stage circuits 910 includes a multiplier circuit device 915 and a combiner circuit device 920. The set of programmable logic stage circuits 925 includes a multiplier circuit device 930 and a combiner circuit device 935.

[0098] For the purpose of illustration, the LFSR circuit 900 is generally described as Figure 7 700 , although LFSR circuit 900 may represent other LFSR circuits. Figure 7 In the LFSR circuit 700, the state storage circuit device 905 may include state storage elements 405, 410 and 415. The set of programmable logic level circuits 910 may include programmable logic level circuits 420A and 420B. The set of programmable logic level circuits 925 may include programmable logic level circuits 420C and 420D. The multiplier circuit device 915 may include multipliers 425A-C and 435A-C. The combiner circuit device 920 may include combiners 430A-C and 440A-C. The combiner circuit device 920 may receive input signals x(n) and x(n+1) (in Fig. 9 , and can generate an output signal y type1 (n) and y type1 (n+1)(in Fig. 9 4. The multiplier circuit 930 may include multipliers 445A-C and 455A-C. The combiner circuit 935 may include combiners 450A-C and 460A-C. The combiner circuit 935 may receive input signals x(n+2) and x(n+3) (in Fig. 9 , and can generate an output signal y type1 (n+2) and y type1 (n+3)(in Fig. 9 925). The digital subscript 0 in X0 and Y0 and the digital subscript 1 in X1 and Y1 may indicate that the input vector X0 and the output vector Y0 are associated with the zeroth set of programmable logic stage circuits (e.g., set 910), and the input vector X1 and the output vector Y1 are associated with the first set of programmable logic stage circuits (e.g., set 925). Pipeline circuit device 940 may include pipeline elements 705, 710, and 715. Delay balancing circuit device 945 may include delay balancing elements 720A and 720B, which apply delays to output signal y, respectively. type1 (n) and y type1 (n+1). Delay balancing circuit device 950 may include delay balancing elements 725A and 725B that apply delays to input signals x(n+2) and x(n+3), respectively.

[0099] Fig. 9 The arrows in the figure show Fig. 9In this regard, the state storage circuit device 905 selectively provides a state signal to the multiplier circuit device and / or pipeline circuit device 940 of the set 910 and / or the set 925 of programmable logic stage circuits, and selectively receives a state signal from the combiner circuit device via a feedback path. As an example, referring to Figure 7 , state storage element 410 selectively receives state signal f1(n+4) from combiner 450A of programmable logic stage circuit 420C. Each combiner circuit device selectively provides output to pipeline circuit device 940 and / or multiplier circuit device. As an example, combiner 430A of programmable logic stage circuit 420A selectively provides state signal f0(n+1) to multiplier 435A of programmable logic stage circuit 420B.

[0100] like Figure 7 and Fig. 9 As shown, pipeline circuit device 940 divides the programmable logic stage circuit of LFSR circuit 900 into set 910 and set 925, wherein each set has a delay balancing circuit device located at its (multiple) input path and / or its (multiple) output path. In this regard, pipeline circuit device 940 can be referred to as a pipeline stage. In one aspect, for a given input and output pair (e.g., x(n) and y(n)) at the same time unit, type1 (n) forms a pair, x(n+2) and y type1 (n+2) forms another pair), the sum of the number of delay balancing elements applied to the input signal and the number of delay balancing elements applied to the output signal is equal to the number of pipeline stages. Figure 7 and Fig. 9 In the case of , set 910 has one delay balancing element positioned at each output path and no delay balancing element positioned at each input path, and set 925 has one delay balancing element positioned at each input path and no delay balancing element positioned at each output path.

[0101] Fig.10 FIG. 1 is a block diagram of an LFSR circuit 1000 according to an embodiment of the present disclosure. For the purpose of illustration, the LFSR circuit 1000 is mainly described as follows: Figure 8 800, although LFSR circuit 1000 may represent other LFSR circuits. Figure 8 The description of LFSR circuit 800 is generally applicable to LFSR circuit 1000 .

[0102] The LFSR circuit 1000 includes Figure 81000. LFSR circuit 1000 includes a pipeline feedforward logic portion 1005 and a feedback logic portion 1010. In addition to the various programmable components described with respect to LFSR circuit 800, LFSR circuit 1000 also includes programmable logic state circuits 1015 and 1020, which form the feedback logic portion 1010 of the LFSR circuit. Since programmable logic state circuits 910 and 1015 selectively receive input signals associated with input vector X0, programmable logic stage circuit 1015 can be considered to correspond to programmable logic state circuit 910. Since programmable logic state circuits 925 and 1020 selectively receive input signals associated with input vector X1, programmable logic stage circuit 1020 can be considered to correspond to programmable logic state circuit 925. In some cases, such as Fig.10 As shown, no pipeline stages are provided between programmable logic stage circuit 1015 and programmable logic stage circuit 1020. Programmable logic circuit 1015 includes multiplier circuitry 1025 and combiner circuitry 1030. Programmable logic circuit 1020 includes multiplier circuitry 1035 and combiner circuitry 1040.

[0103] Although the foregoing describes an LFSR circuit having a single pipeline stage, in some embodiments, the LFSR circuit may have two or more pipeline stages. In some aspects, multiple pipeline stages may be used to allow for more input signals and / or more output signals (e.g., more pipeline stages to accommodate more than about Figures 4 to 10 In some cases, the LFSR circuit can be programmably expanded. For example, additional multipliers, combiners, etc. can be appropriately programmed to expand beyond Figures 4 to 10 The four digits shown.

[0104] Fig.11A block diagram of an LFSR circuit 1100 with multiple pipeline stages according to an embodiment of the present disclosure is shown. The LFSR circuit 1100 includes a state storage circuit device 1105, a set of programmable logic stage circuits 1110, 1125, and 1140, pipeline circuit devices 1155 and 1160, and delay balance circuit devices 1165, 1170, and 1175. The set of programmable logic stage circuits 1110 includes a multiplier circuit device 1115 and a combiner circuit device 1120. The set 1110 (e.g., the zeroth set) selectively receives an input vector X0 and provides an output vector Y0. The set of programmable logic stage circuits 1125 includes a multiplier circuit device 1130 and a combiner circuit device 1135. The set 1125 (e.g., the first set) selectively receives an input vector X1 and provides an output vector Y1. The set 1140 (eg, the N-1th set) of programmable logic level circuits includes a multiplier circuit device 1145 and a combiner circuit device 1150. The set 1140 selectively receives an input vector X N-1 And provide the output vector Y N-1 .

[0105] exist Fig.11 In the embodiment, the N-1 pipeline stages / circuit devices divide the programmable logic level circuit of the LFSR circuit 1100 into N sets of programmable logic levels, where sets 1110, 1125 and 1140 are in Fig.11 In this regard, note that the ellipsis between set 1125 and pipeline circuitry 1160 may represent one or more additional pipeline circuitry and programmable logic stage circuitry, or the absence of pipeline circuitry and programmable logic stage circuitry between set 1125 and pipeline circuitry 1160. Each pipeline stage provides a demarcation that indicates / defines a delay balancing circuitry to be inserted at an input path and / or output path.

[0106] In one embodiment, for any given programmable logic level, the sum of the number of delay balancing elements applied to the input signal and the number of delay balancing elements applied to the output signal is equal to the number of pipeline stages. In this regard, for N-1 pipeline stages, the sum is also N-1. The number of pipeline stages can be determined based on the application, the technology (e.g., silicon technology) for implementing the LFSR, and the associated timing requirements. In one example, the LFSR circuit can have 32 programmable logic levels with three pipeline stages inserted. The pipeline stages can be, but need not be, inserted substantially equidistant from each other (e.g., after the eighth, sixteenth, and twenty-fourth stages).

[0107] As an example, in the case of having two pipeline stages (e.g., LFSR circuit 1100 includes pipeline circuit device 1155 and pipeline circuit device 1160), each programmable logic stage circuit may have two delay balancing elements distributed across each input / output pair. The delay balancing circuit device 1165 coupled to each programmable logic stage circuit of set 1110 may include two delay balancing elements applied to each output path of the programmable logic stage circuit. No delay balancing circuit device is coupled to each input path of the programmable logic stage circuit of set 1110. The delay balancing circuit device 1170 coupled to each programmable logic stage circuit of set 1125 may include one delay balancing element applied to each input path of the programmable logic stage circuit and one delay balancing element applied to each output path of the programmable logic stage circuit. The delay balancing circuit device 1175 coupled to each programmable logic stage circuit of set 1140 may include two delay balancing elements applied to each input path of the programmable logic stage circuit of set 1140. No delay balancing circuit device is coupled to each output path of the programmable logic stage circuit of set 1140.

[0108] As another example, in a case with three pipeline stages (e.g., LFSR circuit 1100 includes pipeline circuit device 1155, pipeline circuit device 1160, and one pipeline circuit device between set 1125 and pipeline circuit device 1160), each programmable logic stage circuit has three delay balancing elements distributed across each input / output pair. The delay balancing circuit device 1165 of each programmable logic stage circuit coupled to set 1110 may include three delay balancing elements applied to each output path of the programmable logic stage, and no delay balancing circuit device is coupled to each input path of the programmable logic stage circuit of set 1110. The delay balancing circuit device 1170 of each programmable logic stage circuit coupled to set 1125 may represent one delay balancing element applied to each input path of the programmable logic stage and two delay balancing elements applied to each output path of the programmable logic stage circuit. The delay balancing circuit device ( Fig.11 The delay balancing circuit device 1175 coupled to each programmable logic stage circuit of the set 940 may include three delay balancing elements applied to each input path of the programmable logic stage circuit of the set 1140, and no delay balancing circuit device is coupled to each output path of the programmable logic stage circuit of the set 1140.

[0109] As about Fig. 9 and Fig.11 As shown, Fig. 9 The LFSR circuit 900 of FIG. 9 provides a case where N=2, and thus a LFSR architecture using a single pipeline stage can be obtained by removing the circuit device following the programmable logic stage circuit 925 (eg, disabling the circuit device), thereby obtaining a LFSR architecture using a single pipeline stage. Fig.11 The LFSR circuit 1100 is derived. Fig. 9 In the LFSR circuit 900, a single pipeline stage separates the programmable logic stage circuit into two sets of programmable logic stage circuits (e.g., set 910 and set 925), wherein the first set (e.g., set 910) has a single delay balancing element (e.g., 720A, 720B) at each output path and no delay balancing element at each input path, and the second set (e.g., set 925) has a single delay balancing element (e.g., 725A, 725B) at each input path and no delay balancing element at each output path. Therefore, Fig. 9 The description generally applies to Fig.11 , which provides examples and additional descriptions of the differences.

[0110] Fig.12 FIG. 1 is a block diagram of an LFSR circuit 1200 according to an embodiment. The LFSR circuit 1200 includes Fig.11 The various programmable components and programmable routing resources shown in the LFSR circuit 1100 and include relative Fig.10 The additional stage of the LFSR circuit 1000. Fig.11 , Fig.11 The feedback loop of LFSR circuit 1100 is removed, and the logic of LFSR circuit 1100 is separated / duplicated to form pipeline feedforward logic portion 1205 and feedback logic portion 1210. In addition to the various programmable components described with respect to LFSR circuit 1100, LFSR circuit 120 also includes programmable logic state circuits 1215, 1220, and 1225, which form feedback logic portion 1210 of LFSR circuit 1200. Since programmable logic state circuits 1110 and 1215 selectively receive input signals associated with input vector X0, programmable logic state circuit 1215 can be considered to correspond to programmable logic state circuit 1110. Since programmable logic state circuits 1125 and 1220 selectively receive input signals associated with input vector X1, programmable logic state circuit 1220 can be considered to correspond to programmable logic state circuit 1125. Since programmable logic state circuits 1140 and 1225 selectively receive input signals associated with input vector X1, programmable logic state circuit 1220 can be considered to correspond to programmable logic state circuit 1125. N-1 The associated input signals, therefore, programmable logic state circuit 1225 can be considered to correspond to programmable logic state circuit 1140 .

[0111] Fig.13 13 is a flowchart of an example process 1300 for operating an LFSR (eg, a stage of an LFSR) according to an embodiment of the present disclosure. Figure 8 The example process 1300 is described with reference to the LFSR circuit 800 of FIG. 1 , although the example process 1300 can be used with other LFSR circuits. Note that one or more operations may be combined, omitted, and / or performed in a different order as desired.

[0112] At block 1305, a set of state signals (e.g., f0(n+2), f1(n+2), and f2(n+2)) may be selectively received by the LFSR circuit 800 (e.g., pipeline elements 705, 710, and 715 of the LFSR circuit 800). At block 1310, the set of state signals may be stored (e.g., buffered) by the LFSR circuit 800 to obtain a set of buffered state signals. At block 1315, an input signal (e.g., x(n+2)) may be selectively received by the LFSR circuit 800 (e.g., delay balancing element 725A of the LFSR circuit 800). At block 1320, the input signal may be stored (e.g., buffered) by the LFSR circuit 800 (e.g., delay balancing element 725A) to obtain a buffered input signal. At block 1325, an output signal (e.g., y) may be determined based on the set of buffered state signals and the buffered input signal. type2 (n+2)). Depending on the application, the output signal may represent scrambled data or descrambled data (e.g., scrambled bits or descrambled bits), encrypted data or decrypted data, etc. In some cases, the output signal may be a type 1 output signal, which may be provided to a conversion logic circuit (e.g., 600) to be converted to a type 2 output signal. In some cases, at least one of the buffer state signals may be provided as a feedback signal (e.g., provided to the state storage elements 405, 410, and / or 415 of the LFSR circuit 800).

[0113] Note that process 1300 is described with respect to a portion of LFSR circuit 800. Other portions of the LFSR circuit (e.g., programmable logic level circuits) may be associated with corresponding sets of state signals, corresponding input signals, corresponding output signals, corresponding pipeline stages, and corresponding delay balances.

[0114] Although the pipeline stages and associated delay balancing are described above with respect to a type 1 LFSR circuit, the pipeline stages and associated delay balancing may be inserted into a type 2 LFSR circuit. Various LFSR circuits having either a type 1 LFSR architecture or a type 2 LFSR architecture are described above, and equivalence between the type 1 LFSR architecture and the type 2 LFSR architecture is provided. In various embodiments, equivalence may be provided between next state equations and output equations between the type 1 LFSR architecture and the type 2 LFSR architecture, which will be discussed below with respect to Figures 14 to 19 As an example, the output conversion logic circuit 600 for converting from type 1 output to type 2 output can be determined based on this equivalence between the type 1 LFSR architecture and the type 2 LFSR architecture. In various embodiments, establishing such equivalence can facilitate high-speed parallel implementation by generating type 1 output or type 2 output suitable for a given application.

[0115] In some embodiments, as described below with respect to Fig.14 The next state vector [F(n+1)] and the output signal y for a general LFSR circuit with a type 1 architecture are described as follows: type1 (n) can be given by the following formula:

[0116]

[0117]

[0118] where [F(n)] is the current state vector, x(n) is the input signal, [M] is the next state matrix, and [U0] is a vector having a unit value at its zeroth position and zero values ​​at the remaining positions. The symbols in the subscripts are <0> indicates the position of the zeroth element of the vector, and <0,0> indicates the position of the zeroth element of the matrix.

[0119] As an example, Fig.14 1 shows a block diagram of a three-tap serial LFSR circuit 1400 having a type 1 architecture. In one embodiment, Figure 4 The LFSR circuit 400 provides a parallel implementation derived from the three-tap serial LFSR circuit 1400. In this regard, in order to parallelize the three-tap serial LFSR circuit 1400, the serial implementation may be unfolded and its logic replicated to obtain the LFSR circuit 400. The three-tap serial LFSR circuit 1400 includes state storage elements 1405, 1410, and 1415, programmable multipliers 1420, 1425, and 1430, and programmable combiners 1435, 1440, and 1445.

[0120] State storage element 1405 is connected to state storage element 1410 and is selectively connected to multiplier 1420. State storage element 1410 is connected to state storage element 1415 and is selectively connected to multiplier 1425. State storage element 1415 is selectively connected to multiplier 1430. State storage element 1405 receives state signal f0(n+1) as its input and provides state signal f0(n) as its output. State storage element 1410 receives state signal f1(n+1) as its input and provides state signal f1(n) as its output. State storage element 1415 receives state signal f2(n+1) as its input and provides state signal f2(n) as its output. Multiplier 1420 is selectively connected to combiner 1440. Multipliers 1425 and 1430 are selectively connected to combiner 1445. Combiner 1445 is selectively connected to combiner 1440. Combiner 1440 is selectively connected to combiner 1435. Combiner 1445 selectively receives c1f1(n) from multiplier 1425 and c2f2(n) from multiplier 1430 as inputs, and generates / provides outputs based on these inputs. Combiner 1440 is selectively connected to combiner 1435. Combiner 1440 selectively receives c0f0(n) from multiplier 1420 and the output of combiner 1445 as inputs, and generates / provides outputs based on these inputs. Combiner 1435 selectively receives input signal x(n) and the output of combiner 1435, and generates / provides state signal f0(n+1) and output signal y type1 In one aspect, because combiners 1435, 1440, and 1445 are provided in the feedback path (eg, outside the path formed by state storage elements 1405, 1410, and 1415), the Type 1 architecture may be referred to as an external logic LFSR architecture.

[0121] The state vector of the three-tap serial LFSR circuit 1400 can be expressed as [f0(n) f1(n) f2(n)] T , which can be written more simply as [f0 f1 f2] T The next state vector formed by the next state equation group f0(n+1), f1(n+1) and f2(n+1) of the three-tap serial LFSR circuit 1400 can be provided by the following equation:

[0122]

[0123] The output equation of the three-tap serial LFSR circuit 1400 may be provided by the following equation:

[0124] y type1(n)) = f0(n+1)

[0125] For the three-tap serial LFSR circuit 1400, [M] is given by:

[0126]

[0127] Using the three-tap serial LFSR circuit 1400 as an example, equations (1) and (2) can be developed for a type 1 LFSR circuit. The initial conditions can be set to:

[0128]

[0129] The first few terms of the next state vector can be provided as follows to determine the general formula for the next state vector. For n=0:

[0130]

[0131] For n=1:

[0132]

[0133] For n=2:

[0134]

[0135] For n=3:

[0136]

[0137] For a given time unit n, the next state vector can be given by:

[0138]

[0139] To obtain the next state vector of equation (1) for a general LFSR circuit (e.g., the number of taps can be less than or greater than three), the specific next state matrix of equation (3) can be replaced by [M], and [1 0 0]T of equation (3) can be replaced by [U0]. type1 (n) follows from equation (1). As shown in equations (1) to (3), such calculations may involve multiple multiplications of the next state matrix with itself.

[0140] The principle of complete induction can be used to prove the general formula proposed in equation (1). In this regard, if the general formula holds for [F(n+1)], then under the principle of complete induction, the general formula also holds for [F(n+2)].

[0141]

[0142]

[0143] Thus, equations (1) and (2) provide a next state vector (e.g., a next state set of equations) and an output equation, respectively, that characterize the three-tap serial LFSR circuit 1400. Equations (1) and (2) involve multiple matrix multiplications of the next state matrix with itself. For any given LFSR circuit, in implementations where one or more of the coefficients c0, c1, or c2 are zero (e.g., where the associated multipliers and / or combiners are disabled), equations (1) and (2) and the other equations provided above may be simplified. The LFSR circuit 1400 implements the programmable generator polynomial c2x 2 +c1x 1 +c0. As an example, to implement the generator polynomial x 2 +1, the coefficients may be programmed as c2=c0=1 and c1=0, wherein the multiplier 1425, combiner 1445, and associated routing resources (eg, represented by downward arrows at the input and output of the multiplier 1425) may be disabled.

[0144] In some embodiments, as described below with respect to Fig.15 As described above, the next state vector [G(n+1)] and the output equation y for a general LFSR circuit with a type 2 architecture are type2 (n) is given by:

[0145]

[0146]

[0147] where [M] is the next-state matrix associated with the type-1 architecture, and [M T ] is a state transfer matrix associated with a Type 2 architecture and obtained by transposing [M] as further described herein.

[0148] As an example, Fig.15 A block diagram of a three-tap serial LFSR circuit 1500 having a type 2 architecture is shown. The three-tap serial LFSR circuit 1500 corresponds to and may be considered equivalent to Fig.14 The three-tap serial LFSR circuit 1400 with a type 1 architecture includes state storage elements 1505, 1510, and 1515, programmable multipliers 1520, 1525, and 1530, and programmable combiners 1535 and 1540.

[0149] State storage element 1505 is selectively connected to combiner 1540. Combiner 1540 is selectively connected to state storage element 1510. State storage element 1510 is selectively connected to combiner 1535. Combiner 1535 is selectively connected to state storage element 1515. State storage element 1515 is selectively connected to multipliers 1520, 1525, and 1530. Multiplier 1520 is selectively connected to combiner 1535. Multiplier 1525 is selectively connected to combiner 1540. Multiplier 1530 is selectively connected to state storage element 1505. State storage element 1505 receives state signal g0(n+1) as its input and provides state signal g0(n) as its output. State storage element 1510 receives state signal g1(n+1) as its input and provides state signal g1(n) as its output. State storage element 1515 receives state signal g2(n+1) as its input and provides state signal g2(n) as its output. Combiner 1540 selectively receives c1g2(n) from multiplier 1525 and state signal g0(n) from state storage element 1505 as input, and generates / provides state signal g1(n+1) based on these inputs. Combiner 1535 selectively receives c0g2(n), state signal g1(n) and input signal x(n) from multiplier 1520 as input, and generates / provides state signal g2(n) based on these inputs. In one aspect, since combiners 1535 and 1540 are provided to be consistent with the path formed by state storage elements 1505, 1510 and 1515, the type 2 architecture can also be referred to as an internal logic LFSR architecture.

[0150] The state vector for the three-tap serial LFSR circuit 1500 can be expressed as [g0(n) g1(n) g2(m)] T The next state vector formed by the next state equation group g0(n+1), g1(n+1) and g2(n+1) for the three-tap serial LFSR circuit 1500 can be provided by the following equation:

[0151]

[0152] The output equation for the three-tap serial LFSR circuit 1500 may be provided by:

[0153] y type2 (n+1)=g2(n+1)

[0154] For the three-tap serial LFSR circuit 1500, [M T ] is provided by the following formula:

[0155]

[0156] where the first column is non-trivial and the remaining columns are trivial.

[0157] Using the three-tap serial LFSR circuit 1500 as an example, equations (4) and (5) can be developed for a type 1 LFSR circuit. The initial conditions can be set to:

[0158]

[0159] The first few terms of the next state vector can be provided as follows to determine the general formula for the next state vector. For n=0:

[0160]

[0161] For n=1:

[0162]

[0163] For n=2:

[0164]

[0165] For n=3:

[0166]

[0167] For a given time instance n, the next state vector can be given by:

[0168]

[0169] To obtain the next-state vector of equation (4) for a general LFSR circuit (e.g., the number of taps may be less than or greater than three), the specific next-state matrix of equation (6) may be replaced by [M T ] (e.g., transposed relative to the corresponding next-state matrix for a type-1 architecture), and [1 0 0] of (6) T Can be replaced by [U0]. Used to represent the main output y type2 (n+1) follows from equation (5). As shown in equations (4) to (6), such calculations may involve multiple multiplications of the next state matrix with itself.

[0170] The principle of complete induction can be used to prove the general formula proposed in equation (4). In this regard, if the general formula holds for [G(n+1)], then under the principle of complete induction, the general formula also holds for [G(n+2)].

[0171]

[0172]

[0173] Equivalence may be shown between output signals of a type 1 LFSR architecture and output signals of a type 2 LFSR architecture. This equivalence provides output conversion from a type 1 output to a type 2 output or vice versa and allows embodiments in which a type 1 LFSR architecture is used (e.g., to take advantage of the smaller chip area and / or better timing performance typically associated with a type 1 LFSR architecture) and selectively convert the output of the type 1 LFSR architecture to the output of the type 2 LFSR architecture if the application requires it.

[0174] Equivalence can be shown between equation (2) and equation (5). In this regard, this equivalence applies to the case where the data entry point is before the first state storage element of type 1 (e.g., state storage element 1505) and before the last state storage element of type 2 (e.g., state storage element 1515). A matrix that is transposed and then raised to a natural power is the same as a matrix that is raised to a natural power and then transposed:

[0175]

[0176] The element at position <0,0> of either matrix is ​​the same, since that position is invariant to transposition:

[0177]

[0178] Therefore, the following equivalence is shown between Type 1 output and Type 2 output:

[0179]

[0180] A general type 2 LFSR architecture may have a data entry point in front of each state storage element (e.g., such as for CRC or FEC calculations). For example, a type 2 LFSR for FEC decoding has a data entry point specified by the remainder of a polynomial division. A type 1 architecture corresponding to a general type 2 LFSR architecture, and the associated equivalence between type 1 outputs and type 2 outputs are provided below.

[0181] As an example, Fig.16 A block diagram of a three-tap serial LFSR circuit 1600 having this general type 2 architecture is shown. The three-tap serial LFSR 1600 includes state storage elements 1606, 1610, and 1615, programmable multipliers 1620, 1625, 1630, 1635, 1640, and 1645, and programmable combiners 1650, 1655, and 1660.

[0182] Combiner 1660 is selectively connected to state storage element 1605. State storage element 1605 is selectively connected to combiner 1655. Combiner 1655 is selectively connected to state storage element 1610. State storage element 1610 is selectively connected to combiner 1650. Combiner 1650 is selectively connected to state storage element 1615. Multipliers 1620, 1625, and 1630 are selectively connected to combiners 1650, 1655, and 1660, respectively. Multipliers 1635, 1640, and 1645 are selectively connected to combiners 1650, 1655, and 1660, respectively.

[0183] State storage element 1605 receives state signal g0(n+1) as its input and provides state signal g0(n) as its output. State storage element 1610 receives state signal g1(n+1) as its input and provides state signal g1(n) as its output. State storage element 1615 receives state signal g2(n+1) as its input and provides state signal g2(n) as its output. Combiner 1650 selectively receives c0g2(n) from multiplier 1620, d0x(n) from multiplier 1635 and state signal g1(n) from state storage element 1610 as input and generates / provides state signal g2(n+1) based on these inputs. Combiner 1655 selectively receives c1g2(n) from multiplier 1625, d1x(n) from multiplier 1640, and state signal g0(n) from state storage element 1605 as inputs, and generates / provides state signal g1(n+1) based on these inputs. Combiner 1660 selectively receives c2g2(n) from multiplier 1630 and d2x(n) from multiplier 1645 as inputs.

[0184] The programmable generator polynomial can be provided as c2x 2 +c1x+c0. The data input polynomial can be provided as d2x 2 +d1x+d0. The state vector for the three-tap serial LFSR circuit 1600 can be expressed as [g0(n) g1(n) g2(n)] T The next state vector formed by the next state equation group g0(n+1), g1(n+1) and g2(n+1) for the three-tap serial LFSR circuit 1600 can be provided by the following equation:

[0185]

[0186] The data input vector is [d0 d1 d2] T Can be expanded:

[0187]

[0188] At this point, the data input vector [d0 d1 d2] T About Fig.15 The three-tap serial LFSR circuit 1500 is described with a data input vector [1 0 0] T Compared to it is broad.

[0189] For a given time instance n, the next state vector for the three-tap serial LFSR circuit 1600 may be provided as:

[0190]

[0191] For a general next-state matrix [MT] and a data input vector [D] (associated with the data input polynomial), the next-state vector can be provided by:

[0192] [G(n+1)]=[MT][G(n)]+[D]x(n)

[0193] It can be expanded as follows:

[0194]

[0195] Where m represents the rank of the transposed matrix [MT].

[0196] Equation (8) represents the superposition of multiple terms representing different values ​​of i. As provided above with respect to equation (7), the solution for i=0 is known. The solution for i>0 is given by [M T ] n-k [U i ] is given, the matrix [M T ] n-k The number of columns is i. Each such matrix is ​​the previous matrix [M T ] n-1-k With [M T ] (i.e., [M T ] n-k =[M T ] n-1-k [M T ]).

[0197] State transfer matrix [M T ] can be provided by the following formula:

[0198]

[0199] State transfer matrix [M T ] is given by the vector of polynomial coefficients:

[0200]

[0201] State transfer matrix [M T The remainder of ] is provided by the shifted identity matrix:

[0202]

[0203] At this point, any matrix [M T ] n-1-k With [M T ] shifts column number i of any matrix to the right. In other words, the product [M T ] n-k =[M T ] n-1-k[ M T ] column number i+1 and [M T ] have the same column number i:

[0204]

[0205] The above provides an equivalence for i=0:

[0206]

[0207] When i=1:

[0208]

[0209] The last term evaluates to zero because [M T ] 0 is the identity matrix, so all elements except those on the main diagonal are zero:

[0210]

[0211] Due to the right-shift property of matrix columns, this formula can be provided as:

[0212]

[0213] This is exactly the same output as the corresponding type 1 output one time unit ago:

[0214]

[0215] Similarly, the type 2 output for any data entry point 0 ≤ i ≤ m-1 corresponds to the type 1 output i time units ago:

[0216]

[0217] After determining the partial solution for each i, the computational solution can be determined. At this point, the full solution can be provided as the sum of each partial solution according to the superposition principle:

[0218]

[0219] The subsequent output of the Type 1 LFSR circuit may be the same as the internal state of the LFSR circuit. This formula represents the scalar product of the data input polynomial vector and the internal state vector.

[0220] Using this equivalence determined between the Type 2 LFSR output and the Type 1 LFSR output, an equivalent Type 1 LFSR circuit can be provided for a Type 2 LFSR circuit. As an example, Fig.17 A block diagram of a three-tap serial LFSR circuit 1700 having a type 1 architecture is shown. In one embodiment, the three-tap serial LFSR circuit 1700 provides additional logic for output equivalence with the three-tap LFSR circuit 1600 (e.g., relative to Fig.14 Three-tap serial LFSR circuit 1400).

[0221] The three-tap serial LFSR circuit 1700 includes state storage elements 1705, 1710, and 1715, programmable multipliers 1720, 1725, 1730, 1735, 1740, and 1745, and programmable combiners 1750, 1755, 1760, 1765, and 1770. Fig.16 The three-tap serial LFSR circuit 1600, Fig.17 The combiners 1750 , 1755 , 1760 , 1765 , and 1770 of the three-tap serial LFSR circuit 1700 are provided in a feedback path and a feedforward path outside the path formed by the state storage elements 1705 , 1710 , and 1715 .

[0222] Various simplified Type 1 LFSR circuits and Type 2 LFSR circuits may also be equivalent in their primary outputs in the case where the vector representing the data input polynomial is the same as the vector representing the generator polynomial (i.e., di=ci). In some cases, these simplified circuits may not support the application of FEC decoders.

[0223] As an example, Fig.18 A block diagram of a three-tap serial LFSR circuit 1800 having a type 1 architecture is shown, and Fig.19 A block diagram of a three-tap serial LFSR circuit 1900 having a type 2 architecture is shown. The three-tap serial LFSR circuits 1800 and 1900 can be considered as simplified circuits relative to the more general three-tap serial LFSR circuits 1700 and 1600. The three-tap serial LFSR circuits 1800 and 1900 can be shown under certain conditions to be equivalent in their main output relative to the more general three-tap serial LFSR circuits 1700 and 1600.

[0224] against Fig.17 The output equation of the three-tap serial LFSR circuit 1700 (eg, a generalized type 1 LFSR output equation) may be provided by:

[0225]

[0226] against Fig.18 The output equation of the three-tap serial LFSR circuit 1800 (eg, a simplified type 1 LFSR output equation) may be provided by:

[0227]

[0228] For [d2 d1 d0] = [c2 c1 c0], output y type1 (n) are the same.

[0229] against Fig.16 The output equation of the three-tap serial LFSR circuit 1600 (eg, a generalized type 2 LFSR output equation) may be provided by the following equation:

[0230]

[0231] against Fig.19 The output equation of the three-tap serial LFSR circuit 1900 (eg, a simplified type 2 LFSR output equation) may be provided by:

[0232]

[0233] For [d0 d1 d2] = [c0 c1 c2], output y type2 (n+1) are the same.

[0234] In some embodiments, for example Figures 14 to 19 The various equivalencies shown between the Type 1 LFSR architecture and the Type 2 LFSR architecture allow conversion from a Type 1 LFSR output to a Type 2 LFSR output or vice versa, such as by using Figure 6 The output conversion logic circuit 600.

[0235] Using various embodiments, LFSR circuits can be programmed to implement applications that are typically associated with type 1 LFSR circuit devices and / or type 2 LFSR circuit devices. Various standards can define serial implementations of LFSRs that process one bit of data per clock cycle. In such embodiments, the LFSR circuit for a given application can be specified by its type, generator polynomial, and / or data input polynomial. Table 1 provides examples of standard LFSRs that can be implemented using the various LFSR circuits provided herein. The examples in Table 1 are not exhaustive, and other applications can also be implemented using the various LFSR circuits provided herein.

[0236] Table 1: Standard LFSR examples

[0237]

[0238] Various examples are discussed in this paper as provided in Table 1. As an example application implemented using a Type 1 LFSR architecture, IEEE 802.3 Section 4 defines a LFSR with a generator polynomial x 31 +x 28 +1 PRBS pattern generator (e.g., FIG. 49-9 of Section 4 of IEEE 802.3) and a corresponding PRBS pattern checker (e.g., FIG. 49-11 of Section 4 of IEEE 802.3). The generated pattern is completely defined / specified by its feedback loop and its initial state in the absence of external data input x(n). In this regard, the pattern generator does not require external data input to generate a pseudo-random sequence. The pattern checker has a feedforward loop to process the pattern sent from the pattern generator and has no feedback loop. As another example, Section 4 of IEEE 802.3 also defines a self-synchronizing scrambler (e.g., FIG. 49-8 of Section 4 of IEEE 802.3) having a generator polynomial x 58 +x 39 +1 and corresponding descrambler (eg, Figure 49-10 of IEEE 802.3 Section 4). The data input goes into the first state storage element. Similar to the PRBS checker, the descrambler has a feed-forward loop to process the data sent from the scrambler and has no feedback loop.

[0239] As an example application implemented using the Type 2 LFSR architecture, PCIe Rev. 4.0 V1.0 defines a generator polynomial x 16 +x 5 +x 4 +x 3 +1 frame synchronization scrambler (e.g., PCI Express Base Specification Rev. 4.0 Version 1.0 Figure 4-10). The data does not enter the LFSR. The data is combined with the LFSR output by an external XOR gate. The corresponding descrambler will be the same as the scrambler. In contrast to the self-synchronous scrambler, the frame-synchronous scrambler requires external synchronization to align the phase of the data with the phase of the LFSR output.

[0240] As another example, JESD204C defines a generator polynomial x 16 +x 5 +x 4 +x 3 +1 CRC field generator (e.g., Figure 77 of JESD204C). The data input point is located at the same location as the feedback loop. The reception will use the same CRC calculator as the transmitter. Another circuit compares the transmitted checksum with the recalculated checksum and determines if a bit transmission error has occurred.

[0241] As another example, JESD204C defines an FEC encoder (e.g., FIG. 79 of JESD2040) and a corresponding FEC decoder (e.g., FIG. 81 of JESD204C). The FEC encoder has the same topology as the CRC calculator, where the data entry point is the same as the feedback point. The FEC decoder has the same feedback point as the encoder, but has a different data entry point. In the first decoding stage, both the data entry point and the feedback entry point are active, and the incoming data is processed to calculate the checksum. A non-zero checksum indicates one or more bit errors. In the second decoding stage, the feedback entry point is disabled, and the incoming checksum is processed to locate and correct the bit errors.

[0242] Where applicable, the various embodiments provided by the present disclosure may be implemented using hardware, software, or a combination of hardware and software. In addition, where applicable, without departing from the spirit of the present disclosure, the various hardware components and / or software components described herein may be combined into composite components including software, hardware, and / or both. Where applicable, without departing from the spirit of the present disclosure, the various hardware components and / or software components set forth herein may be separated into subcomponents including software, hardware, or both. In addition, where applicable, it is conceivable that software components may be implemented as hardware components, and vice versa.

[0243] In this regard, the various embodiments of the LFSR described herein may be implemented with various types of hardware and / or software and allow for significant improvements in, for example, performance and space utilization. As non-limiting examples, the LFSR / LFSR architecture described herein may be implemented using an ASIC, a system on a chip, a general purpose logic circuit, a processor (e.g., a configurable processor, a digital signal processor), generally any programmable resource of any programmable circuit or device, or any combination thereof. For example, the various embodiments may be used in custom built RTL logic that may be implemented in a general purpose integrated circuit and / or as a dedicated block of its own type (e.g., as a separate resource in a programmable fabric).

[0244] Software (such as program code and / or data) according to the present disclosure may be stored on one or more non-transitory machine-readable media. It is also contemplated that the software identified herein may be implemented using one or more general or special-purpose computers and / or computer systems, networked, and / or otherwise. Where applicable, the order of the various steps described herein may be changed, combined into composite steps, and / or separated into sub-steps to provide the features described herein.

[0245] The above embodiments illustrate but do not limit the present invention. It should also be understood that many modifications and variations are possible based on the principles of the present invention. Therefore, the scope of the present invention is limited only by the appended claims.

Claims

1. A linear feedback shift register circuit, comprising: a plurality of state storage elements, wherein each state storage element of the plurality of state storage elements is configured to store a corresponding state signal; A first plurality of programmable logic level circuits, each of the programmable logic level circuits being configured to: selectively receiving a corresponding input signal, and a corresponding set of status signals; determining a respective output signal based at least on a respective said set of said status signals; and providing a corresponding said output signal, wherein each programmable logic stage circuit is connected to at least one other programmable logic stage circuit of said first plurality of programmable logic stage circuits, and wherein a first programmable logic stage circuit of said first plurality of programmable logic stage circuits is configured to selectively receive said state signal from each state storage element of said plurality of state storage elements; a plurality of pipeline elements, wherein each pipeline element of the plurality of pipeline elements is configured to selectively connect at least two programmable logic stage circuits of the first plurality of programmable logic stage circuits; as well as A plurality of sets of delay balancing elements, wherein a first set of delay balancing elements in the plurality of sets is configured to selectively connect an output terminal to a second programmable logic stage circuit in the first plurality of programmable logic stage circuits and selectively buffer the output signal associated with the second programmable logic stage circuit.

2. The linear feedback shift register circuit of claim 1 , wherein a second set of delay balancing elements in the plurality of sets is configured to selectively connect a third programmable logic stage circuit in the first plurality of programmable logic stage circuits to an input terminal and selectively buffer the input signal associated with the third programmable logic stage circuit.

3. The linear feedback shift register circuit of claim 1 , wherein a second set of delay balancing elements in the plurality of sets is configured to selectively connect the second programmable logic stage circuit to an input terminal and selectively buffer the input signal associated with the second programmable logic stage circuit.

4. The linear feedback shift register circuit of claim 1 , wherein each of the first plurality of programmable logic stage circuits comprises: a set of programmable multipliers, wherein each programmable multiplier is configured to selectively receive one state signal from the set of state signals; as well as A programmable combiner circuit is configured to selectively receive one or more outputs from the set of programmable multipliers and generate the output signal based on the one or more outputs.

5. The linear feedback shift register circuit of claim 1 , further comprising a second plurality of programmable logic stage circuits, wherein each of the second plurality of programmable logic stage circuits is configured to: selectively receiving a corresponding input signal and a corresponding set of status signals; and A state signal is provided to another one of the second plurality of programmable logic level circuits, wherein a first one of the second plurality of programmable logic level circuits is configured to selectively receive the state signal from each of the plurality of state storage elements.

6. The linear feedback shift register circuit of claim 5 , wherein each of the plurality of state storage elements is configured to selectively connect the first of the second plurality of programmable logic level circuits to a corresponding one of the second plurality of programmable logic level circuits.

7. The linear feedback shift register circuit of claim 5 , wherein the first plurality of programmable logic stage circuits and the plurality of pipeline elements form a feedforward logic circuit, wherein the second plurality of programmable logic stage circuits form a feedback logic circuit, and wherein the state signals stored in the plurality of state storage elements collectively provide a state of the linear feedback shift register circuit.

8. The linear feedback shift register circuit of claim 1, wherein each of the plurality of state storage elements is configured to selectively connect the first programmable logic stage circuit to a corresponding programmable logic stage circuit of the first plurality of programmable logic stage circuits.

9. The linear feedback shift register circuit of claim 1, further comprising an output conversion circuit configured to receive the output signal from the first plurality of programmable logic stage circuits and generate a second output signal.

10. The linear feedback shift register circuit of claim 9, wherein the output conversion circuit comprises a plurality of programmable conversion logic circuits, each of the programmable conversion logic circuits being configured to generate one of the second output signals, and wherein each of the programmable conversion logic circuits comprises one or more programmable multipliers and one or more programmable combiners.

11. The linear feedback shift register circuit according to claim 10, further comprising a plurality of output storage elements, each of the output storage elements being configured to store a corresponding output signal of the output signals of the first plurality of programmable logic stage circuits, wherein: For each programmable conversion logic circuit, each of the one or more programmable multipliers is selectively connected to an output storage element of the plurality of output storage elements or an output terminal of one of the first plurality of programmable logic stage circuits.

12. The linear feedback shift register circuit of claim 9, wherein the plurality of state storage elements and the first plurality of programmable logic stages collectively provide a Fibonacci linear feedback shift register architecture, and wherein the second output signal is associated with a Galois linear feedback shift register architecture.

13. A programmable logic device (PLD), comprising the linear feedback shift register circuit according to claim 1, the PLD further comprising: configuring an array of memory cells; as well as The processing circuit is configured to: receiving configuration data associated with the PLD; and The array of configuration memory cells is programmed with the configuration data to program the linear feedback shift register circuit.

14. A method comprising: receiving configuration data for a programmable logic device (PLD); as well as An array of configuration memory cells of the PLD is programmed with the configuration data to program the linear feedback shift register circuit of claim 1 .

15. The method of claim 14, wherein the configuration data is provided from a remote system, a memory located within the PLD, and / or the separate memory in a system including the PLD and the separate memory.

16. A linear feedback shift register circuit, comprising: a plurality of state storage elements, wherein each state storage element of the plurality of state storage elements is configured to store a corresponding state signal; A feed-forward logic circuit comprising a first plurality of programmable logic level circuits, wherein each programmable logic level circuit of the first plurality of programmable logic level circuits is configured to: selectively receiving a corresponding input signal, and a corresponding set of status signals; determining a corresponding output signal based on a corresponding said set of said status signals; and providing respective said output signals, wherein each programmable logic level circuit is connected to at least one other programmable logic level circuit of said first plurality of programmable logic level circuits; as well as A feedback logic circuit comprising a second plurality of programmable logic stage circuits, wherein each programmable logic stage circuit of the second plurality of programmable logic stage circuits is configured to: selectively receiving a corresponding input signal, and a corresponding set of status signals; and providing a status signal to another programmable logic stage circuit in the second plurality of programmable logic stage circuits, Wherein a first programmable logic level circuit in the first plurality of programmable logic level circuits and a first programmable logic level circuit in the second plurality of programmable logic level circuits are configured to selectively receive the state signal from each state storage element in the plurality of state storage elements.

17. The linear feedback shift register circuit of claim 16, wherein each state storage element of the plurality of state storage elements is configured to receive the corresponding state signal from a corresponding programmable logic stage circuit of the second plurality of programmable logic stage circuits.

18. The linear feedback shift register circuit of claim 17, wherein each of the second plurality of programmable logic stage circuits comprises: a set of programmable multipliers, wherein each programmable multiplier is configured to selectively receive one state signal from the set of state signals; as well as Programmable combiner circuit, configured to: receiving one or more outputs from the set of programmable multipliers; selectively receiving the input signal; and The status signal is generated based on the set of status signals, the one or more outputs, and the input signal.

19. The linear feedback shift register circuit of claim 16, wherein the feedforward logic circuit further comprises a plurality of pipeline stages, wherein each pipeline stage comprises a corresponding plurality of pipeline elements, wherein: For each pipeline stage, each pipeline element of the corresponding plurality of pipeline elements is configured to selectively connect at least two programmable logic level circuits of the first plurality of programmable logic level circuits.

20. The linear feedback shift register circuit of claim 19, wherein the feedforward logic circuit further comprises a plurality of sets of delay balancing elements, wherein a first set of delay balancing elements in the plurality of sets is configured to selectively connect an input terminal to a second programmable logic level circuit in the first plurality of programmable logic level circuits and selectively store the input signal associated with the second programmable logic level circuit, and wherein a second set of delay balancing elements in the plurality of sets is configured to selectively connect a third programmable logic level circuit in the first plurality of programmable logic level circuits to an output terminal and selectively store the output signal associated with the third programmable logic level circuit.

21. The linear feedback shift register circuit of claim 20, wherein the feedforward logic circuit further comprises a plurality of sets of delay balancing elements, wherein a first set of delay balancing elements in the plurality of sets is configured to selectively connect an input terminal to a second programmable logic stage circuit in the first plurality of programmable logic stage circuits and selectively store an input signal associated with the second programmable logic stage circuit, wherein a second set of delay balancing elements in the plurality of sets is configured to selectively connect the second programmable logic stage circuit to an output terminal and selectively store an output signal associated with the second programmable logic stage circuit, wherein the number of pipeline stages in the plurality of pipeline stages is the same as the sum of the number of delay balancing elements in the first set and the number of delay balancing elements in the second set.

22. The linear feedback shift register circuit of claim 16, further comprising an output conversion circuit configured to receive the output signal from the first plurality of programmable logic stage circuits and generate a second output signal.

23. The linear feedback shift register circuit of claim 22, wherein the output conversion circuit comprises a plurality of programmable conversion logic circuits, each of the programmable conversion logic circuits being configured to generate one of the second output signals, and wherein each programmable conversion logic circuit comprises one or more programmable multipliers and one or more programmable combiners.

24. A programmable logic device (PLD), comprising the linear feedback shift register circuit according to claim 16, the PLD further comprising: configuring an array of memory cells; as well as The processing circuit is configured to: receiving configuration data associated with the PLD; and The array of configuration memory cells is programmed with the configuration data to program the linear feedback shift register circuit.

25. A method comprising: receiving configuration data for a programmable logic device (PLD); as well as An array of configuration memory cells of the PLD is programmed with the configuration data to program the linear feedback shift register of claim 16.

26. The method of claim 25, wherein the configuration data is provided from a remote system, a memory located within the PLD, and / or the separate memory in a system including the PLD and the separate memory.

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