Semiconductor device

Abstract

A semiconductor device is provided with a semiconductor element (40) having an emitter electrode (42) disposed on one face (41a) of a semiconductor substrate (41) and a collector electrode disposed on the back face. The emitter electrode (42) has an exposed portion (421) that is exposed from an opening portion (561) of a protective film (56) to provide a bonding region. The semiconductor substrate (41) has an active region (45) that is a formation region of an RC-IGBT as a vertical element through which a current flows between the emitter electrode (42) and the collector electrode. The active region (45) includes an overlapping region (451) that overlaps the exposed portion (421) in plan view and a non-overlapping region (452) that does not overlap the exposed portion (421). The ratio of a diode region (45d) in the non-overlapping region (452) is higher than the ratio of the diode region (45d) in the overlapping region (451).

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2021-119227, filed on July 20, 2021, and incorporates the contents of the base application in its entirety by reference. Technical Field

[0003] The disclosures in this specification relate to semiconductor devices. Background Technology

[0004] Patent Document 1 discloses a semiconductor device in which main electrodes are disposed on both sides of a semiconductor substrate. The contents of prior art documents are incorporated herein by reference as an explanation of technical elements herein.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2021-5692 Summary of the Invention

[0008] In Patent Document 1, the active region where the element is formed is extended to the outer side of the lower part of the terminal. Furthermore, the element is configured such that when both the switching element in the extended outer region and the switching element in the region below the terminal are switched on, the current density in the extended region is lower than the current density in the region below the terminal. This results in a lower current density in the extended region. From the above-mentioned viewpoints, or other viewpoints not mentioned, further improvements are required for the semiconductor device.

[0009] This disclosure is made in view of such a problem, and aims to provide a semiconductor device that can improve the effect of active region expansion.

[0010] The semiconductor device disclosed herein includes: a semiconductor substrate having one side and a back side opposite to the one side in the thickness direction; a protective film disposed on one side of the semiconductor substrate and having an opening; a first main electrode disposed on one side of the semiconductor substrate and having an exposed portion exposed from the opening to provide a bonding region; and a second main electrode disposed on the back side of the semiconductor substrate; the semiconductor substrate has an active region, which is a region for forming an IGBT with diodes connected in antiparallel as a vertical element through which current flows between the first main electrode and the second main electrode; in planar view in the thickness direction, the opening is provided in a manner that overlaps with the active region; the active region includes an overlapping region that overlaps with the exposed portion of the first main electrode in planar view and a non-overlapping region that does not overlap with the exposed portion; the ratio of diode forming regions in the non-overlapping region is higher than the ratio of diode forming regions in the overlapping region.

[0011] According to the disclosed semiconductor device, the active region includes overlapping and non-overlapping regions. That is, the active region is expanded. Furthermore, the ratio of diode formation regions in the non-overlapping region is increased compared to the ratio of diode formation regions in the overlapping region.

[0012] Corresponding to the increased ratio of diode formation areas in the non-overlapping region, although the ratio of IGBT formation areas in the overlapping region increases, the heat generated by the IGBT operation can be dissipated from the exposed portion of the first main electrode to the bonding object. Furthermore, by increasing the ratio of diode formation areas in the non-overlapping region, it is possible to suppress the situation where the temperature of the non-overlapping region becomes higher than that of the overlapping region. That is, it is possible to suppress the situation where the IGBT must be turned off due to the temperature rise in the non-overlapping region. As a result, the effect of expanding the active region can be improved.

[0013] The various technical solutions disclosed in this specification employ different technical means to achieve their respective purposes. The reference numerals in parentheses within the claims and their items illustratively indicate the correspondence with portions of the embodiments described later, and are not intended to limit the scope of the technology. The purposes, features, and effects disclosed in this specification will become clearer upon reference to the following detailed description and accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a diagram showing the schematic structure of a vehicle drive system using the semiconductor device of the first embodiment.

[0015] Figure 2 This is a plan view showing the semiconductor device of the first embodiment.

[0016] Figure 3 It is along Figure 2 A sectional view along line III-III.

[0017] Figure 4 It is a planar diagram representing a semiconductor element.

[0018] Figure 5 It is along Figure 4 A cross-sectional view of the V-V line.

[0019] Figure 6 This is a plan view showing the semiconductor elements in the semiconductor device of the second embodiment.

[0020] Figure 7 It is along Figure 6 A sectional view along line VII-VII.

[0021] Figure 8 This is a plan view showing the semiconductor elements in the semiconductor device of the third embodiment.

[0022] Figure 9 This is a plan view showing the semiconductor elements in the semiconductor device of the fourth embodiment.

[0023] Figure 10 This is a plan view representing other variations. Detailed Implementation

[0024] Hereinafter, several embodiments will be described based on the accompanying drawings. Additionally, there are instances where repeated descriptions are omitted by assigning the same reference numerals to corresponding constituent elements in each embodiment. Where only a portion of the structure is described in each embodiment, the structures of other previously described embodiments can be applied to the remaining parts of that structure. Furthermore, not only combinations of structures explicitly shown in the descriptions of each embodiment, but also structures of multiple embodiments can be partially combined with each other, even without explicit description, as long as no particular obstacle arises in the combination.

[0025] The semiconductor device in this embodiment is applied, for example, to a power conversion device for a mobile body driven by a rotary electric motor. Examples of mobile bodies include electric vehicles (EVs), hybrid electric vehicles (HVs), plug-in hybrid electric vehicles (PHVs), flying vehicles such as drones, ships, construction machinery, and agricultural machinery. Hereinafter, examples of its application to vehicles will be described.

[0026] (First Embodiment)

[0027] First, based on Figure 1 A general description of the vehicle's drive system structure is provided.

[0028] <Vehicle drive system>

[0029] like Figure 1 As shown, the vehicle's drive system 1 includes a DC power supply 2, an electric generator 3, and a power conversion device 4.

[0030] DC power supply 2 is a DC voltage source composed of rechargeable and discharging secondary batteries. Examples of secondary batteries include lithium-ion batteries and nickel-metal hydride batteries. Electric generator 3 is a three-phase AC rotating electric motor. Electric generator 3 functions as the vehicle's driving force, i.e., an electric motor. During regeneration, electric generator 3 functions as a generator. Power conversion device 4 performs power conversion between DC power supply 2 and electric generator 3.

[0031] <Power Conversion Device>

[0032] Next, based on Figure 1 The circuit structure of the power conversion device 4 is described below. The power conversion device 4 includes a smoothing capacitor 5 and an inverter 6.

[0033] The smoothing capacitor 5 primarily smooths the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P-line 7 (high-potential side) and the N-line 8 (low-potential side). The P-line 7 is connected to the positive terminal of the DC power supply 2, and the N-line 8 is connected to the negative terminal of the DC power supply 2. The positive terminal of the smoothing capacitor 5 is connected to the P-line 7 between the DC power supply 2 and the inverter 6. The negative terminal of the smoothing capacitor 5 is connected to the N-line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel with the DC power supply 2.

[0034] Inverter 6 is a DC-AC conversion circuit. According to the switching control of a control circuit (not shown), inverter 6 converts DC voltage into three-phase AC voltage and outputs it to the electric generator 3. This drives the electric generator 3 to produce the specified torque. During regenerative braking of the vehicle, inverter 6, according to the switching control of the control circuit, converts the three-phase AC voltage generated by the rotational force from the wheels into DC voltage and outputs it to line P 7. Thus, inverter 6 performs bidirectional power conversion between the DC power supply 2 and the electric generator 3.

[0035] Inverter 6 has three-phase upper and lower arm circuits 9. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and lower arm 9L are connected in series between the P-line 7 and the N-line 8, with the upper arm 9H as the P-line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase of the generator 3 via the output line 10. Inverter 6 has six arms. At least a portion of each of the P-line 7, N-line 8, and output line 10 is constituted, for example, by conductive components such as a bus bar.

[0036] Each arm comprises an insulated-gate bipolar transistor 11 (hereinafter referred to as IGBT 11) serving as a switching element and a freewheeling diode 12. In this embodiment, an n-channel IGBT 11 is used. The diode 12 is connected in anti-parallel to the corresponding IGBT 11. In the upper arm 9H, the collector of the IGBT 11 is connected to the P-line 7. In the lower arm 9L, the emitter of the IGBT 11 is connected to the N-line 8. Furthermore, the emitter of the IGBT 11 in the upper arm 9H is connected to the collector of the IGBT 11 in the lower arm 9L. The anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.

[0037] The power conversion device 4 may also include a converter as a power conversion circuit. The converter is a DC-DC converter circuit that converts DC voltage into DC voltages of different values. The converter is located between the DC power supply 2 and the smoothing capacitor 5. The converter may include, for example, a reactor and the aforementioned upper and lower arm circuits 9. With this structure, step-up and step-down voltage conversion is possible. The power conversion device 4 may also include a filter capacitor to remove power supply noise from the DC power supply 2. The filter capacitor is located between the DC power supply 2 and the converter.

[0038] The power conversion device 4 may also include a drive circuit for switching elements that constitute the inverter 6, etc. Based on drive commands from the control circuit, the drive circuit supplies a drive voltage to the gate of the corresponding IGBT 11. The drive circuit drives the corresponding IGBT 11 by applying the drive voltage, i.e., it performs on-drive and off-drive. The drive circuit is sometimes referred to as a driver.

[0039] The power conversion device 4 may also include a control circuit for the switching elements. The control circuit generates drive commands to operate the IGBT 11 and outputs them to the drive circuit. The control circuit generates drive commands based on torque requests input from a higher-level ECU (not shown) and signals detected by various sensors. These various sensors include, for example, current sensors, rotation angle sensors, and voltage sensors. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the electric generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit may include a processor and memory. ECU is short for Electronic Control Unit. PWM is short for Pulse Width Modulation.

[0040] Semiconductor Devices

[0041] Next, based on Figure 2 and Figure 3 A general structure of a semiconductor device that uses semiconductor elements is described. Figure 2 It is a plan view representing a semiconductor device. Figure 2 This is a top-view plan view of a semiconductor device. Figure 3 It is along Figure 2 A sectional view along line III-III. In Figure 3 The structure of semiconductor devices is simplified and illustrated in the diagram.

[0042] Hereinafter, the thickness direction of the semiconductor substrate is defined as the Z direction. A direction orthogonal to the Z direction is defined as the X direction. A direction orthogonal to both the Z and X directions is defined as the Y direction. Unless otherwise specified, the shape seen from a planar view in the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, a planar view from the Z direction is simply referred to as a planar view.

[0043] like Figure 2 and Figure 3 As shown, the semiconductor device 20 includes a sealing resin body 30, a semiconductor element 40, heat sinks 60 and 70, a conductive spacer 80, and external connection terminals 90. The semiconductor device 20 constitutes one of the aforementioned arms. That is, two semiconductor devices 20 constitute the upper and lower arm circuits 9 of one phase.

[0044] The encapsulating resin body 30 encapsulates a portion of other elements constituting the semiconductor device 20. The remainder of the other elements is exposed outside the encapsulating resin body 30. The encapsulating resin body 30 is, for example, made of an epoxy resin. The encapsulating resin body 30 is formed, for example, by a transfer molding method. Figure 2 As shown, the sealing resin body 30 is generally rectangular in shape. The sealing resin body 30 has a surface 30a and a surface opposite to the surface 30a in the Z direction, namely the back surface 30b. The surface 30a and the back surface 30b are, for example, flat surfaces.

[0045] Semiconductor element 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44. Semiconductor element 40 is sometimes referred to as a semiconductor chip. The semiconductor substrate 41 is formed with vertically shaped elements using silicon (Si) or wide-bandgap semiconductors with a larger bandgap than silicon as materials. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0046] The vertical element is configured such that the main current flows in the thickness direction (Z direction) of the semiconductor substrate 41 (semiconductor element 40). In this embodiment, the vertical element is an IGBT 11 and a diode 12 forming one arm. The vertical element is an IGBT with the diode 12 connected in anti-parallel, i.e., an RC (Reverse Conducting) IGBT. The vertical element is a heat-generating element that heats up when energized. A gate electrode (not shown) is formed on the semiconductor substrate 41. The gate electrode is, for example, a trench structure.

[0047] The semiconductor substrate 41 has a surface 41a and a back surface 41b for mounting main electrodes. The surface 41a is the side of the sealing resin 30 on which the resin body 30 is located. The back surface 41b is the side opposite to the surface 41a in the thickness direction. An emitter electrode 42, serving as one of the main electrodes, is disposed on the surface 41a of the semiconductor substrate 41. A collector electrode 43, serving as the other main electrode, is disposed on the back surface 41b of the semiconductor substrate 41. The emitter electrode 42 corresponds to the first main electrode, and the collector electrode 43 corresponds to the second main electrode.

[0048] With the IGBT 11 turned on, current (main current) flows between the main electrodes, namely the emitter electrode 42 and the collector electrode 43. The emitter electrode 42 also serves as the anode electrode of the diode 12. The collector electrode 43 also serves as the cathode electrode of the diode 12. The collector electrode 43 is formed almost entirely on the back side 41b of the semiconductor substrate 41. The emitter electrode 42 is formed on a portion of one side 41a of the semiconductor substrate 41.

[0049] Pad 44 is a signal electrode. Pad 44 is formed in one side 41a of the semiconductor substrate 41 in a region different from the region where the emitter electrode 42 is formed. Pad 44 is formed in the Y direction at the end opposite to the region where the emitter electrode 42 is formed. Pad 44 and emitter electrode 42 are arranged in the Y direction. Pad 44 includes at least a pad for the gate electrode. Details regarding the semiconductor element 40 will be described later.

[0050] Heat sinks 60 and 70 are metal plates made of highly conductive metals such as Cu or Cu alloys. Heat sinks 60 and 70 are arranged such that multiple semiconductor elements 40 are sandwiched between them in the Z-direction. Heat sinks 60 and 70 are arranged such that at least a portion of them are opposite each other in the Z-direction. In planar view, the semiconductor elements 40 are contained within heat sinks 60 and 70.

[0051] Heat sink 60 is electrically connected to emitter electrode 42, providing wiring functionality. Similarly, heat sink 70 is electrically connected to collector electrode 43, providing wiring functionality. Heat sinks 60 and 70 provide heat dissipation functionality for dissipating heat generated by semiconductor device 40. Heat sinks 60 and 70 may have a Ni, Au, or other coating on their surface. In this embodiment, heat sink 60 is electrically connected to emitter electrode 42 via conductive spacer 80. Heat sink 60 and conductive spacer 80 correspond to the first wiring component. Heat sink 70 corresponds to the second wiring component.

[0052] Heat sink 60 has a side facing the semiconductor element 40, i.e., a counter-side surface 60a, and a side opposite to the counter-side surface 60a, i.e., a back surface 60b. Similarly, heat sink 70 also has a counter-side surface 70a and a back surface 70b. Heat sinks 60 and 70 are generally rectangular in shape. The back surfaces 60b and 70b of each of heat sinks 60 and 70 are exposed from the encapsulating resin body 30. Sometimes the back surfaces 60b and 70b are referred to as heat dissipation surfaces, exposed surfaces, etc. The back surface 60b of heat sink 60 is approximately coplanar with one side 30a of encapsulating resin body 30. The back surface 70b of heat sink 70 is approximately coplanar with the back surface 30b of encapsulating resin body 30.

[0053] A conductive spacer 80 is positioned between the semiconductor element 40 and the heat sink 60. The conductive spacer 80 provides a spacer function to ensure a predetermined distance between the semiconductor element 40 and the heat sink 60. For example, the conductive spacer 80 ensures the height used to electrically connect the pads 44 of the semiconductor element 40 to the corresponding signal terminals 93. The conductive spacer 80 is located midway between the emitter electrode 42 of the semiconductor element 40 and the conductive and heat-conducting path of the heat sink 60, providing wiring and heat dissipation functions.

[0054] The conductive spacer 80 is made of a metallic material with good electrical and thermal conductivity, such as Cu. The conductive spacer 80 may have a coating on its surface. The conductive spacer 80 is sometimes referred to as a connection portion, connection block, or metal block. The semiconductor device 20 has the same number of conductive spacers 80 as the semiconductor element 40. The conductive spacers 80 are individually connected to the semiconductor element 40. The conductive spacer 80 is, for example, a columnar body with a generally rectangular planar shape. In planar view, the conductive spacer 80 has a size approximately the same as or slightly smaller than the exposed portion 421 described later.

[0055] External connection terminal 90 is a terminal used to electrically connect semiconductor device 20 to external devices. External connection terminal 90 is formed using a highly conductive metal material such as copper. External connection terminal 90 is, for example, a substrate. External connection terminal 90 is sometimes referred to as a lead. External connection terminal 90 includes main terminals 91 and 92 and signal terminals 93. Main terminals 91 and 92 are external connection terminals 90 that are electrically connected to the main electrodes of semiconductor element 40.

[0056] The main terminal 91 is electrically connected to the emitter electrode 42. The main terminal 91 is sometimes referred to as the emitter terminal. The main terminal 91 is connected to the emitter electrode 42 via a heat sink 60. The main terminal 91 is connected to one end of the heat sink 60 in the Y direction. The main terminal 91 is thinner than the heat sink 60. The main terminal 91 is connected to the heat sink 60 in a manner that, for example, is substantially coplanar with the opposing surface 60a. The main terminal 91 can be integrally connected to the heat sink 60, or it can be provided as a separate component and connected by a joint.

[0057] In this embodiment, the main terminal 91 is integrally provided with the heat sink 60 as part of the lead frame. The main terminal 91 extends from the heat sink 60 in the Y direction and protrudes outward from the side surface 30c of the sealing resin body 30. The main terminal 91 has a bend in the middle of the portion covered by the sealing resin body 30 and protrudes from near the center in the Z direction in the side surface 30c.

[0058] The main terminal 92 is electrically connected to the collector electrode 43. The main terminal 92 is sometimes referred to as the collector terminal. The main terminal 92 is connected to the collector electrode 43 via the heat sink 70. The main terminal 92 is connected to one end of the heat sink 70 in the Y direction. The thickness of the main terminal 92 is thinner than that of the heat sink 70. The main terminal 92 is connected to the heat sink 70, for example, in a manner substantially coplanar with the opposing surface 70a. The main terminal 92 can be integrally connected to the heat sink 70, or it can be provided as a separate component and connected by a joint.

[0059] In this embodiment, the main terminal 92 is integrally provided with the heat sink 70 as part of a lead frame different from the main terminal 91. The main terminal 92 extends from the heat sink 70 in the Y direction and protrudes outward from the same side 30c as the main terminal 91. The main terminal 92 also has a bend midway in the portion covered by the sealing resin body 30 and protrudes from near the center in the Z direction in the side 30c. The two main terminals 91 and 92 are arranged in the X direction with their sides facing each other.

[0060] Signal terminals 93 are electrically connected to pads 44 of semiconductor element 40. In this embodiment, the connection is made via bonding wire 100. Signal terminals 93 extend in the Y direction, protruding from the side surface 30d of the encapsulating resin body 30. Side surface 30d is the surface opposite to side surface 30c in the Y direction. The semiconductor device 20 of this embodiment has five signal terminals 93 corresponding to the pads 44. The signal terminals 93 are configured, for example, as a lead frame common to the heat sink 70 and main terminals 92. The multiple signal terminals 93 are electrically separated from each other by cutting tie rods (not shown).

[0061] The emitter electrode 42 of the semiconductor element 40 is bonded to the conductive spacer 80 via the bonding member 101. The conductive spacer 80 is bonded to the heat sink 60 via the bonding member 102. The collector electrode 43 of the semiconductor element 40 is bonded to the heat sink 70 via the bonding member 103. The bonding members 101 to 103 are conductive. For example, the bonding members 101 to 103 can be solder. An example of solder is a multi-element lead-free solder that contains Cu, Ni, etc., in addition to Sn. Sintered bonding materials such as sintered silver can also be used instead of solder. The bonding members 101 to 103 can be made of common materials or different materials. In this embodiment, solder is used as the bonding members 101, 102, and 103.

[0062] As described above, in the semiconductor device 20, a semiconductor element 40 forming an arm is encapsulated by an encapsulating resin body 30. The encapsulating resin body 30 integrally encapsulates a portion of the semiconductor element 40, a portion of the heat sink 60, a portion of the heat sink 70, a conductive spacer 80, and a portion of the external connection terminal 90.

[0063] A semiconductor element 40 is disposed between heat sinks 60 and 70 in the Z direction. The semiconductor element 40 is sandwiched between the opposing heat sinks 60 and 70. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a two-sided heat dissipation structure. The back surface 60b of the heat sink 60 is substantially coplanar with one surface 30a of the encapsulating resin body 30. The back surface 70b of the heat sink 70 is substantially coplanar with the back surface 30b of the encapsulating resin body 30. Since the back surfaces 60b and 70b are exposed, heat dissipation is improved.

[0064] Semiconductor Components

[0065] Next, based on Figure 4 and Figure 5 The semiconductor element 40 will be described. Figure 4 This is a plan view showing one side of the semiconductor element 40. For convenience, in Figure 4 In the diagram, the active region, including the IGBT region and the diode region, is represented by solid lines. Figure 5 It is along Figure 4 A cross-sectional view of the V-V line. Hereinafter, "inner side" and "outer side" refer to the relative positions relative to the center of the active region of the semiconductor element. The side closer to the center is the inner side, and the side farther from the center is the outer side.

[0066] like Figure 4 As shown, the semiconductor substrate 41 is generally rectangular in shape. The semiconductor substrate 41 has an active region 45. The active region 45 is the formation region for vertically oriented components. The active region 45 is sometimes referred to as the main region, main unit region, unit region, component region, component formation region, etc. The active region 45 has an IGBT region 45i, which serves as the IGBT formation region in an RC-IGBT, and a diode region 45d, which serves as the diode formation region. The IGBT region 45i and the diode region 45d are alternately arranged in the Y direction. Multiple units (unit structures) are provided in the active region 45. These multiple units are connected in parallel to each other, forming an RC-IGBT.

[0067] The semiconductor substrate 41 has an outer peripheral region 46 that surrounds the active region 45. The outer peripheral region 46 is the region located outside the outer peripheral end of the active region 45 in planar view. Although not shown in the figure, a voltage-resistant structure such as a guard ring is formed in the outer peripheral region 46.

[0068] like Figure 5 As shown, the semiconductor substrate 41 has a collector region 47, a cathode region 48, a buffer region 49, a drift region 50, a base region 51, and an emitter region 52. Each semiconductor region is formed in the semiconductor substrate 41 by ion implantation of impurities, etc. Sometimes, the semiconductor region is referred to as a semiconductor layer, a diffusion layer, etc.

[0069] Collector region 47 is formed on the surface layer of the back side 41b of semiconductor substrate 41. Collector region 47 is a p-conductivity (p+) semiconductor region with a higher impurity concentration than base region 51. Cathode region 48 is also formed on the surface layer of the back side 41b. Cathode region 48 is an n-conductivity (n+) semiconductor region with a higher impurity concentration than drift region 50. Cathode region 48 and collector region 47 are arranged in an XY plane. Collector region 47 is located in IGBT region 45i, and cathode region 48 is located in diode region 45d. Cathode region 48 and collector region 47 are alternately arranged in the Y direction.

[0070] A buffer region 49 is formed on the surface of the collector region 47 and the cathode region 48 opposite to the back surface 41b. The buffer region 49 is formed between the collector region 47 and the cathode region 48 and the drift region 50. The buffer region 49 is an n-conductivity type semiconductor region (n) with a lower impurity concentration than the cathode region 48 and a higher impurity concentration than the drift region 50. By providing the buffer region 49, the propagation of the depletion layer towards the collector region 47 can be suppressed.

[0071] Drift region 50 is formed on the side of buffer region 49 opposite to the side of collector region 47. Drift region 50 is an n-conductivity type (n-) semiconductor region with a lower impurity concentration than buffer region 49.

[0072] The base region 51 is formed on the surface of the drift region 50 opposite to the side of the buffer region 49. The base region 51 is a p-conductivity (p) semiconductor region with a lower impurity concentration than the collector region 47. The base region 51 is mainly located in the active region 45 of the semiconductor substrate 41. The base region 51 is formed on the surface layer of one side 41a of the semiconductor substrate 41. Sometimes the base region 51 is referred to as the channel region. If the n-conductivity type is defined as the first conductivity type, then the p-conductivity type is the second conductivity type.

[0073] Emitter region 52 is disposed on the surface layer of side 41a within base region 51. Emitter region 52 is an n-conductivity (n+) semiconductor region with a higher impurity concentration than drift region 50. Emitter region 52 is formed in IGBT region 45i within active region 45. Emitter region 52 is disposed within IGBT region 45i in a manner that connects to the side of trench 53, which will be described later.

[0074] In the semiconductor substrate 41 with the above-described structure, trenches 53 are formed. The trenches 53 are formed with a defined depth starting from one side 41a. The trenches 53 penetrate the base region 51. The bottom end of the trenches 53 reaches the drift region 50. Multiple trenches 53 are formed in the active region 45 of the semiconductor substrate 41. Each trench 53 extends in the X direction. The multiple trenches 53 are arranged at approximately equal intervals in the Y direction, appearing as stripes in planar view. The trenches 53 define a unit cell. Each unit cell contains one trench 53, and multiple units are arranged in the Y direction.

[0075] A gate insulating film 54 is formed on the wall of the trench 53. A gate electrode 55 is formed on the surface of the gate insulating film 54 in a manner that fills the trench 53. The gate electrode 55 penetrates the base region 51 to reach the drift region 50. Multiple gate electrodes 55 are formed in the active region 45 of the semiconductor substrate 41. Each gate electrode 55 extends in the X direction. The multiple gate electrodes 55 are arranged at approximately equal intervals in the Y direction, appearing as stripes in planar view.

[0076] An emitter electrode 42 is formed on one side 41a of the semiconductor substrate 41. The emitter electrode 42 is mainly formed on the active region 45. The emitter electrode 42 is electrically connected to the emitter region 52 and the base region 51. The emitter electrode 42 is electrically isolated from the gate electrode 55. The emitter electrode 42 can also be electrically connected to the base region 51 via a base contact region. The base contact region is located on the surface layer of the base region 51 on one side 41a. The base contact region is adjacent to the emitter region 52. The base contact region is a p-conductivity (p+) semiconductor region with a higher impurity concentration than the base region 51.

[0077] On one side 41a of the semiconductor substrate 41, pads 44 serving as signal electrodes are also formed. The semiconductor element 40 of this embodiment has five pads 44. Specifically, these include a gate electrode pad, a Kelvin emitter pad for detecting the emitter potential of the IGBT 12, a current sensing pad, an anode potential pad for a temperature-sensing diode (temperature-sensing element) for detecting the temperature of the semiconductor element 40, and a cathode potential pad for the temperature-sensing diode. The Kelvin emitter pad 44 is electrically connected to the emitter electrode 42. The other pads 44 are electrically separated from the emitter electrode 42. The five pads 44 are concentrated at one end of the generally rectangular semiconductor substrate 41 in the Y direction and arranged in the X direction. The five pads 44 are positioned near the center of the edge of the semiconductor substrate 41 along the X direction.

[0078] A collector electrode 43 is formed on the back side 41b of the semiconductor substrate 41. The collector electrode 43 is formed over approximately the entire area of ​​the back side 41b. The collector electrode 43 is electrically connected to the collector region 47 and the cathode region 48.

[0079] In the aforementioned semiconductor element 40, an IGBT structure is formed in each cell of the IGBT region 45i. The IGBT structure includes a collector region 47, a buffer region 49, a drift region 50, a base region 51, an emitter region 52, and a gate electrode 55. Furthermore, a diode structure is formed in each cell of the diode region 45d. The diode structure includes a cathode region 48, a buffer region 49, a drift region 50, and a base region 51 that functions as an anode.

[0080] <Emitter Electrode>

[0081] Next, based on Figure 4 and Figure 5 The emitter electrode 42 is described in detail. Figure 4 The protective film is omitted from the illustration.

[0082] Semiconductor element 40 has a protective film 56 disposed on one side 41a of semiconductor substrate 41. The protective film 56 is an insulating film disposed on one side 41a of semiconductor substrate 41 such that it covers the periphery of emitter electrode 42. Materials for the protective film 56 may include, for example, polyimide or silicon nitride film. The protective film 56 has an opening 561 defining a bonding area between emitter electrode 42 and bonding member 101. The opening 561 is a through-hole that extends through the protective film 56 in the Z direction. Similarly, the protective film 56 has an opening (not shown) defining a bonding area in pad 44.

[0083] The emitter electrode 42 has an exposed portion 421 that protrudes from the opening 561 of the protective film 56 and provides a bonding area. The exposed portion 421 forms a bonding portion with the bonding member 101. The emitter electrode 42 has a multilayer structure. The emitter electrode 42 has a base electrode 422 and a connecting electrode 423. The pad 44 also has the same structure as the emitter electrode 42.

[0084] The base electrode 422 is a metal layer formed adjacent to the semiconductor substrate 41 in the multilayer emitter electrode 42. The base electrode 422 is sometimes referred to as the lower electrode, lower layer electrode, wiring electrode, first metal layer, etc. The base electrode 422 is connected to one side 41a of the semiconductor substrate 41. The base electrode 422 is formed, for example, using a material with Al (aluminum) as its main component. In this embodiment, an Al alloy such as AlSi or AlSiCu is used as the material.

[0085] In planar view, the base electrode 422 includes the active region 45 internally and extends to the outer peripheral region 46. The base electrode 422 is connected to the emitter region 52 and the base region 51. In planar view, the base electrode 422 has a peripheral portion 422a that surrounds the exposed portion 421. The peripheral portion 422a is the portion of the base electrode 422 that overlaps with the protective film 56. The protective film 56 is disposed on one side 41a of the semiconductor substrate 41 such that it covers the peripheral portion 422a of the base electrode 422.

[0086] The connecting electrode 423 is stacked on the base electrode 422 for purposes such as improving the bonding strength with the bonding member 101 and improving the wettability of the bonding member 101. The connecting electrode 423 is also referred to as the upper electrode, upper electrode, upper layer electrode, or second metal layer. The connecting electrode 423 includes at least one metal layer. The metal layer constituting the connecting electrode 423 may include, for example, some of Ni, Pd, Au, Pt, or Ag.

[0087] In this embodiment, the connecting electrode 423 includes at least a Ni (nickel) layer. Ni is harder than the Al alloy constituting the base electrode 422. An Au (gold) layer may also be provided on the Ni layer. The Au layer, for example, inhibits the oxidation of the Ni layer and improves wettability with the solder that serves as the bonding member 101. Since Au diffuses into the solder during soldering, the Au layer exists in the state before soldering and does not exist in the state after soldering.

[0088] The connecting electrode 423 is stacked on the base electrode 422 and exposed from the opening 561. As an example, in this embodiment, the connecting electrode 423 is disposed within the opening 561 on the base electrode 422. Furthermore, the outer peripheral end of the connecting electrode 423 contacts, for example, the wall surface of the protective film 56 defining the opening 561. The exposed portion 421 of the emitter electrode 42 includes the portion of the base electrode 422 that overlaps with the opening 561 in planar view, and the connecting electrode 423. The exposed portion 421 is generally rectangular in shape.

[0089] <Positional relationship between exposed area and active area>

[0090] Next, based on Figure 4 The positional relationship between the exposed portion 421 of the emitter electrode 42 and the active region 45 will be explained. For convenience, in Figure 4 In the diagram, the outer peripheral end of the exposed portion 421 of the emitter electrode 42, i.e. the opening end of the protective film 56, is indicated by a dashed line.

[0091] like Figure 4As shown, the active region 45 includes an overlapping region 451 that overlaps with the exposed portion 421 of the emitter electrode 42 in planar view, and a non-overlapping region 452 that does not overlap with the exposed portion 421. The overlapping region 451 is the region of the active region 45 located directly below the exposed portion 421. The non-overlapping region 452 is the region of the active region 45 located outside the exposed portion 421.

[0092] The overlapping region 451 and the pad 44 are arranged in the Y direction. The non-overlapping region 452 is connected to the overlapping region 451 in the Y direction. That is, the non-overlapping region 452 and the exposed portion 421 are arranged in the Y direction. The non-overlapping region 452 is located on the side of the pad 44 relative to the exposed portion 421. Most of the non-overlapping region 452 is arranged with the pad 44 in the X direction. The non-overlapping region 452 includes a pad-side region 452a arranged with the pad 44 in the X direction. The non-overlapping region 452 includes two pad-side regions 452a. The two pad-side regions 452a are located on both sides of the pad 44 in the X direction, sandwiching the pad 44 between them. The Y direction corresponds to the first direction as the arrangement direction of the pad and the overlapping region, and the X direction corresponds to the second direction.

[0093] In this embodiment, the entire non-overlapping region 452 is diode region 45d. No IGBT region 45i is provided in the non-overlapping region 452. Only diode structures (diodes) are formed in the pad-adjacent region 452a. Both IGBT structures (IGBTs) and diode structures are formed in the overlapping region 451. In the overlapping region 451, IGBT regions 45i and diode regions 45d are alternately arranged at a predetermined spacing in the Y-direction of the trench 53. In the overlapping region 451, the area of ​​each IGBT region 45i is larger than the area of ​​each diode region 45d. That is, the number of cells in each IGBT region 45i is greater than the number of cells in each diode region 45d. The area refers to the area along the XY plane.

[0094] <Summary of Implementation Method 1>

[0095] As described above, in this embodiment, the active region 45 includes an overlapping region 451 that overlaps with the exposed portion 421 that contributes to the bonding, and a non-overlapping region 452. That is, the active region 45 is extended to the outside of the exposed portion 421. Furthermore, the ratio of diode regions 45d in the non-overlapping region 452 is increased compared to the ratio of diode regions 45d in the overlapping region 451.

[0096] To enable the RC-IGBT to perform its desired function, the active region 45 comprises an IGBT region 45i and a diode region 45d in a predetermined ratio. In this embodiment, corresponding to the increased ratio of the diode region 45d in the non-overlapping region 452, the ratio of the IGBT region 45i in the overlapping region 451 becomes higher. That is, the heat concentrated in the overlapping region 451 of the IGBT structure, i.e., the heat mainly generated by the IGBT operation, can be efficiently dissipated from the exposed portion 421 located directly above to the conductive spacer 80, which is the object of bonding, and then to the heat sink 60.

[0097] The heat generated by the diode structure is less than that of the IGBT structure. In this embodiment, the ratio of diode regions 45d in the non-overlapping region 452 is increased as described above. This prevents the temperature of the non-overlapping region 452 from becoming higher than the temperature of the overlapping region 451. That is, it prevents the IGBT from having to be turned off due to the temperature rise of the non-overlapping region 452. It also prevents a situation where a larger current cannot flow through the semiconductor device 20 even though the overlapping region 451 is not that hot, allowing a large current to flow through the semiconductor device 20 until the overlapping region 451 becomes hot. This improves the effect of expanding the active region.

[0098] With the above structure, when the IGBT operates to supply a large current to the electric generator 3, such as during hot-spot operations like uphill driving or overtaking, the overall temperature rise of the active region 45 can be suppressed. Furthermore, since the ratio of the IGBT region 45i in the overlapping region 451 can be increased, and temperature rise is suppressed through heat dissipation via the exposed portion 421, the decrease in the IGBT's short-circuit withstand capability caused by temperature rise can be suppressed. Moreover, by increasing the ratio of the diode region 45d in the non-overlapping region 452, the area of ​​the diode region 45d in the entire active region 45 is ensured. Therefore, the current density during diode operation can be reduced, suppressing electromigration.

[0099] In this embodiment, the non-overlapping region 452 includes a pad-adjacent region 452a, which is arranged with the pad 44 in the X direction, which is the second direction. Therefore, the free space next to the pad 44 is effectively utilized, and the active region 45 can be expanded without changing the area of ​​the semiconductor substrate 41, i.e., the chip area.

[0100] In this embodiment, only the diode region 45d is provided in the pad-adjacent region 452a. That is, only the diode structure (diode) is formed in the pad-adjacent region 452a. As described above, the heat generated by the diode structure is less than that of the IGBT structure, so it is possible to more effectively suppress the situation where the temperature of the non-overlapping region 452 becomes higher than the temperature of the overlapping region 451.

[0101] (Second Implementation)

[0102] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, only the diode region 45d is provided in the pad-adjacent region 452a. Alternatively, an IGBT region 45i can be provided in the pad-adjacent region 452a.

[0103] The configuration of the IGBT region 45i in the pad-side region 452a is not particularly limited. In the structure where the pad-side region 452a includes the IGBT region 45i, the ratio of diode regions 45d in the non-overlapping region 452 is higher than the ratio of diode regions 45d in the overlapping region 451. For example, the IGBT region 45i and the diode region 45d can be alternately arranged in the pad-side region 452a.

[0104] Figure 6 This illustrates an example of a semiconductor element 40 in the semiconductor device 20 of this embodiment. Figure 6 Is with Figure 4 The corresponding floor plan. Figure 6 In, with Figure 4 Similarly, the outer peripheral end of the exposed portion 421 of the emitter electrode 42 is represented by a dashed line, and the active region 45, including the IGBT region 45i and the diode region 45d, is represented by a solid line. Figure 7 It is along Figure 6 A sectional view along line VII-VII.

[0105] exist Figure 6 and Figure 7 In the example shown, a diode region 45d and an IGBT region 45i are provided in the pad-side region 452a. In the pad-side region 452a, the IGBT region 45i is located at the end on the side of the outer peripheral region 46. That is, the IGBT region 45i is not located at the end of the active region 45 at the boundary with other regions in the pad-side region 452a, but rather at the end adjacent to the outer peripheral region 46. The IGBT region 45i is located at the end opposite to the guard ring 57 in the pad-side region 452a. The trench 53 (not shown) is arranged in the Y direction, similar to the previous embodiment. In this embodiment, the IGBT region 45i is located at the end of the pad-side region 452a, i.e., the end of the active region 45, in the Y direction.

[0106] In the outer peripheral region 46 of the semiconductor substrate 41, for example, Figure 7As shown, a guard ring 57 is formed. The guard ring 57 is provided for the purpose of mitigating the electric field intensity and improving the withstand voltage of the semiconductor device 20 when a high voltage is applied to the IGBT region 45i, causing the depletion layer extending from the base region 51 to extend along one side 41a of the semiconductor substrate 41. The guard ring 57 is arranged to surround the active region 45. The number of guard rings 57 is not particularly limited; at least one is sufficient. Figure 7 In the example shown, one of the guard rings 57 is disposed adjacent to the end of the base region 51. The other guard ring 57 is disposed at a position away from the inner guard ring 57. Other structures are the same as those described in the prior embodiments.

[0107] <Summary of Implementation Method 2>

[0108] When the diode is forward biased, the guard ring 57 becomes at the same potential as the base region 51. Therefore, holes are also supplied to the drift region 50 from the guard ring 57, which is a p-type semiconductor.

[0109] In this embodiment, an IGBT region 45i is provided at the end of the pad-side region 452a. Corresponding to the IGBT region 45i at the end, the diode region 45d is located further away from the guard ring 57. Therefore, when the diode region 45d is forward biased, a large amount of holes can be suppressed from accumulating in the drift region 50 near the boundary between the pad-side region 452a and the outer peripheral region 46. Therefore, when the diode region 45d is reverse biased, a large amount of holes flowing into the base region 51, which functions as the anode, can be suppressed, i.e., the occurrence of local current concentration. Thus, the recovery withstand capability of the diode can be improved. According to this embodiment, the effect of expanding the active region can be improved while simultaneously increasing the recovery withstand capability.

[0110] like Figure 6 As shown, in this embodiment, in the Y direction, an IGBT region 45i is also provided at the end of the active region 45 opposite to the pad 44. This also improves the recovery capability of the diode. Furthermore, in the X direction, the end of the diode region 45d is more inward than the end of the IGBT region 45i. This also improves the recovery capability of the diode. Thus, the recovery capability of the diode can also be improved in the overlapping region 451. In addition, as... Figure 4 As shown, the prior embodiment also has the same structure. Therefore, the above-described effects can be achieved.

[0111] This illustration shows an example where an IGBT region 45i is provided at the Y-direction end in the pad-adjacent region 452a, but it is not limited to this. For example, an IGBT region 45i may also be provided at the end opposite to the pad 44 in the X-direction. Alternatively, an IGBT region 45i may be provided at both the Y-direction end and the X-direction end.

[0112] The voltage withstand structure of the outer peripheral region 46 is not limited to the aforementioned guard ring 57. Any structure that includes a p-type semiconductor region that achieves the same potential as the base region 51 when the diode is forward biased is acceptable. For example, a RESURF structure can also be used. In this case, the p-type semiconductor region is formed in the outer peripheral region 46 on the surface of the drift region 50. This semiconductor region extends outward from the base region 51. In such a RESURF structure, by also providing the IGBT region 45i at the end of the pad-side region 452a, the effect of expanding the active region can be improved while simultaneously increasing the recovery withstand capability. RESURF is short for Reduced Surface Electric Field.

[0113] (Third Implementation)

[0114] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the non-overlapping region 452 is configured such that its end relative to the overlapping region 451 on the pad 44 side is connected. Alternatively, the non-overlapping region 452 and the exposed portion 421 may be arranged together.

[0115] Figure 8 This refers to the semiconductor element 40 in the semiconductor device 20 of this embodiment. Figure 8 Is with Figure 4 The corresponding floor plan. Figure 8 In, such as Figure 4 Similarly, the outer peripheral end of the exposed portion 421 of the emitter electrode 42 is represented by a dashed line, and the active region 45, including the IGBT region 45i and the diode region 45d, is represented by a solid line.

[0116] like Figure 8As shown, the IGBT region 45i extends across the exposed portion 421 in the X direction. The diode region 45d also extends across the exposed portion 421 in the X direction. The non-overlapping region 452 includes an exposed portion adjacent region 452b parallel to the exposed portion 421 in the X direction. In the non-overlapping region 452, the pad adjacent region 452a is a first region, and the exposed portion adjacent region 452b is a second region. The exposed portion adjacent region 452b is located on both sides of the exposed portion 421 in the X direction. Similar to the prior embodiment, the non-overlapping region 452 includes the pad adjacent region 452a. The non-overlapping region 452 also includes regions other than the pad adjacent region 452a that are located outside the exposed portion 421 in the Y direction. Regarding other structures, they are the same as those described in the prior embodiment.

[0117] <Summary of the Third Implementation>

[0118] In the exposed portion adjacent region 452b, the ratio of IGBT region 45i to diode region 45d is approximately the same as that in the overlapping region 451. That is, the ratio of diode region 45d in the pad adjacent region 452a is higher than that in the exposed portion adjacent region 452b. Therefore, compared to the ratio of diode region 45d in the overlapping region 451, the ratio of diode region 45d in the non-overlapping region 452 as a whole is increased. Thus, while expanding the active region 45 to the periphery of the exposed portion 421 to obtain an area of ​​the active region 45, the effect of expanding the active region is improved.

[0119] The structure described in this embodiment can be combined with any of the structures described in the first embodiment and the second embodiment.

[0120] (Fourth implementation)

[0121] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, a temperature-sensing diode for detecting the temperature of the semiconductor element 40 was not specifically mentioned; in a structure having a pad-side region 452a, a predetermined position for the temperature-sensing diode can be provided. In the prior embodiment, the pad 44 is provided near the center of the edge of the semiconductor substrate 41 in the X direction. Alternatively, the pad 44 may be concentrated at one end in the X direction.

[0122] Figure 9 This refers to the semiconductor element 40 in the semiconductor device 20 of this embodiment. Figure 9 Is with Figure 4 The corresponding floor plan. Figure 9 In, with Figure 4Similarly, the outer peripheral end of the exposed portion 421 of the emitter electrode 42 is represented by a dashed line, and the active region 45, including the IGBT region 45i and the diode region 45d, is represented by a solid line.

[0123] like Figure 9 As shown, multiple pads 44 are concentrated on one end side in the X direction. The multiple pads 44 are offset in the X direction. A pad-side region 452a is located in the X direction at the end opposite to the area where the pads 44 are located. The active region 45 includes only one pad-side region 452a. The active region 45 including the pad-side region 452a is planar and approximately L-shaped.

[0124] Semiconductor element 40 includes a temperature-sensing diode 58. The temperature-sensing diode 58 is constructed, for example, using a wiring material comprising doped polycrystalline silicon and aluminum, and is disposed on one side 41a of the semiconductor substrate 41. In planar view, the temperature-sensing diode 58 is not positioned overlapping the active region 45, but rather positioned in the X direction between the pad 44 and the adjacent region 452a. The anode of the temperature-sensing diode 58 is electrically connected to the anode pad 44, and the cathode is electrically connected to the cathode pad 44. Other structural aspects are the same as those described in the prior embodiment.

[0125] <Summary of Implementation Method 4>

[0126] As described above, in this embodiment, the temperature-sensing diode 58 is disposed outside the active region 45. This increases the area of ​​the exposed portion 421 and improves heat dissipation. That is, even if the ratio of the IGBT region 45i is increased in the overlapping region 451 directly below the exposed portion 421, the generated heat can be dissipated efficiently.

[0127] The area 452a adjacent to the pad is the outer region of the exposed portion 421, and heat dissipation via the exposed portion 421 is more difficult compared to the overlapping region 451. In this embodiment, a temperature-sensing diode 58 is disposed between the pad 44 and the area 452a adjacent to the pad. That is, the temperature-sensing diode 58 is disposed near the area 452a adjacent to the pad. The area near the area 452a adjacent to the pad has a higher temperature than the region outer of the exposed portion 421. Therefore, the temperature of the semiconductor element 40 can be detected even when the temperature-sensing diode 58 is disposed outside the active region 45. In addition, the wiring connecting the temperature-sensing diode 58 to the pad 44 can be shorter.

[0128] The structure described in this embodiment can be combined with any of the structures described in the first embodiment, the second embodiment, and the third embodiment.

[0129] In the structure described above, where the pad 44 is positioned biased towards one end in the X direction and the pad-adjacent region 452a is located on the other end, the temperature-sensing diode 58 can also be positioned in planar view at a position overlapping with, for example, the overlapping region 451 of the active region 45. In the structure described in the prior embodiment, where the diode is located near the center of the edge of the pad 44, the temperature-sensing diode 58 can also be located between the pad 44 and the pad-adjacent region 452a.

[0130] (Other implementation methods)

[0131] The disclosure in this specification and accompanying drawings is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and modifications derived by those skilled in the art based on them. For example, the disclosure is not limited to the combination of parts and / or elements shown in the embodiments. The disclosure can be implemented in a wide variety of combinations. The disclosure can have additional portions that can be added to the embodiments. The disclosure includes forms in which parts and / or elements of the embodiments are omitted. The disclosure includes substitutions or combinations of parts and / or elements between one embodiment and other embodiments. The scope of the disclosed technology is not limited to the description of the embodiments. It should be understood that several technical scopes disclosed are indicated by the description in the claims, and also include all modifications within the meaning and scope equivalent to the description in the claims.

[0132] The disclosure in the specification and drawings is not limited to the claims. The disclosure in the specification and drawings includes the technical ideas described in the claims, but also involves more diverse and broader technical ideas than those described in the claims. Therefore, a wide variety of technical ideas can be extracted from the disclosure in the specification and drawings without being bound by the claims.

[0133] When referring to an element or layer as "on," "connected to," "linked to," or "combined with," it may mean that the element is directly on, connected to, linked to, or combined with other elements or layers, or that there are intervening elements or layers. Conversely, when referring to an element as "directly on," "directly connected to," "directly linked to," or "directly combined with" other elements or layers, there are no intervening elements or layers. Other terms used to describe relationships between elements should be interpreted in the same way (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations relating to one or more of the associated listed items.

[0134] The spatially relative terms "inner," "outer," "back," "lower," "lower," "upper," and "higher," etc., are used herein to facilitate the description of the relationship between one element or feature and other elements or features, as illustrated in the figures. In addition to the orientation depicted in the figures, the spatially relative terms can also imply different orientations of the device in use or operation. For example, if the device in the figure is inverted, the element described as "lower" or "directly lower" to other elements or features is oriented "upper" to other elements or features. Therefore, the term "lower" can encompass both upper and lower orientations. The device may also be oriented in other directions (rotated 90 degrees or to other orientations), and the spatially relative descriptors used in this specification will be explained accordingly.

[0135] The vehicle's drive system 1 is not limited to the structure described above. For example, an example with one electric generator 3 is shown, but it is not limited to this. Multiple electric generators may also be included. An example with an inverter 6 as a power conversion unit is shown, but it is not limited to this. For example, it may be configured to have multiple inverters. It may also be configured to have at least one inverter and a converter. It may also only have a converter.

[0136] The structure of the semiconductor device 20 is not limited to the example described above. The semiconductor device 20 only needs to have at least a semiconductor element 40.

[0137] This illustration shows an example where the back surfaces 60b and 70b of the heat sinks 60 and 70 are exposed from the encapsulating resin body 30, but it is not limited to this. A structure may also be constructed where at least one of the back surfaces 60b and 70b is covered by the encapsulating resin body 30. A structure may also be constructed where at least one of the back surfaces 60b and 70b is covered by an insulating member (not shown) that is different from the encapsulating resin body 30. This illustration shows an example where the semiconductor device 20 includes the encapsulating resin body 30, but it is not limited to this. A structure may also be constructed without the encapsulating resin body 30.

[0138] This illustration shows an example where a heat sink 60 and a conductive spacer 80 are provided as a first wiring component connected to the emitter electrode 42 (first main electrode), and a heat sink 70 is provided as a second wiring component connected to the collector electrode 43 (second main electrode). However, the wiring component is not limited to the above example. For example, a substrate with metal bodies disposed on both sides of an insulating substrate may be used instead of the heat sinks 60 and 70. An example of a substrate is a DBC substrate. DBC is short for Direct Bonded Copper. A protrusion may be provided on the heat sink 60 instead of the conductive spacer 80. Similarly, a protrusion may be provided on the metal body on the inner surface side of the substrate.

[0139] This example illustrates a two-sided heat dissipation structure for semiconductor device 20, but it is not limited to this. A single-sided heat dissipation structure can also be applied. For example, the collector electrode 43 can be connected to a heat sink or a metal body of the substrate, and the emitter electrode 42 can be connected to a lead.

[0140] This example illustrates a semiconductor device 20 having only one semiconductor element 40 constituting one arm, but it is not limited to this. The semiconductor device 20 may also have multiple semiconductor elements 40 constituting one arm. That is, multiple semiconductor elements 40 may be connected in parallel to form one arm. Furthermore, the semiconductor device 20 may also have multiple semiconductor elements 40 constituting an upper and lower arm circuit 9 of one phase. It may also have multiple semiconductor elements 40 constituting an upper and lower arm circuit 9 of multiple phases.

[0141] This example illustrates that the opening shape of the opening 561, i.e., the planar shape of the exposed portion 421, is approximately rectangular, but it is not limited to this. Regardless of the shape of the exposed portion 421, the active region 45 includes an overlapping region 451 and a non-overlapping region 452.

[0142] There is no particular limitation on the number of pads 44. The semiconductor device 40 may have at least one pad 44. The pads 44 may include at least the pad for the gate electrode 55.

[0143] The arrangement of trench 53 (gate electrode 55) is not limited to the strip shape described above. The arrangement of IGBT region 45i and diode region 45d is not limited to the alternating arrangement in the Y direction described above.

[0144] The active region 45 can also be divided into multiple parts. For example, in Figure 10 In the example shown, the active region 45 is divided into two in the X direction. A gate runner (gate wiring, not shown) is configured between the active regions 45. The gate runner electrically connects the gate electrode 55 to the pad 44 for the gate electrode. Figure 10 Is with Figure 4 The corresponding floor plan.

[0145] This illustrates an example where the non-overlapping region 452 includes the pad-adjacent region 452a, but it is not limited to this. A structure that does not include the pad-adjacent region 452a can also be made. The ratio of the diode region 45d can also be increased at locations outside the pad-adjacent region 452a.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate having one side and a back side opposite to the aforementioned side in the thickness direction; A protective film is disposed on one side of the semiconductor substrate and has an opening. The first main electrode is disposed on one side of the semiconductor substrate and has an exposed portion that protrudes from the opening to provide a bonding area; as well as The second main electrode is disposed on the back side of the semiconductor substrate. The semiconductor substrate has an active region, which is the formation region of an IGBT in which a diode is connected in antiparallel as a vertical element through which current flows between the first main electrode and the second main electrode. In a planar view along the thickness of the plate, the opening is arranged to overlap with the active region. The aforementioned active region includes the overlapping region that overlaps with the exposed portion of the first main electrode in the aforementioned planar view, and the non-overlapping region that does not overlap with the exposed portion; The ratio of the diode formation area in the non-overlapping region is higher than the ratio of the diode formation area in the overlapping region.

2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor substrate has pads for signal electrodes disposed on one side thereof. The aforementioned non-overlapping region includes the pad-adjacent region, which is arranged with the pad in a second direction orthogonal to the first direction and the board thickness direction. The first direction is the arrangement direction of the pad and the overlapping region.

3. The semiconductor device as claimed in claim 2, characterized in that, Only the aforementioned diodes are formed in the area adjacent to the aforementioned pads.

4. The semiconductor device as claimed in claim 2, characterized in that, The semiconductor substrate described above has an outer peripheral region that surrounds the active region in the above planar view; The aforementioned diode and IGBT are formed in the area adjacent to the aforementioned pads; The aforementioned IGBT is located at the end of the aforementioned outer peripheral region in the area adjacent to the aforementioned pad.

5. The semiconductor device as claimed in claim 2, characterized in that, The aforementioned non-overlapping areas include the area next to the aforementioned pads and the area next to the aforementioned exposed portion; The ratio of the diode formation area in the area adjacent to the pad is higher than the ratio of the diode formation area in the area adjacent to the exposed portion.

6. The semiconductor device as claimed in claim 2, characterized in that, It includes a temperature-sensing diode located between the aforementioned pad and the area adjacent to the aforementioned pad.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, have: The first wiring component is electrically connected to the aforementioned first main electrode; and The second wiring component is electrically connected to the aforementioned second main electrode.

Images