Circuit and method for calibrating a digital-to-analog converter

Abstract

The present disclosure relates to a circuit and method for calibrating a digital-to-analog converter. A digital-to-analog converter (DAC) calibration system includes a DAC configured to convert a digital input to an analog input, a detector configured to measure analog outputs of the plurality of DAC unit cells and combine the analog outputs to generate a total analog output signal, and a calibration engine. The calibration engine is configured to calibrate the DAC.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to systems and methods for digital-to-analog conversion, and more particularly to calibration of a digital-to-analog converter. BACKGROUND

[0002] A digital-to-analog converter is a circuit that can convert a first signal in a digital representation to a second signal in an analog representation. The signal can be one or more voltages, one or more currents, or any combination thereof. A signal in an analog representation (or analog signal) can indicate data values from a continuous range of values, where a signal in a digital representation (or digital signal) can indicate data values from a finite set of values. An analog signal can provide a more accurate representation of data (e.g., audio data, image data, video data, or any data) than a digital signal, as a digital signal is obtained through quantization of certain bits of data involving truncation of values. At the same time, an analog signal can be more susceptible to noise than a digital signal, and can not be suitable for processing or computation by electronic devices. SUMMARY

[0003] In one aspect, the present disclosure relates to a digital-to-analog converter (DAC) comprising: a plurality of unit cells configured to receive a digital input from a processing circuit and convert the digital input to an analog output; an engine configured to: designate one of the plurality of unit cells as a reference cell having a first value; and calibrate the first value using a lowest or highest value of the unit cells.

[0004] In another aspect, the present disclosure relates to a method for calibrating a digital-to-analog converter (DAC), the method comprising: designating one of a plurality of DAC unit cells as a reference cell; adjusting the reference cell to have a first value of an output signal at a first output; comparing output signals at outputs of remaining DAC unit cells of the plurality of DAC unit cells with the first output; and adjusting the remaining DAC unit cells of the plurality of DAC unit cells according to the first value.

[0005] In another aspect, the present disclosure relates to a calibration system for a digital-to-analog converter (DAC) configured to receive a digital input through a plurality of DAC unit cells and convert the digital input to an analog signal, the analog signal being summed to an output signal, the calibration system comprising: a detector configured to determine a difference between a first value of a first cell of the DAC unit cells and a reference value of a reference cell at a summed output associated with the output signal; and a calibration engine configured to adjust the first cell to match the first value to the reference value in response to an error. BRIEF DESCRIPTION OF DRAWINGS

[0006] The various objects, aspects, features, and advantages of the present disclosure will become more fully understood and appreciated by reference to the detailed description, along with the appended drawings, in which like reference numerals identify corresponding elements throughout the drawings. In the drawings:

[0007] Figure 1 is a schematic block diagram of a digital-to-analog converter (DAC) according to an embodiment.

[0008] Figure 2 is a schematic block diagram of a DAC calibration system according to an embodiment.

[0009] Figure 3 is a schematic block diagram of a comparison system for a DAC calibration system as described in Figure 2

[0010] Figure 4 is a first waveform plot of a DAC calibration system according to an embodiment. Figure 2

[0011] Figure 5 is a second waveform plot of a DAC calibration system according to an embodiment. Figure 2

[0012] Figure 6 is a schematic block diagram of a calibration engine coupled to a comparison system as described in Figure 3

[0013] Figure 7 is a flowchart showing operations for calibrating an amplitude of one or more DAC unit cells according to an embodiment.

[0014] Figure 8 is a flowchart showing operations for calibrating a delay of one or more DAC unit cells according to an embodiment.

[0015] The details of various embodiments of methods and systems are set forth in the accompanying drawings and description below. DETAILED DESCRIPTION

[0016] ​​​​The following disclosure provides many different embodiments, or examples, for implementing various characteristics of the provided subject matter. In this document, concrete examples of components and arrangements are described in order to facilitate the patenting of this real disclosure. These are, of course, merely examples and are in no way limiting, for example, forming a first feature over or on a second feature in the following description can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not be in direct contact. Additionally, the reference numerals and / or letters in the various examples can be repeated in various instances. Such repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0017] Various embodiments disclosed herein relate to a digital-to-analog converter (DAC). In some embodiments, a DAC calibration system includes a DAC configured to convert a digital input to an analog output. The DAC includes processing circuitry configured to provide a digital input to a number of DAC unit cells. The DAC unit cells are configured to receive the digital input from the processing circuitry and convert the digital input to an analog output. The DAC calibration system includes a detector configured to measure the analog output of the DAC unit cells and combine the analog outputs to produce a total analog output signal. The DAC calibration system includes a calibration engine including one or more processing circuits including one or more memory devices coupled to one or more processors, the one or more memory devices configured to store instructions thereon that, when executed by the one or more processors, cause the one or more processors to designate one of the DAC unit cells as a reference cell having a first calibratable value, determine which of the plurality of DAC unit cells has a lowest calibratable value, compare the first calibratable value to the lowest calibratable value, calibrate the first calibratable value to match the lowest calibratable value if the first calibratable value is higher than the lowest calibratable value, and calibrate the remaining portion of the DAC unit cells to match the calibrated first calibratable value. In some embodiments, a subset of the DAC unit cells are calibrated, and the lowest value is the lowest value of the subset of the DAC unit cells. According to some embodiments, the term calibrate means to adjust, change, check, or otherwise tune a value to provide more accurate or precise operation.

[0018] In some embodiments, the digital input is at least one of a current signal and a voltage signal. In some embodiments, the digital input provided to the first DAC unit cell has an opposite sign from the digital input provided to the second DAC unit cell. In some embodiments, the processing circuit is configured to provide clocking for the DAC. In some embodiments, combining the analog outputs to produce a total analog output signal includes subtracting the second analog output from the first analog output. In some embodiments, the first calibratable value and the lowest calibratable value are at least one of an amplitude of the analog output and a timing of the analog output. In some embodiments, the DAC is a transmitter for wireless communication.

[0019] Various embodiments disclosed herein relate to a method. The method includes providing, by a processing circuit of a DAC, digital inputs to a plurality of DAC unit cells; receiving, by the DAC unit cells, the digital inputs and converting the digital inputs to analog outputs; combining the analog outputs to produce a total analog output signal; designating one of the DAC unit cells as a reference cell having a first calibratable value; determining which of the plurality of DAC unit cells has a lowest calibratable value; comparing the first calibratable value to the lowest calibratable value; if the first calibratable value is higher than the lowest calibratable value, calibrating the first calibratable value to match the lowest calibratable value, and calibrating a remainder of the plurality of DAC unit cells to match the calibrated first calibratable value.

[0020] In some embodiments, the digital input is at least one of a current signal and a voltage signal. In some embodiments, the digital input provided to the first DAC unit cell has an opposite sign from the digital input provided to the second DAC unit cell. In some embodiments, the processing circuit is configured to provide clocking for the DAC. In some embodiments, combining the analog outputs to produce a total analog output signal includes subtracting the second analog output from the first analog output. In some embodiments, the first calibratable value and the lowest calibratable value are at least one of an amplitude of the analog output and a timing of the analog output. In other embodiments, the values can be calibrated based on a highest calibrated value. In this case, the first calibratable value and the highest calibratable value are at least one of an amplitude of the analog output and a timing of the analog output. In some embodiments, the DAC is a transmitter for wireless communication.

[0021] Various embodiments disclosed herein relate to a non-transitory computer- readable medium comprising one or more computer-executable instructions that, when executed by at least one processor of a computing device, cause the computing device to provide, by processing circuitry of a DAC, digital inputs to a number of DAC unit cells, receive the digital inputs by the DAC unit cells and convert the digital inputs to analog outputs, combine the analog outputs to produce a total analog output signal, designate one of the DAC unit cells as a reference cell having a first calibratable value, determine which of the DAC unit cells has a lowest calibratable value, compare the first calibratable value to the lowest calibratable value, if the first calibratable value is higher than the lowest calibratable value, calibrate the first calibratable value to match the lowest calibratable value, and calibrate the remainder of the DAC unit cells to match.

[0022] In some embodiments, the digital inputs are at least one of a current signal and a voltage signal. In some embodiments, the digital input provided to the first DAC unit cell has an opposite sign from the digital input provided to the second DAC unit cell. In some embodiments, the processing circuitry is configured to provide clock timing for the DAC. In some embodiments, the first calibratable value and the lowest calibratable value are at least one of an amplitude of the analog output and a timing of the analog output. In some embodiments, the DAC is a transmitter for wireless communication.

[0023] Disclosed herein relates to a DAC calibration system including a number of DAC cells. A cell refers herein to a unit circuit having a set of components in a particular arrangement. Each DAC cell can be configured to receive a corresponding one of a plurality of bits of data and provide a current, voltage, or power corresponding to the received one bit of data. In one aspect, the currents from different DAC cells can be combined to represent a plurality of bits of data in an analog representation. For example, an amplitude of the combined currents in an analog representation can correspond to a plurality of bits of data in a digital representation. In one aspect, calibration can be performed for each DAC cell to reduce errors when performing digital-to-analog conversion.

[0024] In some embodiments, a DAC cell includes a bias control circuit, a driver circuit (or latch), and a current steering circuit. The bias control circuit can be a circuit configured to provide one or more bias voltages for configuring the driver circuit and the current steering circuit. A bias voltage can be a voltage used to set an amount of current or drive strength (e.g., transconductance (gm)) of a transistor or circuit. Drive strength can be an amount of change in current provided in response to a change in applied voltage. The driver circuit can be a circuit configured to provide a second signal having a first edge based on a first signal (e.g., a bias voltage) from the bias control circuit. An edge of a signal can be a change in a state of the signal from one state to another state. A rising edge can be a change from a low state (e.g., 0 V) to a high state (e.g., 1 V), and a falling edge can be a change from a high state (e.g., 1 V) to a low state (e.g., 0 V). The first edge of the second signal can be set or adjusted according to a drive strength of the driver circuit. For example, the second signal can have a faster edge by increasing the drive strength of the driver circuit. In one aspect, the driver circuit includes an adjustable current source that can set the drive strength according to the first signal (e.g., a bias voltage). In one aspect, the current steering circuit can be a circuit configured to generate or provide a current corresponding to one bit of data. The current steering circuit can be configured to generate a third signal having a second edge in response to the first edge of the second signal.

[0025] In one aspect, a DAC is implemented for wireless communication. For example, the DAC can be implemented in a transmitter for radio frequency (RF) communication, such as cellular communication (3G, 4G, 5G, 6G, etc.), Wi-Fi communication, Bluetooth communication, etc. In some embodiments, the transmitter is a transmitter of a base station (e.g., eNode B (eNB), gNodeB (gNB), etc.) that provides wireless communication. In one aspect, the DAC can operate at a high speed (e.g., over 5 Gbps) and can convert a radio frequency modulated signal in a digital representation to an analog signal in an analog representation. The DAC can provide the analog signal to a preamplifier or a power amplifier for transmission through an antenna, such that an analog upconverter or an analog mixer can be omitted. By omitting the analog upconverter or the analog mixer, the transmitter can reduce power consumption and can be implemented in a small form factor. Furthermore, modulating or upconverting a signal in a baseband frequency (e.g., 100 MHz to 1 GHz) to an RF frequency (1 to 10 GHz) can be performed by digital logic circuits that can be less susceptible to noise than analog circuits, such that the transmitter can provide a signal with higher signal integrity. While the DAC disclosed herein is provided for a transmitter for wireless communication, the DAC can be implemented for different applications. For example, the DAC disclosed herein can be implemented for wired communication, optical communication, or any computing device that performs digital-to-analog conversion (e.g., high speed digital-to-analog conversion).

[0026] In some embodiments, one or more components can be embodied as one or more transistors. An implemented transistor can be an N-type transistor or a P-type transistor. An N-type transistor is a transistor that utilizes electrons as majority carriers. A P-type transistor is a transistor that utilizes holes as majority carriers. A transistor can be any suitable type of transistor, including but not limited to a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, a FinFET, a planar MOS transistor with raised source / drain, a nanosheet FET, a nanowire FET, etc. Furthermore, one or more transistors shown or described herein can be embodied as two or more transistors connected in parallel. In one aspect, a transistor includes a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode can be interchangeable depending on the voltage applied to the source electrode and the drain electrode. Thus, the source electrode and the drain electrode can be referred to herein as source / drain electrodes. Depending on the voltage applied to the gate electrode of the transistor, current can flow between the source electrode and the drain electrode. In certain applications, a transistor can be implemented as a switch. For example, if the voltage difference between the gate electrode and the source electrode of the transistor is greater than the threshold voltage of the transistor, the transistor can be enabled to electrically couple between the source electrode and the drain electrode of the transistor. For example, if the voltage difference between the gate electrode and the source electrode of the transistor is less than the threshold voltage of the transistor, the transistor can be disabled to electrically decouple between the source electrode and the drain electrode of the transistor.

[0027] A DAC can include one or more DAC unit cells, processing circuitry, and an accurate reference or reference cell for calibrating the DAC unit cells. During use, each of the DAC unit cells can have a difference between the amplitude, rising edge, and falling edge of the signal associated with the cell. Typically, high performance DACs require calibration of the DAC unit cells so that all of the unit cells behave in the same or near the same manner (e.g., same rising edge and falling edge timing, etc.). Calibration uses a reference value or reference cell. In some embodiments, the reference cell can be set to an accurate reference value. In some embodiments, the calibrated system and method does not require additional circuitry within each DAC unit cell in order to be able to detect errors from the cell. In some embodiments, the calibrated system and method avoids negative impact on the high frequency performance of the DAC due to using separate signal paths to individually calibrate each of the DAC unit cells. Techniques to individually calibrate DAC cells are susceptible to situations where all errors cannot be calibrated in the full path. In some embodiments, the calibrated system and method allows for calibrating all errors in an efficient manner using the same output path.

[0028] Some embodiments of the systems and methods described herein include a DAC calibration system in which all DAC cells are compared to each other to measure differences in signals produced by each of the DAC unit cells within the DAC calibration system. In some embodiments, the DAC calibration system includes a detector configured to measure the output signals of each of the DAC unit cells and subtract the DAC unit cell output signals. Based on the measurements of the output signals of the DAC unit cells, the DAC calibration system determines whether there are differences between the output signals of the DAC unit cells and calibrates the DAC unit cells based on the determined differences. In some embodiments, the systems and methods do not require additional circuitry within each DAC unit cell to detect differences between the unit cells.

[0029] In some embodiments, a digital-to-analog converter (DAC) includes DAC unit cells configured to receive digital inputs from processing circuitry and convert the digital inputs to analog outputs, a detector, and a calibration engine. The calibration engine is configured to designate one of the DAC unit cells as a reference cell having a first value, and calibrate the first value of the reference to match a lowest or highest value of the DAC cells.

[0030] In some embodiments, a method for calibrating a DAC includes designating one of a plurality of DAC unit cells as a reference cell, adjusting the reference cell to have a first value at a first output, and comparing outputs of the remaining DAC unit cells of the plurality of DAC unit cells to the first output. The method also includes adjusting the remaining DAC unit cells of the DAC unit cells to have the first value at the output.

[0031] In some embodiments, a calibration system is provided for a DAC. The DAC is configured to receive digital inputs through a plurality of DAC unit cells and convert the digital inputs to analog signals that are summed to an output signal. The calibration system includes a detector configured to determine an error between a first value of a first cell of the DAC unit cells and a reference value of a reference cell at a summed output associated with the output signal. The calibration system also includes a calibration engine configured to adjust the first cell to match the first value to the reference value in response to the error.

[0032] Figure 1 A DAC 105 configured to convert digital inputs to analog inputs is illustrated. The DAC 105 includes one or more DAC unit cells 110a-110n and processing circuitry 115. The processing circuitry 115 is configured to receive and send data using each of the DAC unit cells 110a-110n, and also run a clock that regulates the timing of each of the individual DAC unit cells. The DAC unit cells 110a-110n can each output a signal, such as a current signal. According to some embodiments, the DAC 105 can use the systems and methods of calibration described below.

[0033] The DAC is operable to receive N-bit data in digital representation and provide a signal in analog representation corresponding to the received N-bit data. For example, the DAC unit cells 110a-110n can receive data in digital format from the processing circuit 115 and then output data in analog format. In some embodiments, the output signal from the DAC unit cells can be in the form of a current signal and / or a voltage signal.

[0034] In some embodiments, the waveform chart 120 illustrates signals corresponding to the DAC unit cells 110a-110n. For example, waveform 125 is a signal illustrating the clock timing of the DAC. Waveform 130 is a signal at one of the inputs of the DAC unit cells 110a-110n. Waveform 135 is a signal at the output of the DAC unit cells 110a-110n. In some embodiments, the output signal can be a current signal. The waveform chart 120 shows that the waveform 135 is delayed (e.g., delayed rising data 145 and delayed falling data 140), which can indicate that the DAC unit cell associated with the waveform 135 can need to be calibrated. Additionally, the waveform 135 has a higher amplitude, which indicates that the DAC unit cell associated with the waveform can need to be calibrated. The DAC 105 can include a detector that detects an error signal at the combined output of the DAC unit cells 110a-110n and a calibration engine that adjusts the DAC unit cells 110a-110n in response to the error. The calibration engine is any type of circuit that performs a calibration operation, such as the calibration operations described herein. In some embodiments, the unit cells can be DAC unit cells or repeating circuits for providing an output signal that can be calibrated as described herein.

[0035] Figure 2 A DAC calibration system 200 configured to calibrate one or more DAC unit cells 210a-210n is illustrated in accordance with some embodiments. The DAC calibration system 200 includes a DAC 205 and a detector 220. The DAC 205 is configured to convert a digital signal to an analog signal. The DAC 205 includes one or more DAC unit cells 210a-210n and a processing circuit 215. The processing circuit 215 is configured to receive and send data using each of the DAC unit cells 210a-210n and also receive a clock signal that regulates the timing of each of the individual DAC unit cells 210a-210n. The DAC unit cells 210a-210n can each output a signal, such as a current signal.

[0036] DAC 205 is operable to receive N-bit data in digital representation and provide a signal in analog representation corresponding to the received N-bit data. N is any integer (e.g., 2, 3, 4, 7, 8, 15, 16, etc.). For example, DAC unit cells 210a-210n can receive data in digital format from processing circuitry 215 and then output a signal corresponding to data in analog format. In some embodiments, the output signal from the DAC unit cells can be in the form of a current signal and / or a voltage signal.

[0037] Each of DAC unit cells 210a-210n is configured to generate an output signal that is summed to provide an analog output signal as output signal 225. To calibrate DAC unit cells 210a-210n, each output signal from each DAC unit cell 210a-210n can be compared to a different cell to determine a difference between the signals generated by each of DAC unit cells 210a-210n. Detector 220 is connected to DAC unit cells 210a-210n and is configured to measure a difference between the output signals of DAC unit cells 210a-210n. Detector 220 determines a difference (e.g., an error) by comparing (e.g., subtracting) the output signals of two DAC unit cells to each other. In some embodiments, detector 220 is an amplitude comparator configured to compare magnitudes of the output signals or a comparator / timing circuit configured to compare circuit delays. In some embodiments, comparisons can be made using latches, subtractors, and other circuits. In some embodiments, DAC unit cells 210a-210n use a fixed connection to the DAC output (summed output) for output signal 225. Two selected DAC unit cells of DAC unit cells 210a-210n are selected and summed. The two selected DAC unit cells 210a-210n can be selected by providing digital data to only the two cells and not providing data (a ground signal to the other DAC unit cells) or otherwise shutting off or preventing contribution from the other DAC unit cells at the summed output. In some embodiments, the two selected cells are provided with data having opposite signs from each other (inverted data) and summed (e.g., to achieve a subtracted signal as output signal 225). Detector 220 receives the output signals from the selected unit cells for comparison (e.g., analog signals that have been subtracted from each other). In some embodiments, detector 220 can compare the difference to a threshold to indicate a timing error or an amplitude error. In some embodiments, detector 220 can process or filter the difference to indicate a timing error or an amplitude error.

[0038] For example, Figure 3A comparison system 300 is illustrated that compares the output signals of two of the DAC unit cells 210a and 210b by a detector 220. In some embodiments, the DAC unit cell 210a receives a positive signal "data" as input, while the DAC unit cell 210b receives a negative signal "data b". Thus, the output signal generated by the DAC unit cell 210a will be positive, and the output signal generated by the DAC unit cell 210b will be negative. In some embodiments, the negative signal is the inverse of the positive signal. In some embodiments, the data signal is a differential signal and the negative signal is an inverted differential signal. Various circuits can be used to provide the positive and negative signals or to invert the data signal.

[0039] Figure 4 A waveform graph 400 is illustrated that demonstrates the comparison made by the detector 220 between the DAC unit cell 210a and the DAC unit cell 210b as Figure 3 shown in FIG. 3. The waveform graph 400 includes a clock signal 405, which is a signal illustrating the clock timing of the DAC 205. The waveform graph 400 also includes a data signal 410, which is a signal illustrating the data received by the DAC unit cell 210a. In some embodiments, the DAC unit cell 210b receives a signal opposite the data signal 410. The waveform graph 400 also includes an output signal 415, which is a signal illustrating the output of the DAC unit cell 210a. The waveform graph 400 also includes an output signal 420, which is a signal illustrating the output of the DAC unit cell 210b. The output signal 420 is summed with the output signal 415 to produce one total output signal 425. As can be seen in the total output signal 425, there is a difference in amplitude between the output signal 415 and the output signal 420. This indicates that the DAC unit cell 210a and the DAC unit cell 210b do not produce the same amplitude (e.g., have an amplitude error relative to each other). In some embodiments, the DAC unit cells 210a and 210b are calibrated to produce output signals with the same amplitude. The detector 220 provides a control signal 427 to the calibration engine representing the error associated with the output signal 425. According to some embodiments, the method for calibrating the amplitudes of the DAC unit cells 210a-210n is described in more detail below with respect to Figure 7

[0040] Figure 5 A waveform graph 500 is illustrated that demonstrates the comparison made by the detector 220 between the DAC unit cell 210a and the DAC unit cell 210b as Figure 3 ​The comparison made by detector 220 between DAC unit cell 210a and DAC unit cell 210b is shown in waveform graph 500. Waveform graph 500 includes a clock signal 505, which is a signal representative of the clock timing of DAC 205. Waveform graph 500 also includes a data signal 510, which is the data received by DAC unit cell 210a and DAC unit cell 210b. Waveform graph 500 also includes an output signal 515, which is the signal at the output of DAC unit cell 210a. Waveform graph 500 also includes an output signal 520, which is the output of DAC unit cell 210b. Output signal 520 can be summed with output signal 515 to produce one total output signal 525. As can be seen in total output signal 525, there is a delay between the rising edge of output signal 515 and the falling edge of output signal 520. This indicates that DAC unit cell 210a and DAC unit cell 210b are not calibrated to produce output signals with the same timing schedule and need to be calibrated. Detector 220 provides a control signal 527 representative of the error or difference associated with output signal 525 to calibration engine. According to some embodiments, the method for calibrating the timing of DAC unit cells 210a-210n is described in more detail below with respect to Figure 8 The method for calibrating the timing of DAC unit cells 210a-210n is described in more detail below.

[0041] Figure 6 A comparison and calibration system 600 configured to compare the output signals of two DAC unit cells and calibrate at least one of the DAC unit cells based on the comparison of the output signals is illustrated. Comparison and calibration system 600 includes a first DAC unit cell 605a and a second DAC unit cell 605b. First DAC unit cell 605a is configured to receive a positive data signal, while second DAC unit cell 605b is configured to receive a negative data signal. Each of DAC unit cells 605a and 605b also receives a clock signal to adjust the timing of the DAC unit cell. Each of DAC unit cells 605a and 605b also includes a calibration input (input 625 and input 635). In some embodiments, the calibration input can be fixed if the DAC unit cell is a reference cell. A reference cell can be defined as a DAC unit cell that is used as a reference to calibrate other cells within the DAC. For example, in Figure 6 In the example of FIG. 6, DAC unit cell 605a can be a reference cell and thus have a fixed calibration input 625. In some embodiments, the calibration input 625 can be variable and dynamic based on input received from calibration engine 615. For example, DAC unit cell 605b includes a calibration input 635 for adjusting the amplitude of the output signal produced by DAC unit cell 605b.

[0042] The calibration engine 615 can be configured to receive input from the detector 610 (similar to the detector 220 described in more detail above) and determine a calibration output signal 635 for one or more DAC unit cells based on the input. In some embodiments, the amplitude of the output signal generated by the DAC unit cells can continue to be adjusted based on the calibration output signal 635 generated by the calibration engine 615 until the error signal from the detector 610 is reduced to an acceptable range. After calibration by the calibration engine 615, the DAC unit cell 605a and the DAC unit cell 605b have the same amplitude and / or timing. The calibration output signal can adjust the amplitude and timing. In some embodiments, the calibration output signal adjusts the gain of the second DAC unit cell 605b to adjust the amplitude or timing.

[0043] Examples of the adjustment of the DAC unit cells 605a and 605b include configurations to adjust the drive strength for generating or providing a current and / or configurations to adjust the amplitude of the current 328. The calibrator 350 can determine a target configuration or target setting for each DAC unit cell 605a and 605b and provide a configuration signal to each DAC unit cell 605a and 605b indicating the determined configuration or setting. For example, if the calibration engine 615 determines that the DAC unit cell 605a is faster than the DAC unit cell 605b based on one or more feedback signals (e.g., from the detector 610), the calibration engine 615 can generate a configuration signal causing the DAC unit cell 605a to decrease the drive strength to provide the current more slowly. For example, if the calibrator 350 determines that the DAC unit cell 605a provides a current having an amplitude that is greater than the amplitude of the current provided by the DAC unit cell 605b based on one or more feedback signals, the calibration engine 615 can generate a configuration signal (by adjusting the gain or drive strength) causing the DAC unit cell 605a to provide the current 328 having a lower amplitude. In some examples, bias values, transconductance, and current steering in the DAC unit cells 605a and 605b can be adjusted to calibrate the DAC unit cells for proper amplitude and timing.

[0044] Figure 7 is a flowchart depicting a process 700 for calibrating an amplitude of one or more DAC unit cells according to an embodiment. In some embodiments, the process 700 is performed by the DAC calibration system 200. In other embodiments, the process 700 is performed by other entities. In some embodiments, the process 700 includes more, fewer, or different steps than those shown in Figure 7

[0045] ​At step 705, the DAC calibration system 200 designates one of the number of DAC unit cells as a reference cell. As mentioned above, the reference cell can be defined as the DAC unit cell that is used as a reference for calibrating the other cells within the DAC. In some embodiments, the reference cell can be arbitrarily designated as any DAC unit cell with an equal opportunity of being designated as the reference cell. At step 710, the DAC calibration system 200 determines which of the number of DAC unit cells has the lowest amplitude of output signal other than the reference cell. The DAC calibration system 200 can determine which DAC unit cell has the lowest amplitude by measuring the amplitude of the output signal of each of the DAC unit cells by the detector 220 and comparing the amplitudes to determine the lowest amplitude. At step 715, the DAC calibration system 200 compares the amplitude of the lowest amplitude DAC unit cell determined at step 710 to the reference cell designated at step 705. If the amplitude of the reference cell designated at step 705 is higher than the DAC unit cell determined to have the lowest amplitude, then the DAC calibration system 200 calibrates (e.g., changes, modifies, updates, etc.) the reference cell to match the amplitude of the lowest amplitude DAC unit cell at step 720. In some embodiments, the reference DAC unit cell is selected and each remaining cell is compared to the reference cell. If the reference cell has a higher amplitude output, the reference cell is adjusted to have the output of that cell. The adjusted reference cell is compared to the remaining cells in this way to ensure that the reference cell has the lowest amplitude. At step 725, the DAC calibration system 200 calibrates the remaining portion of the number of DAC unit cells to match the amplitude of the reference cell. In some embodiments, the highest value can be utilized instead of the lowest value.

[0046] Figure 8 is a flowchart depicting a process 800 for calibrating a delay of one or more DAC unit cells. In some embodiments, the process 800 is performed by the DAC calibration system 200. In other embodiments, the process 800 is performed by other entities. In some embodiments, the process 800 includes more, fewer, or different steps than those shown in Figure 8

[0047] ​At step 805, the DAC calibration system 200 designates one of the plurality of DAC unit cells as a reference cell. As mentioned above, the reference cell can be defined as the DAC unit cell that is used as a reference for calibrating the other cells within the DAC. In some embodiments, the reference cell can be arbitrarily designated as any of the DAC unit cells with equal opportunity to be designated as the reference cell. At step 810, the DAC calibration system 200 determines which of the plurality of DAC unit cells has the longest rising and / or falling delay other than the reference cell. At step 815, the DAC calibration system 200 compares the delay of the longest delay DAC unit cell determined at step 810 to the reference cell designated at step 805. In some embodiments, the reference DAC unit cell is selected and each remaining cell is compared to the reference cell. If the reference cell has a shorter delay, the reference cell is adjusted to have the delay of that cell. The adjusted reference cell is compared to the remaining cells in this manner to ensure that the reference cell has the slowest timing. At step 820, if the reference cell has a shorter delay, the DAC calibration system 200 calibrates the reference cell to match the delay of the longest delay DAC unit cell. At step 825, the DAC calibration system 200 calibrates the remainder of the plurality of DAC unit cells to match the delay of the reference cell. In some embodiments, the reference cell has the fastest timing instead of the slowest timing. In this case, if the reference cell has a longer delay, the reference cell is adjusted to have the delay of that cell. The adjusted reference cell is compared to the remaining cells in this manner to ensure that the reference cell has the fastest timing. At step 820, if the reference cell has a shorter delay, the DAC calibration system 200 calibrates the reference cell to match the delay of the shortest delay DAC unit cell. At step 825, the DAC calibration system 200 calibrates the remainder of the plurality of DAC unit cells to match the delay of the reference cell.

[0048] The term "coupled" and variations thereof, encompass two components directly or indirectly engaging one another. The term "electrically coupled" and variations thereof, encompass two components directly or indirectly engaging one another through an electrically conductive material (e.g., a metal or copper trace). Such engagement can be stationary (e.g., permanent or fixed) or movable (e.g., removable or releasable). Such engagement can be achieved with the two components directly coupled to one another, the two components coupled to one another using separate intermediary components and any additional intermediary components coupled to one another, or the two components coupled to one another using an intermediary component formed integrally with one of the two components as a single unitary body. If "coupled" or variations thereof are modified by an additional term (e.g., directly coupled), the general definition of "coupled" provided above is modified by the plain language meaning of the additional term (e.g., "directly coupled" means engagement of two components without any separate intermediary components), resulting in a definition narrower than the general definition of "coupled" provided above. Such coupling can be mechanical, electrical, or fluidic.

[0049] The foregoing overview of features of several embodiments enables a person of ordinary skill in the art to better understand aspects of the present disclosure. The person of ordinary skill in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. The person of ordinary skill in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0050] It should be noted that certain paragraphs of the present disclosure can refer to terminology related to transmission spatial streams, sounding frames, responses, and subsets of devices (e.g., "first" and "second") for the purpose of identifying or distinguishing from one another or others. These terms are not intended to relate the entities (e.g., first device and second device) only in time or according to order, although in some cases these entities can include such a relationship. These terms also do not limit the number of possible entities that can operate within a system or environment. It should be understood that the systems described above can provide multiple instances of any or each of the described components, and these components can be disposed on independent machines, or in some embodiments, multiple machines in a distributed system. In addition, the systems and methods described above can be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (for example, a soft disc, a hard disc, a CD-ROM, a flash memory card, a PROM, a RAM, a ROM, or a magnetic tape). The programs can be implemented in any programming language, such as LISP, PERL, C, C++, C#, or in any byte code language such as JAVA. The software programs or executable instructions can be stored on or in one or more articles of manufacture as object code. In some embodiments, the DAC is used as an integrated circuit in a transmitter for wireless communication. The DAC is disposed on an integrated circuit that includes a calibration engine. In some embodiments, the DAC and the calibration engine are disposed in a single-chip or multi-chip integrated package.

[0051] While the above written description of the method and system enables one of ordinary skill in the art to make and use embodiments thereof, those of ordinary skill in the art should understand that there are alterations, modifications, and equivalents to the specific embodiments, methods, and examples described herein that fall within the scope and spirit of the present disclosure. Accordingly, the method and system should not be limited to the described embodiments, methods, and examples, but should be given the full scope of the appended claims and the full scope of equivalents to which they are entitled.

Claims

1. A digital-to-analog converter (DAC), comprising: Multiple unit cells configured to receive digital inputs from processing circuitry and convert the digital inputs into analog outputs; The engine, which is configured to: One of the plurality of unit cells is designated as the reference cell with a first value; and The first value is calibrated using the value of the unit cell, wherein the value is a delay value, and wherein the digital input is provided to the first unit cell and has a positive or negative sign opposite to that provided to the reference cell.

2. The DAC of claim 1, wherein the engine is configured to calibrate the remainder of the plurality of unit cells to match the first value.

3. The DAC of claim 1, wherein the analog outputs are combined to produce a total analog output by summing at least the second analog outputs from the first analog output, wherein the total analog output includes a combination of analog outputs from the plurality of unit cells.

4. The DAC according to claim 1, wherein the first value is the minimum or maximum value of the amplitude of the analog output.

5. The DAC according to claim 1, wherein the first value is the lowest or highest value of the timing of the analog output.

6. The DAC of claim 1, wherein the DAC is part of a transmitter for wireless communication.

7. A method for calibrating a digital-to-analog converter (DAC), the method comprising: Designate one of the multiple DAC unit cells as the reference cell; The reference cell is adjusted to have a first value with an output signal at the first output; The output signal at the output of the remaining DAC unit cell in the plurality of DAC unit cells is compared with the first output; and The remaining DAC unit cells of the plurality of DAC unit cells are adjusted according to the first value.

8. The method of claim 7, wherein the comparison uses a first digital input at one of the remaining DAC unit cells, wherein the first digital input is at least one of a current signal and a voltage signal.

9. The method of claim 7, wherein the first value is the minimum or maximum value of the amplitude of the output signal at the output.

10. The method of claim 7, wherein the first value is the lowest or highest value of the amplitude or velocity of the output signal at the output.

11. The method of claim 10, wherein the minimum value of the speed is the longest delay or the maximum value of the speed is the shortest delay.

12. The method of claim 7, wherein the DAC is a transmitter for wireless communication.

13. The method of claim 7, wherein the adjustment provides a change in the drive strength.

14. A calibration system for a digital-to-analog converter (DAC), the DAC being configured to receive digital inputs through a plurality of DAC unit cells and convert the digital inputs into analog signals, the analog signals being summed into an output signal, the calibration system comprising: A detector configured to determine, at a summed output associated with the output signal, the difference between a first value of a first cell of the DAC unit cell and a reference value of a reference cell; and A calibration engine configured to adjust the first cell in response to an error so that the first value matches the reference value.

15. The calibration system of claim 14, wherein the digital input is at least one of a current signal and a voltage signal, and wherein the reference value is the lowest or highest value of amplitude or velocity provided by the plurality of DAC unit cells.

16. The calibration system of claim 14, wherein the reference cell and the first cell receive opposite digital inputs.

17. The calibration system of claim 14, wherein the detector and the calibration engine are used to adjust the remaining cells in the plurality of DAC unit cells.

18. The calibration system of claim 14, wherein the DAC is a transmitter for wireless communication and is disposed on an integrated circuit containing the calibration engine.

19. The calibration system of claim 14, wherein the reference cell is one of the plurality of DAC unit cells.

20. A digital-to-analog converter (DAC) comprising: Multiple unit cells configured to receive digital inputs from processing circuitry and convert the digital inputs into analog outputs; The engine, which is configured to: One of the plurality of unit cells is designated as the reference cell with a first value; The first value is calibrated using the lowest or highest value of the unit cell; and The digital input is provided to the first unit cell and has a positive or negative sign opposite to that provided to the reference cell.

21. The DAC of claim 20, wherein the minimum value is a delay value.

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