Integrated circuit, chip and electronic device
By designing the resistance layer in the integrated circuit across the gate of multiple MOS tubes without spanning the source and drain regions, the problem of unbalanced influence of resistance on MOS tubes in the integrated circuit is solved, and wafer utilization is improved and The compactness of integrated circuits.
Patent Information
- Application Number
- CN202311447060.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-01
- Publication Date
- 2025-02-21
- Estimated Expiration
- 2043-11-01
AI Technical Summary
In the CMOS manufacturing process of integrated circuits, the resistor and MOS tube are respectively arranged in different regions of the substrate, resulting in a low integration degree per unit area of the silicon wafer, resulting in a loss of area cost, and the impact of the resistance on the MOS tube is uneven.
Design an integrated circuit in which the resistive layer spans the gate of multiple MOS tubes, but not the source and drain regions, is connected to the metal connecting layer through the resistance insulation layer and contact holes, limiting the resistance to the MOS tube. Influence in the gate.
The wafer utilization efficiency is improved, and the impact of resistance on MOS tubes is reduced, especially in the source and drain regions, achieving a more compact and reasonable integrated circuit structure.
Smart Images
Figure CN117613037B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuits, and in particular to an integrated circuit, a chip and an electronic device. Background Art
[0002] In the traditional CMOS manufacturing process of integrated circuits, resistors and MOS tubes are often placed in different areas of the substrate. In order to ensure the consistency of the subsequent CMP (chemical mechanical polishing) step, it is necessary to insert a dummy pattern of the active area (AA) below where resistors are used in a large area to increase the active area density (AAdensity) to meet manufacturing requirements. As a result, the area below the resistor array is not actually used to make useful devices for the circuit, and the integration density per unit area of the silicon wafer is low, resulting in a certain degree of area cost loss.
[0003] In some integrated circuits, resistors are formed on the active layer, but the structures of these integrated circuits are not compact and reasonable. Summary of the invention
[0004] Based on the above situation, the main purpose of the present invention is to provide an integrated circuit, a chip and an electronic device, which can reduce the influence of resistance on MOS tubes while making the integrated circuit structure compact and the wafer utilization rate high.
[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows:
[0006] An integrated circuit comprises a resistor and a plurality of MOS transistors arranged side by side, each MOS transistor comprises a gate, and a channel region, a source region and a drain region located in an active layer, and there is a gap between adjacent MOS transistors, and the integrated circuit further comprises a resistor insulating layer formed on the surface of the gate, the resistor insulating layer spans across a plurality of gates and the gaps between adjacent MOS transistors; a resistor layer is formed on the resistor insulating layer, the resistor layer spans across a plurality of gates and the gaps between adjacent MOS transistors, the resistor is formed by the resistor layer, and the projection of the resistor layer toward the active layer does not fall into the source region and the drain region; the resistor layer is connected to respective endpoints in a metal connection layer located above the resistor layer through resistor contact holes located at both ends of the resistor layer, the gate through the gate contact hole, the source region through the source contact hole, and the drain region through the drain contact hole, wherein the projections of the resistor contact hole, the gate contact hole, the source contact hole and the drain contact hole toward the active layer do not overlap each other, and the gate contact hole is staggered from the resistor layer.
[0007] Preferably, the thickness of the resistive insulating layer is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold.
[0008] Preferably, the active layers of the multiple MOS transistors are located in a same well of the active substrate.
[0009] Preferably, the projection of the resistance layer toward the gate is located in the middle of the gate.
[0010] In the above scheme, a resistance layer is provided on a plurality of MOS tubes, and the resistance layer 400 spans across the gates on the plurality of MOS tubes, thereby improving the utilization efficiency of the wafer. At the same time, since the resistance layer does not span across the source region and the drain region, the influence of the resistance on the MOS tube can be limited to the gate, while reducing the influence on the source region and the drain region.
[0011] The present invention also provides an integrated circuit, comprising a resistor and a plurality of MOS tubes arranged side by side, each MOS tube comprising a gate, and a channel region, a source region and a drain region located in an active layer, and there is a gap between adjacent MOS tubes, the integrated circuit also comprises a resistor insulating layer formed on the surface of the gate, the resistor insulating layer spans across a plurality of gates, a plurality of source regions, a plurality of drain regions, and the gap between adjacent MOS tubes; a resistor layer is formed on the resistor insulating layer, the resistor layer spans across a plurality of gates, a plurality of source regions, a plurality of drain regions, and the gap between adjacent MOS tubes, the resistor is formed by the resistor layer; the resistor layer is connected to respective endpoints in a metal connection layer located above the resistor layer through resistor contact holes located at both ends of the resistor layer, the gate through the gate contact hole, the source region through the source contact hole, and the drain region through the drain contact hole, wherein the projections of the resistor contact hole, the gate contact hole, the source contact hole and the drain contact hole toward the active layer do not overlap each other, and the source contact hole and the drain contact hole are staggered from the resistor layer respectively.
[0012] Preferably, the thickness of the resistive insulating layer is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold, so as to prevent the voltage formed on the resistive layer from affecting the channel region.
[0013] Preferably, the active layers of the multiple MOS transistors are located in a same well of the active substrate.
[0014] Preferably, a projection of the resistance layer toward the gate is located in the middle of the gate, the source region and the drain region.
[0015] In the above scheme, a resistance layer is provided on multiple MOS tubes, thereby improving the utilization efficiency of the wafer. At the same time, since the resistance layer spans across the gates, multiple source regions, and multiple drain regions on the multiple MOS tubes, the influence of the resistance on the MOS tubes can be dispersed to the gate, source region, and drain region.
[0016] The present invention also provides an integrated circuit, comprising a resistor and a MOS tube, wherein the MOS tube comprises a gate, and a channel region, a source region and a drain region located in an active layer, and the integrated circuit further comprises a resistive insulating layer formed on the surface of the gate, wherein the projection of the resistive insulating layer toward the gate is smaller than and falls into the region of the gate; a resistive layer is formed on the resistive insulating layer, wherein the projection of the resistive layer toward the gate is smaller than and falls into the region of the gate, and the projection of the resistive layer toward the active layer does not fall into the source region and the drain region, and the resistor is formed by the resistive layer; the resistive layer is connected to respective end points in a metal connection layer located above the resistive layer through resistive contact holes located at both ends of the resistive layer, the gate through the gate contact hole, the source region through the source contact hole, and the drain region through the drain contact hole, respectively, wherein the projections of the resistive contact hole, the gate contact hole, the source contact hole and the drain contact hole toward the active layer do not overlap with each other.
[0017] Since the projection of the resistance layer toward the gate is smaller than and falls within the region of the gate, the length and width of the resistance layer can be set according to actual needs. The length along the drain-source connection direction can be set longer, and the length in the direction perpendicular to the connection direction can also be set longer.
[0018] Preferably, the thickness of the resistive insulating layer is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold, so as to prevent the voltage formed on the resistive layer from affecting the channel region.
[0019] Preferably, the projection of the resistance layer toward the gate is located in the middle of the gate.
[0020] The present invention also provides a chip, comprising any one of the integrated circuits.
[0021] The invention also provides an electronic device, comprising the chip.
[0022] In the above scheme, a resistance layer is provided on a MOS tube, thereby improving the utilization efficiency of the wafer. At the same time, since the projection of the resistance layer toward the gate is smaller than and falls into the region of the gate, the influence of the resistance on the MOS tube can be limited to the gate, while reducing the influence on the source region and the drain region.
[0023] Other beneficial effects of the present invention will be explained in the specific implementation manner through the introduction of specific technical features and technical solutions. Through the introduction of these technical features and technical solutions, those skilled in the art should be able to understand the beneficial technical effects brought about by the technical features and technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
[0025] Figure 1 A schematic cross-sectional view of an integrated circuit according to a preferred embodiment of the present invention;
[0026] Figure 2 for Figure 1 A schematic top view of an integrated circuit of an embodiment;
[0027] Figure 3 is a schematic cross-sectional view of an integrated circuit according to another preferred embodiment of the present invention;
[0028] Figure 4 for Figure 3 A schematic top view of an integrated circuit of an embodiment;
[0029] Figure 5 is a schematic cross-sectional view of an integrated circuit according to another preferred embodiment of the present invention;
[0030] Figure 6 for Figure 5 A schematic top view of an integrated circuit of an embodiment;
[0031] Figure 7 FIG. 4 is a schematic cross-sectional view of an integrated circuit according to another preferred embodiment of the present invention. DETAILED DESCRIPTION
[0032] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. In order to avoid confusing the essence of the present invention, known methods, processes, procedures, and components are not described in detail.
[0033] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.
[0034] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprising" and similar words should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".
[0035] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0036] Example 1
[0037] Figure 1 and 21 is a schematic diagram of an integrated circuit of an embodiment of the present invention, the integrated circuit includes a resistor 400, a resistor insulating layer 300 and a plurality of MOS tubes 200 arranged side by side (such as the three MOS tubes 200 shown in the figure). In this embodiment, the resistor 400 is formed on the plurality of MOS tubes 200. The multiple MOS transistors 200 are arranged in sequence, and each MOS transistor 200 includes a gate 210 (composed of a metal layer located on a channel region 230), and the channel region 230, the source region 240 and the drain region 250 located on the active layer 110. There is a gap between adjacent MOS transistors 200, for example, the adjacent MOS transistors are isolated by shallow trench isolation (STI) 120; a resistive insulating layer 300 is formed on the surface of the gate 210, and the resistive insulating layer 300 spans across the multiple gates 210 and the gaps between adjacent MOS transistors 200; a resistor layer 400 is formed on the resistive insulating layer 300, and the resistor layer 400 also spans across the multiple gates 210 and the gaps between adjacent MOS transistors 200, and the resistor 400 is formed by the resistor layer 400, and the projection of the resistor layer 400 toward the active layer 110 does not fall into the source region 240 and the drain region 250, that is, the resistor layer 400 does not span the source region 240 and the drain region 250. It can be understood that the source region 240 and the drain region 250 in the figure can be swapped with each other.
[0038] The resistor layer 400 is connected to respective endpoints 411 in a metal connection layer (e.g., the first metal layer M1 closest to the active layer 110) above the resistor layer 400 through resistor contact holes 410 (i.e., metal pillars) located at both ends of the resistor layer 400. The resistor 400 can be connected to other components in the integrated circuit through these endpoints 411; the gate 210 is connected to corresponding endpoints 212 in a metal connection layer above the resistor layer 400 through the gate contact hole 211 (i.e., metal pillars). The gate 210 can be connected to other components in the integrated circuit through the endpoint 212; the source region 240 is connected to the source region 241 through the source contact hole 241 (i.e., metal pillars). ) is connected to the corresponding endpoint 242 in the metal connection layer above the resistor layer 400, and the source region 240 can be connected to other components in the integrated circuit through the endpoint 242; the drain region 250 is connected to the corresponding endpoint 252 in the metal connection layer above the resistor layer 400 through the drain contact hole 251 (i.e., the metal column), and the drain region 250 can be connected to other components in the integrated circuit through the endpoint 252; wherein, the projections of the resistor contact hole 410, the gate contact hole 211, the source contact hole 241 and the drain contact hole 251 toward the active layer 110 do not overlap each other, and the gate contact hole 211 is staggered with the resistor layer 400.
[0039] In this embodiment, a resistance layer 400 is provided on the plurality of MOS transistors 200 , and the resistance layer 400 spans across the gates 210 on the plurality of MOS transistors 200 , but does not span across the source region 240 and the drain region 250 , so that the influence of the resistor 400 on the MOS transistor 200 can be limited to the gate 210 , while reducing the influence on the source region 240 and the drain region 250 .
[0040] In some embodiments, the thickness of the resistive insulating layer 300 is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer 300 is greater than a dielectric constant threshold to prevent the voltage formed on the resistive layer 400 from affecting the channel region 230. For example, when the gate 210 is at a low level, the potential on the resistive layer 400 is prevented from causing the channel region 230 to be turned on.
[0041] The active layers 110 of the multiple MOS transistors 200 may be located in the same well of the active substrate 100, or may be arranged in different wells. In some embodiments, the active layers 110 of the multiple MOS transistors 200 are located in the same well of the active substrate 100, so that the parasitic capacitance between the resistance layer 400 and different MOS transistors 200 is kept consistent as much as possible, which may bring some benefits, such as simpler circuit design.
[0042] In some embodiments, the projection of the resistance layer 400 toward the gate 210 is located in the middle of the gate 210 , which can bring some advantages, such as a more balanced effect of the resistance layer 400 on the gate 210 and the channel region 230 , which facilitates circuit design.
[0043] Other metal capacitors such as MOM or MIM can be stacked on the resistor 400. It can be seen that this solution is compatible with the integrated circuit structure of traditional metal capacitors.
[0044] Example 2
[0045] Figure 3 and 41 is a schematic diagram of an integrated circuit of another embodiment of the present invention, the integrated circuit includes a resistor 400, a resistor insulating layer 300 and a plurality of MOS tubes 200 arranged side by side (such as the three MOS tubes 200 shown in the figure). In this embodiment, the resistor 400 is formed on the plurality of MOS tubes 200. The multiple MOS transistors 200 are arranged in sequence, and each MOS transistor 200 includes a gate 210 (composed of a metal layer located on a channel region 230), and a channel region 230, a source region 240, and a drain region 250 located on an active layer 110. There is a gap between adjacent MOS transistors 200, for example, the adjacent MOS transistors are isolated by shallow trench isolation (STI) 120; a resistive insulating layer 300 is formed on the surface of the gate 210, and the resistive insulating layer 300 spans across multiple gates 210, multiple source regions 240, multiple drain regions 250, and the gaps between adjacent MOS transistors 200; a resistive layer 400 is formed on the resistive insulating layer 300, and the resistive layer 400 also spans across multiple gates 210, multiple source regions 240, multiple drain regions 250, and the gaps between adjacent MOS transistors 200, and the resistor 400 is formed by the resistive layer 400. It can be understood that the source region 240 and the drain region 250 in the figure can be interchanged with each other.
[0046] The resistor layer 400 is connected to respective endpoints 411 in a metal connection layer (e.g., the first metal layer M1 closest to the active layer 110) above the resistor layer 400 through resistor contact holes 410 (i.e., metal pillars) located at both ends of the resistor layer 400. The resistor 400 can be connected to other components in the integrated circuit through these endpoints 411; the gate 210 is connected to corresponding endpoints 212 in the metal connection layer above the resistor layer 400 through the gate contact hole 211 (i.e., metal pillars). The gate 210 can be connected to other components in the integrated circuit through the endpoint 212; the source region 240 is connected to the resistor region 241 through the source contact hole 241 (i.e., metal pillar). The source region 240 is connected to the corresponding endpoint 242 in the metal connection layer above the resistor layer 400, and the source region 240 can be connected to other components in the integrated circuit through the endpoint 242; the drain region 250 is connected to the corresponding endpoint 252 in the metal connection layer above the resistor layer 400 through the drain contact hole 251 (i.e., the metal column), and the drain region 250 can be connected to other components in the integrated circuit through the endpoint 252; wherein, the projections of the resistor contact hole 410, the gate contact hole 211, the source contact hole 241 and the drain contact hole 251 toward the active layer 110 do not overlap each other, and the source contact hole 241 and the drain contact hole 251 are staggered with the resistor layer 400, respectively.
[0047] In this embodiment, a resistance layer 400 is provided on the plurality of MOS transistors 200 , and the resistance layer 400 spans across the gates 210 , the plurality of source regions 240 , and the plurality of drain regions 250 on the plurality of MOS transistors 200 , so that the influence of the resistance 400 on the MOS transistors 200 can be dispersed to the gates 210 , the source regions 240 , and the drain regions 250 .
[0048] In some embodiments, the thickness of the resistive insulating layer 300 is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer 300 is greater than a dielectric constant threshold to prevent the voltage formed on the resistive layer 400 from affecting the channel region 230. For example, when the gate 210 is at a low level, the potential on the resistive layer 400 is prevented from causing the channel region 230 to be turned on.
[0049] The active layers 110 of the multiple MOS transistors 200 may be located in the same well of the active substrate 100, or may be arranged in different wells. In some embodiments, the active layers 110 of the multiple MOS transistors 200 are located in the same well of the active substrate 100, so that the parasitic capacitance between the resistance layer 400 and different MOS transistors 200 is kept consistent as much as possible, which may bring some benefits, such as simpler circuit design.
[0050] In some embodiments, the projection of the resistance layer 400 toward the gate 210 is located in the middle of the gate 210, the source region 240, and the drain region 250. This can bring some advantages, such as a more balanced effect of the resistance layer 400 on the gate 210, the channel region 230, the source region 240, and the drain region 250, which facilitates circuit design.
[0051] Other metal capacitors such as MOM or MIM can be stacked on the resistor 400. It can be seen that this solution is compatible with the integrated circuit structure of traditional metal capacitors.
[0052] Example 3
[0053] Figure 5 and 6Schematic diagram of an integrated circuit of another embodiment of the present invention, the integrated circuit includes a resistor 400, a resistor insulating layer 300 and a MOS transistor 200. In this embodiment, the resistor 400 is formed on the MOS transistor 200. The MOS transistor 200 includes a gate 210 (composed of a metal layer located on a channel region 230), and a channel region 230, a source region 240 and a drain region 250 located on an active layer 110; the resistor insulating layer 300 is formed on the surface of the gate 210, and the projection of the resistor insulating layer 300 toward the gate 210 is smaller than and falls into the region of the gate 210; the resistor layer 400 is formed on the resistor insulating layer 300, and the projection of the resistor layer 400 toward the gate 210 is smaller than and falls into the region of the gate 210, and the projection of the resistor layer 400 toward the active layer 110 does not fall into the source region 240 and the drain region 250, and the resistor 400 is formed by the resistor layer 400. It can be understood that the source region 240 and the drain region 250 in the figure can be swapped with each other.
[0054] The resistor layer 400 is connected to respective endpoints 411 in a metal connection layer (e.g., the first metal layer closest to the active layer 110) above the resistor layer 400 through resistor contact holes 410 (i.e., metal pillars) located at both ends of the resistor layer 400. The resistor 400 can be connected to other components in the integrated circuit through these endpoints 411. The gate 210 is connected to corresponding endpoints 212 in a metal connection layer above the resistor layer 400 through the gate contact hole 211 (i.e., metal pillars). The gate 210 can be connected to other components in the integrated circuit through the endpoint 212. The source region 240 is connected to the source region 240 through the source contact hole 211. 241 (i.e., metal pillar) is connected to the corresponding endpoint 242 in the metal connection layer above the resistor layer 400, and the source region 240 can be connected to other components in the integrated circuit through the endpoint 242; the drain region 250 is connected to the corresponding endpoint 252 in the metal connection layer above the resistor layer 400 through the drain contact hole 251 (i.e., metal pillar), and the drain region 250 can be connected to other components in the integrated circuit through the endpoint 252; wherein, the projections of the resistor contact hole 410, the gate contact hole 211, the source contact hole 241 and the drain contact hole 251 toward the active layer 110 do not overlap with each other.
[0055] In this embodiment, a resistance layer 400 is provided on a MOS transistor 200 , and the projection of the resistance layer 400 toward the gate 210 is smaller than and falls into the region of the gate 210 , so that the influence of the resistor 400 on the MOS transistor 200 can be limited to the gate 210 , while the influence on the source region 240 and the drain region 250 is reduced.
[0056] In some embodiments, the thickness of the resistive insulating layer 300 is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer 300 is greater than a dielectric constant threshold to prevent the voltage formed on the resistive layer 400 from affecting the channel region 230. For example, when the gate 210 is at a low level, the potential on the resistive layer 400 is prevented from causing the channel region 230 to be turned on.
[0057] In some embodiments, the projection of the resistance layer 400 toward the gate 210 is located in the middle of the gate 210, the source region 240 and the drain region 250. This can bring some advantages, such as a more balanced effect of the resistance layer 400 on the gate 210 and the channel region 230, which facilitates circuit design.
[0058] like Figure 7 As shown, MOM capacitors, such as multiple MOM layers 510, 520 and 530, can be stacked on top of the resistor 400; in other embodiments, other metal capacitors such as MIM can be stacked on top of the resistor 400. It can be seen that this solution is compatible with the integrated circuit structure of traditional metal capacitors.
[0059] The present invention also provides a chip, which includes the integrated circuit of the foregoing embodiment.
[0060] The present invention also provides an electronic device, which includes the chip.
[0061] Those skilled in the art will appreciate that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.
[0062] Those skilled in the art will appreciate that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.
[0063] It should be understood that the above-mentioned embodiments are merely illustrative and not restrictive. Without departing from the basic principles of the present invention, various obvious or equivalent modifications or substitutions that can be made by those skilled in the art to the above-mentioned details will all be included in the scope of the claims of the present invention.
Claims
1. An integrated circuit comprising a resistor and a plurality of MOS transistors arranged side by side, each MOS transistor comprising a gate, and a channel region, a source region and a drain region located in an active layer, and there is a gap between adjacent MOS transistors, characterized in that: The integrated circuit further comprises a resistive insulating layer formed on the surface of the gate, the resistive insulating layer spanning across multiple gates and the intervals between adjacent MOS tubes; a resistive layer is formed on the resistive insulating layer, the resistive layer spanning across multiple gates and the intervals between adjacent MOS tubes, the resistor is formed by the resistive layer, and the projection of the resistive layer toward the active layer does not fall into the source region and the drain region; The resistor layer is connected to respective endpoints in a metal connection layer above the resistor layer through resistor contact holes at both ends of the resistor layer, the gate through a gate contact hole, the source region through a source contact hole, and the drain region through a drain contact hole, wherein projections of the resistor contact hole, the gate contact hole, the source contact hole, and the drain contact hole toward the active layer do not overlap with each other, and the gate contact hole is staggered with the resistor layer.
2. The integrated circuit according to claim 1, characterized in that The thickness of the resistive insulating layer is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold.
3. The integrated circuit according to claim 1 or 2, characterized in that: The active layers of the multiple MOS tubes are located in the same well of the active substrate.
4. The integrated circuit according to claim 1, characterized in that The projection of the resistance layer toward the gate is located in the middle of the gate.
5. An integrated circuit comprising a resistor and a plurality of MOS transistors arranged side by side, each MOS transistor comprising a gate, and a channel region, a source region and a drain region located in an active layer, and there is a gap between adjacent MOS transistors, characterized in that: The integrated circuit also includes a resistive insulating layer formed on the surface of the gate, the resistive insulating layer spanning across multiple gates, multiple source regions, multiple drain regions, and the intervals between adjacent MOS tubes; a resistive layer is formed on the resistive insulating layer, the resistive layer spanning across multiple gates, multiple source regions, multiple drain regions, and the intervals between adjacent MOS tubes, and the resistor is formed by the resistive layer; The resistor layer is connected to respective endpoints in a metal connection layer above the resistor layer through resistor contact holes at both ends of the resistor layer, the gate through a gate contact hole, the source region through a source contact hole, and the drain region through a drain contact hole, wherein projections of the resistor contact hole, the gate contact hole, the source contact hole, and the drain contact hole toward the active layer do not overlap with each other, and the source contact hole and the drain contact hole are staggered with the resistor layer, respectively.
6. The integrated circuit according to claim 5, characterized in that The thickness of the resistive insulating layer is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold, so as to prevent a voltage formed on the resistive layer from affecting the channel region.
7. The integrated circuit according to claim 5 or 6, characterized in that: The active layers of the multiple MOS tubes are located in the same well of the active substrate.
8. The integrated circuit according to claim 5, characterized in that The projection of the resistance layer toward the gate is located in the middle of the gate, the source region and the drain region.
9. An integrated circuit comprising a resistor and a MOS transistor, wherein the MOS transistor comprises a gate, and a channel region, a source region and a drain region located in an active layer, characterized in that: The integrated circuit further comprises a resistive insulating layer formed on the surface of the gate, wherein the projection of the resistive insulating layer toward the gate is smaller than and falls within the region of the gate; a resistive layer is formed on the resistive insulating layer, wherein the projection of the resistive layer toward the gate is smaller than and falls within the region of the gate, and the projection of the resistive layer toward the active layer does not fall within the source region and the drain region, and the resistor is formed by the resistive layer; The resistor layer is connected to respective endpoints in the metal connection layer above the resistor layer through resistor contact holes at both ends of the resistor layer, the gate is connected through a gate contact hole, the source region is connected through a source contact hole, and the drain region is connected through a drain contact hole, wherein projections of the resistor contact hole, the gate contact hole, the source contact hole, and the drain contact hole toward the active layer do not overlap with each other.
10. The integrated circuit according to claim 9, characterized in that The thickness of the resistive insulating layer is greater than a thickness threshold, and the dielectric constant of the resistive insulating layer is greater than a dielectric constant threshold, so as to prevent a voltage formed on the resistive layer from affecting the channel region.
11. The integrated circuit according to claim 9, characterized in that The projection of the resistance layer toward the gate is located in the middle of the gate.
12. A chip, characterized in that: Comprising an integrated circuit as claimed in any one of claims 1 to 11.
13. An electronic device, characterized in that: Comprising the chip as claimed in claim 12.
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