Data acquisition devices, data acquisition methods, chips and electronic devices

Abstract

This application discloses a data acquisition device, a data acquisition method, a chip, and an electronic device applied to a chip. The device includes a sensor module correspondingly disposed within each processing unit of the chip, and multiple sensor modules are connected sequentially. Each sensor module receives clock signals and data signals, acquires data from the currently located processing unit, generates intermediate data signals based on the acquired data and data signals, samples and processes the intermediate data signals using the clock signal, outputs a new clock signal and a new data signal, and inputs the new clock signal as a clock signal and the new data signal as a data signal into the next-level sensor module. This device is not only easy to wire and has good scalability, but it also reduces the time delay between the clock and data, resulting in stable data acquisition.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a data acquisition device, a data acquisition method, a chip, and an electronic device. Background Technology

[0002] With the continuous development of integrated circuit technology, the integration density of chips is becoming increasingly higher, and their functions are becoming more and more powerful. When developing and designing large-scale integrated circuits, they are generally divided into multiple smaller modules for processing. During the design and implementation of different modules, the timing of these modules must meet design requirements to ensure the correctness of chip functionality.

[0003] In current technologies, sensors are placed inside each module to collect data from other modules within the chip. Each module then sends its collected data to a centralized processing unit, and these modules are synchronized using a clock signal. However, this approach still has some drawbacks. For example, as the number of sensors increases, some sensors need to travel long distances to reach the centralized processing unit. This long-distance data transmission not only leads to complex wiring issues but also increases latency during data transmission, potentially causing data acquisition failures. Summary of the Invention

[0004] This application proposes a data acquisition device, a data acquisition method, a chip, and an electronic device, which can not only reduce wiring complexity but also reduce the time difference between clock and data during transmission, making data acquisition stable and having good scalability.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0006] In a first aspect, embodiments of this application provide a data acquisition device applied to a chip. The data acquisition device includes a sensor module correspondingly disposed within each processing unit of the chip, and multiple sensor modules are connected sequentially. Each sensor module is configured to receive clock signals and data signals, acquire data from the currently located processing unit, generate intermediate data signals based on the acquired data and data signals, sample and process the intermediate data signals using a clock signal, and output new clock signals and new data signals. Furthermore, the new clock signal is input as a clock signal to the next-level sensor module, and the new data signal is input as a data signal to the next-level sensor module.

[0007] In some embodiments, multiple sensor modules are connected sequentially via a link.

[0008] In some embodiments, the new data signal output by the last sensor module includes the data acquired by each processing unit of the chip.

[0009] In some embodiments, the sensor module includes a data acquisition sensor and a trigger, wherein the input terminal of the trigger is connected to the output terminal of the data acquisition sensor, the clock terminal of the trigger is used to receive a clock signal, and the output terminal of the trigger is used to output a new data signal; wherein the data acquisition sensor is used to acquire data from the processing unit where the sensor module is located, and obtain the acquired data of the processing unit; the trigger is used to sample and process the intermediate data signal using a clock signal after generating an intermediate data signal based on the acquired data and the received data signal, and output a new data signal; wherein the new data signal is the input data signal of the next-level sensor module.

[0010] In some embodiments, the triggering mode of the trigger includes: rising edge triggering or falling edge triggering; wherein, when the triggering mode is rising edge triggering, the trigger is used to sample the intermediate data signal using the rising edge of the clock signal and output a new data signal; or, when the triggering mode is falling edge triggering, the trigger is used to sample the intermediate data signal using the falling edge of the clock signal and output a new data signal.

[0011] In some embodiments, the sensor is a PVT sensor; wherein the acquired data includes at least one of the following: temperature data, process data, and voltage data.

[0012] In some embodiments, a clock line and a data line are provided between the sensor module and the next-level sensor module. The clock line is used to transmit a new clock signal output by the sensor module, and the data line is used to transmit a new data signal output by the sensor module. The transmission distance of the clock line and the data line between the sensor module and the next-level sensor module is the same.

[0013] In some embodiments, a combinational logic module is further provided on the data line between the sensor module and the next-level sensor module. The input terminal of the combinational logic module is connected to the output terminal of the sensor module, and the output terminal of the combinational logic module is connected to the input terminal of the next-level sensor module. The combinational logic module is used to receive new data signals output by the sensor module, perform combinational logic processing on the new data signals to obtain processed data signals, and use the processed data signals as input data signals for the next-level sensor module.

[0014] In some embodiments, the sum of the path delay time between the output of the sensor module and the input of the combinational logic module, the delay time required for the combinational logic module to perform combinational logic processing, and the path delay time between the output of the combinational logic module and the input of the next-level sensor module is less than the difference between the preset clock period and the clock setup time; wherein, the preset clock period is the clock period of the new clock signal, and the clock setup time represents the time that the new data signal needs to arrive at the input of the next-level sensor module earlier than the new clock signal.

[0015] Secondly, embodiments of this application provide a data acquisition method applied to a data acquisition device, the data acquisition device including sensor modules correspondingly disposed within each processing unit of a chip, and multiple sensor modules being connected sequentially; the method includes:

[0016] The system receives clock and data signals from the sensor module and acquires data from the current processing unit. It generates intermediate data signals based on the acquired data and data signals. It then uses the clock signal to acquire data from the data signals and outputs new clock and data signals. Finally, it inputs the new clock signal as a clock signal into the next-level sensor module and the new data signal as a data signal into the next-level sensor module. This process is repeated until the last connected sensor module outputs a new clock and data signal.

[0017] In some embodiments, the sensor module includes a data acquisition sensor and a trigger to acquire data from the processing unit currently in which it resides, and to generate an intermediate data signal based on the acquired data and the data signal. The process involves acquiring data from the processing unit using the data acquisition sensor to obtain the acquired data from the processing unit; after generating the intermediate data signal based on the acquired data and the received data signal, sampling the intermediate data signal using the clock signal via the trigger to output a new data signal; wherein the new data signal is the input data signal for the next-level sensor module.

[0018] In some embodiments, the triggering mode of the trigger includes rising edge triggering or falling edge triggering; correspondingly, the intermediate data signal is sampled and processed by the trigger using a clock signal to output a new data signal, including: when the triggering mode of the trigger is rising edge triggering, the intermediate data signal is sampled and processed by the rising edge of the clock signal to output a new data signal; or, when the triggering mode of the trigger is falling edge triggering, the intermediate data signal is sampled and processed by the falling edge of the clock signal to output a new data signal.

[0019] In some embodiments, the sensor is a PVT sensor; wherein the acquired data includes at least one of the following: temperature data, process data, and voltage data.

[0020] In some embodiments, the method further includes sequentially connecting a plurality of the sensor modules via a link.

[0021] Thirdly, embodiments of this application provide a chip that includes multiple processing units and a data acquisition device as described in any one of the first aspects.

[0022] Fourthly, embodiments of this application provide an electronic device that includes the chip described in the third aspect.

[0023] This application provides a data acquisition device, data acquisition method, chip, and electronic device. The data acquisition device includes sensor modules correspondingly disposed within each processing unit of the chip, with multiple sensor modules connected sequentially. Each sensor module receives clock signals and data signals, acquires data from the current processing unit, generates intermediate data signals based on the acquired data and data signals, samples the intermediate data signals using the clock signal, outputs new clock signals and new data signals, and inputs the new clock signals and data signals as clock signals to the next-level sensor module. Because these sensor modules are connected sequentially, not only can all acquired data be aggregated, but data acquisition is also stable, flexible, and scalable. Furthermore, each sensor module can provide its own clock and data signals for transmission to the next-level sensor module, reducing wiring complexity and ensuring that the data and clock transmission paths between any two sensor modules are identical, thereby reducing clock and data transmission delays and preventing data acquisition failures. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of an interconnection method for PVT sensors inside a chip;

[0025] Figure 2 This is a schematic diagram of an application framework for data transmission;

[0026] Figure 3 This is a schematic diagram of the composition structure of a data acquisition device provided in an embodiment of this application;

[0027] Figure 4 A schematic diagram of the composition structure of a sensor module provided in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the composition structure of another data acquisition device provided in an embodiment of this application;

[0029] Figure 6 A flowchart illustrating a data acquisition method provided in an embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the composition structure of a chip provided in an embodiment of this application;

[0031] Figure 8 A schematic diagram of the composition structure of an electronic device provided in an embodiment of this application;

[0032] Figure 9 This is a schematic diagram of the composition structure of another electronic device provided in an embodiment of this application. Detailed Implementation

[0033] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0035] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. It should also be noted that the terms "first, second, third" used in the embodiments of this application are merely for distinguishing similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0036] It is understandable that large-scale integrated circuits, such as system-on-chips (SoCs), may be divided into dozens or even hundreds of modules for separate design during the specific circuit design process. For example, these modules can be divided according to their functions and spatial relationships. Each module can perform a specific function, and each module will send its collected data to a centralized processing unit.

[0037] Currently, with the increasing integration of chips, sensors can be placed at various sampling locations within the chip to collect data. These sensors can be process, voltage, and temperature (PVT) sensors, or simply PVT sensors. The data that can be collected using PVT sensors includes parameters such as temperature, process, and voltage. The data from each sampling location is then aggregated and processed by a unified central processing unit. In related technologies, each PVT sensor needs to connect to the central processing unit after collecting its data.

[0038] Figure 1 A schematic diagram illustrating the interconnection method of PVT sensors within a chip is shown. Figure 1 As shown, different filling areas represent different modules, and each module contains a PVT sensor; each module needs to send its collected data to a centralized processing unit, and each module uses the same clock for synchronization. Specifically, in Figure 1 In this chip, the chip can be divided into multiple modules. Within these modules, the PVT sensor can be represented as Module A, Module B, Module C, Module D, Module E, Module F, Module G, Module H, and Module I, respectively, with Module I serving as the centralized processing unit. Furthermore, combinational logic modules can be configured between Module A and Module I, Module B and Module I, Module C and Module I, Module D and Module I, Module E and Module I, Module F and Module I, and Module H and Module I, respectively, represented as Logic Module 11, Logic Module 12, Logic Module 13, Logic Module 14, Logic Module 15, Logic Module 16, Logic Module 17, and Logic Module 18. It is important to note that... Figure 1 In the diagram, the bold solid line represents the data signal, and the bold dashed line represents the clock signal.

[0039] according to Figure 1 The technical solution shown presents two main problems: First, as the number of PVT sensors increases, each sensor needs to transmit data to the centralized processing unit individually. This requires long-distance transmission of the wiring, which can cause problems for layout and wiring. Second, since the distance between each PVT sensor is not consistent and some are far apart, timing issues may arise when using a clock for synchronization. The following example illustrates this using the distance between trigger A and trigger B as an example.

[0040] For example, Figure 2 A schematic diagram of an application framework for data transmission is shown. For example... Figure 2As shown, long-distance data transmission is simply summarized as transmission from flip-flop A to flip-flop B. Therefore, when data is transmitted according to a synchronous clock, this application framework can be decomposed into several delays, namely: T ab T cd T de T ef T fh T ag T clock and T setup Among them, T ab T represents the delay in the clock's rising edge propagating from point a to point b; cd T represents the delay used to transmit data from point c to point d after the rising edge of the clock is received at point b; de T represents the time it takes for data to travel from point d to point e; ef T represents the delay required for the data to be processed by combinational logic module 11; fh T represents the delay from the output of combinational logic module 11 to the data input point h of the next stage flip-flop B; ag T represents the delay required for the clock rising edge to reach flip-flop B; clock T represents the size of the clock cycle; setup This indicates the time that the data needs to arrive at point h before the rising edge of the clock reaches flip-flop B.

[0041] Therefore, for each of the above delays, the following relationship must be satisfied:

[0042] T ab +T cd +T ef +T de +T fh ≤T ag +T clock -T setup (1)

[0043] In other words, the data needs to arrive at point g at least T before the rising edge of the clock. setup The time has elapsed; otherwise, trigger B will not be able to collect the data transmitted from trigger A.

[0044] Equation (1) can be transformed into:

[0045] T ef ≤T ag -T ab +T clock -T setup -T cd -T de -T fh (2)

[0046] It should be noted that in formula (2), T clock It is related to the clock frequency and is a fixed value; T setup T cd It is related to the device itself and is a fixed value, so it can determine the value left to T. ef Time and T ag -T ab and T de +T fh The size is related to the chip's internal dimensions. To ensure that all components can work synchronously, the chip design must guarantee T. ag -T ab The value should be as close to 0 as possible; while for T de +T fh As the transmission distance increases, the value will become larger and larger, so what is left for T? ef The remaining time will become increasingly limited.

[0047] In short, for the data transmission method of PVT sensors in related technologies, long-distance transmission not only presents wiring problems, but also requires inserting buffers into the clock tree to balance the clock tree, ensuring that the clock arrives at each PVT sensor at the same time, so that the timing meets the design requirements; in addition, due to the long-distance transmission of data, the delay in the data transmission process will also increase, as shown in formula (2), when T ef When the value is less than 0, data will be unable to be collected at the target trigger.

[0048] Based on this, this application provides a data acquisition device applied to a chip. The data acquisition device may include sensor modules correspondingly disposed within each processing unit of the chip, with multiple sensor modules connected sequentially. Each sensor module is used to receive clock signals and data signals, and to acquire data from the currently located processing unit, generating intermediate data signals based on the acquired data and data signals. The intermediate data signals are then sampled using a clock signal to output new clock signals and new data signals. The new clock signals are then input as clock signals to the next-level sensor module, and the new data signals are input as data signals to the next-level sensor module. Because these sensor modules are connected sequentially, not only can all the acquired data be aggregated, but the data acquisition is also stable, flexible, and has good scalability. Furthermore, each sensor module can provide its own clock and data signals for transmission to the next-level sensor module, thereby reducing wiring complexity and ensuring that the data and clock transmission paths between any two sensor modules are identical, thus reducing the time delay between clock and data transmission and avoiding data acquisition failures.

[0049] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0050] In one embodiment of this application, see Figure 3 This illustration shows a schematic diagram of the composition structure of a data acquisition device provided in an embodiment of this application. Figure 3 As shown, the data acquisition device 30 may include a sensor module correspondingly disposed inside each processing unit of the chip, and multiple sensor modules are connected sequentially; wherein,

[0051] The sensor module is used to receive clock signals and data signals, and to acquire data from the current processing unit. It generates intermediate data signals based on the acquired data and data signals; it samples and processes the intermediate data signals using the clock signal, and outputs new clock signals and new data signals.

[0052] The new clock signal is input as the clock signal to the next-level sensor module, and the new data signal is input as the data signal to the next-level sensor module.

[0053] In this embodiment, the data acquisition device can be applied to a chip. Each chip may contain multiple processing units. To acquire parameters such as temperature, process, and voltage of each processing unit, a sensor module can be installed within each processing unit. This sensor module not only enables data acquisition from the processing unit but also allows for synchronized data processing using a clock signal.

[0054] Specifically, such as Figure 3 As shown, multiple processing units can be represented by 311, 312, 313, 314, 315, 316, 317, 318, and 319, respectively; wherein, sensor module A is provided inside processing unit 311, sensor module B is provided inside processing unit 312, sensor module C is provided inside processing unit 313, sensor module D is provided inside processing unit 314, sensor module E is provided inside processing unit 315, sensor module F is provided inside processing unit 316, sensor module G is provided inside processing unit 317, sensor module H is provided inside processing unit 318, and sensor module I is provided inside processing unit 319.

[0055] Here, sensor modules A, B, C, D, E, F, G, H, and I are connected sequentially, so that all the data collected by the different sensor modules are aggregated together, ultimately summarizing into sensor module I. In other words, the processing unit containing sensor module I can be regarded as a centralized processing unit (or "central processing unit").

[0056] It should also be noted that in some embodiments, these multiple sensor modules are connected sequentially via a link. Specifically, in the data acquisition device 30, a chain structure can be used to connect the sensor modules distributed across various processing units, so that when subsequent modules are expanded, only the corresponding sensor modules need to be added to the head of the link, thus providing good scalability.

[0057] Furthermore, for these multiple sensor modules, except for the first sensor module, the input data signals of the other sensor modules are the output data signals of the previous stage sensor module, until the last sensor module outputs a new data signal. In some embodiments, the new data signal output by the last sensor module may include the data collected by each processing unit of the chip.

[0058] It should be noted that, in the embodiments of this application, for Figure 3 For the first sensor module A, it receives a clock signal and a data signal, at which point the data signal can be zero. After acquiring data from the processing unit 311, the generated intermediate data signal represents the acquired data corresponding to the processing unit 311. Then, the intermediate data signal is sampled using the clock signal to output a new clock signal and a new data signal. Alternatively, for the first sensor module A, it can only receive the clock signal, acquire data from the processing unit 311 to obtain a data signal, and then sample the data signal using the clock signal to obtain a new clock signal and a new data signal. Then, the new clock signal is used as the input clock signal for sensor module B, and the new data signal is used as the input data signal for sensor module B.

[0059] for Figure 3For non-first sensor modules (e.g., sensor modules B, C, D, E, F, G, H, I, etc.), they can receive clock and data signals from the previous sensor module. By acquiring data from the current processing unit, an intermediate data signal is generated based on the acquired data and the data signal from the previous sensor module. This intermediate data signal includes the acquired data from the current processing unit and the acquired data from previous processing units. The intermediate data signal is then sampled using a clock signal to obtain a new clock signal and a new data signal. This new clock signal is then used as the input clock signal for the next-level sensor module, and the new data signal is used as the input data signal for the next-level sensor module, until the last sensor module I outputs a new data signal. Because these multiple sensor modules are connected together, the acquired data from all processing units can be aggregated at the final sensor module I. In other words, this embodiment of the application allows all acquired data to be aggregated and subsequently processed uniformly by a centralized processing unit.

[0060] Understandably, taking a certain sensor module as an example, the input of the sensor module can be a clock signal and a data signal, and the output of the sensor module can be a new clock signal and a new data signal; at the same time, the new clock signal can be used as the input clock signal of the next level sensor module, and the new data signal can be used as the input data signal of the next level sensor module.

[0061] In some embodiments, for any one sensor module, see [link to documentation]. Figure 4 The sensor module may include a data acquisition sensor 411 and a trigger 412; wherein, the input terminal of the trigger 412 is connected to the output terminal of the data acquisition sensor 411, the clock terminal of the trigger 412 is used to receive a clock signal, and the output terminal of the trigger 412 is used to output a new data signal.

[0062] The data acquisition sensor 411 is used to acquire data from the processing unit where the sensor module is located, and to obtain the data acquired by the processing unit.

[0063] Trigger 412 is used to sample and process the intermediate data signal using a clock signal after generating an intermediate data signal based on the acquired data and the received data signal, and output a new data signal; wherein the new data signal is the input data signal of the next stage sensor module.

[0064] It should be noted that, in this embodiment, the sensor 411 can be a PVT sensor, capable of sensing the magnitude of parameters such as process, voltage, and temperature of the processing unit. In other words, the acquired data can include at least one of the following: temperature data, process data, and voltage data.

[0065] It should also be noted that, in this embodiment of the application, the triggering method of the trigger 412 may include: rising edge triggering or falling edge triggering; wherein,

[0066] Flip-flop 412 is used to sample the intermediate data signal using the rising edge of the clock signal and output a new data signal when the triggering mode is rising edge triggered; or,

[0067] The flip-flop 412 is used to sample the intermediate data signal using the falling edge of the clock signal when the triggering mode is falling edge triggering, and output a new data signal.

[0068] Here, the flip-flop 412 can be a basic unit of sequential logic circuit, used to store 1 bit of binary information, and has memory and storage functions. For example, the flip-flop 412 can be a D-type flip-flop (Data Flip-Flop or DelayFlip-Flop, DFF). This flip-flop has two stable states, namely "0" and "1", and can flip from one stable state to another under the action of a certain external signal.

[0069] In practical applications, the flip-flop 412 is typically "triggered" and activated only when the rising edge of the clock signal arrives, changing the state of the output signal according to the input signal. Furthermore, the input transition between two rising edges of the clock signal does not affect the value stored in the flip-flop; however, sufficient clock setup time must be reserved at the input before the rising edge arrives to ensure signal stability.

[0070] Furthermore, in this embodiment, the collected data is represented in binary. For example, temperature data can be represented using eight bits, and voltage data can be represented using four bits. Each bit requires a flip-flop; therefore, there is not just one flip-flop 412. The number of flip-flops 412 is related to the number of bits. Figure 4 Only one trigger 412 is provided for illustration.

[0071] In one specific implementation, it is still based on Figure 3For example, assuming the data collected by processing unit 311 is represented by four bits, then there are four triggers in sensor module A; the data collected by processing unit 312 is also represented by four bits, so there are eight triggers in sensor module B (four triggers are used to collect data from processing unit 311, and the other four triggers are used to collect data from processing unit 312); the data collected by processing unit 313 is also represented by four bits, so there are twelve triggers in sensor module C (four triggers are used to collect data from processing unit 311, the other four triggers are used to collect data from processing unit 312, and the remaining four triggers are used to collect data from processing unit 313); and so on, so that all the collected data can be aggregated at the final sensor module I.

[0072] In another specific implementation, it is still based on Figure 3 For example, assume that the data collected by each processing unit is represented by four bits, and that each sensor module contains four triggers. Thus, the data collected by processing unit 311 is acquired by the four triggers in sensor module A. In sensor module B, after processing the data collected by processing units 311 and 312, the resulting first intermediate data is also represented by four bits, which can be acquired by the four triggers in sensor module B. Similarly, in sensor module C, after processing the data collected by processing units 311, 312, and 313, the resulting second intermediate data is also represented by four bits, which can be acquired by the four triggers in sensor module C. This process continues, ensuring that all the acquired data is aggregated in the final sensor module I.

[0073] It should be noted that in practical applications, the number of triggers in each sensor module can be specifically set according to the actual situation, and this application embodiment does not impose any limitation.

[0074] It is also understood that, in the embodiments of this application, for each pair of adjacent sensor modules, a clock line and a data line are provided between the sensor module and the next-level sensor module. See details. Figure 3 , Figure 3 The bold dashed line shown represents the clock line. Figure 3The bold solid lines shown represent data lines. Here, clock lines can be used to transmit new clock signals output by the sensor module, and data lines can be used to transmit new data signals output by the sensor module.

[0075] To reduce the time delay between data and clock during transmission, in some embodiments, the clock and data lines between the sensor module and the next-level sensor module are set to have the same transmission distance.

[0076] It should be noted that for each sensor module, the sensor module can provide an independent clock signal and data signal to transmit to the next level sensor module. Therefore, the transmission distance of the clock line and data line between the sensor module and the next level sensor module is the same, so that the data transmission delay and clock transmission delay between any two sensor modules are basically the same. That is, the transmission delay difference between data and clock is very small. In this way, each sensor module can collect the output of the previous level sensor module.

[0077] It should also be noted that, although Figure 3 The diagram shows only one data line, but this is merely for illustration. In actual applications, there is more than one data line; the number of data lines depends on the number of flip-flops, with each flip-flop's output connected to a data line.

[0078] It should also be noted that, in this embodiment, the rising edge of the clock signal of the sensor module is offset by one clock cycle from the rising edge of the clock signal of the next-stage sensor module, denoted by T. clock This means that, taking sensor module A and the next-level sensor module B as an example, the clock sampling of the data signal by sensor module A, plus the signal transmission delay, needs to be completed within one clock cycle before reaching the input terminal of sensor module B.

[0079] Furthermore, different sensor modules can use different clock domains. In other words, sensor module A can use a clock signal generated by a clock generation circuit, while sensor module B can use a new clock signal provided by sensor module A, sensor module C can use a new clock signal provided by sensor module B, sensor module D can use a new clock signal provided by sensor module C, and so on. Here, the new clock signal provided by each sensor module can be different, or they can all be generated by a clock generation circuit, only with the rising edges of the clock signals staggered by one clock cycle. This application does not impose any limitations on this.

[0080] Furthermore, in some embodiments, in Figure 3 Based on the data acquisition device 30 shown, see... Figure 5A combinational logic module is also provided on the data line between the sensor module and the next-level sensor module. The input of the combinational logic module is connected to the output of the sensor module, and the output of the combinational logic module is connected to the input of the next-level sensor module.

[0081] The combinational logic module is used to receive new data signals output by the sensor module, perform combinational logic processing on the new data signals to obtain processed data signals, and use the processed data signals as input data signals for the next-level sensor module.

[0082] It should be noted that, in this embodiment, since the data signal can be represented in binary, meaning there is not only one data line, a combinational logic module can be used to perform combinational logic to generate a processed signal to be provided to the input of the next-level sensor module. This combinational logic module can be composed of logic gates such as OR gates and NOR gates.

[0083] It should also be noted that, such as Figure 5 As shown, the data acquisition device 30 may include multiple combinational logic modules, and one combinational logic module is provided on the data line between every two sensor modules. Specifically, these multiple combinational logic modules can be represented by 11, 12, 13, 14, 15, 16, 17, and 18, respectively. Among them, combinational logic module 11 is provided between sensor module A and sensor module B, combinational logic module 12 is provided between sensor module B and sensor module C, combinational logic module 13 is provided between sensor module C and sensor module D, combinational logic module 14 is provided between sensor module D and sensor module E, combinational logic module 15 is provided between sensor module E and sensor module F, combinational logic module 16 is provided between sensor module F and sensor module G, combinational logic module 17 is provided between sensor module G and sensor module H, and combinational logic module 18 is provided between sensor module H and sensor module I.

[0084] Furthermore, in some embodiments, the delay time on the data line between the output of the sensor module and the input of the next-stage sensor module is less than the difference between the preset clock cycle and the clock setup time.

[0085] In this embodiment, the delay time on the data line between the output of the sensor module and the input of the next-stage sensor module can include: the path delay time between the output of the sensor module and the input of the combinational logic module, the delay time required for the combinational logic module to perform combinational logic processing, and the path delay time between the output of the combinational logic module and the input of the next-stage sensor module. That is, in a specific embodiment, the sum of the path delay time between the output of the sensor module and the input of the combinational logic module, the delay time required for the combinational logic module to perform combinational logic processing, and the path delay time between the output of the combinational logic module and the input of the next-stage sensor module is less than the difference between a preset clock period and the clock setup time.

[0086] It should also be noted that the preset clock period here is the clock period of the new clock signal, which can be represented by T. clock Clock setup time represents the time it takes for a new data signal to arrive at the input of the next-level sensor module before the new clock signal arrives. It can be represented by T. setup In a specific embodiment, T is indicated. setup This can represent the time required for a new data signal to arrive at the input of the next-level sensor module before the rising edge of the new clock signal arrives at the input of the next-level sensor module.

[0087] Therefore, for the input clock signal and input data signal of each sensor module, sufficient clock setup time must be reserved at the input end before the rising edge of the clock signal arrives. In other words, for the input data signal of each sensor module, the transmission delay between the output of the previous-level sensor module and the input of the current sensor module must be less than the difference between the preset clock period and the clock setup time. This ensures that each sensor module can acquire the output of the previous-level sensor module, resulting in stable data acquisition and avoiding data acquisition failures.

[0088] This application provides a data acquisition device in which multiple sensor modules are connected sequentially. Each sensor module receives clock signals and data signals, acquires data from its current processing unit, generates intermediate data signals based on the acquired data and data signals, samples the intermediate data signals using the clock signal, outputs new clock signals and new data signals, and inputs the new clock signals and data signals as clock signals to the next-level sensor module. Because these sensor modules are connected sequentially in a link-like manner, not only can all the acquired data be aggregated, but the data acquisition is also stable, flexible, and has good scalability. Furthermore, each sensor module can provide its own clock and data signals to transmit to the next-level sensor module, thereby reducing wiring complexity and ensuring that the data and clock transmission paths between any two sensor modules are identical, thus reducing the time delay between clock and data transmission and preventing data acquisition failures.

[0089] In another embodiment of this application, based on the data acquisition device 30 described in the foregoing embodiments, this application proposes a ring data transmission strategy, as described above. Figure 3 or Figure 5 As shown, the lines represented by bold dashed lines are clock lines, and the lines represented by bold solid lines are data lines. Each sensor module can independently send clock and data signals to the next-level sensor module. In this way, all sensor modules can be connected together, and finally, all data will be aggregated to the last sensor module (i.e., the central processing module), as shown. Figure 3 or Figure 5 The sensor module I is shown in the diagram. Since each sensor module can transmit its own clock signal and data to the next-level sensor module, the transmission distances of the clock and data lines are the same, and the delay between any two sensor modules is also the same. Therefore, each sensor module can collect the output of the previous-level sensor module. The sensor module here can include a PVT sensor and a trigger; the former is used to collect data such as temperature and voltage, while the latter uses a clock to achieve data synchronization.

[0090] The technical solution of this application embodiment uses the same transmission path for the collected PVT data and the clock, which allows the delay to be canceled, thereby reducing the delay difference between the PVT data and the clock during transmission and making the data acquisition stable.

[0091] In short, considering that the real-time requirements for data interaction of PVT sensors are not high, and that each PVT sensor is distributed in various locations within the chip with a long distance between them, if centralized communication is used for data collection, problems such as complex back-end wiring and data acquisition failures may be encountered. Therefore, this embodiment uses a chain structure to connect the sensor modules scattered in various locations. Each stage of the chain can use a different clock domain. Moreover, during data transmission, since the distance between the clock line and data line between every two sensor modules is the same, the delay difference is very small, which makes the data acquisition by the sensor modules more stable.

[0092] This embodiment provides a data acquisition device. The specific implementation of the aforementioned embodiments has been described in detail through the above embodiments. It can be seen that by using the technical solution of the aforementioned embodiments to connect PVT sensors in the form of a link, the data acquisition is stable, highly flexible, and has good scalability. Only the corresponding sensor module needs to be added to the head of the link. In addition, since only one set of data lines and clock lines are used between each two sensor modules, the wiring complexity can be reduced.

[0093] In another embodiment of this application, based on the data acquisition device 30 described in the foregoing embodiments, see [link to previous embodiment]. Figure 6 This illustrates a flowchart of a data acquisition method provided in an embodiment of this application. Figure 6 As shown, the method may include:

[0094] S601: Receives clock signals and data signals through the sensor module, and performs data acquisition on the current processing unit. Generates intermediate data signals based on the acquired data and data signals. Uses the clock signal to acquire data signals and outputs new clock signals and new data signals.

[0095] S602: Determine whether the sensor module is the last sensor module in the link.

[0096] S603: If the judgment result is negative, the new clock signal is input as the clock signal into the next level sensor module, the new data signal is input as the data signal into the next level sensor module, and the process returns to continue executing step S601.

[0097] S604: If the judgment result is yes, then the last sensor module outputs a new clock signal and a new data signal.

[0098] It should be noted that the method described in this application embodiment is applied to the data acquisition device described in the foregoing embodiment. The data acquisition device may include multiple processing units and a sensor module correspondingly disposed inside each processing unit, and these multiple sensor modules are connected sequentially.

[0099] It should also be noted that, in the embodiments of this application, after these multiple sensor modules are connected in sequence, the following detailed description is given using the sensor module and the next-level sensor module. Specifically, it may include: receiving clock signals and data signals through the sensor module, and acquiring data from the current processing unit, generating intermediate data signals based on the acquired data and data signals; acquiring data from the data signals using the clock signal, and outputting new clock signals and new data signals; and inputting the new clock signal as a clock signal into the next-level sensor module, and inputting the new data signal as a data signal into the next-level sensor module, and cyclically executing the steps of receiving clock signals and data signals and outputting new clock signals and new data signals through the next-level sensor module, until the last sensor module connected in sequence outputs new clock signals and new data signals.

[0100] In some embodiments, the method may further include: sequentially connecting multiple sensor modules via links.

[0101] Specifically, in the data acquisition device, a chain structure can be used to connect the sensor modules distributed across various processing units. This allows for expansion of subsequent modules simply by adding the corresponding sensor module to the head of the chain, thus providing good scalability. Furthermore, because these multiple sensor modules are connected together, the data collected by all processing units can be aggregated at the final sensor module. In other words, this embodiment of the application also allows all collected data to be aggregated and subsequently processed uniformly by a centralized processing unit.

[0102] In some embodiments, for any sensor module, the sensor module may include a data acquisition sensor and a trigger. Therefore, for S601, this step may include:

[0103] The data is collected by the processing unit where the sensor module is located by the acquisition sensor to obtain the acquisition data of the processing unit;

[0104] After generating intermediate data signals based on the collected data and received data signals, the intermediate data signals are sampled and processed by a clock signal through a trigger to output new data signals; the new data signals are the input data signals of the next stage sensor module.

[0105] It should be noted that, in this embodiment, the data acquisition sensor can be a PVT sensor, capable of sensing the magnitude of parameters such as process, voltage, and temperature of the processing unit. In other words, the acquired data may include at least one of the following: temperature data, process data, and voltage data.

[0106] It should also be noted that, in the embodiments of this application, the triggering method of the flip-flop may include: rising edge triggering or falling edge triggering. Correspondingly, in some embodiments, the flip-flop uses a clock signal to sample and process the intermediate data signal to output a new data signal, which may include:

[0107] When the trigger mode is rising edge triggered, the intermediate data signal is sampled and processed using the rising edge of the clock signal, and a new data signal is output; or,

[0108] When the trigger mode is falling edge trigger, the intermediate data signal is sampled and processed using the falling edge of the clock signal, and a new data signal is output.

[0109] In practical applications, flip-flops are typically "triggered" and activated when the rising edge of the clock signal arrives, changing the state of the output signal according to the input signal. Furthermore, transitions at the input between two rising edges of the clock signal do not affect the value stored in the flip-flop; however, sufficient clock setup time must be reserved at the input before the rising edge arrives to ensure signal stability.

[0110] Furthermore, in this embodiment, the collected data is represented in binary. For example, temperature data can be represented using eight bits, and voltage data can be represented using four bits. Each bit requires a trigger, therefore there is not just one trigger; the number of triggers is related to the number of bits, as mentioned above. Figure 4 Only one trigger 412 is provided for illustration. That is to say, in practical applications, the number of triggers in each sensor module can be specifically set according to the actual situation, and this application embodiment does not impose any limitation.

[0111] Furthermore, a clock line and a data line are provided between the sensor module and the next-level sensor module. The clock line can be used to transmit new clock signals output by the sensor module, and the data line can be used to transmit new data signals output by the sensor module. Accordingly, in some embodiments, the transmission distance of the clock line and the data line between the sensor module and the next-level sensor module is the same.

[0112] It should be noted that for each sensor module, the sensor module can provide an independent clock signal and data signal to transmit to the next level sensor module. Therefore, the transmission distance of the clock line and data line between the sensor module and the next level sensor module is the same, so that the data transmission delay and clock transmission delay between any two sensor modules are basically the same. That is, the transmission delay difference between data and clock is very small. In this way, each sensor module can collect the output of the previous level sensor module.

[0113] Furthermore, a combinational logic module may also be provided on the data line between the sensor module and the next-level sensor module. Accordingly, in some embodiments, the method may further include:

[0114] The combinational logic module receives new data signals output by the sensor module, performs combinational logic processing on the new data signals to obtain processed data signals, and uses the processed data signals as input data signals for the next-level sensor module.

[0115] It should be noted that on the data lines, the input of the combinational logic module is connected to the output of the sensor module, and the output of the combinational logic module is connected to the input of the next-level sensor module. Here, since the data signal is represented in binary, there is not just one data line. The combinational logic module performs combinational logic to generate a processed signal to be provided to the input of the next-level sensor module.

[0116] In some embodiments, the sum of the path delay time between the output of the sensor module and the input of the combinational logic module, the delay time required for the combinational logic module to perform combinational logic processing, and the path delay time between the output of the combinational logic module and the input of the next-level sensor module is less than the difference between the preset clock cycle and the clock setup time.

[0117] It should be noted that the preset clock period here is the clock period of the new clock signal, which can be represented by T. clock Clock setup time represents the time it takes for a new data signal to arrive at the input of the next-level sensor module before the new clock signal arrives. It can be represented by T. setup In a specific embodiment, T is indicated. setup This can represent the time required for a new data signal to arrive at the input of the next-level sensor module before the rising edge of the new clock signal arrives at the input of the next-level sensor module.

[0118] Therefore, for the input clock signal and input data signal of each sensor module, sufficient clock setup time must be reserved before the rising edge of the clock signal arrives. In other words, for the input data signal of each sensor module, the transmission delay between the output of the previous-level sensor module and the input of the current sensor module must be less than the difference between the preset clock period and the clock setup time. This ensures that each sensor module can acquire the output of the previous-level sensor module, resulting in more stable data acquisition during sensor module operation.

[0119] This application provides a data acquisition method in which multiple sensor modules are connected sequentially. The sensor modules receive clock signals and data signals, and acquire data from the processing unit they are currently in. An intermediate data signal is generated based on the acquired data and data signals. The intermediate data signal is then sampled using the clock signal to output a new clock signal and a new data signal. The new clock signal and the new data signal are then input as clock signals and data signals to the next-level sensor module, respectively. This process of receiving clock signals and data signals and outputting new clock signals and data signals through the next-level sensor modules is repeated until the last connected sensor module outputs a new clock signal and a new data signal. Because these sensor modules are connected sequentially in a link-like manner, not only can all the acquired data be aggregated, but the data acquisition is also stable, flexible, and scalable. Furthermore, each sensor module can provide its own clock signal and data signal to the next-level sensor module, thereby reducing wiring complexity and ensuring that the data and clock transmission paths between any two sensor modules are identical, thus reducing the transmission delay difference between clock and data and avoiding data acquisition failures.

[0120] In another embodiment of this application, see [link to application]. Figure 7 This illustrates a schematic diagram of the chip's structural composition according to an embodiment of this application. Figure 7 As shown, chip 70 may include multiple processing units and the data acquisition device 30 described in the foregoing embodiments. For details, see [link to relevant documentation]. Figure 7 These multiple processing units may include processing unit 1, processing unit 2, ..., processing unit n, where n is an integer greater than 1.

[0121] In this embodiment, for chip 70, multiple processing units can be obtained based on a preset partitioning rule, such as processing unit 1, processing unit 2, ..., processing unit n. In order to obtain parameters such as temperature, process, and voltage of each processing unit, a sensor module can be set inside each processing unit. The sensor module can not only realize data acquisition of the processing unit, but also realize synchronous data processing using a clock signal.

[0122] In this embodiment, for chip 70, the multiple sensor modules can also be connected in the form of a link, which makes data acquisition stable, flexible and scalable. Only the corresponding sensor module needs to be added to the head of the link. In addition, since only one set of data line and clock line is used between each two sensor modules, the wiring is relatively simple.

[0123] In another embodiment of this application, see [link to application]. Figure 8 This illustrates a schematic diagram of the structural composition of an electronic device provided in an embodiment of this application. For example... Figure 8 As shown, the electronic device 80 may include multiple processing units (specifically: processing unit 1, processing unit 2, ..., processing unit n) and the data acquisition device 30 described in the foregoing embodiments.

[0124] In another embodiment of this application, see [link to application]. Figure 9 This illustrates a schematic diagram of the structural composition of another electronic device provided in an embodiment of this application. For example... Figure 9 As shown, the electronic device 80 may include the chip 70 described in the foregoing embodiments.

[0125] In this embodiment, the electronic device 80 includes a chip 70, which comprises multiple processing units and sensor modules correspondingly configured within each processing unit. These sensor modules are sequentially connected in a link configuration. This not only allows all collected data to be aggregated but also ensures stable and flexible data acquisition with good scalability. Furthermore, each sensor module can provide its own clock and data signals for transmission to the next-level sensor module, thereby reducing wiring complexity and ensuring that the data and clock transmission paths between any two sensor modules are identical. This reduces the time delay between clock and data transmission and prevents data acquisition failures.

[0126] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0127] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0128] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0129] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0130] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0131] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data acquisition device applied to a chip, characterized in that, The data acquisition device includes a sensor module correspondingly disposed within each processing unit of the chip, and multiple sensor modules are connected sequentially; wherein, The sensor module is used to receive clock signals and data signals, and to acquire data from the processing unit it is currently in, generating intermediate data signals based on the acquired data and the data signals; sampling and processing the intermediate data signals using the clock signals, and outputting new clock signals and new data signals; and The new clock signal is input as a clock signal into the next-level sensor module, and the new data signal is input as a data signal into the next-level sensor module. The new data signal output by the last sensor module includes the data collected by each processing unit of the chip. A clock line and a data line are provided between the sensor module and the next-level sensor module. The clock line is used to transmit the new clock signal output by the sensor module, and the data line is used to transmit the new data signal output by the sensor module. The transmission distance of the clock line and the data line between the sensor module and the next-level sensor module is the same.

2. The data acquisition device according to claim 1, characterized in that, Multiple sensor modules are connected sequentially via a link.

3. The data acquisition device according to claim 1, characterized in that, The sensor module includes a data acquisition sensor and a trigger, wherein the input terminal of the trigger is connected to the output terminal of the data acquisition sensor, the clock terminal of the trigger is used to receive the clock signal, and the output terminal of the trigger is used to output the new data signal; The acquisition sensor is used to acquire data from the processing unit where the sensor module is located, and to obtain the acquisition data of the processing unit. The trigger is used to sample the intermediate data signal using the clock signal after generating an intermediate data signal based on the acquired data and the received data signal, and output a new data signal; wherein the new data signal is the input data signal of the next-level sensor module.

4. The data acquisition device according to claim 3, characterized in that, The triggering methods of the trigger include: rising edge triggering or falling edge triggering; wherein, The trigger is configured to, when triggered by a rising edge, sample the intermediate data signal using the rising edge of the clock signal and output the new data signal; or, The trigger is used to sample the intermediate data signal using the falling edge of the clock signal when the triggering mode is falling edge triggering, and output the new data signal.

5. The data acquisition device according to claim 3, characterized in that, The acquisition sensor is a PVT sensor; wherein the acquired data includes at least one of the following: temperature data, process data, and voltage data.

6. The data acquisition device according to any one of claims 1 to 5, characterized in that, A combinational logic module is also provided on the data line between the sensor module and the next-level sensor module. The input terminal of the combinational logic module is connected to the output terminal of the sensor module, and the output terminal of the combinational logic module is connected to the input terminal of the next-level sensor module. The combinational logic module is used to receive the new data signal output by the sensor module, perform combinational logic processing on the new data signal to obtain a processed data signal, and use the processed data signal as the input data signal of the next-level sensor module.

7. The data acquisition device according to claim 6, characterized in that, The sum of the path delay time between the output of the sensor module and the input of the combinational logic module, the delay time required for the combinational logic module to perform combinational logic processing, and the path delay time between the output of the combinational logic module and the input of the next-level sensor module is less than the difference between the preset clock cycle and the clock setup time. Wherein, the preset clock period is the clock period of the new clock signal, and the clock setup time represents the time by which the new data signal needs to arrive at the input terminal of the next-level sensor module earlier than the new clock signal.

8. A data acquisition method, characterized in that, The method is applied to a data acquisition device, which includes a sensor module correspondingly disposed within each processing unit of a chip, and multiple sensor modules are connected sequentially; the method includes: The sensor module receives clock and data signals, and performs data acquisition on the current processing unit. Based on the acquired data and the data signals, an intermediate data signal is generated. The clock signal is used to acquire data from the data signals, and a new clock and data signals are output. The new clock signal is input as a clock signal into the next level sensor module, and the new data signal is input as a data signal into the next level sensor module. The steps of receiving clock signals and data signals and outputting new clock signals and new data signals through the next level sensor module are executed cyclically until the last sensor module connected in sequence outputs new clock signals and new data signals. The new data signal output by the last sensor module includes the data collected by each processing unit of the chip. A clock line and a data line are provided between the sensor module and the next-level sensor module. The clock line is used to transmit the new clock signal output by the sensor module, and the data line is used to transmit the new data signal output by the sensor module. The transmission distance of the clock line and the data line between the sensor module and the next-level sensor module is the same.

9. The method according to claim 8, characterized in that, The sensor module includes a data acquisition sensor and a trigger. The processing unit currently in which the data is acquired performs data acquisition and generates an intermediate data signal based on the acquired data and the data signal. The data signal is acquired using the clock signal, and a new clock signal and a new data signal are output, including: The data acquisition sensor collects data from the processing unit where the sensor module is located, thereby obtaining the data collected by the processing unit. After generating an intermediate data signal based on the acquired data and the received data signal, the intermediate data signal is sampled and processed by the clock signal through the trigger to output a new data signal; wherein, the new data signal is the input data signal of the next-level sensor module.

10. The method according to claim 9, characterized in that, The triggering methods of the trigger include rising edge triggering and falling edge triggering. The step of sampling the intermediate data signal using the clock signal through the trigger and outputting a new data signal includes: When the trigger is triggered by a rising edge, the intermediate data signal is sampled using the rising edge of the clock signal, and the new data signal is output; or, When the trigger is triggered by a falling edge, the intermediate data signal is sampled using the falling edge of the clock signal, and the new data signal is output.

11. The method according to claim 9, characterized in that, The acquisition sensor is a PVT sensor; wherein the acquired data includes at least one of the following: temperature data, process data, and voltage data.

12. The method according to any one of claims 8 to 11, characterized in that, The method further includes: Multiple sensor modules are connected sequentially via a link.

13. A chip, characterized in that, The chip includes multiple processing units and a data acquisition device as described in any one of claims 1 to 7.

14. An electronic device, characterized in that, The electronic device includes the chip as described in claim 13.

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