Chip Aging Analysis Method, Device, Electronic Device, and Computer Storage Medium

Abstract

The present disclosure provides a chip aging analysis method, apparatus, electronic device, and computer storage medium. The method includes: performing an aging analysis test based on a test circuit to obtain at least one timing attenuation factor; the timing attenuation factor is used to characterize the clock frequency change coefficient of the test chip under a preset working life, and the timing attenuation factors corresponding to the clock frequencies in different frequency bands to be measured are different; during static timing analysis, performing timing analysis on the timing path of the test chip based on the timing attenuation factor to obtain a timing analysis result; and determining whether there is a timing violation in the timing path according to the timing analysis result. By adopting the technical solution of the present disclosure, an aging analysis test can be performed on the test chip equivalently with a test circuit, which can reduce the cost of aging analysis; performing aging analysis in the design stage can not only discover aging problems in advance, but also reduce the cost of solving aging problems.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip aging analysis, and in particular to a chip aging analysis method, device, electronic device and computer storage medium. Background Art

[0002] After the chip is powered on and running for a long time, the transistors in the chip will age, causing the chip's operating frequency to drop and causing the chip to fail.

[0003] The current chip aging analysis is a reliability analysis performed after the chip is returned. If the aging test fails, it will affect the product specifications and even lead to the risk of re-ECO (Engineering Change Order). There is a disadvantage that the cost of solving the aging problem is too high. When performing chip aging analysis, using actual chips for analysis and testing will also lead to high aging analysis costs. Summary of the invention

[0004] The purpose of the present disclosure is to provide a chip aging analysis method, device, electronic device and computer storage medium. The aging analysis test is performed using a test circuit equivalent to a test chip, which can reduce the cost of aging analysis. Performing aging analysis in the design stage can not only discover aging problems in advance, but also reduce the cost of solving aging problems.

[0005] According to one aspect of the present disclosure, a chip aging analysis method is provided, the method comprising:

[0006] Perform an aging analysis test based on the test circuit to obtain at least one timing attenuation factor; the timing attenuation factor is used to characterize the coefficient of change of the clock frequency of the test chip under a preset working life, and the timing attenuation factors corresponding to the clock frequencies in different frequency ranges to be tested are different;

[0007] In the static timing analysis process, the timing path of the test chip is analyzed based on the timing attenuation factor to obtain the timing analysis result;

[0008] Determine whether there is a timing violation in the timing path based on the timing analysis results.

[0009] In a feasible implementation of the present disclosure, the steps of performing an aging analysis test based on a test circuit to obtain a timing attenuation factor include:

[0010] Initialize the test circuit so that the factory frequency of the test circuit is within the frequency range to be tested;

[0011] Under simulation conditions, an aging simulation is performed on the test circuit after initialization settings to obtain an aging frequency;

[0012] The timing attenuation factor is calculated based on the aging frequency.

[0013] In a feasible implementation of the present disclosure, the test circuit includes a prediction unit, a capacitor, and a connection unit. The prediction unit and the connection unit are connected in series end to end, the number of capacitors is the same as that of the prediction units, and the capacitors are connected to the prediction units in a one-to-one correspondence.

[0014] In a feasible implementation of the present disclosure, the prediction unit includes a first inverter, a NAND gate, a NOR gate, and a second inverter. The output end of the first inverter is connected to the input end of the NAND gate, the output end of the NAND gate is connected to the input end of the NOR gate, the output end of the NOR gate is connected to the input end of the second inverter, the input end of the first inverter is connected to one of the other prediction units, or the input end of the first inverter is connected to the connection unit; the output end of the second inverter is connected to one of the other prediction units, or the output end of the second inverter is connected to the connection unit, and the output end of the second inverter is also connected to the corresponding capacitor.

[0015] In a feasible implementation of the present disclosure, the connection unit includes a third inverter. If the prediction unit and the capacitor are one, one end of the prediction unit is connected to one end of the third inverter, and the other end of the prediction unit is connected to the other end of the third inverter and the capacitor;

[0016] If the prediction unit and the capacitor are two, the prediction unit includes a first prediction unit and a second prediction unit, the capacitor includes a first capacitor and a second capacitor. One end of the first prediction unit is connected to one end of the third inverter, the other end of the first prediction unit is connected to one end of the first capacitor and the second prediction unit, and the other end of the second prediction unit is connected to the second capacitor and the other end of the third inverter;

[0017] If the number of the prediction units and the capacitors exceeds two, the prediction unit includes a head prediction unit, a tail prediction unit, and at least one middle prediction unit. One end of the head prediction unit is connected to one end of the third inverter; if the middle prediction unit is one, the other end of the head prediction unit is connected to one end of the middle prediction unit, the other end of the middle prediction unit is connected to one end of the tail prediction unit, and the other end of the tail prediction unit is connected to the other end of the third inverter; if the middle prediction unit is multiple, the other end of the head prediction unit is connected to one end of the mutually connected middle prediction units in series, the other end of the mutually connected middle prediction units in series is connected to one end of the tail prediction unit; the other ends of the head prediction unit, the tail prediction unit, and the middle prediction unit are respectively connected to the corresponding capacitors.

[0018] In a feasible implementation of the present disclosure, the steps of initializing the test circuit to make the factory frequency of the test circuit within the frequency band to be measured include:

[0019] Adjust the number of prediction units and the capacitance value of the capacitor so that the factory frequency of the test circuit is within the frequency range to be measured.

[0020] In a feasible implementation manner of the present disclosure, the simulation conditions include transient simulation conditions and stress simulation conditions;

[0021] Under the simulation conditions, the steps of performing aging simulation on the initialized test circuit to obtain the aging frequency include:

[0022] Under the transient simulation conditions, perform transient simulation on the initialized test circuit to obtain the initial frequency;

[0023] Under the stress simulation conditions, perform stress simulation on the initialized test circuit to obtain the hardware parameters of the initialized test circuit after aging;

[0024] Adjust the initialized test circuit based on the hardware parameters after aging to obtain the adjusted test circuit;

[0025] Under the transient simulation conditions, perform transient simulation on the adjusted test circuit to obtain the aging frequency.

[0026] In a feasible implementation manner of the present disclosure, under the transient simulation conditions, the steps of performing transient simulation on the initialized test circuit to obtain the initial frequency include:

[0027] Under the transient operating temperature environment, provide a transient operating voltage to the initialized test circuit to make the initialized test circuit start to oscillate;

[0028] After the initialized test circuit starts to oscillate stably, obtain the initial frequency.

[0029] In a feasible implementation manner of the present disclosure, after the initialized test circuit starts to oscillate stably, the steps of obtaining the initial frequency include:

[0030] After the initialized test circuit starts to oscillate stably, obtain the initial waveform of the initialized test circuit;

[0031] Obtain the initial frequency according to the initial waveform.

[0032] In a feasible implementation manner of the present disclosure, under the stress simulation conditions, the steps of performing stress simulation on the initialized test circuit to obtain the hardware parameters of the initialized test circuit after aging include:

[0033] Under the stress operating temperature environment, provide a stress operating voltage to the initialized test circuit to make the initialized test circuit start to oscillate; and

[0034] Provide a hardware parameter variation function to the test circuit after initialization settings, so that during the operation of the preset working time limit, the initial hardware parameters of the test circuit after initialization settings are changed to aged hardware parameters according to the hardware parameter variation function.

[0035] In a feasible implementation manner of the present disclosure, the hardware parameter variation function is generated by an aging model according to the preset working time limit.

[0036] In a feasible implementation manner of the present disclosure, the hardware parameters include gate oxide thickness, surface inversion potential, sidewall capacitance, depletion capacitance, and body effect parameters.

[0037] In a feasible implementation manner of the present disclosure, the steps of adjusting the test circuit after initialization settings based on the aged hardware parameters to obtain the adjusted test circuit include:

[0038] Adjust the gate oxide thickness, surface inversion potential, sidewall capacitance, depletion capacitance, and body effect parameters of the transistors in the test circuit after initialization settings based on the aged hardware parameters.

[0039] In a feasible implementation manner of the present disclosure, the steps of calculating the timing decay factor according to the aging frequency include:

[0040] Perform a subtraction operation on the aging frequency and the initial frequency to obtain a delay decay parameter;

[0041] Perform a division operation on the delay decay parameter and the initial frequency to obtain the timing decay factor.

[0042] In a feasible implementation manner of the present disclosure, during the static timing analysis process, the steps of performing timing analysis on the timing path of the test chip based on the timing decay factor to obtain the timing analysis result include:

[0043] During the static timing analysis process, obtain the actual timing used by the timing path of the test chip to transmit the test signal;

[0044] Perform a multiplication operation on the actual timing and the timing decay factor to obtain the aged timing;

[0045] Compare the aged timing with the preset timing to obtain the timing analysis result.

[0046] According to another aspect of the present disclosure, there is also provided a chip aging analysis device, which includes:

[0047] A timing decay factor acquisition module, configured to perform aging analysis tests based on the test circuit to obtain at least one timing decay factor; the timing decay factor is used to characterize the clock frequency change coefficient of the test chip under the preset working years, and the timing decay factors corresponding to the clock frequencies in different frequency ranges to be measured are different;

[0048] A static timing analysis module, which is used to perform timing analysis on the timing paths of a test chip based on a timing decay factor during static timing analysis to obtain a timing analysis result;

[0049] A timing violation judgment module, which is used to judge whether there is a timing violation in the timing path according to the timing analysis result.

[0050] According to another aspect of the present disclosure, there is also provided an electronic device, including a memory and one or more processors. The memory is used to store one or more programs; when the one or more programs are executed by the one or more processors, the above method is implemented.

[0051] According to another aspect of the present disclosure, there is also provided a computer storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented. Description of the Drawings

[0052] Figure 1 It is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

[0053] Figure 2 It is a schematic flowchart of a chip aging analysis method according to an embodiment of the present disclosure;

[0054] Figure 3 It is a schematic structural diagram of a test circuit according to an embodiment of the present disclosure;

[0055] Figure 4 It is a schematic circuit diagram of a test circuit according to an embodiment of the present disclosure;

[0056] Figure 5 It is a schematic structural diagram of a chip aging analysis device according to an embodiment of the present disclosure.

[0057] Icon:

[0058] 100 - Electronic device; 101 - Memory; 102 - Processor; 103 - Communication interface; 300 - Chip aging analysis device; 310 - Test circuit; 311 - Prediction unit; 312 - Connection unit; 313 - Capacitor; 320 - Timing decay factor acquisition module; 330 - Static timing analysis module; 340 - Timing violation judgment module; U1 - First inverter; U2 - NAND gate; U3 - NOR gate; U4 - Second inverter; U5 - Third inverter; 400 - Test chip. Detailed Embodiments

[0059] Before introducing the embodiments of the present disclosure, it should be noted that:

[0060] Some embodiments of the present disclosure are described as processing flows. Although the individual operation steps of the flow may be numbered with sequential step numbers, the operation steps can be implemented in parallel, concurrently, or simultaneously.

[0061] In the embodiments of the present disclosure, terms such as "first" and "second" may be used to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

[0062] In the embodiments of the present disclosure, the term "and / or" may be used, and "and / or" includes any and all combinations of one or more of the listed associated features.

[0063] It should be understood that when describing the connection relationship or communication relationship between two components, unless it is clearly specified that the two components are directly connected or directly communicate, otherwise, the connection or communication between the two components can be understood as either direct connection or communication, or indirect connection or communication through an intermediate component.

[0064] In order to make the technical solutions and advantages in the embodiments of the present disclosure clearer and more understandable, the following further details the exemplary embodiments of the present disclosure with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.

[0065] The purpose of the present disclosure is to provide a chip aging analysis solution. Among them, the chip refers to a chip with multiple clock frequencies, and the chip can be a system-on-chip (SOC) including multiple clock frequencies.

[0066] Please refer to Figure 1 , which is a schematic structural diagram of an electronic device 100 provided by an embodiment of the present disclosure. As Figure 1 shown, the electronic device 100 includes a memory 101, a processor 102, and a communication interface 103. The memory 101, the processor 102, and the communication interface 103 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0067] The memory 101 can be used to store software programs and modules, such as the program instructions / modules corresponding to the chip aging analysis method provided by the embodiments of the present disclosure. The processor 102 executes various functional applications and data processing by executing the software programs and modules stored in the memory 101. The communication interface 103 can be used to communicate signals or data with the test chip 400. In the present disclosure, the electronic device 100 can have multiple communication interfaces 103.

[0068] It should be noted that Figure 1 the block diagram shown is for the convenience of explaining the embodiments of the present disclosure, and the present disclosure is not limited to Figure 1 this. The electronic device 100 may also include other components.

[0069] Among them, the memory 101 may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0070] The processor 102 may be an integrated circuit chip with signal processing capabilities. The processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0071] Next, based on Figure 1 the electronic device 100 shown below, an embodiment of the present disclosure provides a chip aging analysis method. Please refer to Figure 2 , Figure 2 which is a schematic flow diagram of a chip aging analysis method provided by an embodiment of the present disclosure. The chip aging analysis method may include the following steps:

[0072] S210, perform an aging analysis test based on a test circuit to obtain at least one timing decay factor. The timing decay factor is used to characterize the clock frequency change coefficient of the test chip under a preset working life, and the timing decay factors corresponding to the clock frequencies in different frequency bands to be measured are different.

[0073] S220. During the static timing analysis process, perform timing analysis on the timing paths of the test chip based on a timing decay factor to obtain a timing analysis result.

[0074] S230. Determine whether there is a timing violation in the timing path according to the timing analysis result.

[0075] According to some implementations of the present disclosure, the test circuit can be a ring oscillator circuit. When performing an aging analysis test, the test circuit can be described in a circuit language, which can be PSPICE language and Verilog language. Writing this circuit language into the above-mentioned electronic device 100, the processor 102 in the electronic device 100 executes this circuit language, and can simulate the test chip 400, and can simulate the clock frequency of the test chip 400.

[0076] The test chip 400 in the present disclosure refers to a chip with multiple clock frequencies. The test chip 400 can be a system-on-chip including multiple clock frequencies.

[0077] The static timing analysis (STA) in the present disclosure is to confirm whether there is a timing violation in the chip design stage. When the circuit cells in the chip meet the timing requirements under the set parameter library, the chip can be taped out.

[0078] In the present disclosure, using a test circuit to equivalently test the test chip 400 for aging analysis testing can reduce the aging analysis cost; performing aging analysis during the static timing analysis process can discover aging problems at the design stage, and the cost required to solve the aging problems is relatively low.

[0079] According to another embodiment of the present disclosure, as Figure 3 shown, it is a schematic structural diagram of a test circuit 310 provided by the present disclosure. The test circuit 310 includes a prediction unit 311, a capacitor 313, and a connection unit 312. The prediction unit 311 and the connection unit 312 are connected in series end to end. The number of capacitors 313 is the same as that of the prediction units 311, and the capacitors 313 and the prediction units 311 are connected in one-to-one correspondence.

[0080] It should be understood that by adjusting the number of the prediction units 311 and the capacitance value of the capacitors 313, the initialization setting of the test circuit 310 can be realized, so that the factory frequency of the test circuit 310 is within the frequency range to be measured.

[0081] By adjusting the number of the prediction units 311 and the capacitance value of the capacitors 313, the magnitude of the factory frequency generated by the test circuit 310 can be adjusted. This factory frequency can be understood as the oscillation frequency after the initialization setting of the test circuit 310, and the factory frequency can characterize the clock frequency of the test chip 400 at the factory stage.

[0082] It should be understood that if the number of prediction units 311 is increased and / or the capacitance value of the capacitor 313 is increased, the level conversion time of the test circuit 310 is increased, and thus the factory frequency of the test circuit 310 is decreased. If the number of prediction units 311 is decreased and / or the capacitance value of the capacitor 313 is decreased, the level conversion time of the test circuit 310 is decreased, and thus the factory frequency of the test circuit 310 is increased.

[0083] As Figure 4 shown, the prediction unit 311 includes a first inverter U1, a NAND gate U2, a NOR gate U3, and a second inverter U4. The output terminal of the first inverter U1 is connected to the input terminal of the NAND gate U2. The output terminal of the NAND gate U2 is connected to the input terminal of the NOR gate U3. The output terminal of the NOR gate U3 is connected to the input terminal of the second inverter U4. The input terminal of the first inverter U1 is connected to one of the other prediction units 311, or the input terminal of the first inverter U1 is connected to the connection unit 312. The output terminal of the second inverter U4 is connected to one of the other prediction units 311, or the output terminal of the second inverter U4 is connected to the connection unit 312. The output terminal of the second inverter U4 is also connected to the corresponding capacitor 313.

[0084] It should be understood that if both the prediction unit 311 and the capacitor 313 are one, the input terminal of the first inverter U1 and the output terminal of the second inverter U4 are both connected to the connection unit 312.

[0085] If there are two prediction units 311 and two capacitors 313, namely the first prediction unit 311, the second prediction unit 311, the first capacitor 313, and the second capacitor 313. The input terminal of the first inverter U1 of the first prediction unit 311 is connected to the connection unit 312. The output terminal of the second inverter U4 of the first prediction unit 311 is connected to both the input terminal of the first inverter U1 of the second prediction unit 311 and the first capacitor 313. The output terminal of the second inverter U4 of the second prediction unit 311 is connected to both the connection unit 312 and the second capacitor 313.

[0086] If the number of prediction units 311 and capacitors 313 exceeds two, they are respectively a head prediction unit 311, a tail prediction unit 311, and at least one middle prediction unit 311. The input end of the first inverter U1 in the head prediction unit 311 is connected to the connection unit 312; if there is one middle prediction unit 311, the output end of the second inverter U4 in the head prediction unit 311 is connected to the input end of the first inverter U1 of the middle prediction unit 311, the output end of the second inverter U4 of the middle prediction unit 311 is connected to the input end of the first inverter U1 of the tail prediction unit 311, and the output end of the second inverter U4 of the tail prediction unit 311 is connected to the connection unit 312; if there are multiple middle prediction units 311, the multiple middle prediction units 311 are connected in series. The input end of the first inverter U1 of the first prediction unit 311 among the multiple serially connected middle prediction units 311 is not connected to other middle prediction units 311, so the input end of the first inverter U1 in the first prediction unit 311 is connected to the output end of the second inverter U4 in the head prediction unit 311. The output end of the second inverter U4 of the last prediction unit 311 among the multiple serially connected middle prediction units 311 is not connected to other middle prediction units 311, so the output end of the second inverter U4 in the last prediction unit 311 is connected to the input end of the first inverter U1 in the tail prediction unit 311. The output end of the second inverter U4 in each prediction unit 311 is also connected to the corresponding capacitor 313.

[0087] Please continue to refer to Figure 4 , the connection unit 312 includes a third inverter U5. If there is one prediction unit 311 and one capacitor 313, one end of the prediction unit 311 is connected to one end of the third inverter U5, and the other end of the prediction unit 311 is connected to the other end of the third inverter U5 and the capacitor 313.

[0088] It should be understood that the input end of the first inverter U1 in the prediction unit 311 is connected to one end of the third inverter U5, and the output end of the second inverter U4 in the prediction unit 311 is connected to the other end of the third inverter U5 and the capacitor 313.

[0089] If there are two prediction units 311 and two capacitors 313, the prediction units 311 include a first prediction unit 311 and a second prediction unit 311, and the capacitors 313 include a first capacitor 313 and a second capacitor 313. One end of the first prediction unit 311 is connected to one end of the third inverter U5, the other end of the first prediction unit 311 is connected to one end of the first capacitor 313 and the second prediction unit 311, and the other end of the second prediction unit 311 is connected to the second capacitor 313 and the other end of the third inverter U5.

[0090] It should be understood that the input terminal of the first inverter U1 in the first prediction unit 311 is connected to one end of the third inverter U5, and the output terminal of the second inverter U4 in the second prediction unit 311 is connected to the other end of the third inverter U5.

[0091] If the number of prediction units 311 and capacitors 313 exceeds two, the prediction unit 311 includes a head prediction unit 311, a tail prediction unit 311, and at least one middle prediction unit 311. One end of the head prediction unit 311 is connected to one end of the third inverter U5; if there is one middle prediction unit 311, the other end of the head prediction unit 311 is connected to one end of the middle prediction unit 311, the other end of the middle prediction unit 311 is connected to one end of the tail prediction unit 311, and the other end of the tail prediction unit 311 is connected to the other end of the third inverter U5; if there are multiple middle prediction units 311, the other end of the head prediction unit 311 is connected to one end of the serially connected middle prediction units 311, and the other end of the serially connected middle prediction units 311 is connected to one end of the tail prediction unit 311; the other ends of the head prediction unit 311, the tail prediction unit 311, and the middle prediction unit 311 are respectively connected to the corresponding capacitors 313.

[0092] It should be understood that the input terminal of the first inverter U1 in the head prediction unit 311 is connected to one end of the third inverter U5, and the output terminal of the second inverter U4 in the tail prediction unit 311 is connected to the other end of the third inverter U5.

[0093] In the present disclosure, one end of the third inverter U5 is the input terminal of the inverter, and the other end of the third inverter U5 is the output terminal of the inverter.

[0094] When initializing the test circuit 310, a working voltage is provided at one end of the third inverter U5, and the rising-edge voltage period at one end of the third inverter U5 is measured to obtain the factory frequency. By adjusting the number of prediction units 311 and the capacitance value of the capacitor 313, the magnitude of the factory frequency can be adjusted, and thus the factory frequency can be adjusted within the frequency range to be measured.

[0095] In the present disclosure, in order to ensure that the test circuit 310 can equivalently test the chip 400 and better simulate the chip 400. The signal probability (SP) of the test circuit 310 can be set to 0.5, and the loop gain can be set to 1.

[0096] The test chip 400 mainly consists of inverters, NAND gates, NOR gates, and capacitors. Therefore, the circuit components of the test circuit 310 are the same as those of the test chip 400. Aging analysis based on the test circuit 310 can equivalently test the test chip 400. Moreover, when performing aging analysis on the test circuit 310, the factory frequency can be adjusted according to requirements, while the frequency of the test chip 400 is fixed after design and cannot be adjusted. Therefore, the test circuit 310 has higher flexibility than the test chip 400. At the same time, when performing aging analysis, the test circuit 310 is described in circuit language rather than being built from actual circuit components. Therefore, using the test circuit 310 for aging analysis results in lower experimental costs.

[0097] Since the test chip 400 includes multiple clocks, the clock frequencies between different clocks may be different. If aging analysis is performed for the frequency of each clock, the aging analysis process will be too cumbersome. To simplify the aging analysis process, clocks with adjacent frequencies share a timing decay factor, that is, clocks with clock frequencies within the frequency range to be measured share a timing decay factor. That is to say, the frequency range to be measured can include at least one clock frequency of the test chip. To cover all clock frequencies of the test chip 400 and ensure the accuracy of the aging analysis of the test chip 400, the frequency range to be measured can be set to different frequency bands.

[0098] For example, if the test chip includes n clocks and the total frequency range of the n clocks is from 0M to 750M, a frequency range to be measured can be set every 250MHz. That is, the range from 0M to 250M is set as the frequency range to be measured a, the range from 250M to 500M is set as the frequency range to be measured b, and the range from 500M to 750M is set as the frequency range to be measured c. If the frequencies of m clocks among the n clocks are within the range from 0M to 250M, these m clocks share a timing decay factor; if the frequencies of p clocks among the n clocks are within the range from 250M to 500M, these p clocks share a timing decay factor; if the frequencies of q clocks among the n clocks are within the range from 500M to 750M, these q clocks share a timing decay factor.

[0099] It should be understood that with different clock frequencies, within the same time, the number of switching times of the MOS transistors in the test chip 400 is different, and the aging speed of the transistors in the test chip 400 is different. The timing decay factors corresponding to different frequency ranges to be measured are different. The timing decay factors corresponding to different frequency ranges to be measured can be calculated according to the chip aging analysis method of the present disclosure. Based on different timing decay factors, timing analysis can be performed to obtain the timing analysis results of different clocks, and the aging conditions of each clock can be obtained according to the timing analysis results.

[0100] In the present disclosure, the principle of obtaining the timing decay factor corresponding to each frequency band to be measured is the same. By using different frequency ranges for the frequency bands to be measured, the corresponding timing decay factors can be obtained.

[0101] The principle of obtaining the timing decay factor can be as follows: Under simulation conditions, perform aging simulation on the test circuit 310 after initial setting to obtain the aging frequency; calculate the timing decay factor based on the aging frequency.

[0102] It should be understood that the simulation conditions include transient simulation conditions and stress simulation conditions. The transient simulation conditions are the simulation conditions required for transient simulation. The transient simulation conditions include the transient operating temperature and the transient operating voltage. The transient operating temperature is the product temperature; the transient operating voltage is the product operating voltage. The stress simulation conditions are the simulation conditions required for stress simulation. The stress simulation conditions include the stress operating temperature, the stress operating voltage, and the hardware parameter variation function; the stress operating temperature is the product of the product temperature and the temperature coefficient of resistance; the stress operating voltage is the product of the product operating voltage and the voltage coefficient, and the voltage coefficient can take a value of 1.1; the hardware parameter variation function is generated by the aging model according to the preset operating time limit. The aging model is provided by the foundry, and the aging model can be an HCI (Hot Carrier Injection effect) & PBTI (Positive Bias Temperature Instability) co-aging model.

[0103] Among them, the stress simulation conditions are more severe than the transient simulation conditions, that is, the stress operating temperature is higher than the transient operating temperature, and the stress operating voltage is higher than the transient operating voltage.

[0104] The hardware parameter variation function can be understood as the variation relationship of the hardware parameters of the test circuit 310 or the test chip 400 under the preset operating time limit. The hardware parameter variation function can be deduced by the foundry according to empirical values. The variation relationships of the hardware parameters of the test circuit 310 under different preset operating time limits can be the same or different. That is to say, the hardware parameter variation functions obtained under different preset operating time limits can be the same or different. It can be obtained according to the actual variation relationships of different hardware parameters in the test circuit 310.

[0105] Under simulation conditions, aging simulation is performed on the test circuit 310 after initialization settings. The principle of obtaining the aging frequency is as follows: Under transient simulation conditions, transient simulation is performed on the test circuit 310 after initialization settings to obtain the initial frequency; under pressure simulation conditions, pressure simulation is performed on the test circuit 310 after initialization settings to obtain the hardware parameters of the test circuit 310 after aging; based on the hardware parameters after aging, the test circuit 310 after initialization settings is adjusted to obtain the adjusted test circuit 310; under transient simulation conditions, transient simulation is performed on the adjusted test circuit 310 to obtain the aging frequency.

[0106] It should be understood that under a transient operating temperature environment, a transient operating voltage is provided to the test circuit 310 after initialization settings to cause the test circuit 310 after initialization settings to start oscillating; after the test circuit 310 after initialization settings starts oscillating stably, the initial frequency is obtained.

[0107] Under a transient operating temperature environment, a transient operating voltage is provided to the test circuit 310 with the number of prediction units 311 and the capacitance value of the capacitor 313 adjusted. This transient operating voltage is provided to one end of the third inverter U5. After the test circuit 310 obtains the transient operating voltage, it starts to oscillate. After the oscillation stabilizes, the rising edge voltage period at one end of the third inverter U5 is measured to obtain the initial frequency.

[0108] It can be understood that after the test circuit 310 after initialization settings starts oscillating stably, the initial waveform of the test circuit 310 after initialization settings is obtained; the initial frequency is obtained according to the initial waveform.

[0109] In the present disclosure, after the test circuit 310 after initialization settings starts oscillating stably, the initial waveform at one end of the third inverter U5 can be measured, and the rising edge voltage period is obtained according to the initial waveform to obtain the initial frequency.

[0110] For example, taking the 50% voltage value of a certain rising edge in the initial waveform as the starting point, with an interval of k cycles, and taking the 50% voltage value of the rising edge of the kth cycle as the end point, the total duration from the starting point to the end point is measured, and the initial frequency can be obtained by dividing the total duration from the starting point to the end point by k.

[0111] Under a pressure operating temperature environment, a pressure operating voltage is provided to the test circuit 310 after initialization settings to cause the test circuit 310 after initialization settings to start oscillating; a hardware parameter change function is provided to the test circuit 310 after initialization settings, so that during the operation of the preset working time limit, the initial hardware parameters are changed to the hardware parameters after aging according to the hardware parameter change function.

[0112] It should be understood that after the initialization setting, the test circuit 310 provides the pressure operating voltage to one end of the third inverter U5 in the test circuit 310 under the pressure operating temperature environment, and the test circuit 310 after the initialization setting starts to oscillate. During the operation of the preset working time limit by the test circuit 310 after the initialization setting, the hardware parameter variation function changes the initial hardware parameters into the aged hardware parameters and obtains the aged hardware parameters. Among them, the initial hardware parameters are the hardware parameters of the test circuit 310 in the initialization state, which can also be understood as the hardware parameters of the test circuit 310 just out of the factory; the aged hardware parameters are the hardware parameters of the test circuit 310 after working for the preset working time limit.

[0113] In the present disclosure, the hardware parameters include the gate oxide thickness, surface inversion potential, sidewall capacitance, depletion capacitance, and body effect parameter. It should be understood that the gate oxide thickness, surface inversion potential, sidewall capacitance, depletion capacitance, and body effect parameter are the parameters of the transistor structure in the test circuit 310 and the test chip 400.

[0114] Different hardware parameters have corresponding variation functions. It can be understood that the hardware parameter variation functions include the gate oxide thickness variation function, surface inversion potential variation function, sidewall capacitance variation function, depletion capacitance variation function, and body effect parameter variation function. The gate oxide thickness variation function characterizes the variation relationship of the gate oxide thickness under the preset working time limit, the surface inversion potential variation function characterizes the variation relationship of the surface inversion potential under the preset working time limit, the sidewall capacitance variation function characterizes the variation relationship of the sidewall capacitance under the preset working time limit, the depletion capacitance variation function characterizes the variation relationship of the depletion capacitance under the preset working time limit, and the body effect parameter variation function characterizes the variation relationship of the body effect parameter under the preset working time limit.

[0115] The variation functions of different hardware parameters are different, and the variation functions of the same hardware parameter are different under different preset working time limits. For example, if the total working time limit (i.e., the maximum service life) of the test chip 400 or the test circuit 310 is 10 years, the first year is the preset working time limit a, the second to the third year is the preset working time limit b, and the fourth to the tenth year is the preset working time limit c. The variation functions of each hardware parameter under the preset working time limit a are the gate oxide thickness variation function a1, the surface inversion potential variation function b1, the sidewall capacitance variation function c1, the depletion capacitance variation function d1, and the body effect parameter variation function e1; the variation functions of each hardware parameter under the preset working time limit b are the gate oxide thickness variation function a2, the surface inversion potential variation function b2, the sidewall capacitance variation function c2, the depletion capacitance variation function d2, and the body effect parameter variation function e2; the variation functions of each hardware parameter under the preset working time limit c are the gate oxide thickness variation function a3, the surface inversion potential variation function b3, the sidewall capacitance variation function c3, the depletion capacitance variation function d3, and the body effect parameter variation function e3.

[0116] If it is necessary to obtain the hardware parameters of the test circuit 310 after the preset working time limit a, the initialized test circuit 310 changes the initial hardware parameters into aged hardware parameters according to the gate oxide thickness variation function a1, the surface inversion potential variation function b1, the sidewall capacitance variation function c1, the depletion capacitance variation function d1, and the body effect parameter variation function e1. The initial hardware parameters include the gate oxide thickness a1, the surface inversion potential b1, the sidewall capacitance c1, the depletion capacitance d1, and the body effect parameter e1, and the aged hardware parameters include the gate oxide thickness a2, the surface inversion potential b2, the sidewall capacitance c2, the depletion capacitance d2, and the body effect parameter e2. The initialized test circuit 310 changes the gate oxide thickness a1 into the gate oxide thickness a2 according to the gate oxide thickness variation function a1, the initialized test circuit 310 changes the surface inversion potential b1 into the surface inversion potential b2 according to the surface inversion potential variation function b1, the initialized test circuit 310 changes the sidewall capacitance c1 into the sidewall capacitance c2 according to the sidewall capacitance variation function c1, the initialized test circuit 310 changes the depletion capacitance d1 into the depletion capacitance d2 according to the depletion capacitance variation function d1, and the initialized test circuit 310 changes the body effect parameter e1 into the body effect parameter e2 according to the body effect parameter variation function e1.

[0117] If it is necessary to obtain the hardware parameters after the test circuit 310 has operated for a preset working time limit b, pressure simulation should be performed on the test circuit 310 that has operated for a preset working time limit a to obtain the hardware parameters after the test circuit 310 has operated for a preset working time limit b. It can be understood that the test circuit 310 that has operated for a preset working time limit a starts to oscillate after receiving the pressure working voltage in the pressure working temperature environment. During the oscillation process, the initial hardware parameters are changed to the aged hardware parameters according to the gate oxide thickness change function a2, the surface inversion potential change function b2, the sidewall capacitance change function c2, the depletion capacitance change function d2, and the body effect parameter change function e2.

[0118] That is to say, the initial hardware parameters here are the hardware parameters after the test circuit 310 after initialization setting has operated for a preset working time limit a, which include the gate oxide thickness a2, the surface inversion potential b2, the sidewall capacitance c2, the depletion capacitance d2, and the body effect parameter e2. The aged hardware parameters here are the hardware parameters after the test circuit 310 has operated for a preset working time limit b, which include the gate oxide thickness a3, the surface inversion potential b3, the sidewall capacitance c3, the depletion capacitance d3, and the body effect parameter e3.

[0119] The test circuit 310 that has operated for a preset working time limit a changes the gate oxide thickness a2 to the gate oxide thickness a3 according to the gate oxide thickness change function a2; the test circuit 310 that has operated for a preset working time limit a changes the surface inversion potential b2 to the surface inversion potential b3 according to the surface inversion potential change function b2; the test circuit 310 that has operated for a preset working time limit a changes the sidewall capacitance c2 to the sidewall capacitance c3 according to the sidewall capacitance change function c2; the test circuit 310 that has operated for a preset working time limit a changes the depletion capacitance d2 to the depletion capacitance d3 according to the depletion capacitance change function d2; the test circuit 310 that has operated for a preset working time limit a changes the body effect parameter e2 to the body effect parameter e3 according to the body effect parameter change function e2.

[0120] Similarly, if it is necessary to obtain the hardware parameters after the test circuit 310 has operated for a preset working time limit c, the principle of obtaining the hardware parameters after the test circuit 310 has operated for a preset working time limit b can be referred to, which will not be elaborated here.

[0121] If it is necessary to obtain the aging frequency after the test circuit 310 has operated for a preset working time limit a, in the present disclosure, two implementation manners are provided. The first implementation manner is: after the pressure simulation is performed on the test circuit 310 after initialization setting, based on the test circuit 310 after pressure simulation, the pressure simulation conditions are changed to transient simulation conditions, and transient simulation is continued to obtain the aging frequency after operating for a preset working time limit a.

[0122] The second implementation method is as follows: After the pressure simulation is performed on the test circuit 310 after the initialization settings, the parameters of the test circuit 310 after the initialization settings are adjusted based on the hardware parameters after the preset working time limit a of operation, and the adjusted test circuit 310 is obtained; the adjusted test circuit 310 performs a transient simulation under transient simulation conditions to obtain the aging frequency.

[0123] It can be understood that both implementation methods of the present disclosure can obtain the aging frequency of the test circuit 310 after the preset working time limit a of operation. The first method requires fewer process steps than the second method, and the second method has a simpler implementation logic than the first method. The first method requires a piece of code to implement all steps, while the second method can use multiple pieces of code to implement the content of different steps and implement all steps by calling sub-functions.

[0124] In the second method, the content of adjusting the parameters of the test circuit 310 after the initialization settings based on the hardware parameters after the preset working time limit a of operation to obtain the adjusted test circuit 310 includes: adjusting the gate oxide thickness, surface inversion potential, sidewall capacitance, depletion capacitance, and body effect parameters of the transistors in the test circuit 310 after the initialization settings based on the aged hardware parameters.

[0125] It can be understood that based on the hardware parameters after the preset working time limit a of operation, the gate oxide thickness a1, surface inversion potential b1, sidewall capacitance c1, depletion capacitance d1, and body effect parameter e1 of the transistors in the test circuit 310 after the initialization settings are adjusted to the gate oxide thickness a2, surface inversion potential b2, sidewall capacitance c2, depletion capacitance d2, and body effect parameter e2.

[0126] Similarly, to obtain the aging frequencies of the test circuit 310 after the preset working time limits b and c of operation, it can be achieved based on the principle of obtaining the aging frequency of the preset working time limit a, which will not be elaborated here.

[0127] In the present disclosure, the principle of performing a transient simulation on the adjusted test circuit 310 to obtain the aging frequency is the same as the principle of performing a transient simulation on the test circuit 310 after the initialization settings to obtain the initial frequency, which will not be elaborated here.

[0128] It should be understood that the aging frequency is the frequency obtained by performing a transient simulation again on the test circuit 310 after the preset working time limit of the initialization settings.

[0129] In the present disclosure, the principle of calculating the timing decay factor based on the aging frequency can be: performing a subtraction operation on the aging frequency and the initial frequency to obtain the delay decay parameter; performing a division operation on the delay decay parameter and the initial frequency to obtain the timing decay factor.

[0130] If the aging frequency is obtained after the test circuit 310 operates according to the preset timing sequence a, the corresponding timing attenuation factor is the timing attenuation factor of the test circuit 310 operating according to the preset timing sequence a. If the aging frequency is obtained after the test circuit 310 operates according to the preset timing sequence b, the corresponding timing attenuation factor is the timing attenuation factor of the test circuit 310 operating according to the preset timing sequence b. If the aging frequency is obtained after the test circuit 310 operates according to the preset timing sequence c, the corresponding timing attenuation factor is the timing attenuation factor of the test circuit 310 operating according to the preset timing sequence c.

[0131] In the present disclosure, the principle of performing timing analysis on the timing paths of the test chip 400 based on the timing attenuation factor to obtain the timing analysis result can be as follows: during the static timing analysis process, obtain the actual timing used by the timing paths of the test chip 400 to transmit the test signal; perform a multiplication operation on the actual timing and the timing attenuation factor to obtain the aged timing; compare the aged timing with the preset timing to obtain the timing analysis result.

[0132] It should be understood that if the timing attenuation factor is the timing attenuation factor obtained under the condition of the frequency band a to be measured and the preset working time limit a, the corresponding timing analysis result can characterize the aging condition of the clock within the frequency band a to be measured after the test chip 400 operates for the preset working time limit a.

[0133] In the present disclosure, if the aged timing is greater than the preset timing, the timing analysis result indicates that there is a violation problem in this timing path, which also means that there will be an aging problem in this timing path after the test chip 400 operates for the preset working time limit. If the aged timing is less than or equal to the preset timing, the timing analysis result indicates that there is no violation problem in this timing path, which also means that there will be no aging problem in this timing path after the test chip 400 operates for the preset working time limit.

[0134] In the present disclosure, a single timing attenuation factor is used for the timing analysis of different timing paths of all the timing paths on the test chip 400. For the clocks in different frequency bands to be measured, different timing attenuation factors are used for the timing analysis of all the timing paths; for the clocks in the same frequency band to be measured, different timing attenuation factors are used for the timing analysis of all the timing paths under different preset working time limits.

[0135] In the present disclosure, by performing timing analysis based on the timing attenuation factor during the static timing analysis process, aging failure analysis can be achieved efficiently and quickly, and preventive measures can be taken at the design stage of the test chip 400, thereby reducing the cost of solving aging problems.

[0136] The embodiment of the present disclosure also provides a chip aging analysis device, as Figure 5 shown, the chip aging analysis device 300 includes:

[0137] The timing decay factor acquisition module 320 is configured to perform aging analysis tests based on the test circuit 310 to obtain at least one timing decay factor; the timing decay factor is used to characterize the clock frequency change coefficient of the test chip under a preset working life, and the timing decay factors corresponding to the clock frequencies in different frequency bands to be measured are different.

[0138] The static timing analysis module 330 is configured to perform timing analysis on the timing paths of the test chip 400 based on the timing decay factor during the static timing analysis process to obtain a timing analysis result.

[0139] The timing violation judgment module 340 is configured to judge whether there is a timing violation in the timing path according to the timing analysis result.

[0140] In the present disclosure, the static timing analysis module 320 is further configured to obtain the actual timing used by the timing path of the test chip 400 to transmit the test signal during the static timing analysis process; perform a multiplication operation on the actual timing and the timing decay factor to obtain the aging timing; compare the aging timing with the preset timing to obtain the timing analysis result.

[0141] In the present disclosure, the product form of the above-mentioned electronic device 100 may be a desktop computer, a notebook, a server, a test device, etc.

[0142] Based on the above solution, using the test circuit to equivalently test the chip for aging analysis tests can reduce the cost of aging analysis; performing aging analysis during the design stage can not only discover aging problems in advance, but also reduce the cost of solving aging problems.

[0143] Those skilled in the art should understand that the embodiments of the present disclosure may be provided as a method, an apparatus, or an electronic device. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer programs.

[0144] The present disclosure is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or block in the flowcharts and / or block diagrams, and the combination of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate for implementation in the process Figure 1One or more processes and / or blocks Figure 1 Apparatus for the functions specified in one or more blocks

[0145] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction apparatus that implements the functions in the process Figure 1 One or more processes and / or blocks Figure 1 The functions specified in one or more blocks

[0146] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus, such that a series of operational steps are performed on the computer or other programmable apparatus to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions in the process Figure 1 One or more processes and / or blocks Figure 1 The steps of the functions specified in one or more blocks

[0147] Although the preferred embodiments of the present disclosure have been described, additional changes and modifications can be made by those skilled in the art once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to cover the preferred embodiments as well as all changes and modifications that fall within the scope of the present disclosure

[0148] Obviously, those skilled in the art can make various changes and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations

Claims

1. A chip aging analysis method, the method comprising: Based on the test circuit, aging analysis tests are carried out to obtain at least one timing decay factor; The timing decay factor is used to characterize the clock frequency change coefficient of the test chip under the preset working years, and the timing decay factors corresponding to the clock frequencies in different frequency ranges to be measured are different; wherein, the test circuit includes a prediction unit, a capacitor and a connection unit, the prediction unit and the connection unit are connected in series end to end, the number of the capacitors is the same as that of the prediction units, and the capacitors and the prediction units are connected in one-to-one correspondence; the prediction unit includes a first inverter, a NAND gate, a NOR gate and a second inverter, the output end of the first inverter is connected to the input end of the NAND gate, the output end of the NAND gate is connected to the input end of the NOR gate, the output end of the NOR gate is connected to the input end of the second inverter, the input end of the first inverter is connected to one of the other prediction units, or the input end of the first inverter is connected to the connection unit; the output end of the second inverter is connected to one of the other prediction units, or the output end of the second inverter is connected to the connection unit, and the output end of the second inverter is also connected to the corresponding capacitor; the connection unit includes a third inverter, and the third inverter is connected to both the prediction unit and the capacitor; During the static timing analysis process, based on the timing decay factor, timing analysis is carried out on the timing path of the test chip to obtain a timing analysis result; Judge whether there is a timing violation in the timing path according to the timing analysis result.

2. The method according to claim 1, the step of performing an aging analysis test based on a test circuit to obtain a timing decay factor comprises: Perform initialization settings on the test circuit so that the factory frequency of the test circuit is within the frequency range to be measured; Under simulation conditions, perform aging simulation on the initialized test circuit to obtain an aging frequency; Calculate the timing decay factor according to the aging frequency.

3. The method according to claim 2, if the prediction unit and the capacitor are one, one end of the prediction unit is connected to one end of the third inverter, and the other end of the prediction unit is connected to the other end of the third inverter and the capacitor; If the prediction unit and the capacitor are two, the prediction unit includes a first prediction unit and a second prediction unit, the capacitor includes a first capacitor and a second capacitor, one end of the first prediction unit is connected to one end of the third inverter, the other end of the first prediction unit is connected to one end of the first capacitor and the second prediction unit, and the other end of the second prediction unit is connected to the second capacitor and the other end of the third inverter; If the number of the prediction unit and the capacitor exceeds two, the prediction unit includes a head prediction unit, a tail prediction unit and at least one middle prediction unit, and one end of the head prediction unit is connected to one end of the third inverter; if the middle prediction unit is one, the other end of the head prediction unit is connected to one end of the middle prediction unit, the other end of the middle prediction unit is connected to one end of the tail prediction unit, and the other end of the tail prediction unit is connected to the other end of the third inverter; if the middle prediction unit is multiple, the other end of the head prediction unit is connected to one end of the serially connected middle prediction units, the other end of the serially connected middle prediction units is connected to one end of the tail prediction unit; the other ends of the head prediction unit, the tail prediction unit and the middle prediction unit are respectively connected to corresponding capacitors.

4. The method according to claim 3, the step of performing an initialization setting on the test circuit to make the factory frequency of the test circuit within the frequency band to be measured comprises: Adjust the number of the prediction units and the capacitance value of the capacitors so that the factory frequency of the test circuit is within the frequency range to be measured.

5. The method according to claim 2, the simulation conditions include transient simulation conditions and stress simulation conditions; The step of performing aging simulation on the initialized test circuit under simulation conditions to obtain an aging frequency includes: Under the transient simulation conditions, perform transient simulation on the initialized test circuit to obtain an initial frequency; Under the stress simulation conditions, perform stress simulation on the initialized test circuit to obtain the hardware parameters of the initialized test circuit after aging; Based on the hardware parameters after aging, adjust the initialized test circuit to obtain an adjusted test circuit; Under the transient simulation conditions, perform transient simulation on the adjusted test circuit to obtain the aging frequency.

6. According to the method described in claim 5, the step of performing a transient simulation on the test circuit after the initialization settings under the transient simulation conditions to obtain an initial frequency includes: Under the transient operating temperature environment, provide a transient operating voltage to the initialized test circuit to make the initialized test circuit start to oscillate; After the initialized test circuit starts to oscillate stably, obtain the initial frequency.

7. According to the method described in claim 6, the step of obtaining the initial frequency after the test circuit starts to oscillate and stabilizes after the initialization settings includes: After the initialized test circuit starts to oscillate stably, obtain the initial waveform of the initialized test circuit; Obtain the initial frequency according to the initial waveform.

8. According to the method described in claim 5, the step of performing a stress simulation on the test circuit after the initialization settings under the stress simulation conditions to obtain the hardware parameters of the test circuit after aging includes: Under a pressure working temperature environment, a pressure working voltage is provided to the initialized test circuit to cause the initialized test circuit to start oscillating; and A hardware parameter change function is provided to the initialized test circuit, so that during the operation of the preset working time limit of the initialized test circuit, the initial hardware parameters are changed to the aged hardware parameters according to the hardware parameter change function.

9. According to the method described in claim 8, the hardware parameter variation function is generated by an aging model according to the preset operating time limit.

10. According to the method described in claim 5, the hardware parameters include gate oxide thickness, surface inversion potential, sidewall capacitance, depletion capacitance, and body effect parameters.

11. According to the method described in claim 10, the step of adjusting the test circuit after the initialization settings based on the aged hardware parameters to obtain an adjusted test circuit includes: Based on the aged hardware parameters, the gate oxide thickness, surface inversion potential, sidewall capacitance, depletion capacitance, and body effect parameters of the transistors in the initialized test circuit are adjusted.

12. According to the method described in claim 5, the step of calculating the timing decay factor based on the aging frequency includes: Subtract the aged frequency from the initial frequency to obtain a delay attenuation parameter; Divide the delay attenuation parameter by the initial frequency to obtain the timing attenuation factor.

13. According to the method described in claim 1, the step of performing timing analysis on the timing paths of the test chip based on the timing decay factor during static timing analysis to obtain a timing analysis result includes: During static timing analysis, obtain the actual timing used by the test chip to transmit the test signal on the timing path; Multiply the actual timing by the timing attenuation factor to obtain the aged timing; Compare the aged timing with the preset timing to obtain the timing analysis result.

14. A chip aging analysis device, the device comprising: A timing attenuation factor acquisition module, configured to perform aging analysis and testing based on a test circuit to obtain at least one timing attenuation factor; The timing attenuation factor is used to characterize the clock frequency change coefficient of the test chip under a preset working life, and the timing attenuation factors corresponding to the clock frequencies in different frequency bands to be measured are different; wherein, the test circuit includes a prediction unit, a capacitor, and a connection unit, the prediction unit and the connection unit are connected in series end to end, the number of the capacitors is the same as that of the prediction units, and the capacitors and the prediction units are connected in one-to-one correspondence; the prediction unit includes a first inverter, a NAND gate, a NOR gate, and a second inverter, the output end of the first inverter is connected to the input end of the NAND gate, the output end of the NAND gate is connected to the input end of the NOR gate, the output end of the NOR gate is connected to the input end of the second inverter, the input end of the first inverter is connected to one of the other prediction units, or the input end of the first inverter is connected to the connection unit; the output end of the second inverter is connected to one of the other prediction units, or the output end of the second inverter is connected to the connection unit, and the output end of the second inverter is also connected to the corresponding capacitor; the connection unit includes a third inverter, and the third inverter is connected to both the prediction unit and the capacitor; A static timing analysis module, configured to perform timing analysis on the timing path of the test chip based on the timing attenuation factor during static timing analysis to obtain a timing analysis result; A timing violation judgment module, configured to judge whether there is a timing violation in the timing path according to the timing analysis result.

15. An electronic device, comprising a memory and one or more processors, the memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the method according to any one of claims 1 to 13 is implemented.

16. A computer storage medium, having stored thereon a computer program, which when executed by a processor implements the steps of the method according to any one of claims 1 to 13.

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