Semiconductor devices

Abstract

The invention discloses a semiconductor device, which includes: a substrate; a drift layer; a first groove, wherein the spacing groove includes two sub-groove parts spaced apart in a first direction, wherein the sub-groove parts include a plurality of gate groove groups and a plurality of dummy gate grooves; a second groove, wherein the second groove is spaced apart in the first direction between the two sub-groove parts; a first connecting groove, wherein one of the two first connecting grooves connects one end of the plurality of second grooves in the first direction, and the other connects the other end of the plurality of second grooves in the first direction; and a second connecting groove, wherein the second connecting groove connects one end of the gate groove in the gate groove group adjacent to the second groove, and connects one end of the adjacent two gate groove groups adjacent to the second groove. Thus, not only can the insulated gate bipolar transistor region and the fast recovery diode region be prevented from interfering with each other in the process, and the respective performance of the two regions be guaranteed, but also the current carrying capacity of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device. Background Art

[0002] RC-IGBT (reverse conducting-Insulated Gate Bipolar Transistor) integrates IGBT (Insulated Gate Bipolar Transistor) and FRD (Fast Recovery Diode) into the same chip, making it have both forward and reverse conduction characteristics, with many advantages such as small size, high power density, low cost and high reliability.

[0003] In the related art, in the structure of RC-IGBT, the FRD region is often made by disconnecting the grooves to separate the IGBT region from the FRD region. However, this will not only lead to a deterioration in the current carrying capacity of the device, but also make the FRD region susceptible to the effects of processes such as the injection of the IGBT region, thereby deteriorating the performance of the FRD region and even the RC-IGBT. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device with better working performance and reliability.

[0005] According to an embodiment of the present invention, a semiconductor device comprises: a substrate, the substrate having a first main surface and a second main surface on the opposite side of the first main surface; a drift layer of a first conductive type, the drift layer being arranged between the first main surface and the second main surface; a first groove, the first groove extending from the first main surface toward the second main surface and reaching the drift layer, the first groove extending in a first direction and being multiple, the multiple first grooves being spaced apart in a second direction, and a portion of the multiple first grooves being spaced grooves; the spaced groove comprising two sub-groove portions spaced apart in the first direction, the sub-groove portions comprising a plurality of gate groove groups and a plurality of dummy gate grooves, the plurality of gate groove groups being spaced apart in the second direction, at least one dummy gate groove being arranged between two adjacent gate groove groups, the gate groove group comprising at least two gate grooves spaced apart in the second direction, wherein the gate groove is electrically connected to a gate of the semiconductor device, and the dummy gate groove is electrically connected to an emitter of the semiconductor device; a second groove, the second A groove extends from the first main surface toward the second main surface and reaches the drift layer, the second groove is extended in the first direction, there are multiple second groove parts and they are spaced apart from each other in the second direction, and the second groove is spaced apart between two sub-groove parts in the first direction; a first connecting groove, the first connecting groove extends from the first main surface toward the second main surface and reaches the drift layer, the first connecting groove extends in the second direction, there are two first connecting grooves, one of the two first connecting grooves connects one end of multiple second grooves in the first direction, and the other connects the other end of multiple second grooves in the first direction; a second connecting groove, the second connecting groove extends from the first main surface toward the second main surface and reaches the drift layer, the second connecting groove extends in the second direction, the second connecting groove connects one end of the gate groove in the gate groove group adjacent to the second groove, and connects one end of two adjacent gate groove groups adjacent to the second groove.

[0006] Therefore, by making one of the two first connecting grooves connect one end of the multiple second grooves in the first direction, and the other connecting the other end of the multiple second grooves in the first direction, and making the second connecting groove connect one end of the gate groove in the gate groove group adjacent to the second groove, and connecting one end of the adjacent second grooves of two adjacent gate groove groups, this can not only prevent the insulated gate bipolar transistor region and the fast recovery diode region from interfering with each other in the process and ensure the performance of each of the two regions, but also improve the current carrying capacity of the semiconductor device, thereby improving the working performance of the semiconductor device.

[0007] In some examples of the present invention, one end of the gate trench adjacent to the second trench protrudes beyond one end of the dummy gate trench adjacent to the second trench, and the dummy gate trench and the second connection trench are spaced apart from each other in the first direction.

[0008] In some examples of the present invention, the semiconductor device also includes: a third connecting trench, the third connecting trench extending from the first main surface toward the second main surface and reaching the drift layer, the third connecting trench extending in the second direction, at least two of the dummy gate trenches are arranged between two adjacent gate trench groups, and the third connecting trench connects one end of the dummy gate trench adjacent to the second trench between two adjacent gate trench groups.

[0009] In some examples of the present invention, the plurality of second trenches include a first sub-trench and a second sub-trench, the plurality of first sub-trenches and the plurality of gate trenches correspond one-to-one and are spaced apart from each other, and the plurality of second sub-trenches and the plurality of dummy gate trenches correspond one-to-one and are spaced apart from each other.

[0010] In some examples of the present invention, two of the second trenches on both sides of the second direction are respectively the first boundary trench and the second boundary trench, and the area enclosed by the first boundary trench, the second boundary trench and the two first connection trenches is a fast recovery diode area.

[0011] In some examples of the present invention, the outside of the area enclosed by the first boundary trench, the second boundary trench, and the two first connection trenches is an insulated gate bipolar transistor area.

[0012] In some examples of the present invention, the first connecting groove and the second connecting groove are spaced apart in the first direction.

[0013] In some examples of the present invention, the spacing distance between the first connecting groove and the second connecting groove in the first direction is D1, the spacing distance between two adjacent first grooves in the second direction is D2, and the spacing distance between two adjacent second grooves in the second direction is D3, and D1, D2 and D3 satisfy the relationship: D1=D2=D3.

[0014] In some examples of the present invention, D1 satisfies the relationship: 1 μm≤D1≤2 μm.

[0015] In some examples of the present invention, D1 satisfies the relationship: 1.5 μm≤D1≤2 μm.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0020] Figure 3 is a cross-sectional view of a semiconductor device along the AA direction according to an embodiment of the present invention;

[0021] Figure 4 is a partial schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0022] Figure 5 is a partial schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0023] Figure 6 is a cross-sectional view of a structure 1 according to an embodiment of the present invention;

[0024] Figure 7 is a cross-sectional view of structure 2 according to an embodiment of the present invention;

[0025] Figure 8 is a cross-sectional view of structure 3 according to an embodiment of the present invention;

[0026] Fig. 9 is a cross-sectional view of structure 4 according to an embodiment of the present invention;

[0027] Fig.10 is a cross-sectional view of a structure 5 according to an embodiment of the present invention.

[0028] Reference numerals:

[0029] 100, semiconductor device; 101, insulated gate bipolar transistor region; 102, fast recovery diode region;

[0030] 10. drift layer; 11. well region; 12. second emitter layer; 13. dielectric layer; 14. emitter metal layer; 15. field stop layer; 16. collector layer; 17. first emitter layer; 18. collector metal layer;

[0031] 20, first trench; 21, spacing trench; 221, sub-trench portion; 222, gate trench group; 2221, gate trench; 223, dummy gate trench;

[0032] 30. second groove; 31. first sub-groove; 32. second sub-groove; 33. first boundary groove; 34. second boundary groove;

[0033] 40. first connecting groove; 50. second connecting groove; 60. third connecting groove;

[0034] 70. Oxidation insulating layer; 71. Polysilicon;

[0035] 80. substrate; 81. first main surface; 82. second main surface. DETAILED DESCRIPTION

[0036] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0037] Reference below Figure 1-Figure 10 A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description.

[0038] Combination Figure 1-Figure 3 As shown, the semiconductor device 100 according to the present invention may mainly include: a substrate 80 , a drift layer 10 of a first conductivity type, a first trench 20 and a second trench 30 .

[0039] Specifically, a drift layer 10 of the first conductivity type is arranged in the substrate 80 and is located between the first main surface 81 and the second main surface 82. A well region 11 of the second conductivity type is also arranged in the substrate 80. The well region 11 is arranged on the side of the drift layer 10 close to the first main surface 81. A second emitter layer 12 of the first conductivity type is also arranged in the well region 11. In addition, a field stop layer 15 of the first conductivity type is also arranged in the substrate 80. The field stop layer 15 is arranged on the side of the drift layer 10 close to the second main surface 82. A collector layer 16 of the second conductivity type and a first emitter layer 17 of the first conductivity type are arranged on the side of the field stop layer 15 close to the second main surface 82. In addition, a dielectric layer 13 is arranged on the first main surface 81. An emitter metal layer 14 is arranged on the side of the dielectric layer 13 facing away from the first main surface 81. A collector metal layer 18 is also arranged on the second main surface 82 side of the substrate 80. In this way, the basic structure of the semiconductor device 100 can be formed.

[0040] The semiconductor device 100 may include an active region and a terminal region disposed at the periphery of the active region, the region corresponding to the collector layer 16 is the insulated gate bipolar transistor region 101, and the region corresponding to the first emitter layer 17 is the fast recovery diode region 102, that is, the active region of the semiconductor device 100 may include the insulated gate bipolar transistor region 101 and the fast recovery diode region 102, the emitter metal layer 14 may not only serve as the emitter lead-out terminal of the insulated gate bipolar transistor region 101, but also serve as the anode lead-out terminal of the fast recovery diode region 102, the collector metal layer 18 may not only serve as the collector lead-out terminal of the insulated gate bipolar transistor region 101, but also serve as the cathode lead-out terminal of the fast recovery diode region 102, so that the insulated gate bipolar transistor region 101 can realize forward conduction of the semiconductor device 100, and the fast recovery diode region 102 can realize reverse conduction of the semiconductor device 100, so that the semiconductor device 100 has the characteristics of forward conduction and reverse conduction at the same time.

[0041] Further, the first groove 20 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, and the first groove 20 is extended in the first direction, and the first groove 20 is arranged to be multiple, and the multiple first grooves 20 are arranged at intervals in the second direction, wherein a part of the multiple first grooves 20 is a spaced groove 21, and the spaced groove 21 can mainly include two sub-groove portions 221 spaced apart in the first direction, and the sub-groove portions 221 can include multiple gate groove groups 222 and multiple dummy gate grooves 223, and the multiple gate groove groups 222 are spaced apart in the second direction, and at least one dummy gate groove 223 is arranged between two adjacent gate groove groups 222, and the gate groove group 222 includes at least two gate grooves 2221 spaced apart in the second direction.

[0042] Specifically, both the gate trench 2221 and the dummy gate trench 223 are provided with an oxide insulating layer 70, and polysilicon 71 is deposited. Among them, the second emitter layer 12 is provided on both sides of the second direction of the gate trench 2221, and the gate trench 2221 has a conductive channel and has a current-carrying capacity, and can be electrically connected to the gate to ensure the normal operation of the insulated gate bipolar transistor region 101 and even the semiconductor device 100, while the second emitter layer 12 is not provided on both sides of the second direction of the dummy gate trench 223, and has no current-carrying capacity. The dummy gate trench 223 can be electrically connected to the emitter, and the Miller capacitance is reduced and the current density is reduced under the premise of ensuring the withstand voltage capability of the semiconductor device 100, thereby improving the short-circuit capability of the semiconductor device 100.

[0043] Furthermore, the second trench 30 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The second trench 30 is extended in the first direction. By setting the second trench 30 as a plurality and corresponding one-to-one with the plurality of first spacing trenches 21, not only can the junction depth and doping concentration of the well region 11 of the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 be the same, thereby ensuring that the two regions have the same withstand voltage, but also the process steps of the semiconductor device 100 can be simplified. Moreover, by setting the second trench 30 between the two sub-groove portions 221 in the first direction, the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 can be separated, thereby ensuring the performance of each of the two regions and ensuring the working performance of the semiconductor device 100.

[0044] Combination Figure 1-Figure 3 As shown, the semiconductor device 100 may also include: a first connecting groove 40, the first connecting groove 40 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, the first connecting groove 40 is extended in the second direction, there are two first connecting grooves 40, one of the two first connecting grooves 40 connects one end of the multiple second grooves 30 in the first direction, and the other connects the other end of the multiple second grooves 30 in the first direction.

[0045] Specifically, one ends of the plurality of second grooves 30 are flush with each other, and the other ends of the plurality of second grooves 30 are flush with each other. By setting the first connecting groove 40, the first connecting groove 40 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The first connecting groove 40 extends in the second direction, and the first connecting groove 40 is set as two, so that one of the two first connecting grooves 40 can be extended in the second direction while connecting one ends of the plurality of second grooves 30, and the other of the two first connecting grooves 40 can be extended in the second direction while connecting the other ends of the plurality of second grooves 30.

[0046] On the one hand, the two first connection grooves 40 can enclose the multiple second grooves 30, that is, the two first connection grooves 40 can separate the insulated gate bipolar transistor region 101 and the fast recovery diode region 102, thereby preventing the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 from interfering with each other in the process and ensuring the performance of the two regions. On the other hand, the two first connection grooves 40 can increase the current carrying capacity of the fast recovery diode region 102, so that the working performance of the semiconductor device 100 can be improved and the reliability of the semiconductor device 100 can be improved.

[0047] Combination Figure 1 and Figure 2As shown, the semiconductor device 100 may also include: a second connecting groove 50, the second connecting groove 50 extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, the second connecting groove 50 is extended in the second direction, the second connecting groove 50 connects the gate groove 2221 in the gate groove group 222 to one end of the second groove 30 adjacent to the gate groove 2221, and connects one end of the second groove 30 adjacent to two adjacent gate groove groups 222.

[0048] Specifically, the gate trench 2221 in each gate trench group 222 is flush with one end of the second trench 30 adjacent to the gate trench 30. By setting the second connecting groove 50, the second connecting groove 50 can connect one end of the gate trench 2221 in the gate trench group 222 adjacent to the second trench 30 when extending along the second direction, and the end portions of multiple gate trenches 2221 in two adjacent gate trench groups 222 adjacent to the second trench 30 are flush. The second connecting groove 50 connects one end of the gate trench 2221 in the gate trench group 222 adjacent to the second trench 30 and can continue to extend to connect one end of the second trench 30 adjacent to two adjacent gate trench groups 222.

[0049] That is, the second connecting groove 50 can connect all the gate grooves 2221 in the sub-groove portion 221 to one end adjacent to the second groove 30, and the second connecting groove 50 can enclose all the gate grooves 2221 in the sub-groove portion 221, thereby not only improving the current carrying capacity of the insulated gate bipolar transistor region 101 and even the semiconductor device 100, but also enclosing one end adjacent to the second groove 30 of the gate groove 2221 in each gate groove group 222, avoiding mutual interference between the gate groove group 222 and the second groove 30 in the process, preventing the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 from interfering with each other in the process, and ensuring the performance of the two regions.

[0050] Therefore, by making one of the two first connecting grooves 40 connect one end of the multiple second grooves 30 in the first direction, and the other connects the other end of the multiple second grooves 30 in the first direction, and making the second connecting groove 50 connect the end of the gate groove 2221 in the gate groove group 222 adjacent to the second groove 30, and connecting the ends of the two adjacent gate groove groups 222 adjacent to the second groove 30, this can not only prevent the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 from interfering with each other in the process and ensure the performance of each of the two regions, but also improve the current carrying capacity of the semiconductor device 100, thereby improving the working performance of the semiconductor device 100.

[0051] Combination Figure 1 and Figure 2As shown, one end of the gate trench 2221 adjacent to the second trench 30 protrudes beyond one end of the dummy gate trench 223 adjacent to the second trench 30 , and the dummy gate trench 223 and the second connection trench 50 are spaced apart from each other in the first direction.

[0052] Specifically, one end of the gate trench 2221 adjacent to the second trench 30 protrudes out from one end of the dummy gate trench 223 adjacent to the second trench 30. By making the end of the dummy gate trench 223 adjacent to the second trench 30 and the second connecting trench 50 also spaced apart in the first direction, the second connecting trench 50 can separate the dummy gate trench 223 from the first connecting trench 40 in the first direction, thereby avoiding mutual interference between the dummy gate trench 223 and the first connecting trench 40 or the second trench 30 in the process, further preventing the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 from interfering with each other in the process, and ensuring the performance of the two regions.

[0053] Furthermore, the semiconductor device 100 may also include: a third connecting groove 60, which extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10, and the third connecting groove 60 is extended in the second direction, and at least two dummy gate grooves 223 are arranged between two adjacent gate groove groups 222, and the third connecting groove 60 connects one end of the dummy gate groove 223 between the two adjacent gate groove groups 222 adjacent to the second groove 30.

[0054] Specifically, when at least two dummy gate trenches 223 are provided between two adjacent gate trench groups 222, one end of at least two dummy gate trenches 223 between two adjacent gate trench groups 222 is flush with one end of the second trench 30, and by providing a third connecting trench 60, the third connecting trench 60 is extended in the second direction and is spaced apart from the second connecting trench 50 in the second direction, so that the third connecting trench 60 can extend in the second direction while the dummy gate trench 223 between two adjacent gate trench groups 222 is adjacent to the second connecting trench 50. One end of the two trenches 30 is connected, so that not only can all the dummy gate trenches 223 between two adjacent gate trench groups 222 be connected, the third connecting trench 60 can play a role in current conduction, thereby improving the current conduction capacity of the semiconductor device 100, and the dummy gate trench 223 between two adjacent gate trench groups 222 can be enclosed at one end of the second trench 30, which can further prevent the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 from interfering with each other in the process, thereby ensuring the working performance of the semiconductor device 100.

[0055] Combination Figure 2As shown, the plurality of second grooves 30 may include a first sub-groove 31 and a second sub-groove 32, the plurality of first sub-grooves 31 and the plurality of gate grooves 2221 correspond one to one and are spaced apart from each other, and the plurality of second sub-grooves 32 and the plurality of dummy gate grooves 223 correspond one to one and are spaced apart from each other. In this way, on the premise of preventing the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 from interfering with each other in the process, not only can the circuit distribution of the semiconductor device 100 be made more uniform, the working performance of the semiconductor device 100 can be improved, but also the first sub-grooves 31 and the corresponding gate grooves 2221 can be conveniently etched synchronously, and the second sub-grooves 32 and the corresponding dummy gate grooves 223 can be conveniently etched synchronously, and the manufacturing process of the semiconductor device 100 can be simplified.

[0056] It should be noted that, in other embodiments of the present invention, Figure 4 and Figure 5 As shown, when there is no dummy gate trench 223 between two adjacent gate trench groups 222, that is, when no dummy gate trench 223 is set in the insulated gate bipolar transistor region 101 and only the gate trench 2221 is set, the semiconductor device 100 does not need to set the third connecting trench 60. It is only necessary to make the second connecting trench 50 connect one end of the multiple gate trenches 2221 adjacent to the second trench 30, and make one of the two first connecting trenches 40 connect one end of the multiple second trenches 30 in the first direction, and the other connect the other end of the multiple second trenches 30 in the first direction. This can not only prevent the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 from interfering with each other in the process and ensure the performance of the two regions respectively, but also increase the current carrying capacity of the two regions and improve the working performance of the semiconductor device 100.

[0057] As described above, two of the second grooves 30 on both sides of the second direction are defined as the first boundary groove 33 and the second boundary groove 34, so that the inside of the area enclosed by the first boundary groove 33, the second boundary groove 34 and the two first connection grooves 40 is the fast recovery diode area 102, and the outside of the area enclosed by the first boundary groove 33, the second boundary groove 34 and the two first connection grooves 40 is the insulated gate bipolar transistor area 101.

[0058] Considering that the first connection groove 40 is located at the junction of the fast recovery diode region 102 and the insulated gate bipolar transistor region 101, by arranging the first connection groove 40 and the second connection groove 50 at intervals in the first direction, not only can the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 be separated, and the mutual interference between the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 in the process can be effectively and reliably avoided, thereby ensuring the performance of the insulated gate bipolar transistor region 101 and the fast recovery diode region 102, but also the current carrying capacity of the semiconductor device 100 can be increased, thereby improving the working performance of the semiconductor device 100.

[0059] Combination Figure 2 and Figure 3 As shown, the spacing distance between the first connecting groove 40 and the second connecting groove 50 in the first direction is D1, the spacing distance between two adjacent first grooves 20 in the second direction is D2, and the spacing distance between two adjacent second grooves 30 in the second direction is D3. D1, D2 and D3 satisfy the relationship: D1=D2=D3.

[0060] Specifically, by setting the spacing distance between the first connecting groove 40 and the second connecting groove 50 in the first direction, the spacing distance between two adjacent first grooves 20 in the second direction, and the spacing distance between two adjacent second grooves 30 in the second direction to be equal, the distribution of the first connecting groove 40 and the second connecting groove 50 can be more uniform, which can improve the uniformity of the circuit distribution of the semiconductor device 100 and improve the working performance of the semiconductor device 100.

[0061] In addition, the processes in the first groove 20, the second groove 30, the first connecting groove 40, the second connecting groove 50, and the third connecting groove 60 are the same, and an oxide insulating layer 70 can be generated inside and polysilicon 71 can be deposited. The width and depth of the first groove 20, the second groove 30, the first connecting groove 40, the second connecting groove 50, and the third connecting groove 60 can be set to be the same, so that the first groove 20, the second groove 30, the first connecting groove 40, the second connecting groove 50, and the third connecting groove 60 can be etched simultaneously, which can simplify the process steps of the semiconductor device 100.

[0062] Further, D1 satisfies the relationship: 1.5μm≤D1≤2μm. Specifically, by setting the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction within a reasonable range, it is possible to avoid the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction being too small, resulting in the spacing distance between the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 being too small, resulting in the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 still having mutual interference in the process, and it is possible to avoid the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction being too large, resulting in the overall area of ​​the semiconductor device 100 being too large. In this way, a balance between the separation effect of the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 and the overall area of ​​the semiconductor device 100 can be achieved, and the structural design of the semiconductor device 100 can be further optimized to improve the working performance of the semiconductor device 100.

[0063] Furthermore, D1 satisfies the relationship: 1.5μm≤D1≤2μm, so that the spacing distance between the first connecting groove 40 and the second connecting groove 50 in the first direction can be set within a more optimal range, thereby further ensuring the balance between the separation effect of the insulated gate bipolar transistor region 101 and the fast recovery diode region 102 and the overall area of ​​the semiconductor device 100, and further optimizing the structural design of the semiconductor device 100 and improving the working performance of the semiconductor device 100.

[0064] Combine the following Figure 3 as well as Figure 6-Figure 10 The method for manufacturing the semiconductor device 100 is described by way of example. The semiconductor device 100 is an RC-IGBT:

[0065] like Figure 6 As shown, an N-substrate material is provided to form a structure 1.

[0066] like Figure 7 As shown, based on the structure 1, the first trench 20, the second trench 30, the first connecting trench 40, the second connecting trench 50 and the third connecting trench 60 are etched, and an oxidized insulating layer 70 is grown to form the structure 2.

[0067] like Figure 8 As shown, based on structure 2, polysilicon 71 is deposited and etched, and then the P well region 11 and the N+ second emitter layer 12 are implanted in sequence to form structure 3.

[0068] like Fig. 9 As shown, on the basis of structure 3, a dielectric layer 13 is deposited, and contact holes are etched on the dielectric layer 13 to form structure 4.

[0069] like Fig.10As shown, on the basis of structure 4, metal layer sputtering is performed to prepare an emitter metal layer 14 to form structure 5.

[0070] like Figure 3 As shown, based on the structure 5, the back N+ field stop layer 15 is implanted, the back P+ collector layer 16 is implanted, the back FRD region N+ first emitter layer 17 is implanted, laser annealing is performed, and the back metal sputtering is performed to prepare the collector metal layer 18. Finally, the semiconductor device 100 is formed.

[0071] Other structures and operations of the semiconductor device 100 according to the embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0072] In the description of the present invention, it is to be understood that the terms “center”, “”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0073] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0074] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A substrate (80), wherein the substrate (80) has a first main surface (81) and a second main surface (82) opposite to the first main surface (81); A drift layer (10) of a first conductivity type, the drift layer (10) being arranged between the first main surface (81) and the second main surface (82); a first trench (20), the first trench (20) extending from the first main surface (81) toward the second main surface (82) and reaching the drift layer (10), the first trench (20) extending in a first direction and being a plurality of first trenches (20), the plurality of first trenches (20) being spaced apart in a second direction, and a portion of the plurality of first trenches (20) being spaced trenches (21); The spacing groove (21) comprises two sub-groove portions (221) spaced apart in a first direction, the sub-groove portion (221) comprises a plurality of gate groove groups (222) and a plurality of dummy gate grooves (223), the plurality of gate groove groups (222) being spaced apart in a second direction, at least one dummy gate groove (223) being arranged between two adjacent gate groove groups (222), the gate groove group (222) comprising at least two gate grooves (2221) spaced apart in the second direction, wherein the gate groove (2221) is electrically connected to a gate of the semiconductor device (100), and the dummy gate groove (223) is electrically connected to an emitter of the semiconductor device (100); a second trench (30), the second trench (30) extending from the first main surface (81) toward the second main surface (82) and reaching the drift layer (10), the second trench (30) extending in the first direction, the second trench (30) being multiple and spaced apart from each other in the second direction, the second trench (30) being spaced apart between two sub-trench portions (221) in the first direction; a first connecting groove (40), the first connecting groove (40) extending from the first main surface (81) toward the second main surface (82) and reaching the drift layer (10), the first connecting groove (40) extending in the second direction, there being two first connecting grooves (40), one of the two first connecting grooves (40) connecting one end of a plurality of second grooves (30) in the first direction, and the other connecting the other end of a plurality of second grooves (30) in the first direction; a second connecting trench (50), the second connecting trench (50) extending from the first main surface (81) toward the second main surface (82) and reaching the drift layer (10), the second connecting trench (50) extending in a second direction, the second connecting trench (50) connecting one end of the gate trench (2221) in the gate trench group (222) adjacent to the second trench (30), and connecting one end of two adjacent gate trench groups (222) adjacent to the second trench (30); One end of the gate trench (2221) adjacent to the second trench (30) protrudes beyond one end of the dummy gate trench (223) adjacent to the second trench (30), and the dummy gate trench (223) and the second connecting trench (50) are spaced apart from each other in a first direction; A third connecting trench (60), the third connecting trench (60) extending from the first main surface (81) toward the second main surface (82) and reaching the drift layer (10), the third connecting trench (60) extending in the second direction, at least two dummy gate trenches (223) being arranged between two adjacent gate trench groups (222), the third connecting trench (60) connecting one end of the dummy gate trench (223) between two adjacent gate trench groups (222) adjacent to the second trench (30).

2. The semiconductor device according to claim 1, wherein: The plurality of second trenches (30) comprise a first sub-trench (31) and a second sub-trench (32); the plurality of first sub-trench (31) and the plurality of gate trenches (2221) correspond one-to-one and are arranged at intervals from each other; and the plurality of second sub-trench (32) and the plurality of dummy gate trenches (223) correspond one-to-one and are arranged at intervals from each other.

3. The semiconductor device according to claim 1, wherein: Two of the second grooves (30) on both sides of the second direction are respectively a first boundary groove (33) and a second boundary groove (34); and the interior of the area enclosed by the first boundary groove (33), the second boundary groove (34) and the two first connection grooves (40) is a fast recovery diode area (102).

4. The semiconductor device according to claim 3, wherein: The outside of the area enclosed by the first boundary trench (33), the second boundary trench (34) and the two first connection trenches (40) is an insulated gate bipolar transistor area (101).

5. The semiconductor device according to claim 3, wherein: The first connecting groove (40) and the second connecting groove (50) are arranged at intervals in the first direction.

6. The semiconductor device according to claim 1, wherein: The spacing distance between the first connecting groove (40) and the second connecting groove (50) in the first direction is D1, the spacing distance between two adjacent first grooves (20) in the second direction is D2, and the spacing distance between two adjacent second grooves (30) in the second direction is D3, and D1, D2 and D3 satisfy the relationship: D1=D2=D3.

7. The semiconductor device according to claim 6, wherein: D1 satisfies the relationship: 1μm≤D1≤2μm.

8. The semiconductor device according to claim 7, wherein: D1 satisfies the relationship: 1.5μm≤D1≤2μm.

Images