A Circuit Timing Optimization Method, Device, Electronic Device and Storage Medium

Abstract

The present application relates to a circuit timing optimization method, apparatus, electronic device, and computer-readable storage medium, belonging to the field of integrated circuits. The circuit timing optimization method includes: for a plurality of different specified input transition times, obtaining a first propagation delay of a target transmission circuit under each specified input transition time, where the target transmission circuit is the transmission circuit with the smallest propagation delay among a plurality of different transmission circuits, the transmission line lengths of each transmission circuit are the same, and different transmission circuits are simulated and constituted by basic units with different parameters; obtaining a target propagation delay with the smallest propagation delay among the plurality of first propagation delays, where the propagation delay of the transmission circuit constituted by the target basic unit corresponding to the target propagation delay is the smallest. This solution can shorten the simulation time of circuit timing optimization and improve the effect.

Description

Technical Field

[0001] This application belongs to the field of integrated circuits, and particularly relates to a circuit timing optimization method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0002] In the chip design of deep sub-micron (μm) process, with the evolution of the chip process, the width of metal interconnect lines continues to shrink, and the resistance effect of interconnect lines becomes more and more serious. In the scenario of long-distance (such as length exceeding 500 μm) critical signal transmission, the original design method faces challenges in aspects such as signal integrity, transmission delay, power consumption, and routing resource overhead. With the increase in chip complexity, in some chips, there is a scenario where the farthest module may be tens of thousands of microns away from the clock source. Therefore, improving the design quality, especially improving the design quality of the clock tree, has positive significance for accelerating timing convergence and shortening the design cycle. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a circuit timing optimization method, apparatus, electronic device, and computer-readable storage medium to shorten the simulation time of circuit timing optimization and improve the simulation effect.

[0004] The embodiments of this application are implemented as follows:

[0005] In a first aspect, an embodiment of this application provides a circuit timing optimization method, including: for multiple different specified input transition times, obtaining the first transmission delay of a target transmission circuit under each specified input transition time, where the target transmission circuit is the transmission circuit with the smallest transmission delay among multiple different transmission circuits, the transmission line lengths of each transmission circuit are the same, and different transmission circuits are simulated and constituted by basic units with different parameters; obtaining the target transmission delay with the smallest transmission delay among the multiple first transmission delays, where the transmission delay of the transmission circuit constituted by the target basic unit corresponding to the target transmission delay is the smallest.

[0006] In the embodiments of this application, by simulating the transmission delays of transmission circuits constituted by basic units with different parameters and obtaining the first transmission delay of the target transmission circuit with the smallest transmission delay under the specified input transition time, since there is no need to build a transmission circuit, the simulation duration can be shortened. At the same time, in order to obtain the minimum transmission delay of the transmission circuit as accurately as possible, the first transmission delay of the target transmission circuit under each of multiple different specified input transition times will be obtained, avoiding directly taking the first transmission delay of the target transmission circuit under a single specified input transition time as the minimum delay, which may lead to inaccurate determination of the transmission delay. This method can shorten the simulation time of circuit timing optimization and improve the simulation effect.

[0007] In a possible implementation manner of the first aspect, obtaining the first transmission delay of the target transmission circuit at each specified input transition time includes: obtaining the second transmission delays of a plurality of different transmission circuits at each specified input transition time; based on the plurality of second transmission delays, obtaining the first transmission delay of the target transmission circuit at each specified input transition time, where the first transmission delay is the minimum second transmission delay among the plurality of second transmission delays, and the target transmission circuit is simulated and constituted by the basic unit corresponding to the minimum second transmission delay.

[0008] In the embodiments of the present application, by obtaining the second transmission delays of a plurality of different transmission circuits at a specified input transition time and taking the minimum second transmission delay as the first transmission delay, the basic unit corresponding to the minimum second transmission delay is simulated to constitute the transmission circuit, which is the target transmission circuit. Through this method, the first transmission delay of the target transmission circuit at each specified input transition time can be obtained quickly and accurately. In a possible implementation manner of the first aspect, obtaining the second transmission delays of a plurality of different transmission circuits at each specified input transition time includes: obtaining the simulation results of simulating each basic unit in the same netlist with the clock signal at each specified input transition time as the simulation excitation, where the simulation results include the transmission delays of each basic unit, and the netlist contains basic units with multiple different parameters; based on the transmission delays of each basic unit, determining the second transmission delays of each transmission circuit simulated and constituted by each basic unit.

[0009] In the embodiments of the present application, by obtaining the simulation results of simulating each basic unit in the same netlist with the clock signal at each specified input transition time as the simulation excitation, the second transmission delays of each transmission circuit simulated and constituted by each basic unit can be obtained quickly. Since the simulation results of multiple basic units can be obtained at one time, a variety of possible transmission circuits are covered, ensuring the accuracy of the results.

[0010] In a possible implementation manner of the first aspect, obtaining the simulation results of simulating each basic unit in the same netlist with the clock signal at each specified input transition time as the simulation excitation includes: obtaining the netlist with parasitic parameters; using the clock signal at each specified input transition time as the simulation excitation to simulate each basic unit in the netlist to obtain the simulation results.

[0011] In the embodiments of the present application, a clock signal with each specified input transition time is used as a simulation excitation to simulate a netlist with parasitic parameters, so that simulation results at each specified input transition time can be quickly obtained. At the same time, during the simulation, instead of simulating the netlist containing the complete transmission circuit, only the netlist containing basic units is simulated, so that there is no need to build a complete transmission circuit, greatly shortening the simulation time.

[0012] Combined with a possible implementation manner of the first aspect embodiment, the simulation results include the output transition time of each basic unit. Based on the transmission delay of each basic unit, determining the second transmission delay of each transmission circuit simulated by each basic unit includes: based on the transmission delay of each first basic unit, determining the second transmission delay of each transmission circuit composed of each of the first basic units, where each of the first basic units is a basic unit whose output transition time is the same as the specified input transition time.

[0013] In the embodiments of the present application, first, the first basic units whose output transition time is the same as the specified input transition time are determined based on the simulation results of each basic unit, and then, based on the transmission delay of each first basic unit, the second transmission delay of each transmission circuit composed of each first basic unit is determined. By adding the condition that the input-output transition time (transition time) of each basic unit is the same, the phase jitter difference of each stage of basic units is effectively controlled, and the problem that the deviation cumulative effect will eventually deteriorate the phase jitter of the transmission target due to different transition time deviations of different basic units is reduced.

[0014] Combined with a possible implementation manner of the first aspect embodiment, obtaining the first transmission delay of the target transmission circuit at each specified input transition time includes: gradually reducing the specified input transition time and obtaining the first transmission delay of the target transmission circuit at each reduced specified input transition time until the input transition time is reduced to the default value, or stopping reducing the specified input transition time when the first transmission delay of the target transmission circuit at the reduced specified input transition time is greater than the previous first transmission delay for multiple consecutive times.

[0015] In the embodiments of the present application, by gradually reducing the specified input transition time in this way, the first transmission delay of the target transmission circuit at multiple specified input transition times can be quickly obtained.

[0016] In a possible implementation manner combining the embodiments of the first aspect, obtaining the first transmission delay of the target transmission circuit at each reduced specified input transition time includes: obtaining the second transmission delays of multiple different transmission circuits at each reduced specified input transition time; based on the multiple second transmission delays, obtaining the first transmission delay of the target transmission circuit at each reduced specified input transition time, where the first transmission delay is the minimum second transmission delay among the multiple second transmission delays, and the target transmission circuit is simulated and constituted by the basic unit corresponding to the minimum second transmission delay.

[0017] In the embodiments of the present application, by obtaining the second transmission delays of multiple different transmission circuits at each reduced specified input transition time, the first transmission delay of the target transmission circuit at each reduced specified input transition time can be quickly and accurately obtained.

[0018] In a possible implementation manner combining the embodiments of the first aspect, each basic unit includes two inverters and two transmission lines connecting the two inverters, or includes a buffer and a transmission line connecting the buffer.

[0019] In the embodiments of the present application, with the above basic unit, since each basic unit is driven by another basic unit identical to it, and its load is also another basic unit identical to it, it can be approximately considered that the transition time of the output signal of each basic unit is the same, that is, the transition time of the input signal of each basic unit and the transition time of its output signal are the same. By constraining the input and output transition times of the basic unit to be the same, the phase jitter difference of each stage of the basic unit is effectively controlled.

[0020] In a possible implementation manner combining the embodiments of the first aspect, the length of the transmission line of the transmission circuit is an integer multiple of the transmission line of the corresponding basic unit.

[0021] In the embodiments of the present application, when the length of the transmission line of the transmission circuit is an integer multiple of the transmission line of the corresponding basic unit, the transmission delay of the transmission circuit constituted by the basic unit can be accurately simulated. For example, the transmission delay of the transmission circuit = L / l * Td, where Td is the transmission delay of the basic unit, L is the length of the transmission line of the transmission circuit, and l is the length of the transmission line of the basic unit.

[0022] In a second aspect, an embodiment of the present application further provides a circuit timing optimization device, including: an acquisition module and an analysis module; the acquisition module is configured to obtain, for a plurality of different specified input transition times, a first transmission delay of a target transmission circuit at each specified input transition time, where the target transmission circuit is the transmission circuit with the smallest transmission delay among a plurality of different transmission circuits, the transmission line lengths of each transmission circuit are the same, and different transmission circuits are simulated and constituted by basic units with different parameters; the analysis module is configured to obtain a target transmission delay with the smallest transmission delay among the plurality of first transmission delays, where the transmission delay of the transmission circuit constituted by the target basic unit corresponding to the target transmission delay is the smallest.

[0023] In a third aspect, an embodiment of the present application further provides an electronic device, including: a memory and a processor, the processor is connected to the memory; the memory is configured to store a program; the processor is configured to call the program stored in the memory to execute the method provided in the first aspect embodiment and / or any possible implementation manner in combination with the first aspect embodiment as described above.

[0024] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, it executes the method provided in the first aspect embodiment and / or any possible implementation manner in combination with the first aspect embodiment as described above.

[0025] Other features and advantages of the present application will be described in the subsequent specification. The objectives and other advantages of the present application can be achieved and obtained through the structures specifically pointed out in the written specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. As shown in the drawings, the above-mentioned and other objectives, features, and advantages of the present application will become clearer.

[0027] Figure 1 The flowchart of a circuit timing optimization method provided by an embodiment of the present application is shown.

[0028] Figure 2a The schematic diagram of the principle of a basic unit provided by an embodiment of the present application is shown.

[0029] Figure 2b The schematic diagram of the principle of another basic unit provided by an embodiment of the present application is shown.

[0030] Figure 3 The schematic diagram of the principle of a circuit timing optimization method provided by an embodiment of the present application is shown.

[0031] Figure 4 The schematic diagram of the modules of a circuit timing optimization device provided by an embodiment of the present application is shown.

[0032] Figure 5 The schematic diagram of the structure of an electronic device provided by an embodiment of the present application is shown. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, but cannot be used to limit the protection scope of the present application. Those skilled in the art can understand that, without conflict, the features in the following embodiments and the embodiments can be combined with each other.

[0034] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0035] Furthermore, the term "and / or" in the present application is only a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone.

[0036] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, the technical term "electrically connected" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0037] Considering that the transmission delay of a transmission line is related to the resistance and capacitance of the transmission line and is proportional to the square of the length of the transmission line. Therefore, for long-distance transmission (such as a length exceeding 500μm, and the length for long-distance can be configured), an effective way to reduce the propagation delay is to insert multiple buffers or inverters at intervals on the transmission line, dividing the long transmission distance into multiple short-distance transmissions, so as to transform the propagation delay from a relationship proportional to the square of the line length into a linear relationship and reduce the total propagation delay. However, the inserted buffers or inverters themselves will bring additional delays, and inserting too many buffers or inverters may cause the total propagation delay to increase rather than decrease. In short, inserting buffers or inverters with different numbers and sizes will result in different total propagation delays, and different line widths and line spacings will also result in different total propagation delays.

[0038] As a feasible implementation solution: different numbers and sizes of buffers or inverters and different line widths and line spacings can be used to build a transmission circuit in a long-distance transmission scenario. By experimenting with random combinations of different numbers and sizes of buffers or inverters and different line widths and line spacings, continuous simulation iterations are carried out, and finally a smaller propagation delay is obtained. However, this method has problems such as long simulation time and unsatisfactory results.

[0039] In view of the problems of long simulation time and unsatisfactory results in the above simulation method. This application provides a circuit timing optimization method, device, electronic device and computer-readable storage medium, and presents a new design solution to achieve the optimization of key signal transmission in a long-distance scenario, which has positive significance for improving the quality of chip design, especially for improving the design quality of the clock tree and accelerating timing convergence. The circuit timing optimization method provided in this application no longer uses different numbers and sizes of buffers or inverters and different line widths and line spacings to build a transmission circuit in a long-distance transmission scenario, but simulates the transmission delay when a transmission circuit is composed of basic units with different parameters, and obtains the target basic unit corresponding to the minimum transmission delay based on this. Since there is no need to build a transmission circuit, the simulation duration can be shortened. At the same time, a transmission circuit in this application is only simulated and composed of the same basic unit, so as to ensure that the load of each stage of basic unit is the same, reduce the adverse effects caused by different loads of each stage of basic unit, and thus improve the timing optimization effect.

[0040] For better understanding, the following combines Figure 1 the process shown to illustrate the circuit timing optimization method provided in the embodiments of this application.

[0041] S1: For multiple different specified input transition times, obtain the first transmission delay of the target transmission circuit at each specified input transition time.

[0042] In order to obtain the minimum transmission delay of the transmission circuit in the long-distance transmission scenario as accurately as possible, in the embodiments of the present application, the first transmission delay of the target transmission circuit under each of multiple different specified input transition times will be obtained, avoiding directly taking the first transmission delay of the target transmission circuit under a single specified input transition time as the minimum delay, thereby resulting in inaccurate determination of the transmission delay.

[0043] Among them, the target transmission circuit is the transmission circuit with the minimum transmission delay among multiple different transmission circuits. The transmission line lengths of each transmission circuit are the same, and different transmission circuits are simulated and constituted by basic units with different parameters. For multiple different transmission circuits, the transmission circuit with the minimum transmission delay (i.e., the target transmission circuit) can be obtained under each specified input transition time. Therefore, there will be a target transmission circuit under each specified input transition time.

[0044] Among them, in the design requirements of the clock signal, phase jitter is one of the important indicators. If the phase jitter is too large, it has a huge impact on the stability of the clock signal, and further affects the timing performance of the entire chip. The slew rate is the main reason affecting phase jitter. A lower slew rate usually results in higher additional jitter. The slew rate and the transition time are reciprocal to each other.

[0045] The transition time refers to the change of the signal in the digital circuit, which indicates the process of the signal transitioning from one logical state to another logical state. In the digital circuit, the signal can be different logical levels, such as high level (1) or low level (0). The time required for the signal to transition from one logical level to another logical level is the transition time. It can be the falling-edge transition from high level to low level, or the rising-edge transition from low level to high level. The transition time includes the input transition time and the output transition time. Among them, the input transition time is relative to the input signal, and the output transition time is relative to the output signal. For the analysis and verification of timing reliability, the transition time is very important. During the testing and simulation process, the moment and stability of the input transition need to be considered to ensure that the circuit correctly responds to the input change and generates the expected output.

[0046] Among them, each basic unit includes two inverters and two transmission lines connecting the two inverters, or includes a buffer and a transmission line connecting the buffer. Since each basic unit is driven by another basic unit identical to it, and its load is also another basic unit identical to it, it can be approximately considered that the transition time of the output signal of each basic unit is the same, that is, the transition time of the input signal of each basic unit is the same as the transition time of its output signal. By constraining the input and output transition times of the basic unit to be the same, the phase jitter difference of each stage of the basic unit is effectively controlled.

[0047] The structures of the two basic units provided by this application are as Figure 2a , Figure 2b shown, where Figure 2a shows the case where the basic unit includes two inverters and two transmission lines connecting the two inverters, Figure 2b shows the case where the basic unit includes a buffer and a transmission line connecting the buffer.

[0048] Among them, for the basic unit including two inverters and two transmission lines connecting the two inverters, the lengths of these two transmission lines are the same. Taking Figure 2a as an example, the lengths of the interconnections between the inverters of this basic unit are equal, then the delay of this basic unit is equal to the delay of 2 inverters plus the delay of two transmission lines t = 2 * r * c * (l / 2) 2 / 2 = rcl 2 / 4, where r is the resistance per unit line length and c is the capacitance per unit line length. Conversely, if the lengths of the two transmission lines are different, for example, the length of the first segment is (l / 2 + a) and the length of the second segment is (l / 2 - a), where a is a number greater than 0 and less than l / 2, then the delay of this basic unit is equal to the delay of 2 inverters plus the delay of two transmission lines t = r * c * (l / 2 + a) 2 / 2 + r * c * (l / 2 - a) 2 / 2 = r * c * (l 2 / 4 + a 2 ), obviously this design has a greater delay than the equidistant design. Therefore, in order to obtain the minimum total delay, the lengths of the two transmission lines in the basic unit are selected to be the same.

[0049] In the embodiments of the present application, the parameters of different basic units are different, and the parameters may be parameters affecting the transmission delay, such as the size of an inverter or a buffer, the line width of a transmission line, and the line pitch (line length). In this way, the transmission delay of a transmission circuit composed of different basic units can be simulated, and the lengths of the transmission lines of different transmission circuits are the same, thereby avoiding the influence caused by different lengths of the transmission lines of the transmission circuits.

[0050] Among them, when designing the basic unit, it is necessary to ensure that the length of the transmission line of the transmission circuit is an integer multiple of the transmission line of the corresponding basic unit. Assuming that the length of the transmission line of the transmission circuit is L and the length of the transmission line of the basic unit is l, then it is necessary to ensure that L is an integer multiple of l, L / l = n. If L is not an integer multiple of l, such as L > l*n and L < l*(n + 1), then it is necessary to fine-tune the line length in the basic unit so that the total line length L and the line length of the basic unit satisfy l1 = L / n or l2 = L / (n + 1). Among them, l1 or l2 is the line length of the transmission line in the fine-tuned basic unit.

[0051] In an alternative embodiment, obtaining the first transmission delay of the target transmission circuit at each specified input transition time may be directly obtained from a database or a disk. In this embodiment, the first transmission delays of the target transmission circuit at different specified input transition times can be stored in advance, and when needed later, they can be directly obtained from the storage space.

[0052] In an alternative embodiment, the process of obtaining the first transmission delay of the target transmission circuit at each specified input transition time may be: obtaining the second transmission delays of multiple different transmission circuits at each specified input transition time; based on the multiple second transmission delays, obtaining the first transmission delay of the target transmission circuit at each specified input transition time, where the first transmission delay is the minimum second transmission delay among the multiple second transmission delays, and the target transmission circuit is simulated and composed of the basic unit corresponding to the minimum second transmission delay. In this embodiment, the second transmission delays of multiple different transmission circuits at each specified input transition time will be obtained, and then the minimum second transmission delay will be selected from the multiple second transmission delays. Correspondingly, the transmission circuit corresponding to the minimum second transmission delay is the first transmission delay of the target transmission circuit at the specified input transition time. For each specified input transition time, a target transmission circuit can be obtained by using the same method.

[0053] In an alternative implementation, the way to obtain the first transmission delay of the target transmission circuit at each specified input transition time can be: gradually reduce the specified input transition time, and obtain the first transmission delay of the target transmission circuit at each reduced specified input transition time until the modification stop condition is met, and then stop reducing the specified input transition time. The modification stop condition can be when the input transition time is reduced to the default value (such as the minimum value), or when the first transmission delay of the target transmission circuit at the specified input transition time after reduction is greater than the previous first transmission delay for multiple consecutive times (such as three times). Through this method, the first transmission delay of the target transmission circuit at different specified input transition times can be obtained quickly. When gradually reducing the specified input transition time, it can be a proportional reduction, such as reducing by 1% each time. Of course, it is not limited to proportional reduction, and the proportional reduction is not limited to 1%.

[0054] In this implementation, the process of obtaining the first transmission delay of the target transmission circuit at each reduced specified input transition time can be: obtain the second transmission delays of multiple different transmission circuits at each reduced specified input transition time; based on the multiple second transmission delays, obtain the first transmission delay of the target transmission circuit at each reduced specified input transition time. The above-mentioned specified input transition time is set according to the circuit design requirements, that is, the specified input transition time should be between the minimum input transition time and the maximum input transition time allowed by the circuit design requirements.

[0055] In an alternative implementation, the way to obtain the second transmission delays of multiple different transmission circuits at each specified input transition time can be to directly obtain them from a database or disk. In this implementation, the second transmission delays of multiple different transmission circuits at different specified input transition times can be stored in advance, and when needed later, they can be directly obtained from the storage space.

[0056] In an alternative implementation, the process of obtaining the second transmission delays of multiple different transmission circuits at each specified input transition time can be: obtain the simulation results of simulating each basic cell in the same netlist with the clock signal at each specified input transition time as the simulation excitation, and the simulation results include the transmission delay of each basic cell; based on the transmission delay of each basic cell, determine the second transmission delay of each transmission circuit simulated by each basic cell. In this implementation, according to the simulation results of simulating each basic cell in the same netlist with the clock signal at each specified input transition time as the simulation excitation, the second transmission delay of each transmission circuit simulated by each basic cell is determined.

[0057] In an alternative implementation, obtaining the second transmission delay of multiple different transmission circuits at each specified input transition time may be obtaining the second transmission delay of multiple different transmission circuits at each specified input transition time after reduction. In this implementation, the process of obtaining the first transmission delay of the target transmission circuit at each specified input transition time may be: obtaining the second transmission delay of multiple different transmission circuits at each specified input transition time after reduction; and based on the multiple second transmission delays, obtaining the first transmission delay of the target transmission circuit at each specified input transition time after reduction.

[0058] Among them, the netlist contains basic units with multiple different parameters. To achieve timing optimization for the transmission of critical signals in long-distance scenarios, a netlist containing various possible basic units can be established in advance. For any two basic units, there is at least one parameter difference in terms of the components they consist of, the size of the components, the length and width of the transmission lines, so as to improve the timing optimization effect as accurately as possible.

[0059] Among them, various possible basic units can be established in the place and route tool in advance, and the SPEF (Standard Parasitic Exchange Format) parameters can be extracted to obtain a netlist with parasitic parameters. By adjusting the size of the inverters or buffers in the basic unit and the line length (line pitch) and line width of the transmission line, many basic units can be generated at one time. Among them, the size of the inverters or buffers in the basic unit can be selected according to empirical values, and the value of the line length can be any value between 50um and 100um, but it is necessary to ensure that the transmission line length of the transmission circuit is an integer multiple of the transmission line length of the basic unit.

[0060] Among them, SPEF is a standard file format for describing the capacitance and resistance data in the interconnect power grid on the chip. Its main purpose is to perform timing analysis and interconnect delay estimation of the chip. It can help design engineers evaluate the performance of signal transmission delay, electromagnetic interference, and power consumption at the chip level.

[0061] In an alternative implementation, the process of determining the second transmission delay of each transmission circuit simulated by each basic unit based on the transmission delay of each basic unit may be: the second transmission delay of the transmission circuit is equal to the transmission delay of the basic unit multiplied by the number of basic units, that is, the second transmission delay of the transmission circuit = L / l * Td. Where Td is the transmission delay of the basic unit, L is the transmission line length of the transmission circuit, and l is the length of the transmission line of the basic unit.

[0062] In an alternative embodiment, the simulation result further includes the output transition time of each basic unit. Based on the transmission delay of each basic unit, the process of determining the second transmission delay of each transmission circuit formed by simulating each basic unit may be as follows: Based on the transmission delay of each first basic unit, determine the second transmission delay of each transmission circuit formed by each first basic unit, where each first basic unit is a basic unit whose output transition time is the same as the specified input transition time. In this embodiment, instead of directly determining the second transmission delay of each transmission circuit formed by simulating each basic unit based on the transmission delay of each basic unit, first determine the first basic unit whose output transition time is the same as the specified input transition time based on the simulation result of each basic unit, and then based on the transmission delay of each first basic unit, determine the second transmission delay of each transmission circuit formed by each first basic unit. By adding the condition that the input-output transition time of each basic unit is the same in this application, the phase jitter difference of each stage of basic units is effectively controlled, and the problem that the deviation cumulative effect will eventually deteriorate the phase jitter of the transmission target due to different transition time deviations of different basic units is reduced.

[0063] It can be understood that if the output transition time is the same as the specified input transition time, it is considered that the output transition time is the same as the specified input transition time. As long as the error between the output transition time and the specified input transition time is within the specified range (for example, the error does not exceed 3%), it is considered that the two are the same or consistent.

[0064] In an alternative embodiment, the process of obtaining the simulation results of simulating each basic unit in the same netlist with the clock signal of each specified input transition time as the simulation excitation may be: directly obtain from the database or disk. In this embodiment, the simulation results of simulating each basic unit in the same netlist with the clock signal of each specified input transition time as the simulation excitation can be stored in advance, and when needed later, directly obtain from the storage space.

[0065] In an alternative embodiment, the process of obtaining the simulation results of simulating each basic unit in the same netlist with the clock signal of each specified input transition time as the simulation excitation may be to obtain a netlist with parasitic parameters, use the clock signal of each specified input transition time as the simulation excitation, simulate each basic unit in the netlist, and obtain the simulation results. By using a simulation tool to simulate the netlist with parasitic parameters by applying excitation, the simulation results can be obtained.

[0066] S2: Obtain a target transmission delay which is the minimum among multiple said first transmission delays. Among them, the transmission delay of the transmission circuit formed by the target basic unit corresponding to the target transmission delay is the minimum.

[0067] After obtaining the first transmission delays of the target transmission circuit under multiple different specified input transition times, obtain the target transmission delay with the minimum transmission delay therefrom (which is the minimum transmission delay value among multiple first transmission delays). Among them, the transmission delay of the transmission circuit formed by the target basic unit corresponding to the target transmission delay is the minimum. That is, subsequently when designing a circuit, the transmission circuit can be formed by this target basic unit, and the transmission delay of the transmission circuit at this time is the minimum.

[0068] After determining the target basic unit, subsequently when performing circuit design, the transmission circuit can be built with this target basic unit, thereby ensuring that the transmission delay of the transmission circuit is optimal. The circuit timing optimization solution shown in this application can be applied to various circuit designs with signal transmission requirements. For example, it can be applicable to various SOC (System On Chip) chips. The SOC chip can be various processor, various memory and other SOC chips.

[0069] In an alternative implementation, the schematic diagram of circuit timing optimization can be as Figure 3 shown, where Figure 3 is only one of many embodiments of this application. It mainly includes: obtaining a netlist with parasitic parameters; using a clock signal with a specified input transition time as a simulation excitation to simulate each basic unit in the netlist to obtain simulation results. Among them, the simulation results include the output transition time and the transmission delay of each basic unit; based on the simulation results, determine the first basic unit whose output transition time is consistent with the specified input transition time, based on the transmission delays of each first basic unit, determine the transmission delays of each transmission circuit simulated by each first basic unit, and obtain the first transmission delay of the target transmission circuit with the minimum transmission delay; gradually reduce the specified input transition time of the clock signal and determine whether the modification stop condition is reached. If not, repeat the above steps to obtain the first transmission delay of the target transmission circuit under each reduced specified input transition time until the modification stop condition is reached and stop reducing the input transition time; if so, obtain the target transmission delay with the minimum transmission delay among multiple first transmission delays. Among them, the transmission delay of the transmission circuit formed by the target basic unit corresponding to the target transmission delay is the minimum. Among them, the modification stop condition can be until the input transition time is reduced to the default value, or the first transmission delay of the target transmission circuit under the specified input transition time is greater than the previous first transmission delay for multiple consecutive times.

[0070] The circuit timing optimization solution provided by the embodiments of this application can improve the jitter accumulation of the critical path, reduce the design complexity, and accelerate the design convergence. Under the constraint that the input and output transition times are equal, this method greatly reduces the total workload, shortens the design cycle, and improves the design quality by establishing and simulating basic units.

[0071] The embodiments of this application also provide a circuit timing optimization device 100, as Figure 4 shown. The circuit timing optimization device 100 includes an acquisition module 110 and an analysis module 120.

[0072] The acquisition module 110 is configured to obtain the first transmission delay of the target transmission circuit at each specified input transition time for multiple different specified input transition times, where the target transmission circuit is the transmission circuit with the smallest transmission delay among multiple different transmission circuits, the transmission line lengths of each transmission circuit are the same, and different transmission circuits are simulated and constituted by basic units with different parameters.

[0073] The analysis module 120 is configured to obtain the target transmission delay with the smallest transmission delay among the multiple first transmission delays, where the transmission delay of the transmission circuit constituted by the target basic unit corresponding to the target transmission delay is the smallest.

[0074] Optionally, the acquisition module 110 is configured to obtain the second transmission delays of multiple different transmission circuits at each specified input transition time; based on the multiple second transmission delays, obtain the first transmission delay of the target transmission circuit at each specified input transition time, where the first transmission delay is the smallest second transmission delay among the multiple second transmission delays, and the target transmission circuit is simulated and constituted by the basic unit corresponding to the smallest second transmission delay

[0075] Optionally, the acquisition module 110 is configured to obtain the simulation results of simulating each basic unit in the same netlist with the clock signal at each specified input transition time as the simulation excitation, where the simulation results include the transmission delays of each basic unit, and the netlist includes multiple basic units with different parameters; based on the transmission delays of each basic unit, determine the second transmission delays of each transmission circuit simulated and constituted by each basic unit.

[0076] Optionally, the acquisition module 110 is configured to obtain the netlist with parasitic parameters; use the clock signal at each specified input transition time as the simulation excitation to simulate each basic unit in the netlist to obtain the simulation results.

[0077] The simulation result further includes the output transition time of each basic unit. Optionally, an acquisition module 110 is configured to determine a second transmission delay of each transmission circuit formed by each of the first basic units based on the transmission delay of each first basic unit, where each of the first basic units is a basic unit whose output transition time is consistent with the specified input transition time.

[0078] Optionally, the acquisition module 110 is configured to sequentially reduce the specified input transition time, and acquire a first transmission delay of a target transmission circuit at each reduced specified input transition time until the input transition time is reduced to a default value, or stop reducing the specified input transition time when the first transmission delay of the target transmission circuit at the reduced specified input transition time is greater than the previous first transmission delay for multiple consecutive times.

[0079] Optionally, the acquisition module 110 is configured to acquire second transmission delays of multiple different transmission circuits at each reduced specified input transition time; and acquire a first transmission delay of the target transmission circuit at each reduced specified input transition time based on the multiple second transmission delays, where the first transmission delay is the minimum second transmission delay among the multiple second transmission delays, and the target transmission circuit is simulated and formed by the basic units corresponding to the minimum second transmission delay.

[0080] The circuit timing optimization device 100 provided in the embodiments of the present application has the same implementation principle and the same technical effects as those in the foregoing method embodiments. For a brief description, for parts not mentioned in the device embodiments, reference may be made to the corresponding content in the foregoing method embodiments.

[0081] As Figure 5 shown, Figure 5 FIG. shows a structural block diagram of an electronic device 200 provided in the embodiments of the present application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0082] The elements of the transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements may be electrically connected to each other through one or more communication buses 230 or signal lines. Among them, the transceiver 210 is used for receiving and transmitting data. The memory 220 is used for storing a computer program, such as storing Figure 4The software function module shown in is the circuit timing optimization device 100. The circuit timing optimization device 100 includes at least one software function module that can be stored in the memory 220 in the form of software or firmware or solidified in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the executable module stored in the memory 220, such as the software function module or computer program included in the circuit timing optimization device 100. For example, the processor 240 is used to execute the above-mentioned circuit timing optimization method.

[0083] Among them, the memory 220 can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0084] The processor 240 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. Alternatively, the processor 240 may also be any conventional processor, etc.

[0085] The electronic devices 200 mentioned above include but are not limited to mobile phones, tablets, computers, industrial computers, servers, etc.

[0086] The embodiment of the present application also provides a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium), on which a computer program is stored. When the computer program is run by a computer such as the above-mentioned electronic device 200, the circuit timing optimization method shown above is executed.

[0087] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0088] In several embodiments provided by the present application, it should be understood that the disclosed device and method can also be implemented in other ways. The device embodiments described above are only illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the device, method, and computer program product according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0089] In addition, the various functional modules in the embodiments of the present application can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0090] When the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions for causing a computer device (which may be a personal computer, a laptop, a server, or an electronic device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0091] As described above, the above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A method for optimizing circuit timing, characterized in that, it includes: For multiple different specified input transition times, obtain the first transmission delay of the target transmission circuit under each specified input transition time, where the target transmission circuit is the transmission circuit with the smallest transmission delay among multiple different transmission circuits. The transmission line lengths of each transmission circuit are the same, and different transmission circuits are simulated and constituted by basic units with different parameters. One transmission circuit is only simulated and constituted by the same basic unit, and the length of the transmission line of the transmission circuit is an integer multiple of the transmission line of the corresponding basic unit; Obtain the target transmission delay with the smallest transmission delay among the multiple first transmission delays, where the transmission delay of the transmission circuit constituted by the target basic unit corresponding to the target transmission delay is the smallest.

2. The method according to claim 1, characterized in that, obtaining the first transmission delay of the target transmission circuit under each specified input transition time includes: Obtain the second transmission delays of multiple different transmission circuits under each specified input transition time; Based on the multiple second transmission delays, obtain the first transmission delay of the target transmission circuit under each specified input transition time, where the first transmission delay is the smallest second transmission delay among the multiple second transmission delays, and the target transmission circuit is simulated and constituted by the basic unit corresponding to the smallest second transmission delay.

3. The method according to claim 2, characterized in that, obtaining the second transmission delays of multiple different transmission circuits under each specified input transition time includes: Obtain the simulation results of simulating each basic unit in the same netlist with the clock signal of each specified input transition time as the simulation excitation, where the simulation results include the transmission delay of each basic unit, and the netlist contains multiple basic units with different parameters; Based on the transmission delay of each basic unit, determine the second transmission delay of each transmission circuit simulated and constituted by each basic unit.

4. The method according to claim 3, characterized in that, obtaining the simulation results of simulating each basic unit in the same netlist with the clock signal of each specified input transition time as the simulation excitation includes: Obtain the netlist with parasitic parameters; Use the clock signal of each specified input transition time as the simulation excitation to simulate each basic unit in the netlist to obtain the simulation results.

5. The method according to claim 3, characterized in that, the simulation results also include the output transition time of each basic unit. Based on the transmission delay of each basic unit, determining the second transmission delay of each transmission circuit simulated and constituted by each basic unit includes: Based on the transmission delay of each first basic unit, determine the second transmission delay of each transmission circuit constituted by each of the first basic units, and each of the first basic units is a basic unit whose output transition time is the same as the specified input transition time.

6. The method according to claim 1, characterized in that, obtaining the first transmission delay of the target transmission circuit under each specified input transition time includes: Gradually reduce the specified input transition time, and obtain the first transmission delay of the target transmission circuit at each reduced specified input transition time until the input transition time is reduced to the default value, then stop reducing the specified input transition time, or, if the first transmission delay of the target transmission circuit at the specified input transition time after reduction is greater than the previous first transmission delay for multiple consecutive times, stop reducing the input transition time.

7. The method according to claim 6, wherein, obtaining the first transmission delay of the target transmission circuit at each reduced specified input transition time includes: obtaining the second transmission delays of multiple different transmission circuits at each reduced specified input transition time; based on the multiple second transmission delays, obtaining the first transmission delay of the target transmission circuit at each reduced specified input transition time, where the first transmission delay is the minimum second transmission delay among the multiple second transmission delays, and the target transmission circuit is simulated and constituted by the basic unit corresponding to the minimum second transmission delay.

8. The method according to any one of claims 1-7, wherein, each basic unit includes two inverters and two transmission lines connecting the two inverters, or includes a buffer and one transmission line connecting the buffer.

9. A circuit timing optimization device, wherein, it includes: an acquisition module, configured to obtain the first transmission delay of the target transmission circuit at each of multiple different specified input transition times, where the target transmission circuit is the transmission circuit with the minimum transmission delay among the multiple different transmission circuits, the transmission line lengths of each transmission circuit are the same, and different transmission circuits are simulated and constituted by basic units with different parameters, one transmission circuit is only simulated and constituted by the same basic unit, and the length of the transmission line of the transmission circuit is an integer multiple of the transmission line of the corresponding basic unit; an analysis module, configured to obtain the target transmission delay with the minimum transmission delay among the multiple first transmission delays, where the transmission delay of the transmission circuit constituted by the target basic unit corresponding to the target transmission delay is the minimum.

10. An electronic device, wherein, it includes: a memory and a processor, the processor is connected to the memory; the memory is configured to store a program; the processor is configured to call the program stored in the memory to execute the method according to any one of claims 1-8.

11. A computer-readable storage medium, wherein, a computer program is stored thereon, and when the computer program is run by a processor, it executes the method according to any one of claims 1-8.

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