Display panel and display device

Abstract

Provided is a display panel, including a driving backplane (1) and a pixel defining layer (3). A partition groove is provided between two adjacent pixel openings (31) of the pixel defining layer (3). The partition groove includes a first groove segment and a second groove segment that are successively away from the driving backplane (1), and the orthographic projection of the second groove segment on the driving backplane (1) is located within the orthographic projection of the first groove segment on the driving backplane (1). The partition groove disconnects the common layer between different sub-pixels, and the current of a light-emitting material layer (422) of a certain color will not flow to the light-emitting material layer (422) of another color, thereby reducing the mutual crosstalk between the light-emitting material layers (422) of different colors caused by lateral leakage, avoiding false light emission, and enabling the display of the display panel to always remain normal. Also provided is a manufacturing method of the display panel and a display device including the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel, a manufacturing method thereof, and a display device. Background Art

[0002] Crosstalk is one of the important indicators for evaluating the quality of a display panel. It mainly refers to the situation where the display state of a certain pixel in a display device is affected by the changes in the states of other pixels or signal electrodes.

[0003] When an existing organic light-emitting display panel displays a monochromatic picture, the pixels of other adjacent colors will slightly emit light, thereby causing crosstalk between the light-emitting material layers of different colors and affecting the light-emitting quality of the display panel.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel, a manufacturing method thereof, and a display device.

[0006] According to one aspect of the present disclosure, a display panel is provided, including a driving backplane, a planarization layer group, a plurality of pixel electrodes, a pixel defining layer, a light-emitting layer group, and a common electrode. The planarization layer group is disposed on one side of the driving backplane; the plurality of pixel electrodes are spaced apart and disposed on the side of the planarization layer group away from the driving backplane; the pixel defining layer is disposed on the side of the planarization layer group away from the driving backplane. The pixel defining layer is provided with pixel openings exposing the pixel electrodes, and a partition groove is provided between two adjacent pixel openings. The partition groove includes a first groove segment and a second groove segment sequentially away from the driving backplane, and the orthographic projection of the second groove segment on the driving backplane is located within the orthographic projection of the first groove segment on the driving backplane; the light-emitting layer group is disposed on the side of the plurality of pixel electrodes and the pixel defining layer away from the driving backplane, and the light-emitting layer group includes a common layer, and the common layer is disconnected within the partition groove; the common electrode is disposed on the side of the light-emitting layer group away from the driving backplane.

[0007] In an embodiment of the present disclosure, the second groove segment is a first opening provided between two adjacent pixel openings, the planarization layer group includes a first planarization layer, the first planarization layer is disposed between the driving backplane and the pixel defining layer, and the first groove segment is a groove provided on the first planarization layer.

[0008] In an embodiment of the present disclosure, the planarization layer group further includes a second planarization layer disposed between the first planarization layer and the driving backplane.

[0009] In one embodiment of the present disclosure, the second groove segment includes a first opening disposed between two adjacent pixel openings. The planarization layer group includes a first planarization layer and a second planarization layer. The first planarization layer is disposed between the driving backplane and the pixel defining layer. The second groove segment further includes a second opening disposed on the first planarization layer. The second planarization layer is disposed between the first planarization layer and the driving backplane. The first groove segment is a groove disposed on the second planarization layer.

[0010] In one embodiment of the present disclosure, the orthographic projection of the first opening on the driving backplane coincides with the orthographic projection of the second opening on the driving backplane.

[0011] In one embodiment of the present disclosure, the orthographic projection of the first opening on the substrate is located within the orthographic projection of the second opening on the substrate.

[0012] In one embodiment of the present disclosure, a first opening is disposed between two adjacent pixel openings. The planarization layer group includes a first planarization layer, a second planarization layer, and a first metal layer. The first planarization layer is disposed between the driving backplane and the pixel defining layer. A second opening is disposed on the first planarization layer, and the second opening is in communication with the first opening. The second planarization layer is disposed between the first planarization layer and the driving backplane. A groove is disposed on the second planarization layer, and the first groove segment is the groove. The first metal layer is disposed between the first planarization layer and the second planarization layer and is located between two adjacent pixel electrodes. A third opening is disposed on the first metal layer, and the second groove segment is the third opening, and the third opening is in communication with the second opening.

[0013] In one embodiment of the present disclosure, the orthographic projection of the first opening on the driving backplane, the orthographic projection of the second opening on the driving backplane, and the orthographic projection of the groove on the driving backplane coincide with each other.

[0014] In one embodiment of the present disclosure, the orthographic projection of the first opening on the driving backplane is located within the orthographic projection of the second opening on the driving backplane.

[0015] In one embodiment of the present disclosure, the orthographic projection of the second opening on the driving backplane is located within the orthographic projection of the groove on the driving backplane.

[0016] In one embodiment of the present disclosure, a first opening is disposed between two adjacent pixel openings. The second groove segment is the first opening. The display panel further includes a barrier layer. The barrier layer is disposed between the driving backplane and the pixel defining layer and is located between two adjacent pixel electrodes. A fourth opening is disposed on the barrier layer, and the first groove segment is the fourth opening.

[0017] In one embodiment of the present disclosure, the material of the barrier layer is the same as the material of the pixel electrode.

[0018] In one embodiment of the present disclosure, the material of the barrier layer is an inorganic material.

[0019] In one embodiment of the present disclosure, the driving backplane includes a substrate and a plurality of thin film transistors disposed on one side of the substrate. The display panel further includes a plurality of third electrodes disposed between the first planarization layer and the second planarization layer. The pixel electrode is electrically connected to the third electrode through a via hole in the second planarization layer, and the third electrode is electrically connected to the first electrode or the second electrode of the thin film transistor through a via hole in the first planarization layer.

[0020] In one embodiment of the present disclosure, the light-emitting layer group further includes a light-emitting material layer. The common layer includes a first common layer group and a second common layer group. The first common layer group and the second common layer group are respectively disposed on opposite sides of the light-emitting material layer. The first common layer includes at least a hole injection layer and a hole transport layer, and the second common layer includes at least an electron transport layer and an electron injection layer.

[0021] In one embodiment of the present disclosure, the light-emitting layer group further includes two light-emitting material layers. The common layer includes a third common layer, a first common layer group, and a second common layer group. The third common layer is disposed between two adjacent light-emitting material layers. The first common layer group and the second common layer group are respectively disposed on one side of the light-emitting material layer away from the third common layer. The third common layer is a charge generation layer. The first common layer includes at least a hole injection layer and a hole transport layer, and the second common layer includes at least an electron transport layer and an electron injection layer.

[0022] According to another aspect of the present disclosure, there is provided a method for manufacturing a display panel, including:

[0023] Providing a driving backplane;

[0024] Forming a planarization layer group on one side of the driving backplane;

[0025] Forming a plurality of pixel electrodes on one side of the planarization layer group away from the driving backplane;

[0026] Forming a pixel defining layer with pixel openings on the planarization layer group, and the pixel openings expose the pixel electrodes;

[0027] Forming a partition groove between two adjacent pixel openings. The partition groove includes a first groove segment and a second groove segment that are successively away from the driving backplane, and the orthographic projection of the second groove segment on the driving backplane is located within the orthographic projection of the first groove segment on the driving backplane;

[0028] Forming a light-emitting layer group on one side of the pixel electrode away from the driving backplane. The light-emitting layer group includes a common layer, and the common layer is disconnected within the partition groove;

[0029] Forming a common electrode on one side of the light-emitting layer group away from the driving backplane.

[0030] In one embodiment of the present disclosure, the planarization layer group includes a first planarization layer and a second planarization layer stacked in sequence along the direction away from the driving backplane. A partition groove is formed between two adjacent pixel openings, including:

[0031] Etch the pixel definition layer to form a first opening, and the first opening is a part of the second groove segment;

[0032] Etch the first planarization layer to form a second opening, and the second opening is another part of the second groove segment;

[0033] Etch the second planarization layer to form a groove, and the groove is the first groove segment;

[0034] Wherein, the lateral etching rate of the second planarization layer is greater than the lateral etching rate of the first planarization layer and the lateral etching rate of the pixel definition layer, and the lateral etching rate of the first planarization layer is greater than or equal to the lateral etching rate of the pixel definition layer.

[0035] According to another aspect of the present disclosure, a display device is provided, including the display panel described in any one of the above.

[0036] The display panel of the present disclosure includes a driving backplane and a pixel definition layer. A partition groove is provided between two adjacent pixel openings of the pixel definition layer. The partition groove includes a first groove segment and a second groove segment that are sequentially away from the driving backplane. The orthographic projection of the second groove segment on the driving backplane is located within the orthographic projection of the first groove segment on the driving backplane. When forming the common layer, the partition groove disconnects the common layer between different sub-pixels, and the current of a certain color light-emitting material layer will not flow to another color light-emitting material layer, thereby reducing the mutual crosstalk between different color light-emitting material layers caused by lateral leakage, avoiding false light emission, and keeping the display of the display panel normal all the time.

[0037] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 It is a schematic structural diagram of the light-emitting layer group of the display panel with a single-layer structure according to the embodiment of the present disclosure.

[0040] Figure 2 It is a schematic structural diagram of the light-emitting layer group of the display panel with a stacked structure according to the embodiment of the present disclosure.

[0041] Figure 3 Schematic diagram of a display panel structure in which the first groove section related to the embodiment of the present disclosure is disposed in the first planarization layer.

[0042] Figure 4 Schematic diagram of another display panel structure in which the first groove section related to the embodiment of the present disclosure is disposed in the first planarization layer.

[0043] Figure 5 Schematic diagram of a display panel structure in which the second groove section related to the embodiment of the present disclosure includes a first opening and a second opening.

[0044] Figure 6 Schematic diagram of another display panel structure in which the second groove section related to the embodiment of the present disclosure includes a first opening and a second opening.

[0045] Figure 7 Schematic diagram of a display panel structure in which the second groove section related to the embodiment of the present disclosure is a third opening.

[0046] Figure 8 Schematic diagram of another display panel structure in which the second groove section related to the embodiment of the present disclosure is a third opening.

[0047] Figure 9 Schematic diagram of yet another display panel structure in which the second groove section related to the embodiment of the present disclosure is a third opening.

[0048] Figure 10 Schematic diagram of still another display panel structure in which the second groove section related to the embodiment of the present disclosure is a third opening.

[0049] Figure 11 Schematic diagram of a display panel structure in which the first groove section related to the embodiment of the present disclosure is a fourth opening.

[0050] Figure 12 Schematic diagram of another display panel structure in which the first groove section related to the embodiment of the present disclosure is a fourth opening.

[0051] Figure 13 Flow chart of the manufacturing method of the display panel related to the embodiment of the present disclosure.

[0052] Figures 14 - 16 Schematic diagram of the manufacturing process of the partition groove of another display panel in which the second groove section related to the embodiment of the present disclosure includes a first opening and a second opening.

[0053] Figures 17 - 19 Schematic diagram of the manufacturing process of the partition groove of a display panel in which the first groove section related to the embodiment of the present disclosure is a fourth opening.

[0054] Figures 20 - 22 Schematic diagram of the manufacturing process of the partition groove of another display panel where the first groove section related to the embodiment of the present disclosure is the fourth opening.

[0055] Description of reference numerals:

[0056] 1 - Driving backplane, 11 - Substrate, 12 - Buffer layer, 13 - Thin film transistor, 131 - Active layer, 132 - Gate insulating layer, 133 - Gate electrode, 134 - Interlayer insulating layer, 135 - Interlayer dielectric layer, 136 - First electrode, 137 - Second electrode, 138 - Protective layer, 139 - Third electrode, 2 - Planarization layer group, 21 - First planarization layer, 22 - Second planarization layer, 23 - Second opening, 24 - Groove, 3 - Pixel defining layer, 31 - Pixel opening, 32 - First opening, 4 - Pixel layer, 41 - Pixel electrode, 42 - Light emitting layer group, 421 - Sub - light emitting layer group, 422 - Light emitting material layer, 423 - First common layer group, 4231 - Hole injection layer, 4232 - Hole transport layer, 4233 - Electron blocking layer, 424 - Second common layer group, 4241 - Electron injection layer, 4242 - Electron transport layer, 4243 - Hole blocking layer, 425 - Third common layer, 43 - Common electrode, 5 - Encapsulation layer, 51 - First inorganic encapsulation layer, 52 - Organic encapsulation layer, 53 - Second inorganic encapsulation layer, 6 - First metal layer, 61 - Third opening, 7 - Barrier layer, 71 - Fourth opening, 8 - Photoresist layer, 81 - Etching area to be etched. Detailed implementation manners

[0057] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Identical reference numerals in the figures denote identical or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0058] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0059] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0060] According to the different structures of the light-emitting layer group, the display panel can be divided into an OLED display panel with a single-layer structure and an OLED display panel with a stacked structure. Compared with the OLED display panel with a single-layer structure, the OLED display panel with a stacked structure has a longer lifespan and lower power consumption. Therefore, the OLED panel with a stacked structure has also been gradually widely used.

[0061] Currently, as Figure 1 shown, the light-emitting layer group 42 of the OLED display panel with a single-layer structure may include a layer of light-emitting material layer 422 (EML), a first common layer group 423 and a second common layer group. The first common layer group 423 and the second common layer group are respectively disposed on opposite sides of the light-emitting material layer. The first common layer at least includes a hole injection layer 4231 (HIL) and a hole transport layer 4232 (HTL), and may also include an electron blocking layer (EBL). The second common layer at least includes an electron transport layer 4242 (ETL) and an electron injection layer 4241 (EIL), and may also include a hole blocking layer 4243 (HBL). The hole injection layer 4231 is disposed on the side of the pixel electrode 41 away from the driving backplane. The hole transport layer 4232 is disposed on the side of the hole injection layer 4231 away from the driving backplane. The electron blocking layer 4233 is disposed on the side of the hole transport layer 4232 away from the driving backplane. The light-emitting material layer 422 is disposed on the side of the electron blocking layer 4233 away from the driving backplane. The light-emitting material layer 422 may include a red light-emitting material unit, a green light-emitting material unit and a blue light-emitting material unit. The hole blocking layer 4243 is disposed on the side of the light-emitting material layer 422 away from the driving backplane. The electron transport layer 4242 is disposed on the side of the hole blocking layer 4243 away from the driving backplane. The electron injection layer 4241 is disposed on the side of the electron transport layer 4242 away from the driving backplane.

[0062] As Figure 2As shown, the OLED display panel with a stacked structure includes two sub-emitting layer groups. One of the sub-emitting layer groups includes a layer of light-emitting material layer 422 and a first common layer group 423. The first common layer group 423 is disposed on the side of the layer of light-emitting material away from the third common layer 425. This sub-emitting layer group may also include a layer of hole-blocking layer (HBL), which is disposed on the other side of the light-emitting material layer 422. The other sub-emitting layer group includes another layer of light-emitting material layer 422 and a second common layer group 424. The second common layer group 424 is disposed on the side of the other layer of light-emitting material 422 away from the third common layer 425. A third common layer 425 is provided between the two sub-emitting layer groups. The third common layer 425 is a charge generation layer (CGL). The OLED display panel with a stacked structure connects two independent sub-emitting layer groups through the third common layer 425. However, the third common layer 425 has strong conductivity and is prone to lateral leakage, resulting in crosstalk between different sub-pixels of different sub-emitting layer groups.

[0063] The third common layer 425 generates electrons and holes and effectively transports the electrons and holes to the adjacent sub-emitting layer groups. Since the current preparation of the third common layer 425 is carried out by full-surface evaporation using the same mask plate as the hole injection layer 4231 (HTL) and the electron injection layer 4241 (ETL), and the third common layer 425 has strong conductivity, when the red light-emitting layer of a sub-emitting layer group emits light normally, a part of the current will flow to the green light-emitting layer, causing the green light-emitting layer to emit light erroneously and resulting in abnormal display visually.

[0064] Based on this, the embodiments of the present disclosure provide a display panel. As Figures 3 to 11 shown, the display panel includes a driving backplane 1, a planarization layer group 2, a plurality of pixel electrodes 41, a pixel defining layer 3, a light-emitting layer group 42, and a common electrode 43. The planarization layer group 2 is disposed on one side of the driving backplane 1; the plurality of pixel electrodes 41 are spaced apart and disposed on the side of the planarization layer group 2 away from the driving backplane 1; the pixel defining layer 3 is disposed on the side of the planarization layer group 2 away from the driving backplane 1. The pixel defining layer 3 is provided with pixel openings 31 exposing the pixel electrodes 41. A partition groove is provided between two adjacent pixel openings 31. The partition groove includes a first groove segment and a second groove segment successively away from the driving backplane 1. The orthographic projection of the second groove segment on the driving backplane 1 is located within the orthographic projection of the first groove segment on the driving backplane 1; the light-emitting layer group 42 is disposed on the side of the plurality of pixel electrodes 41 and the pixel defining layer 3 away from the driving backplane 1. The light-emitting layer group 42 includes a common layer, and the common layer is disconnected within the partition groove; the common electrode 43 is disposed on the side of the light-emitting layer group 42 away from the driving backplane 1.

[0065] A partition groove is provided between two adjacent pixel openings 31 of the pixel definition layer 3. The partition groove includes a first groove segment and a second groove segment that successively move away from the driving backplane 1. The orthographic projection of the second groove segment on the driving backplane 1 is located within the orthographic projection of the first groove segment on the driving backplane 1. When forming the common layer, the partition groove disconnects the common layer between different sub-pixels, and the current of a certain color light-emitting material layer will not flow to another color light-emitting material layer, thereby reducing the mutual crosstalk between different color light-emitting material layers caused by lateral leakage, avoiding false light emission, and keeping the display of the display panel normal all the time.

[0066] It should be noted that the planarization layer group may include one planarization layer, or may include two or more planarization layers. The orthographic projection of the second groove segment on the driving backplane 1 being located within the orthographic projection of the first groove segment on the driving backplane 1 means that the area of the orthographic projection of the second groove segment on the driving backplane 1 is smaller than the area of the orthographic projection of the first groove segment on the driving backplane 1, excluding the case where the area of the orthographic projection of the second groove segment on the driving backplane 1 is equal to the area of the orthographic projection of the first groove segment on the driving backplane 1, that is, the case where the orthographic projection of the second groove segment on the driving backplane 1 overlaps with the orthographic projection of the first groove segment on the driving backplane 1.

[0067] It should be noted that the common electrode may be broken or unbroken in the partition groove. Usually, the common electrode breaks in the partition groove, but in the actual forming process, the common electrode may also be continuously distributed in the partition groove.

[0068] See Figures 3 to 11 , the driving backplane 1 may include a substrate 11 and a driving circuit layer, and the driving backplane 1 may further include a buffer layer 12, and the buffer layer 12 is provided between the substrate 11 and the driving circuit layer.

[0069] The substrate 11 can be a substrate of inorganic material or a substrate of organic material. For example, in an embodiment of the present disclosure, the material of the substrate 11 can be glass materials such as soda-lime glass, quartz glass, sapphire glass, etc., or can be metal materials such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate 11 can be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Poly carbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN) or a combination thereof.

[0070] In another embodiment of the present disclosure, the substrate 11 can also be a flexible substrate. For example, the material of the substrate 11 can be polyimide (PI). The substrate 11 can also be a composite of multilayer materials. For example, in an embodiment of the present disclosure, the substrate 11 can include a BottomFilm layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer that are sequentially stacked.

[0071] In the present disclosure, a driving circuit layer is provided with a driving circuit for driving sub-pixels. In the driving circuit layer, any one driving circuit can include a transistor and a storage capacitor. Further, the transistor can be a thin film transistor 13, and the thin film transistor 13 can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a double-gate thin film transistor; taking the top-gate thin film transistor as an example, the thin film transistor 13 can include an active layer 131, a gate insulating layer 132, a gate electrode 133, a first electrode 136, and a second electrode 137, wherein:

[0072] The active layer 131 is disposed on one side of the substrate 11, and the material of the active layer 131 can be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, or other types of semiconductor materials; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor. The active layer 131 can include a channel region and two doped regions of different doping types located on both sides of the channel region.

[0073] The gate insulating layer 132 can cover the active layer 131 and the substrate 11, and the material of the gate insulating layer 132 is an insulating material such as silicon oxide.

[0074] The gate 133 is disposed on the side of the gate insulating layer 132 away from the substrate 11 and is opposite to the active layer 131, that is, the projection of the gate 133 on the substrate 11 is within the projection range of the active layer 131 on the substrate 11. For example, the projection of the gate 133 on the substrate 11 coincides with the projection of the channel region of the active layer 131 on the substrate 11.

[0075] The thin film transistor 13 further includes an interlayer insulating layer 134 that covers the gate 133 and the gate insulating layer 132. The thin film transistor 13 further includes an interlayer dielectric layer 135 that is disposed on the side of the interlayer insulating layer 134 away from the substrate 11. Both the interlayer insulating layer 134 and the interlayer dielectric layer 135 are insulating materials, but the materials of the interlayer insulating layer 134 and the interlayer dielectric layer 135 can be different.

[0076] The first electrode 136 and the second electrode 137 are disposed on the surface of the interlayer dielectric layer 135 away from the substrate 11. The first electrode 136 can be a first source electrode, and the second electrode 137 can be a drain electrode. The first electrode 136 and the second electrode 137 are connected to the active layer 131. For example, the first electrode 136 and the second electrode 137 are respectively connected to two doped regions of the corresponding active layer 131 through vias.

[0077] A protective layer 138 is disposed on the side of the first electrode 136 away from the substrate 11, and the protective layer 138 covers the first electrode 136 and the second electrode 137. A planarization layer group 2 is disposed on the side of the first electrode 136 and the second electrode 137 away from the substrate 11. The planarization layer group 2 is disposed on the side of the protective layer 138 away from the substrate 11, and the planarization layer group 2 covers the protective layer 138, and the surface of the planarization layer group 2 away from the substrate 11 is a plane.

[0078] A pixel defining layer 3 and a pixel layer 4 can be disposed on the side of the planarization layer group 2 away from the substrate 11. The pixel defining layer 3 has a plurality of openings, and the pixel layer 4 includes a plurality of sub-pixels, and the plurality of sub-pixels are respectively disposed in the plurality of openings. The plurality of sub-pixels are arranged in an array on the side of the driving backplane 1 away from the substrate 11, and the specific sub-pixels can be located on the side of the planarization layer group 2 away from the substrate 11. It should be noted that the sub-pixels can include red sub-pixels, green sub-pixels, and blue sub-pixels according to different emission colors.

[0079] The pixel layer 4 may include a plurality of pixel electrodes 41, a light-emitting layer group 42, and a common electrode 43. The pixel electrode 41 is located on the surface of the driving backplane 1 away from the substrate 11. The light-emitting layer group 42 is disposed on the surface of the pixel electrode 41 away from the substrate 11. The common electrode 43 is disposed on the surface of the light-emitting layer group 42 away from the substrate 11. The common electrode 43 may be broken or unbroken in the partition groove.

[0080] The pixel electrode 41 is connected to the first electrode 136. When the thin-film transistor 13 only includes the first electrode 136, the pixel electrode 41 is connected to the first electrode 136, and the pixel defining layer 3 is provided to cover the pixel electrode 41 and the planarization layer group 2.

[0081] The common electrode 43 may serve as a cathode, and the pixel electrode 41 may serve as an anode. The pixel electrode 41 is connected to the positive electrode of the power supply, and the common electrode 43 is connected to the negative electrode of the power supply. A signal can be applied through the pixel electrode 41 and the common electrode 43 to drive the light-emitting layer group 42 to emit light for displaying an image. The specific light-emitting principle will not be elaborated here. The light-emitting layer group 42 may include an electro-luminescent organic material. For example, the light-emitting layer group 42 may include a auxiliary layer and a light-emitting layer stacked in sequence on the pixel electrode 41. Generally, a pattern area is provided on the mask plate, and the auxiliary layer of different color sub-pixels and the light-emitting layer of different color sub-pixels are formed by processes such as evaporation.

[0082] In addition, the display panel of the present disclosure may further include a packaging layer 5. The packaging layer 5 is disposed on the side of the pixel layer 4 away from the substrate 11 to wrap the pixel layer 4 and prevent water and oxygen from eroding. The packaging layer 5 may be a single-layer or multi-layer structure, and the material of the packaging layer 5 may include organic or inorganic materials, which are not specifically limited herein.

[0083] In this embodiment, the packaging layer 5 may include a first inorganic packaging layer 51, an organic packaging layer 52, and a second inorganic packaging layer 53. The first inorganic packaging layer 51 is disposed on the side of the pixel layer 4 away from the substrate 11. The organic packaging layer 52 is disposed on the side of the first inorganic packaging layer 51 away from the substrate 11. The second inorganic packaging layer 53 is disposed on the side of the organic packaging layer 52 away from the substrate 11.

[0084] Among them, the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 can be made of inorganic materials such as silicon nitride (SiN), but are not limited thereto. The first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 can be prepared by PECVD (Plasma Enhanced Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). The organic encapsulation layer 52 can be made of curable (this curing includes photocuring or thermal curing) organic materials. Specifically, the organic encapsulation layer 52 can be made of at least one of epoxy resin-based organic materials, acrylate-based organic materials, and silicone-based materials. And the aforementioned organic encapsulation layer 52 can be prepared by an IJP (Ink Jet Printing) process or screen printing.

[0085] As Figure 3 shown, the planarization layer group 2 includes a first planarization layer 21. The first planarization layer 21 is disposed on the side of the protective layer 138 away from the substrate 11. The first planarization layer 21 covers the protective layer 138, and the surface of the first planarization layer 21 away from the substrate 11 is a plane. A plurality of pixel electrodes 41 are spaced apart and disposed on the side of the planarization layer group 2 away from the driving backplane 1. A groove 24 is provided in the portion of the first planarization layer 21 between two adjacent pixel electrodes 41. The first groove segment is the groove 24 provided on the first planarization layer 21. The pixel defining layer 3 is provided with a first opening 32 in the portion between two adjacent pixel openings 31. The second groove segment is the first opening 32.

[0086] Figure 4 The shown display panel and Figure 3 the shown display panel are different in that the planarization layer group 2 includes a second planarization layer 22. The second planarization layer 22 is disposed between the first planarization layer 21 and the driving backplane 1. The display panel may further include a third electrode 139. The third electrode 139 is disposed between the first planarization layer 21 and the second planarization layer 22. The third electrode 139 can be a second source electrode. Via holes are provided on both the first planarization layer 21 and the second planarization layer 22. The pixel electrode 41 is electrically connected to the third electrode 139 through the via hole provided on the first planarization layer 21. The third electrode 139 is connected to the first electrode 136 through the via hole provided on the second planarization layer 22.

[0087] Figure 5 The shown display panel and Figure 4The difference of the shown display panel is that, in addition to including a first opening 32 disposed between two adjacent pixel openings 31, a second opening 23 is provided on the first planarization layer 21, and the second groove section further includes the second opening 23. The second planarization layer 22 is disposed between the first planarization layer 21 and the driving backplane 1, and a groove 24 is provided on the second planarization layer 22, and the first groove section is the groove 24. It should be noted that the orthographic projection of the first opening 32 on the driving backplane 1 coincides with the orthographic projection of the second opening 23 on the driving backplane 1.

[0088] Figure 6 The difference between the shown display panel and Figure 5 the shown display panel is that the orthographic projection of the first opening 32 on the substrate 11 is located within the orthographic projection of the second opening 23 on the substrate 11, specifically referring to that the area of the orthographic projection of the second groove section on the driving backplane 1 is smaller than the area of the orthographic projection of the first groove section on the driving backplane 1, excluding the case where the area of the orthographic projection of the second groove section on the driving backplane 1 is equal to the area of the orthographic projection of the first groove section on the driving backplane 1, that is, the case where the orthographic projection of the second groove section on the driving backplane 1 overlaps with the orthographic projection of the first groove section on the driving backplane 1.

[0089] It can be understood that the orthographic projection of the first opening 32 on the driving backplane 1 is smaller than the orthographic projection of the second opening 23 on the driving backplane 1, and the orthographic projection of the second opening 23 on the driving backplane 1 is smaller than the orthographic projection of the groove 24 on the driving backplane 1. Therefore, the partition groove includes two stepped sections. When forming the third common layer, the third common layer can be disconnected within the first stepped section. Even if it is not disconnected within the first stepped section, it can also be disconnected within the second stepped section, which can better prevent the current of the light-emitting material layer of a certain color in one sub-light-emitting layer group 421 from flowing to the light-emitting material layer of another color in another sub-light-emitting layer group 421.

[0090] Figures 7 to 9 The difference between the shown display panel and Figure 5 the display panel is that this display panel further includes a first metal layer 6. The first metal layer 6 is disposed between the first planarization layer 21 and the second planarization layer 22 and is located between two adjacent pixel electrodes 41. A third opening 61 is provided on the first metal layer 6, the second groove section is the third opening 61, and the first groove section is the groove 24 provided on the second planarization layer 22. The first opening 32 on the pixel defining layer 3 and the second opening 23 on the first planarization layer 21 are communicated with the third opening 61, so that when forming the third common layer, the third common layer can enter the partition groove and be disconnected within the partition groove. It should be noted that the first metal layer 6 can be set on the same layer and made of the same material as the third electrode 139.

[0091] Such as Figure 7As shown, the orthographic projection of the first opening 32 on the driving backplane 1, the orthographic projection of the second opening 23 on the driving backplane 1, and the orthographic projection of the groove 24 on the driving backplane 1 coincide with each other. It can also be as Figure 8 shown, the orthographic projection of the first opening 32 on the driving backplane 1 is located within the orthographic projection of the second opening 23 on the driving backplane 1, and the orthographic projection of the second opening 23 on the driving backplane 1 coincides with the orthographic projection of the groove 24 on the driving backplane 1. It can also be as Figure 9 shown, the orthographic projection of the first opening 32 on the driving backplane 1 is located within the orthographic projection of the second opening 23 on the driving backplane 1, and the orthographic projection of the second opening 23 on the driving backplane 1 is located within the orthographic projection of the groove 24 on the driving backplane 1.

[0092] Figures 8 to 10 In the display panel shown, the first opening 32 and the second opening 23 can form a stepped hole. When forming the third common layer, the third common layer can be disconnected within the stepped hole formed by the first opening 32 and the second opening 23. Even if it is not disconnected within the stepped hole, it can also be disconnected within the partition groove formed by the third opening 61 and the groove 24, which can further reduce or eliminate the situation where the current of the light-emitting material layer of a certain color in one sub-light-emitting layer group 421 flows to the light-emitting material layer of another color in another sub-light-emitting layer group 421. Figure 10 Different from Figure 9 is that Figure 9 the common electrode in Figure 10 is continuously distributed within the partition groove, and

[0093] As Figure 11 and Figure 12 shown, the display panel may further include a barrier layer 7. The barrier layer 7 is disposed at intervals between adjacent two pixel electrodes 41. The barrier layer 7 and the pixel electrodes 41 are on the same side of the planarization layer group 2. A fourth opening 71 is provided on the barrier layer 7, and the first groove segment is the fourth opening 71. The pixel defining layer 3 is disposed on the side of the planarization layer group 2 away from the driving backplane 1. The pixel defining layer 3 is provided with a pixel opening 31 exposing the pixel electrode 41. A first opening 32 is provided between adjacent two pixel openings 31, and the second groove segment is the first opening 32.

[0094] It should be noted that the material of the barrier layer 7 can be the same as that of the pixel electrode 41. The main component of the specific material of the barrier layer 7 can be ITO and Ag. The material of the barrier layer 7 can also be the same as that of the protective layer 138, and the specific material of the barrier layer 7 can be an inorganic material.

[0095] The embodiments of the present disclosure provide a method for manufacturing a display panel. As Figure 13 shown, the method may include:

[0096] Step S10: Provide a driving backplane;

[0097] Step S20: Form a planarization layer group on one side of the driving backplane;

[0098] Step S30: Form a plurality of pixel electrodes on the planarization layer group;

[0099] Step S40: Form a pixel defining layer with pixel openings on the planarization layer group, and the pixel openings expose the pixel electrodes;

[0100] Step S50: Form a partition groove between two adjacent pixel openings. The partition groove includes a first groove segment and a second groove segment that are successively away from the driving backplane, and the orthographic projection of the second groove segment on the driving backplane is located within the orthographic projection of the first groove segment on the driving backplane;

[0101] Step S60: Form a light-emitting layer group on the side of the pixel electrode away from the driving backplane. The light-emitting layer group includes a common layer, and the common layer is disconnected within the partition groove;

[0102] Step S70: Form a common electrode on the side of the light-emitting layer group away from the driving backplane.

[0103] This method may further include: forming a packaging layer on the side of the common electrode away from the driving backplane.

[0104] The following details Step S50.

[0105] For Figure 3 a specific description of the shown display panel is given.

[0106] Step S10 may specifically include: fabricating a pixel driving circuit and corresponding film layers on a substrate 11. This process flow is the process flow of the existing driving backplane 1 and will not be elaborated here.

[0107] Step S20 may specifically include: forming a first planarization layer 21 on one side of the driving backplane 1, and the planarization layer group 2 only includes the first planarization layer 21.

[0108] Step S30 may specifically include: coating a metal layer of the pixel electrode 41 on the planarization layer group 2, and through exposure, development, and etching, forming the pixel electrode 41.

[0109] Step S40 may specifically include: coating the pixel defining layer 3 and forming pixel openings 31 through exposure and development.

[0110] Step S50 may specifically include: completely etching away the portion of the pixel defining layer 3 between two adjacent pixel openings 31 in the thickness direction to form a first opening 32, where the first opening 32 is a second groove segment; using the pixel defining layer 3 after forming the pixel openings 31 as a mask layer, partially etching the portion of the first planarization layer 21 between two adjacent pixel electrodes 41 in the thickness direction to form a groove 24, where the groove 24 is a first groove segment.

[0111] For Figure 4 the display panel shown, a specific description will be given.

[0112] Step S20 may specifically include: forming a second planarization layer 22 on one side of the driving backplane 1, forming a third electrode 139 on the side of the second planarization layer 22 away from the driving backplane 1, connecting the third electrode 139 to the first electrode 136 or the second electrode 137 of the thin film transistor 13 through a via hole in the second planarization layer 22, and forming a first planarization layer 21 on the side of the second planarization layer 22 and the third electrode 139 away from the driving backplane 1.

[0113] The specific process of step S50 is the same as Figure 3 the specific process of step S50 in

[0114] For Figure 5 the display panel shown, a specific description will be given.

[0115] The specific process of step S20 is the same as Figure 4 the specific process of step S20 in

[0116] Step S50 may specifically include:

[0117] Completely etching away the portion of the pixel defining layer 3 between two adjacent pixel openings 31 in the thickness direction to form a first opening 32, where the first opening 32 is a second groove segment; completely etching away the portion of the first planarization layer 21 between two adjacent pixel electrodes 41 in the thickness direction to form a second opening 23, where the second opening 23 is a part of the second groove segment; partially etching the portion of the second planarization layer 22 between two adjacent pixel electrodes 41 in the thickness direction to form a groove 24, where the groove 24 is a first groove segment.

[0118] As Figure 14 shown, the second opening 23 can be set after the coating of the first planarization layer 21 is completed to achieve patterning of the first planarization layer 21. As Figure 15 shown, the first opening 32 can be formed simultaneously with the setting of the pixel openings 31 to achieve patterning of the pixel defining layer 3. As Figure 16As shown, the patterned second planarization layer 22 and the patterned pixel defining layer 3 can be used as mask layers to etch the second planarization layer 22 to form grooves 24.

[0119] Among them, the lateral etching rate of the pixel defining layer 3 is equal to the lateral etching rate of the first planarization layer 21, and the lateral etching rate of the second planarization layer 22 is greater than the lateral etching rates of the first planarization layer 21 and the pixel defining layer 3.

[0120] For Figure 6 a specific description of the shown display panel is given.

[0121] The specific process of step S20 is the same as the specific process of step S20 in Figure 5 and the specific process of step S50 is the same as the specific process of step S50. Therefore, it will not be elaborated here.

[0122] The difference is that the lateral etching rate of the pixel defining layer 3 is different from being less than the lateral etching rate of the first planarization layer 21.

[0123] For Figure 7 a specific description of the shown display panel is given.

[0124] Step S20 may specifically include: forming a second planarization layer 22 on one side of the driving backplane 1, forming a third electrode 139 on the side of the second planarization layer 22 away from the driving backplane 1, simultaneously forming a first metal layer 6 between two adjacent pixel electrodes 41, and forming a first planarization layer 21 on the sides of the second planarization layer 22 and the third electrode 139 away from the driving backplane 1.

[0125] Step S50 may specifically include:

[0126] Completely etching away the part of the pixel defining layer 3 located between two adjacent pixel openings 31 in the thickness direction to form a first opening 32; completely etching away the part of the first planarization layer 21 located between two adjacent pixel electrodes 41 in the thickness direction to form a second opening 23; completely etching away the part of the first metal layer 6 located between two adjacent pixel electrodes 41 in the thickness direction to form a third opening 61, and the third opening 61 is a second groove segment; partially etching the part of the second planarization layer 22 located between two adjacent pixel electrodes 41 in the thickness direction to form a groove 24, and the groove 24 is a first groove segment.

[0127] Among them, the lateral etching rates of the pixel defining layer 3, the first planarization layer 21, and the second planarization layer 22 are the same.

[0128] For Figure 8 a specific description of the shown display panel is given.

[0129] The specific process of step S20 is the same as Figure 7 the specific process of step S20 and the specific process of step S50 in

[0130] The difference is that the lateral etching rate of the pixel defining layer 3 is less than the lateral etching rate of the first planarization layer 21, and the lateral etching rate of the first planarization layer 21 is the same as the lateral etching rate of the second planarization layer 22.

[0131] For Figure 9 and Figure 10 the display panel shown, a specific description is given below.

[0132] The specific process of step S20 is the same as Figure 8 the specific process of step S20 and the specific process of step S50 in

[0133] The difference is that the lateral etching rate of the first planarization layer 21 is less than the lateral etching rate of the second planarization layer 22.

[0134] For Figure 11 the display panel shown, a specific description is given below.

[0135] Step S50 may specifically include: as shown in Figure 17 , performing photolithography on the pixel defining layer 3 to form a first opening 32 between two adjacent pixel openings 31, and then coating a photoresist layer 8 to cover the pixel defining layer 3, a plurality of pixel electrodes 41, and a plurality of barrier layers 7, and forming an area to be etched 81 in the photoresist layer 8 through a photolithography process. As shown in Figure 18 , etching the barrier layer 7 to form a fourth opening 71 on the barrier layer 7. As shown in Figure 19 , removing the remaining part of the photoresist layer 8 through a photolithography process. The first opening 32 is the second groove segment, and the fourth opening 71 is the first groove segment.

[0136] It should be noted that Figure 11 in the manufacturing process of the display panel, the patterning of the photoresist layer 8 is completed through a corresponding mask plate, and in the process of forming the pixel electrodes 41, the patterning of the barrier layer 7 is realized.

[0137] For Figure 12 the display panel shown, a specific description is given below.

[0138] This method may further include: before forming the pixel electrodes 41, forming a barrier layer 7 made of an inorganic material on the side of the planarization layer group 2 away from the driving backplane 1; through a photolithography process and an etching process, retaining the barrier layer 7 made of an inorganic material between two sub-pixels.

[0139] As Figures 20 to 22 shown, step S50 andFigure 11 The specific process of step 50 is basically the same, so it will not be elaborated here.

[0140] Figure 12 In the process of manufacturing the display panel of , the patterning of the photoresist layer 8 is completed through the corresponding mask plate, and the patterning of the inorganic material barrier layer 7 is completed through the corresponding mask plate.

[0141] It should be noted that although the steps of the method for manufacturing the display panel in the present disclosure are described in a specific order in the drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0142] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include well-known knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only considered exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A display panel, characterized in that, Comprising: A driving backplane; A planarization layer group disposed on one side of the driving backplane; A plurality of pixel electrodes spaced apart and disposed on the side of the planarization layer group away from the driving backplane; A pixel definition layer disposed on the side of the planarization layer group away from the driving backplane. The pixel definition layer is provided with pixel openings exposing the pixel electrodes, and a partition groove is provided between two adjacent pixel openings. The partition groove includes a first groove segment and a second groove segment sequentially away from the driving backplane, and the orthographic projection of the second groove segment on the driving backplane is located within the orthographic projection of the first groove segment on the driving backplane; A light-emitting layer group disposed on the side of the plurality of pixel electrodes and the pixel definition layer away from the driving backplane. The light-emitting layer group includes a common layer, and the common layer is disconnected within the partition groove; A common electrode disposed on the side of the light-emitting layer group away from the driving backplane; A first opening is provided between two adjacent pixel openings. The planarization layer group includes: A first planarization layer disposed between the driving backplane and the pixel definition layer. The first planarization layer is provided with a second opening, and the second opening is in communication with the first opening; A second planarization layer disposed between the first planarization layer and the driving backplane. The second planarization layer is provided with a groove, and the first groove segment is the groove; A first metal layer disposed between the first planarization layer and the second planarization layer and located between two adjacent pixel electrodes. The first metal layer is provided with a third opening, and the second groove segment is the third opening, and the third opening is in communication with the second opening; 2. The display panel according to claim 1, wherein The orthographic projection of the first opening on the driving backplane, the orthographic projection of the second opening on the driving backplane, and the orthographic projection of the groove on the driving backplane coincide with each other; 3. The display panel according to claim 1, wherein The orthographic projection of the first opening on the driving backplane is located within the orthographic projection of the second opening on the driving backplane; 4. The display panel according to claim 3, wherein The orthographic projection of the second opening on the driving backplane is located within the orthographic projection of the groove on the driving backplane; 5. The display panel according to claim 1, wherein The driving backplane includes a substrate and a plurality of thin-film transistors disposed on one side of the substrate. The display panel further includes: A plurality of third electrodes disposed between the first planarization layer and the second planarization layer. The pixel electrode is electrically connected to the third electrode through a via hole in the second planarization layer, and the third electrode is electrically connected to the first electrode or the second electrode of the thin-film transistor through a via hole in the first planarization layer; 6. The display panel according to claim 1, wherein The light-emitting layer group further includes a layer of light-emitting material layer. The common layer includes a first common layer group and a second common layer group. The first common layer group and the second common layer group are respectively disposed on opposite sides of the light-emitting material layer. The first common layer at least includes a hole injection layer and a hole transport layer, and the second common layer at least includes an electron transport layer and an electron injection layer.

7. The display panel according to claim 1, wherein The light-emitting layer group further includes two light-emitting material layers. The common layer includes a third common layer, a first common layer group, and a second common layer group. The third common layer is disposed between two adjacent light-emitting material layers. The first common layer group and the second common layer group are respectively disposed on a side of the light-emitting material layer away from the third common layer. The third common layer is a charge generation layer. The first common layer includes at least a hole injection layer and a hole transport layer. The second common layer includes at least an electron transport layer and an electron injection layer.

8. A display device, characterized in that, A display panel including the display panel according to any one of claims 1 to 7.

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