Standard cells, integrated circuits, standard cell libraries and electronic devices

Abstract

The embodiment of the application provides a standard cell, an integrated circuit, a standard cell library and an electronic device, relates to the technical field of semiconductors, and is used for optimizing the structure of a standard cell to realize that different types of standard cells can be spliced at will. The standard cell comprises a first active region and a second active region which are N-type active regions and P-type active regions; a first gate strip which extends along a first direction and is located on a side of the first active region and the second active region away from a substrate; two second gate strips, the first gate strip being located between the two second gate strips; two ends of the second active region being located on a side of the two second gate strips close to the substrate; two spacing regions and two first trench isolation regions; the first active region being located between the two spacing regions, the second active region being located between the two first trench isolation regions, the width of the spacing region and the width of the first trench isolation region being equal to the arrangement pitch of the first gate strip and the second gate strip, and the standard cell being extended by one contact poly pitch (CPP) to the edge gate on each side.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a standard cell, integrated circuit, standard cell library, and electronic device. Background Technology

[0002] The standard cell library, including layout libraries, symbol libraries, and circuit logic libraries, is a fundamental part of the back-end design process for integrated circuit chips. In the current FinFET technology node, the standard cell library can be divided into three categories based on the isolation type between standard cells (STCs): double diffusion break (DDB) standard cells, single diffusion break (SDB) standard cells, and mixed diffusion break (MDB) standard cells.

[0003] DDB standard cells have lower fabrication costs, SDB standard cells have smaller design areas, and MDB standard cells have superior performance. Each type of standard cell has its own advantages, and how to enable the free assembly of these three types of standard cells is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a standard cell, an integrated circuit, a standard cell library, and an electronic device for optimizing the structure of the standard cell so that different types of standard cells can be freely spliced ​​together.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] A first aspect of this application provides a standard cell, which is a standard cell with a specific circuit function in an integrated circuit. The standard cell can be a DDB standard cell or an MDB standard cell. The standard cell includes a first active region and a second active region, the first active region extending along a second direction, and the second active region also extending along the second direction. The first active region and the second active region are disposed side-by-side along a first direction on one side of a substrate. Of course, the substrate can be a structure belonging to the standard cell, or it can be a structure not belonging to the standard cell. The first active region and the second active region are respectively an N-type active region and a P-type active region. For example, the first active region is a P-type active region, and the second active region is an N-type active region. The standard cell also includes at least one first gate strip, the first gate strip extending along the first direction and located above the first and second active regions (away from the substrate), and multiple first gate strips arranged along the second direction. The standard cell also includes two second gate strips, the second gate strips extending along the first direction. At least one first gate strip is located between two second gate strips, and the two second gate strips and at least one first gate strip are arranged at equal intervals along a second direction; the first direction intersects the second direction and is parallel to the substrate; along the second direction, the two ends of the second active region are located below the two second gate strips (on the side closer to the substrate). The standard cell also includes two spacer regions and two first trench isolation regions. Along the second direction, the spacer regions are located on the extension lines of the first active regions, and the first active regions are located between the two spacer regions; the first trench isolation regions are located on the extension lines of the second active regions, and the second active regions are located between the two first trench isolation regions. The width of the spacer regions and the width of the first trench isolation regions are equal to the arrangement spacing of the two second gate strips and at least one first gate strip.

[0007] Because the width of the portion of the traditional DDB and MDB standard cells that diffuses outward from the second gate is half the spacing between the first and second gates (e.g., 0.5 contact polysilicon spacing CPP), the traditional DDB and MDB standard cells are extended by half a spacing (0.5 CPP) on one side relative to the traditional SDB standard cells, making it impossible to align and splice them with the traditional SDB standard cells. The DDB or MDB standard cells provided in this application embodiment, by setting the width of the portion (spacer area and first trench isolation area) that diffuses outward from the second gate in the standard cell to be equal to the spacing between the first and second gates (1 CPP), instead of half the aforementioned spacing (0.5 CPP), allows the standard cells provided in this application embodiment to extend by one of the aforementioned spacings (1 CPP) on one side relative to the traditional SDB standard cells along the width direction. Therefore, when splicing standard cells, the distance from the splicing line to the second gate is an integer multiple of the aforementioned spacing (CPP). Different types of standard cells can be placed directly adjacent to each other to achieve mixed splicing of different types of standard cells. This solves the problem that standard cells of the same height (or multiples of the height) and different types are not compatible with each other in an integrated circuit due to different splicing alignment methods, thus enabling the application of HDB technology.

[0008] In one possible implementation, the second gate strip includes a first barrier gate, a first barrier portion, and a first diffusion fracture; the first barrier portion is located between the first barrier gate and the first diffusion fracture; along a direction perpendicular to the substrate (third direction), the first diffusion fracture extends to the bottom surface of the first active region near the substrate, and the first barrier gate is located on the side of the second active region away from the substrate. The standard cell can be an MDB standard cell to achieve a hybrid splicing of MDB standard cells and SDB standard cells.

[0009] In one possible implementation, the spacer region and the first active region are of the same type of active region. In this way, the spacer region can be formed simultaneously with the formation of the first active region, eliminating the need for a separate process to form the spacer region and simplifying the process.

[0010] In one possible implementation, the second gate strip is located on the side of the first and second active regions away from the substrate; the spacer region is a second trench isolation region. The standard cell can be a DDB standard cell to achieve a hybrid splicing of DDB and SDB standard cells.

[0011] In one possible implementation, the standard unit further includes two first splicing strips; along a second direction, two second grid strips are located between the two first splicing strips, and the distance between the first splicing strips and the second grid strips is equal to the aforementioned spacing. By setting the first splicing strips, the alignment and splicing accuracy of the standard unit can be improved.

[0012] In one possible implementation, the first splicing strip is arranged in the same layer as the first grid strip. This allows the first splicing strip and the first grid strip to be formed simultaneously using the same process, simplifying the manufacturing process.

[0013] In one possible implementation, the first splice strip extends along a direction perpendicular to the substrate to the spacer region and the first trench isolation region near the bottom surface of the substrate. In this way, the first splice strip directly constitutes a diffusion break, reducing the structural requirements for diffusion-blocking in the standard cells it is spliced ​​with.

[0014] In one possible implementation, the standard cell further includes two second splicing strips; along a second direction, the two second gate strips are located between the two second splicing strips; along a direction perpendicular to the substrate, the second splicing strips extend to the bottom surface of the first and second active regions near the substrate. By adding second splicing strips to the standard cell, the width of one side of the standard cell is extended outward by at least 2 CPPs, diffusion is interrupted inside the standard cell, and the standard cells can be directly adjacent during design and use without reserving a gap of at least 1 CPP.

[0015] In one possible implementation, the standard cell further includes two first extended active regions and two second extended active regions located on the side of the second splice strip facing the second grid strip; along the second direction, two spacer regions are located between the two first extended active regions, and two first trench isolation regions are located between the two second extended active regions; the first extended active regions are active regions of the same type as the first active regions, and the second extended active regions are active regions of the same type as the second active regions. By setting the areas on both sides of the spacer regions as first extended active regions and setting the structures on both sides of the first trench isolation regions as second extended active regions, the performance of the standard cell can be improved.

[0016] In one possible implementation, the standard cell also includes multiple extension bars located on the side of the second splice bar facing the second bar. By adding extension bars to the standard cell, the width of the standard cell can be changed without altering its performance, thus meeting the needs of different layouts.

[0017] In one possible implementation, the second splicing strip, the extended grid strip, the first splicing strip, the second grid strip, and the first grid strip are arranged at equal intervals along the second direction. This is one possible implementation.

[0018] In one possible implementation, the standard cell further includes a gate connection hole that communicates with the first gate bar. This is one possible implementation.

[0019] A second aspect of the embodiments of this application provides an integrated circuit, the integrated circuit including a first standard unit and a second standard unit, the first standard unit and the second standard unit being arranged side by side along a direction intersecting a first gate bar; the first standard unit is a standard unit of any one of the first aspects, and / or the second standard unit is a standard unit of any one of the first aspects.

[0020] Since the standard units provided in the first aspect of this application have the same splicing and alignment method, different types of standard units can be spliced ​​arbitrarily. The integrated circuit can simultaneously include DDB standard units, MDB standard units and SDB standard units, so as to take advantage of the advantages of each type of standard unit, and further improve the performance of the integrated circuit or reduce the power consumption of the integrated circuit while keeping the integrated circuit area unchanged, so as to further optimize the performance of the integrated circuit.

[0021] In one possible implementation, the second standard cell is a single-diffusion-fracture standard cell; the single-diffusion-fracture standard cell includes two second diffusion fractures arranged parallel to the second gate strip; the spacer region and the first trench isolation region are located between the adjacent second gate strips and the second diffusion fractures. Thus, the integrated circuit can include SDB standard cells and MDB standard cells or DDB standard cells.

[0022] In one possible implementation, the spacer region and the first trench isolation region are in contact with the side of the second diffusion fracture. The first standard cell included in the integrated circuit can be a standard cell that does not include the second splice strip.

[0023] In one possible implementation, a first extended active region is further disposed between the second diffusion fracture and the spacer region, and a second extended active region is further disposed between the second diffusion fracture and the first trench isolation region. The first standard cell included in the integrated circuit can be a standard cell including a second splicing strip.

[0024] In one possible implementation, the integrated circuit includes two third diffusion breaks parallel to the first gate strip, extending to the bottom surface of the first active region near the substrate; a spacer region for the first standard cell is disposed on the side of the third diffusion break facing the second gate strip, and a spacer region for the second standard cell is disposed on the side of the other third diffusion break facing the edge gate; the integrated circuit also includes a first spliced ​​active region and a second spliced ​​active region, located between the two third diffusion breaks. Thus, the integrated circuit can include MDB standard cells and / or DDB standard cells.

[0025] In one possible implementation, the first standard unit and the second standard unit include a second splicing strip; the second splicing strip of the first standard unit coincides with the second splicing strip of the second standard unit. This is one possible structure.

[0026] In one possible implementation, the first standard unit includes a second splicing strip; the spacing region and the first groove break region of the second standard unit are in contact with the side of the second splicing strip. This is one possible structure.

[0027] In one possible implementation, the first standard unit and the second standard unit have the same structure. This is one possible structure.

[0028] In one possible implementation, the second gate strip of the first standard cell includes a first barrier gate, a first barrier portion, and a first diffusion break, and the second gate strip of the second standard cell is located on the side of the first active region and the second active region away from the substrate. This is one possible structure.

[0029] In one possible implementation, the integrated circuit includes multiple rows of standard cells, each row containing at least one first standard cell and / or a second standard cell. This is one possible structure.

[0030] A third aspect of this application provides an electronic device, including a circuit board and an integrated circuit, wherein the integrated circuit is any one of the integrated circuits in the second aspect.

[0031] A fourth aspect of the embodiments of this application provides a standard element library, including multiple standard elements, wherein the multiple standard elements include the standard elements of any one of the first aspects and the single diffusion fracture standard elements. Attached Figure Description

[0032] Figure 1A A schematic diagram of the frame of an electronic device provided in an embodiment of this application;

[0033] Figure 1B A schematic diagram of a SOC framework provided in an embodiment of this application;

[0034] Figure 2A A schematic diagram of the structure of a DDB standard unit provided for related technologies;

[0035] Figure 2B A schematic diagram of the structure of an MDB standard unit is provided for related technologies;

[0036] Figure 2C A schematic diagram of the structure of an SDB standard unit provided for related technologies;

[0037] Figure 3A A schematic diagram of a DDB standard unit spliced ​​together is provided for related technologies;

[0038] Figure 3B A schematic diagram of a structure for splicing MDB standard units to provide information for related technologies;

[0039] Figure 3C A schematic diagram of a structure for splicing SDB standard units together, provided for related technologies;

[0040] Figure 4A A schematic diagram of the structure of a standard unit provided in an embodiment of this application;

[0041] Figure 4B A schematic diagram of another standard unit provided in the embodiments of this application;

[0042] Figure 5A A schematic diagram of the structure of an MDB standard unit provided in an embodiment of this application;

[0043] Figure 5B For along Figure 5A Cross-sectional view along the A1-A2 direction;

[0044] Figure 6A A schematic diagram of the structure of a DDB standard unit provided in an embodiment of this application;

[0045] Figure 6B For along Figure 6A Cross-sectional view along the B1-B2 direction;

[0046] Figure 7 This is a schematic diagram of the structure of another standard unit provided in the embodiments of this application;

[0047] Figure 8A This is a schematic diagram of another MDB standard unit provided in an embodiment of this application;

[0048] Figure 8B For along Figure 8A Cross-sectional view along the C1-C2 direction;

[0049] Figure 9A A schematic diagram of another DDB standard unit provided in this application embodiment;

[0050] Figure 9B For along Figure 9A Cross-sectional view along the D1-D2 direction;

[0051] Figure 10A This is a schematic diagram of the structure of another standard unit provided in the embodiments of this application;

[0052] Figure 10B This is a schematic diagram of the structure of another standard unit provided in the embodiments of this application;

[0053] Figure 11A A schematic diagram of the structure of another MDB standard unit provided in the embodiments of this application;

[0054] Figure 11BA schematic diagram of the structure of another DDB standard unit provided in the embodiments of this application;

[0055] Figure 11C This is a schematic diagram of the structure of another standard unit provided in the embodiments of this application;

[0056] Figure 12A This application provides a schematic diagram of a structure for splicing SDB standard units and MDB standard units in an embodiment.

[0057] Figure 12B A schematic diagram illustrating a method of splicing an SDB standard unit with an MDB standard unit excluding the first splicing strip, provided for an embodiment of this application;

[0058] Figure 12C A schematic diagram illustrating a method of splicing an SDB standard unit with an MDB standard unit including a first splicing strip, provided for an embodiment of this application;

[0059] Figure 12D This is a schematic diagram illustrating another method of splicing SDB standard units and MDB standard units according to an embodiment of this application;

[0060] Figure 13A This application provides a schematic diagram of a structure for splicing SDB standard units and DDB standard units in an embodiment.

[0061] Figure 13B This is a schematic diagram illustrating another structural connection between an SDB standard unit and a DDB standard unit, provided in an embodiment of this application.

[0062] Figure 14A This application provides a schematic diagram of a structure for splicing MDB standard units and DDB standard units in an embodiment.

[0063] Figure 14B This is a schematic diagram illustrating another structural connection between an MDB standard unit and a DDB standard unit, provided in an embodiment of this application.

[0064] Figures 15A-15C This application provides a schematic diagram of a structure for splicing MDB standard units together.

[0065] Figure 16 A schematic diagram of the structure of splicing SDB standard unit, DDB standard unit and DDB standard unit provided in the embodiments of this application;

[0066] Figure 17A and Figure 17B This is a layout diagram of an integrated circuit provided in an embodiment of this application. Detailed Implementation

[0067] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0068] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0069] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0070] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0071] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0072] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). In-vehicle electronics products include in-vehicle navigation systems and in-vehicle high-density digital video discs (DVDs). Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics products include servers, storage devices, radar, base stations, and other communication equipment.

[0073] For ease of explanation, we will use a mobile phone as an example below. Figure 1A As shown, the electronic device mainly includes a cover plate 1, a display screen 2, a middle frame 3, and a back cover 4. The back cover 4 and the display screen 2 are located on both sides of the middle frame 3, and the middle frame 3 and the display screen 2 are disposed inside the back cover 4. The cover plate 1 is disposed on the side of the display screen 2 away from the middle frame 3, and the display surface of the display screen 2 faces the cover plate 1.

[0074] The aforementioned display screen 2 can be a liquid crystal display (LCD). In this case, the LCD includes a liquid crystal display panel and a backlight module. The liquid crystal display panel is disposed between the cover plate 1 and the backlight module, and the backlight module provides a light source for the liquid crystal display panel. Alternatively, the aforementioned display screen 2 can be an organic light-emitting diode (OLED) display. Since OLED displays are self-emissive, a backlight module is not required.

[0075] The aforementioned middle frame 3 includes a carrier plate 31 and a frame 32 surrounding the carrier plate 31. The aforementioned electronic device may also include printed circuit boards (PCBs), batteries, cameras, and other electronic components, which may be mounted on the carrier plate 31.

[0076] The aforementioned electronic devices may also include system-on-chip (SOC), radio frequency (RF) chips, etc., disposed on a PCB. The PCB is used to carry the SOC, RF chips, etc., and is electrically connected to the SOC, RF chips, etc.

[0077] This application also provides a SOC, for example, such as Figure 1B As shown, the SOC includes a processor 11, a memory 12, a digital-to-analog converter (ADC / DAC) module 13, a power management module 14, an interface module 15, and user-defined logic 16. The above structure can be coupled to the bus 17 to perform communication.

[0078] The processor 11 can perform specific calculations or tasks. The processor 11 may include, for example, a microprocessor, a central processing unit (CPU), or a digital signal processor (DSP). The memory 12 can store data necessary for operating the SOC. For example, the memory 12 can be dynamic random access memory (DRAM), static random access memory (SRAM), ferroelectric random access memory (FRAM), or magnetic random access memory (MRAM). The digital-to-analog converter module 13 is used to convert data signals to analog signals. The power management module 14 provides power to the various modules in the SOC. The interface module 15 enables communication between the SOC and external devices. User-defined logic 16 or other digital modules may be application-specific integrated circuits (ASICs) formed using field-programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs). The bus 17 may include, for example, an address bus, a control bus, a data bus, or an expansion bus.

[0079] Modules such as the out-of-order integer executive (OEX) module in the CPU core, FPGA, and CPLD can use electronic design automation (EDA) to perform layout design. EDA refers to the design method that uses computer-aided design (CAD) software to complete the functional design, synthesis, verification, and physical design (including placement, routing, layout, design rule checking, etc.) of very large scale integration (VLSI) chips.

[0080] Use EDA to retrieve standard cells from the standard cell library and splice the standard cells together to complete the integrated circuit design.

[0081] In the current technology, the standard cell library of the FinFET technology node can be divided into three categories according to the isolation type between standard cells (STC): double diffusion break (DDB) standard cells, single diffusion break (SDB) standard cells, and mixed diffusion break (MDB) standard cells.

[0082] like Figure 2A As shown, the DDB standard unit includes multiple first grid strips G, two edge grids, a P-type active region (Pactive, PA), and an N-type active region (Nactive, NA). The edge grids are arranged on the same layer as the first grid strips G, above the P-type active region PA and the N-type active region NA. The two edge grids are located on either side of the multiple first grid strips G. From a top view, the P-type active region PA and the N-type active region NA are located between the two edge grids. Connecting holes are correspondingly provided above the first grid strips G, the P-type active region PA, and the N-type active region NA, but no connecting holes are provided above the edge grids. The P-type active region PA, the N-type active region NA, the edge grids, and the first grid strips are located between two polycut isolation strips.

[0083] From a top view, a shallow trench isolation (STI) region is provided on the outer side of the edge gate of the DDB standard cell, away from the first gate bar G. The distance from the edge of the STI to the edge gate is approximately half (0.5 CPP) of the spacing between adjacent first gate bars G (or, in other words, the contact poly pitch (CPP)). In other words, to achieve isolation between the P-type active region (PA) and the N-type active region (NA) of adjacent standard cells, the boundary of the DDB standard cell is marked by an STI 0.5 CPP outward from the edge gate, providing a gap for blocking the P-type active region (PA) and the N-type active region (NA).

[0084] like Figure 2B As shown, the MDB standard cell includes multiple first grid bars G, two edge grids, a P-type active region PA, and an N-type active region NA. The two edge grids are located on either side of the multiple first grid bars G, with the first grid bars G positioned above the P-type active region PA and the N-type active region NA. Each edge grid includes a diffusion break, a barrier grid, and a barrier portion separating the two. The diffusion break penetrates the P-type active region PA, serving as a barrier, and the barrier grid is located above the N-type active region NA. Connection holes are correspondingly provided above the first grid bars G, the P-type active region PA, and the N-type active region NA; no connection holes are provided above the edge grids. The P-type active region PA, the N-type active region NA, the edge grids, and the first grid bars are located between the two barrier bars.

[0085] From the top view, the P-type active region PA extends beyond the edge gate, and the N-type active region NA has an STI (Spacing Intensity Transmission) outside. The distance from the edge of the P-type active region PA to the edge gate is approximately 0.5 CPP, and the distance from the edge of the STI to the edge gate is also approximately 0.5 CPP. In other words, to achieve isolation of the N-type active region NA between adjacent standard cells, the boundary of the MDB standard cell is 0.5 CPP outward from the edge gate, with an STI to provide a gap for blocking the N-type active region NA. When the boundary of the MDB standard cell is 0.5 CPP outward from the edge gate, the P-type active region PA is already blocked by diffusion fracture; therefore, a P-type active region PA can be formed outside the diffusion fracture to improve the performance of the standard cell.

[0086] like Figure 2CAs shown, the SDB standard cell includes multiple first grid bars G, two edge grids, a P-type active region PA, and an N-type active region NA. The two edge grids are located on either side of the multiple first grid bars G, with the first grid bars G positioned above the P-type active region PA and the N-type active region NA. The edge grids are diffusion-broken, penetrating both the P-type active region PA and the N-type active region NA, which are located between the two edge grids. Connection holes are correspondingly provided above the first grid bars G, the P-type active region PA, and the N-type active region NA; no connection holes are provided above the edge grids. The P-type active region PA, the N-type active region NA, the edge grids, and the first grid bars are located between two isolation bars.

[0087] From the top view, the center line of the edge grid in the SDB standard cell serves as the boundary of the SDB standard cell. This means that the P-type active region (PA) and the N-type active region (NA) are blocked by diffusion fracture, and the boundary of the SDB standard cell does not need to extend beyond the edge grid. Therefore, the left and right ends of the DDB and MDB standard cells are each extended by approximately 0.5 CPP compared to the left and right ends of the SDB standard cell.

[0088] DDB standard cells require two fewer masks for diffusion fracture fabrication, resulting in lower manufacturing costs. SDB standard cells do not require the active region and insulating layer to extend beyond the edge gate, leading to a smaller design area. MDB standard cells utilize the layout dependent effect (LDE) to combine DDB and SDB standard cells, achieving a speed improvement over either SDB or DDB standard cells, resulting in superior performance. Each of these three types of standard cells has its own advantages. Currently, foundries provide multiple standard cell libraries to meet the performance and power consumption requirements of different products. Typically, there are high-performance (HP) and high-density (HD) standard cell libraries. HP standard cell libraries are generally implemented using DDB standard cells, while HD standard cell libraries are generally based on SDB standard cells.

[0089] As shown in Table 1, taking the out-of-order execution module in the CPU core as an example, the performance power area (PPA) is compared between implementing this module using MDB standard cells and implementing it using SDB standard cells. Physical synthesis implementations are compared under the following conditions: a power supply voltage (VDD) of 0.6V, a temperature of 85℃, and a typical corner (TT) of TT0 (i.e., tt0p6v85c in Table 1); and a power supply voltage (VDD) of 1.0V, a temperature of 85℃, and a typical corner (TT) of TT1 (i.e., tt1p0v85c in Table 1). The results show that while MDB standard cells offer a 2%–8% speed improvement over SDB standard cells, their area increases by 5%–12%. Using MDB standard cells increases chip area, thus increasing chip cost. Meanwhile, the leakage power consumption of the MDB standard cell is more than 25% higher than that of the SDB standard cell. For consumer products, leakage power consumption is a relatively important indicator, and an excessive increase in leakage power consumption is unacceptable.

[0090] Table 1: Comparison of Module-Level PPAs between MDB and SDB

[0091] MDB vs SDB tt0p6v85c tt1p0v85c <![CDATA[Area (um 2 )]]> 105％ 112％ Speed ​​(GHz) 108％ 102％ Leakage current (W) 123％ 130％ Power consumption (W / GHz) 94％ 98％

[0092] Therefore, MDB, SDB, and DDB standard cells each have their own advantages and disadvantages. Only by using all three in the same integrated circuit can the performance of the integrated circuit be effectively improved.

[0093] However, because the left and right ends of the MDB standard cell and the DDB standard cell are extended by approximately 0.5 CPP compared to the left and right ends of the SDB standard cell, such as... Figure 3A As shown, when two DDB standard cells are spliced ​​together, the splicing line is located between the edge grids of the two DDB standard cells, and the distance between the splicing line and the edge grid is approximately 0.5 CPP. Figure 3B As shown, when two MDB standard cells are spliced, the splice line is located between the edge grids of the two MDB standard cells, and the distance between the splice line and the edge grid is approximately 0.5 CPP. Figure 3CAs shown, when two SDB standard cells are spliced ​​together, the splicing line is located on the center line of the edge gate in the SDB standard cell, and the edge gates of the two SDB standard cells overlap. Because the splicing alignment methods of the three types of standard cells are different, standard cells of the same height (or multiples of the height) but different types are not compatible with each other in a single integrated circuit. EDA tools cannot support the direct mixing of MDB standard cells and DDB standard cells with SDB standard cells in the same integrated circuit. For example, whether based on the HP standard cell library or the HD standard cell library, the integrated circuit is designed using only one type of standard cell. However, hybrid diffusion break (HDB) using different types of standard cells can achieve a more optimized design.

[0094] To address the issue of incompatibility between different types of standard units in an integrated circuit, embodiments of this application provide a new DDB standard unit and MDB standard unit, enabling the splicing of standard units of the same type and standard units of different types.

[0095] like Figure 4A As shown, this application embodiment provides a standard cell (STC), the standard cell STC including components disposed on a substrate (…). Figure 4A (Not shown in the diagram) The diagram includes a first active region A1, a second active region A2, at least one first grid bar G, two second grid bars 20, two spacer regions M1, and two first trench isolation regions STI1. Among these, Figure 4A The following is an illustration of a standard unit consisting of multiple first grid bars G.

[0096] The standard cell STC provided in this application embodiment may or may not include a substrate. This application embodiment illustrates the standard cell STC including a substrate as an example. In this application embodiment, the substrate is not marked in the top view, but the relative positional relationship between the substrate and the first active region A1 and the second active region A2 can be seen from the subsequent cross-sectional view.

[0097] The first active region A1 and the second active region A2 are N-type active regions and P-type active regions, respectively. The first active region A1 and the second active region A2 are disposed side by side on the substrate 10 along the first direction Y, and both the first active region A1 and the second active region A2 extend along the second direction X.

[0098] N-type active regions are formed by doping an N-type impurity into a semiconductor, and P-type active regions are formed by doping a P-type impurity into a semiconductor. In the embodiments of this application, the second direction X intersects (e.g., is perpendicular to) the first direction Y. The first active region A1 and the second active region A2 are each an N-type active region and a P-type active region, respectively. This can be understood as the first active region A1 being one of the N-type and P-type active regions, and the second active region A2 being the other of the N-type and P-type active regions. For example, if the first row is a P-type active region row and the second row is an N-type active region row, then... Figure 4A As shown, the first active region A1 is a P-type active region, and the second active region A2 is an N-type active region. Alternatively, as an example... Figure 4B As shown, the second active region A2 is a P-type active region, and the first active region A1 is an N-type active region. For ease of explanation, the first active region A1 will be considered a P-type active region, and the second active region A2 will be considered an N-type active region for illustration purposes.

[0099] In some embodiments, the standard unit STC further includes at least one first fin and at least one second fin. Figure 4A and Figure 4B The first and second fins are not shown. The first fin is located above the first active region A1 and extends along the second direction X to the edge of the standard cell STC. Multiple first fins are arranged along the first direction Y. The second fin is located above the second active region A2 and extends along the second direction X to the edge of the standard cell STC. Multiple second fins are arranged along the first direction Y.

[0100] The first gate bar G extends along the first direction Y and is located above the first active region A1 and the second active region A2 (the first gate bar G is located on the side of the first and second fins away from the first active region A1 and the second active region A2). That is, the projection of the first gate bar G onto the plane of the substrate overlaps with the projections of the first active region A1 and the second active region A2 onto the plane of the substrate. Alternatively, it can be understood that the first gate bar G crosses the first active region A1 and the second active region A2. In the case where the standard cell STC includes multiple first gate bars G, the multiple first gate bars G are arranged along the second direction X.

[0101] The portion of the first grid bar G that crosses the first active region A1 and the portion that crosses the second active region A2 can be disconnected, and the portion of the first grid bar G that crosses the first active region A1 and the portion that crosses the second active region A2 can also be coupled. In this embodiment, the coupling of the two parts is only used as an example for illustration.

[0102] The second grid bar 20 extends along the first direction Y, and two second grid bars 20 and at least one first grid bar G are arranged along the second direction X, with the at least one first grid bar G located between the two second grid bars 20. For example, the two second grid bars 20 and at least one first grid bar G are arranged at equal intervals along the second direction X, such as CPP. The distance between the second grid bar 20 and the first grid bar G can be, for example, the distance between the center lines of the second grid bar 20 and the first grid bar G. The distance between adjacent first grid bars G can be, for example, the distance between the center lines of the first grid bars G and the center lines of the first grid bars G.

[0103] It is understood that "equal spacing" in the embodiments of this application does not require the spacing to be completely equal. Spacing that is approximately equal is also considered equal spacing in the embodiments of this application. Spacing variations within the range of process error (e.g., ±1.5%) are all considered equal spacing in the embodiments of this application.

[0104] Along the second direction X, the two ends of the second active region A2 are located below the two second gate strips 20 (on the side closer to the substrate 10), and the ends of the first active region A1 and the second active region A2 are flush or nearly flush. Alternatively, it can be understood that the projections of the first active region A1 and the second active region A2 onto the plane of the substrate are located between the projections of the two second gate strips 20 onto the plane of the substrate.

[0105] The spacer region M1 is located on the extension line of the first active region A1 along the second direction X, and the first active region A1 is located between the two spacer regions M1. The boundary between the first active region A1 and the spacer region M1 can be located, for example, at the center line of the second grid bar 20 (extending along the first direction Y).

[0106] The second grid bar 20, in conjunction with the spacer region M1, is used to interrupt the first active region A1. The second grid bar 20 and the spacer region M1 will be described in detail later; they will not be discussed further here.

[0107] The first trench isolation region STI1 is located on the extension line of the second active region A2 along the second direction X, and the second active region A2 is located between the two first trench isolation regions STI1. The boundary between the second active region A2 and the first trench isolation region STI1 can be located, for example, at the center line of the second grid bar 20 (extending along the first direction Y).

[0108] like Figure 4A As shown, along the second direction X, the width L1 of the spacer region M1 and the width L2 of the first trench isolation region STI1 are equal to the spacing between the second grid bar 20 and the first grid bar G along the second direction X (e.g., CPP as described above). The width L1 of the spacer region M1 can be, for example, the distance from the end of the spacer region M1 to the centerline of the second grid bar 20. The width L2 of the first trench isolation region STI1 can be, for example, the distance from the end of the first trench isolation region STI1 to the centerline of the second grid bar 20.

[0109] The standard cell STC provided in this application embodiment sets the width of the portion of the standard cell STC that extends outward from the second gate strip 20 to CPP instead of 0.5CPP. That is, the standard cell STC extends by 1 CPP on one side relative to the traditional SDB standard cell, and along the second direction X, each side of the standard cell STC extends outward from the second gate strip 20 by 1 CPP. Therefore, when standard cell STCs are spliced, the distance between the splicing line and the second gate strip 20 is an integer multiple of CPP. Thus, different types of standard cell STCs can be directly arranged adjacently to achieve mixed splicing of different types of standard cell STCs. This solves the problem that different types of standard cell STCs with the same height (or an integer multiple of the height) cannot be compatible in a single integrated circuit due to different splicing alignment methods, thereby enabling the application of HDB technology.

[0110] Depending on the structure of the second grid bar 20, the standard cell STC can be divided into MDB standard cells and DDB standard cells.

[0111] In one implementation, such as Figure 5A As shown, the standard unit STC is the MDB standard unit, combined with Figure 5A and Figure 5B (along Figure 5A As can be seen from the cross-sectional view along the A1-A2 direction, the second grid bar 20 includes a first barrier grid 21, a first barrier portion 22, and a first diffusion break 23.

[0112] like Figure 5B As shown, along a direction perpendicular to the substrate 10 (a third direction Z perpendicular to the first direction Y and the second direction X), the first diffusion fracture 23 extends to the bottom surface of the first active region A1 near the substrate 10. That is, the first active region A1 and the spacer region M1 on both sides of the first diffusion fracture 23 are separated by the first diffusion fracture 23, and the diffusion of the first active region A1 is blocked by the first diffusion fracture.

[0113] like Figure 5B As shown, along the third direction Z, the first barrier gate 21 is located on the side of the second active region A2 away from the substrate 10. For example, the first barrier gate 21 is disposed in the same layer as the first gate strip G (formed synchronously using the same process). That is, the second active region A2 and the first trench isolation region STI1 are not separated by the first barrier gate 21, the second active region A2 and the first trench isolation region STI1 are in contact, and the first trench isolation region STI1 blocks the diffusion of the second active region A2.

[0114] Along the first direction Y, the first barrier portion 22 is located between the first barrier gate 21 and the first diffusion break 23. That is, the first barrier gate 21 and the first diffusion break 23 are separated by the first barrier portion 22. Along the thickness direction of the MDB standard cell (the third direction Z perpendicular to the substrate 10), the lower surface of the first barrier portion 22 near the substrate 10 can be in the same plane as the lower surface of the first barrier gate 21 near the substrate 10, and the lower surface of the first barrier portion 22 can also be in the same plane as the lower surface of the first diffusion break 23. The material of the first barrier portion 22 can be, for example, a dielectric material.

[0115] In some embodiments, the first barrier portion 22 has an axisymmetric structure, with the axis of symmetry being the centerline of the second grid bar 20. Of course, the first barrier portion 22 can also have other shapes.

[0116] In some embodiments, an insulating layer (e.g., a SiO2 layer) is further disposed on the surfaces of the first active region A1 and the second active region A2, the insulating layer filling the first active region A1 and the second active region A2, and the second gate strip 20 is disposed on the insulating layer.

[0117] In the case where the standard cell STC is an MDB standard cell, in some embodiments, the spacer region M1 is a trench isolation region.

[0118] In other embodiments, the spacer region M1 is an active region, and the spacer region M1 and the first active region A1 are active regions of the same type A1.

[0119] For example, the first active region A1 is a P-type active region, and the interval region M1 is also a P-type active region. The second active region A2 is an N-type active region, and the interval region M2 is also an N-type active region.

[0120] Figure 5B The MDB standard cell includes a substrate 10 as an example for illustration. The substrate 10 carries the first active region A1 and the second active region A2.

[0121] In another implementation, such as Figure 6A As shown, the standard unit STC is the DDB standard unit, combined with... Figure 6A and Figure 6B (along Figure 6A As can be seen from the cross-sectional view along the B1-B2 direction, the second gate strip 20 is located above the first active region A1 and the second active region A2 (on the side away from the substrate 10), and the spacer region M1 is the second trench isolation region STI2.

[0122] For example, the second gate bar 20 is disposed in the same layer as the first gate bar G (formed synchronously using the same process). In this case, the second gate bar 20 can be referred to as a dummy gate.

[0123] In some embodiments, such as Figure 7As shown, the standard unit STC also includes two first splicing strips 30.

[0124] The first splicing strip 30 extends along a first direction Y and along a second direction X, with two second grid strips 20 and at least one first grid strip G located between the two first splicing strips 30. The two first splicing strips 30, the two second grid strips 20, and the at least one first grid strip G are arranged at equal intervals. For example, the distance from the first splicing strip 30 to the second grid strip 20 is equal to the spacing between the second grid strips 20 and the first grid strip G along the second direction X (e.g., CPP as described above).

[0125] In some embodiments, combined with Figure 8A and Figure 8B (along Figure 8A As shown in the cross-sectional view along the C1-C2 direction, along the direction perpendicular to the substrate 10 (third direction Z), the first splice strip 30 is a diffusion fracture, and the first splice strip 30 extends to the bottom surface of the spacer region M1 and the first trench isolation region STI1.

[0126] For example, such as Figure 8A and Figure 8B As shown, the standard unit STC is the MDB standard unit, and the first splicing strip 30 and the first diffusion fracture 23 are set in the same layer.

[0127] In other embodiments, combined with Figure 9A and Figure 9B (along Figure 9A As shown in the cross-sectional view along the D1-D2 direction, the first splicing strip 30 is disposed in the same layer as the first gate strip G along the direction perpendicular to the substrate 10 (third direction Z). For example, the first splicing strip 30 is disposed above the spacer region M1 and the first trench isolation region STI1 (on the side away from the substrate 10).

[0128] For example, such as Figure 9A and Figure 9B As shown, the standard unit STC is a DDB standard unit, and the first splicing strip 30 is set on the same layer as the first grid strip G.

[0129] Compared to the SDB standard cell with the same number of first grid bars G, the aforementioned standard cell STC has an increased width of two CPPs along the second direction X. With the first active region A1 being a P-type active region and the second active region A2 being an N-type active region, physical synthesis revealed that the standard cell STC can improve speed by approximately 8% and increase leakage power consumption by approximately 30%. When the aforementioned standard cell STC is used in combination with the SDB standard cell, using the standard cell STC on timing-critical paths and the SDB standard cell on timing-non-critical paths, it is possible to improve design speed and energy efficiency while maintaining the same area and power consumption.

[0130] In the standard cell STC, when the second active region A2 is a P-type active region and the first active region A1 is an N-type active region, physical synthesis revealed that the standard cell STC is about 3% slower and has about 25% less leakage power consumption. Using the above-mentioned standard cell STC in combination with the SDB standard cell can further reduce the leakage power consumption of the integrated circuit.

[0131] In some embodiments, such as Figure 10A As shown, the standard unit STC also includes two second splicing strips 40.

[0132] Along the second direction X, two first splicing strips 30, two edge grids 20, and at least one first grid strip G are all located between two second splicing strips 40. The two second splicing strips 40, two first splicing strips 30, two second grid strips 20, and at least one first grid strip G are arranged at equal intervals. For example, the distance from the second splicing strip 40 to the first splicing strip 30 is equal to the arrangement spacing of the second grid strips 20 and the first grid strip G along the second direction X (e.g., CPP as described above).

[0133] The second splice strip 40 is a diffusion fracture, extending along the third direction Z to the plane where the bottom surfaces of the first active region A1 and the second active region A2 are located.

[0134] In some embodiments, such as Figure 10A As shown, the standard unit STC also includes two first extended active regions A1' and two second extended active regions A2' located on the side of the second splicing strip 40 facing the first splicing strip 30.

[0135] Along the second direction X, the first extended active region A1' is located on the extension line of the first active region A1, and the first extended active region A1' is spliced ​​with the spacer region MI. The two spacer regions M1 are located between the two first extended active regions A1'. The second extended active region A2' is located on the extension line of the second active region A2, and the second extended active region A2' is spliced ​​with the first trench isolation region STI1. The two first trench isolation regions STI1 are located between the two second extended active regions A2'.

[0136] The first extended active region A1' and the first active region A1 are active regions of the same type, and the second extended active region A2' and the second active region A2 are active regions of the same type.

[0137] For example, the first extended active region A1' and the first active region A1 are P-type active regions, and the second extended active region A2' and the second active region A2 are N-type active regions.

[0138] In other embodiments, the locations where the first extended active region A1' and the two second extended active regions A2' are set are provided with trench isolation structures.

[0139] Thus, along the second direction X, and Figure 7 Compared to the standard cell STC shown, the width of the standard cell STC increases by one CPP, but the width of the standard cell STC is still an integer multiple of CPP.

[0140] By adding a second splicing strip 40 to the standard unit STC, the width of one side of the standard unit STC is extended outward by at least 2 CPPs, and the diffusion interruption is realized inside the standard unit STC. When designing and using, the standard unit STCs can be directly adjacent (abut) without reserving a gap of at least 1 CPP (spacing). The standard unit STCs can be directly spliced.

[0141] In some embodiments, such as Figure 10B As shown, the standard unit STC also includes multiple extended grid strips G', which are located between the first splice strip 30 and the second splice strip 40. For example, the extended grid strips G' are arranged on the same layer as the first grid strip G.

[0142] Example, from Figure 10B From a medium perspective, the number of extension bars G' between the first splicing bar 30 and the second splicing bar 40 on the left is equal to the number of extension bars G' between the first splicing bar 30 and the second splicing bar 40 on the right.

[0143] Figure 10B The example shown is an extension grid G' set between the first splicing strip 30 and the second splicing strip 40. Multiple extension grids G' can also be set between the first splicing strip 30 and the second splicing strip 40 to adjust the layout of the standard cell STC.

[0144] By adding an extension bar G' to the standard cell STC, the width of the standard cell STC can be changed without changing its performance, thus meeting the needs of different layouts.

[0145] In some embodiments, such as Figure 10B As shown, along the second direction X, the second splicing strip 40, the extended grid strip G', the first splicing strip 30, the second grid strip 20, and the first grid strip G are arranged at equal intervals.

[0146] In some embodiments, such as Figure 11A and Figure 11B As shown, the standard unit also includes a gate via (GV) and a source drain via (SDV).

[0147] The gate connection hole GV is connected to the first gate strip G, meaning that the projection of the gate connection hole GV onto the plane of the substrate overlaps with the projection of the first gate strip G onto the plane of the substrate. During subsequent wiring, the gate lines are coupled to the first gate strip G through the gate connection hole GV.

[0148] In some embodiments, a gate connection hole GV is also provided above the extended gate bar G' (on the side away from the substrate 10). The extended gate bar G', together with the first fin and the second fin, constitutes a transistor to improve the performance of the standard cell STC.

[0149] The source / drain connection via SDV located above the first active region A1 (on the side away from the substrate 10) is connected to the portion of the first fin that serves as the source electrode. In the case where the standard cell STC includes multiple first fins, for example, a connection portion M0 is provided on the side of the multiple first fins away from the substrate. The connection portion M0 is coupled to the multiple first fins. The source / drain connection via SDV is connected to the connection portion M0 to realize the connection between the source / drain connection via SDV and the portion of the first fin that serves as the source electrode.

[0150] The source / drain connection via SDV located above the second active region A2 (on the side away from the substrate 10) is connected to the portion of the second fin that serves as the source electrode. In the case where the standard cell STC includes multiple second fins, for example, a connection portion M0 is provided on the side of the multiple second fins away from the substrate. The connection portion M0 is coupled to the multiple second fins, and the source / drain connection via SDV is connected to the connection portion M0 to realize the connection between the source / drain connection via SDV and the portion of the second fin that serves as the source electrode.

[0151] Similarly, the source-drain connection via SDV located above the first active region A1 (on the side away from the substrate 10) is connected to the portion of the first fin that serves as the drain electrode. In the case where the standard cell STC includes multiple first fins, for example, a connection portion M0 is provided on the side of the multiple first fins away from the substrate. The connection portion M0 is coupled to the multiple first fins, and the source-drain connection via SDV is connected to the connection portion M0 to realize the connection between the source-drain connection via SDV and the portion of the first fin that serves as the drain electrode.

[0152] The source-drain connection via SDV located above the second active region A2 (on the side away from the substrate 10) is connected to the drain portion of the second fin. In the case where the standard cell STC includes multiple second fins, for example, a connection portion M0 is provided on the side of the multiple second fins away from the substrate. The connection portion M0 is coupled to the multiple second fins. The source-drain connection via SDV is connected to the connection portion M0 to realize the connection between the source-drain connection via SDV and the drain portion of the second fin.

[0153] The connection portion M0 located above the first active region A1 (on the side away from the substrate 10) and the connection portion M0 located above the second active region A2 (on the side away from the substrate 10) are insulated from each other. The connection portion M0 coupled to the source and the connection portion M0 coupled to the drain are insulated from each other.

[0154] For clarity, the first fin, second fin, gate connection hole GV, and source / drain connection hole SDV in the standard cell STC are not shown in the following illustration.

[0155] In some embodiments, such as Figure 11C As shown, the standard cell STC also includes two isolation strips (poly cuts) that extend along the second direction X. The first active region A1 and the second active region A2 are located between the two isolation strips, and the first gate strip G is located between the isolation strips.

[0156] Of course, the isolation strip can extend continuously from the second splicing strip 40 on the left to the second splicing strip 40 on the right, or it can extend intermittently from the second splicing strip 40 on the left to the second splicing strip 40 on the right. That is, the isolation strip can include multiple intermittent parts. Figure 11C The image shown is for illustrative purposes only and is not intended to be limiting. Of course, the standard unit STC may also omit the isolation strip.

[0157] In some embodiments, the standard unit STC includes a plurality of first active regions A1 and a plurality of second active regions A2, the active regions being arranged in a pattern similar to first active region A1, second active region A2, second active region A2, first active region A1, first active region A1, second active region A2.

[0158] It should be noted that the standard unit STC provided in this application embodiment can be a standard unit with logical function, or a physical filler standard unit. This application embodiment does not limit this.

[0159] This application also provides a standard cell library, including any of the aforementioned standard cells (STCs). The standard cell library serves as an input component in EDA (Electronic Design Automation) processes; it is retrieved in conjunction with software programs to complete the design of integrated circuits.

[0160] This application embodiment optimizes the standard cells (STCs) in the standard cell library, enabling the EDA to select a better splicing scheme when retrieving the standard cell library, thereby optimizing the performance of the final integrated circuit.

[0161] The application provides an integrated circuit including multiple standard cells (STCs) arranged along a second direction X. At least one of the multiple standard cells STCs is any of the aforementioned standard cell STCs. The multiple standard cells STCs can be of the same type or different types.

[0162] In one possible scenario, the first standard unit and the second standard unit are different types of standard units.

[0163] In some embodiments, this application provides an integrated circuit, such as... Figure 12A As shown, the integrated circuit includes a first standard unit and a second standard unit. The first standard unit is the aforementioned MDB standard unit, and the second standard unit is an SDB standard unit. The MDB standard unit and the SDB standard unit are allowed to be directly overlapped and spliced ​​together without the need for one or more CPPs between them.

[0164] Among them, the SDB standard unit is any SDB standard unit in the relevant technology. The SDB standard unit and the MDB standard unit have the same height, or their heights are integer multiples of each other.

[0165] For example, the SDB standard cell includes two second diffusion breaks 50 arranged parallel to the second grid bar 20.

[0166] In the MDB standard cell, the spacer region M1 (active region A1”) and the first trench isolation region STI1 are located between the second grid bar 20 and the second diffusion break 50. Of course, the second grid bar 20 and the second diffusion break 50 are adjacent to each other.

[0167] like Figure 12B As shown, SDB standard units can be spliced ​​with MDB standard units that do not include the first splice strip 30. Figure 12C As shown, the SDB standard cell can also be spliced ​​with the MDB standard cell, which includes the first splice strip 30. In this case, the first splice strip 30 overlaps with the second diffusion fracture 50, regardless of whether the first splice strip 30 is disposed in the same layer as the first grid strip G, or whether the first splice strip 30 extends to the bottom surface of the spacer region M1 and the first trench isolation region STI1. After the SDB standard cell and the MDB standard cell are spliced, the final structure retained is the same as the structure of the second diffusion fracture 50.

[0168] In this configuration, the spacer region M1 and the first trench isolation region STI1 are in contact with the side of the second diffusion fracture 50. Therefore, the spacing between adjacent second grid bars 20 and the second diffusion fracture 50 is equal to the spacing between adjacent second grid bars 20 and the first grid bar G. For example, the spacing between the second grid bars 20 and the second diffusion fracture 50, and the spacing between the second grid bars 20 and the first grid bar G, are both CPP.

[0169] like Figure 12D As shown, the SDB standard cell can also be spliced ​​with the MDB standard cell, which includes the second splice strip 40. In this case, the second splice strip 40 overlaps with the second diffusion fracture 50. After the SDB standard cell and the MDB standard cell are spliced, the final structure is the same as the structure of the second splice strip 40 and the second diffusion fracture 50; only one of them needs to be retained.

[0170] When the MDB standard unit includes the second splice strip 40, the MDB standard unit may include an extension strip G', or the MDB standard unit may not include the extension strip G'. Figure 12D The MDB standard cell, including the extended grid bar G', is used as an example for illustration.

[0171] In this configuration, a first splicing active region A1' is provided between the spacer region M1 and the second diffusion fracture 50, and a second splicing active region A2' is provided between the first trench isolation region STI1 and the second diffusion fracture 50. Therefore, the second grid bar 20 and the second diffusion fracture 50 are at least two CPP apart.

[0172] Since the splicing line of the MDB standard cell is located at the end of the spacer region M1 (active region A1”) and the first trench isolation region STI, and the end of the spacer region M1 (active region A1”) and the first trench isolation region STI is 1 CPP away from the second grid bar 20. Alternatively, the splicing line of the MDB standard cell is located at the center line of the second splicing bar 40. At the same time, the splicing line of the SDB standard cell is located at the center line of the second diffusion break 50. After the splicing lines of the MDB standard cell and the SDB standard cell coincide and are spliced, the second diffusion break 50 is 1 or more CPP away from the second grid bar 20 of the MDB standard cell, which satisfies the distribution law of the EDA midpoint. Therefore, the splicing of MDB standard cells and SDB standard cells can be realized.

[0173] Taking the out-of-order execution module (OEX module) in the CPU core as an example, a PPA comparison is performed on the OEX module implemented using MDB standard cells, the OEX module implemented using SDB standard cells, and the OEX module implemented using HDB (a mixture of MDB and SDB standard cells). Physical synthesis was performed under the conditions of a frequency of 2.1 GHz, a power supply voltage of 0.6 VDD, a temperature of 85 °C, and a typical corner (TT). The physical synthesis results are shown in Table 2. Compared with the OEX module implemented using SDB standard cells, the OEX module implemented using MDB standard cells has a 5% larger standard area, an 8% faster speed, a 23% greater leakage current, and a 6% lower dynamic power consumption. However, the OEX module implemented using HDB (a mixture of SDB and MDB standard cells) has a 3% smaller area, a 6% faster speed, a 1% greater leakage current, and a 5% lower power consumption compared with the OEX module implemented using SDB standard cells. An OEX module implemented using a combination of SDB and MDB standard cells in HDB is 8% smaller in area, 2% slower, has 22% less leakage current, and 1% higher power consumption than an OEX module implemented using MDB standard cells. Therefore, considering cost, area, power consumption, performance, speed, and leakage current, HDB offers superior performance compared to either MDB or SDB standard cells.

[0174] Table 2 Comparison of PPAs for OEX modules implemented by MDB, SDB, and HDB

[0175] MDB vs SDB HDB vs SDB <![CDATA[Area (um 2 )]]> 105％ 97％ Speed ​​(GHz) 108％ 106％ Leakage current (W) 123％ 101％ Power consumption (W / GHz) 94％ 95％

[0176] In other embodiments, this application provides an integrated circuit, such as... Figure 13A As shown, the integrated circuit includes a first standard unit and a second standard unit. The first standard unit is the aforementioned DDB standard unit, and the second standard unit is the SDB standard unit. The DDB standard unit and the SDB standard unit are directly overlapped and spliced ​​together, without the need for one or more CPPs between them.

[0177] Among them, the SDB standard unit is any SDB standard unit in the related technology, and the height of the SDB standard unit is the same as or an integer multiple of the height of the DDB standard unit.

[0178] For example, the SDB standard cell includes two second diffusion breaks 50 arranged parallel to the second grid bar 20, with at least one first grid bar disposed between the two second diffusion breaks 50.

[0179] In the DDB standard cell, the spacer area M1 (second trench isolation area STI2) and the first trench isolation area STI1 are located between the second grid bar 20 and the second diffusion fracture 50. Of course, the second grid bar 20 and the second diffusion fracture 50 are adjacent to each other.

[0180] Similarly, SDB standard cells can be spliced ​​with DDB standard cells that do not include the first splice strip 30. SDB standard cells can also be spliced ​​with DDB standard cells that include the first splice strip 30. In this case, the first splice strip 30 overlaps with the second diffusion fracture 50, regardless of whether the first splice strip 30 is disposed in the same layer as the first grid strip G, or whether the first splice strip 30 extends to the bottom surface of the second trench isolation region STI2 and the first trench isolation region STI1. After the SDB standard cell and the DDB standard cell are spliced, the final structure retained is the same as the structure of the second diffusion fracture 50.

[0181] In this configuration, the second trench isolation region STI2 and the first trench isolation region STI1 are in contact with the side of the second diffusion fracture 50. Therefore, the spacing between adjacent second grid bars 20 and the second diffusion fracture 50 is equal to the spacing between adjacent second grid bars 20 and the first grid bar G. For example, the spacing between the second grid bars 20 and the second diffusion fracture 50, and the spacing between the second grid bars 20 and the first grid bar G, are both CPP.

[0182] like Figure 13B As shown, the SDB standard cell can also be spliced ​​with the DDB standard cell, which includes the second splicing strip 40. In this case, the second splicing strip 40 overlaps with the second diffusion break 50, regardless of whether the second splicing strip 40 is arranged in the same layer as the first grid strip G or extends to the plane where the bottom surface of the first active region A1 is located. After the SDB standard cell and the DDB standard cell are spliced, the final structure retained is the same as the structure of the second diffusion break 50.

[0183] When the DDB standard unit includes the second splicing strip 40, the DDB standard unit may include an extended grid strip G', or the DDB standard unit may not include the extended grid strip G'. Figure 13B The following is an illustration using the DDB standard cell excluding the extended grid bar G'.

[0184] In this configuration, a first spliced ​​active region A1' is provided between the second trench isolation region STI2 and the second diffusion fracture 50, and a second spliced ​​active region A2' is provided between the first trench isolation region STI1 and the second diffusion fracture 50. Therefore, the second grid bar 20 and the second diffusion fracture 50 are spaced two CPPs apart.

[0185] Since the splicing line of the DDB standard cell is located at the end of the interval region M1 (i.e., the second trench isolation region STI2) and the first trench isolation region STI, and the end of the interval region M1 (the second trench isolation region STI2) and the first trench isolation region STI is 1 CPP away from the second grid bar 20. Alternatively, the splicing line of the DDB standard cell is located at the center line of the second splicing bar 40. At the same time, the splicing line of the SDB standard cell is located at the center line of the second diffusion break 50. After the splicing lines of the DDB standard cell and the SDB standard cell coincide and are spliced, the second diffusion break 50 is 1 or more CPP away from the second grid bar 20 of the DDB standard cell, which satisfies the distribution law of the EDA midpoint. Therefore, the splicing of DDB standard cells and SDB standard cells can be realized.

[0186] like Figure 13A As shown, in addition to DDB standard units and SDB standard units, integrated circuits can also include MDB standard units. MDB standard units can be spliced ​​with SDB standard units, and MDB standard units can also be spliced ​​with DDB standard units.

[0187] In some other embodiments, this application provides an integrated circuit, such as... Figure 14A As shown, the integrated circuit includes a first standard unit and a second standard unit. The first standard unit is any of the aforementioned MDB standard units, and the second standard unit is any of the aforementioned DDB standard units.

[0188] The integrated circuit also includes two third diffusion breaks 60 arranged side-by-side, extending along a first direction Y, and the two third diffusion breaks 60 are arranged side-by-side. Along a third direction Z, the third diffusion breaks 60 extend to the bottom surface of the spacer region M1 and the first trench isolation region STI1. The spacer region M1 of the MDB standard cell is located on the side of the third diffusion break 60 facing the second gate strip 20 in the MDB standard cell, and the spacer region M1 of the DDB standard cell is located on the side of another third diffusion break 60 facing the edge gate 20 in the DDB standard cell.

[0189] The integrated circuit also includes a first splicing active region A1”' and a second splicing active region A2”', which are located between two third diffusion fractures 60.

[0190] Regarding formation Figure 14A The method for the integrated circuit shown, in some embodiments, such as Figure 14A As shown, both the MDB standard unit and the DDB standard unit are standard units that do not include the second splicing of 40 lines.

[0191] In this case, for example, neither the MDB standard unit nor the DDB standard unit includes the first splice strip 30, and the MDB standard unit and the DDB standard unit can be spliced ​​together by the first filler standard unit FL1.

[0192] The first filler standard unit FL1 includes, for example, two parallel third diffusion fractures 60, and a first filler active region A1”' and a second filler active region A2”' located between the two third diffusion fractures 60. In this case, the first filler standard unit FL1 can be understood as "filler1" as commonly referred to in the art. After the first filler standard unit FL1 is spliced ​​with the MDB standard unit and the DDB standard unit, the splicing line of the MDB standard unit and the splicing line of the DDB standard unit coincide with the centerline (splicing line) of one of the third diffusion fractures 60, to form Figure 14A The structure shown.

[0193] Of course, the first filler standard unit FL1 used to splice the MDB standard unit and the DDB standard unit may also include at least one redundant strip located between the two third diffusion breaks 60. In this case, the first filler standard unit FL1 can be understood as "filler2", "filler3", "filler4", etc., as commonly referred to in the art.

[0194] Alternatively, for example, both the MDB standard cell and the DDB standard cell include a first splicing strip 30, and the first splicing strip 30 is disposed on the same layer as the first gate strip G. The MDB standard cell and the DDB standard cell can be spliced ​​together using the aforementioned first filling standard cell FL1. During splicing, the first splicing strip 30 and the third diffusion break 60 coincide, and the third diffusion break 60 is retained in the final integrated circuit, compared to... Figure 14A The integrated circuit shown has a first splicing strip 30.

[0195] Alternatively, for example, both the MDB standard cell and the DDB standard cell include a first splice strip 30, and the first splice strip 30 extends to the bottom surface of the spacer region M1 and the first trench isolation region STI1. In this case, the first splice strip 30 can be understood as a diffusion fracture. The MDB standard cell and the DDB standard cell can be spliced ​​together using the aforementioned first filler standard cell FL1. The MDB standard cell and the DDB standard cell can also be spliced ​​together using other filler standard cells that include a first filler active region A1”' and a second filler active region A2”'. The first splice strip 30 (the first splice strip 30 serves as a third diffusion fracture 60) or the third diffusion fracture 60 will ultimately remain at the splice location. The first filler active region A1”' and the second filler active region A2”' are located between the first splice strip 30 of the MDB standard cell and the first splice strip 30 of the DDB standard cell, compared to Figure 14AThe integrated circuit shown has a first splicing strip 30.

[0196] In other embodiments, such as Figure 14B As shown, both the MDB standard unit and the DDB standard unit are standard units that include the second splicing strip 40.

[0197] In this configuration, MDB standard units and DDB standard units are allowed to be directly spliced ​​together via the second splicing strip 40, with the second splicing strips 40 of the MDB standard units and DDB standard units overlapping to form a... Figure 14B The structure shown.

[0198] In another possible scenario, the first standard unit and the second standard unit are standard units of the same type.

[0199] In some embodiments, this application also provides an integrated circuit, such as... Figure 15A As shown, the integrated circuit includes a first standard unit and a second standard unit, both of which are MDB standard units.

[0200] The integrated circuit also includes two third diffusion breaks 60 arranged side-by-side, extending along a first direction Y, and the two third diffusion breaks 60 are arranged side-by-side. Along a third direction Z, the third diffusion breaks 60 extend to the bottom surface of the spacer region M1 and the first trench isolation region STI1. The spacer region M1 of the MDB standard cell is located on the side of the third diffusion break 60 facing the second gate bar 20 in that MDB standard cell, and the spacer region M1 of another MDB standard cell is located on the side of another third diffusion break 60 facing the edge gate 20 in that MDB standard cell.

[0201] The integrated circuit also includes a first splicing active region A1”' and a second splicing active region A2”', which are located between two third diffusion fractures 60.

[0202] Regarding formation Figure 14A The method for the integrated circuit shown, in some embodiments, such as Figure 15A As shown, both the first standard unit and the second standard unit are MDB standard units that do not include the second splicing strip 40.

[0203] In this case, for example, such as Figure 15A As shown, neither of the two MDB standard units includes the first splicing strip 30, and the two MDB standard units can be spliced ​​together using the aforementioned first filling standard unit FL1.

[0204] After the first filling standard unit FL1 is spliced ​​with two MDB standard units, the splicing line of the two MDB standard units coincides with the centerline (splicing line) of a third diffusion fracture 60, to form Figure 15A The structure shown.

[0205] Alternatively, for example, both MDB standard cells include a first splicing strip 30, and the first splicing strip 30 is disposed on the same layer as the first gate strip G. The two MDB standard cells can be spliced ​​together using the aforementioned first filler standard cell FL1. During splicing, the first splicing strip 30 and the third diffusion break 60 coincide, and the final integrated circuit retains the third diffusion break 60, compared to... Figure 15A The integrated circuit shown has a first splicing strip 30.

[0206] Alternatively, for example, both MDB standard cells include a first splice strip 30, and the first splice strip 30 extends to the bottom surface of the spacer region M1 and the first trench isolation region STI1. The two MDB standard cells can be spliced ​​using the aforementioned first filler standard cell FL1. The two MDB standard cells can also be spliced ​​using other filler standard cells FL that include a first filler active region A1”' and a second filler active region A2”'. At the splicing location, the first splice strip 30 (which serves as a third diffusion break 60) or the third diffusion break 60 will ultimately be retained. The first filler active region A1”' and the second filler active region A2”' are located between the first splice strip 30 of the two MDB standard cells, compared to... Figure 15A The integrated circuit shown has a first splicing strip 30.

[0207] In other embodiments, such as Figure 15B As shown, both MDB standard units are standard units that include the second splicing strip 40.

[0208] In this configuration, two MDB standard units are directly spliced ​​together via the second splicing strip 40, with the second splicing strips 40 of the two MDB standard units overlapping to form a... Figure 15B The structure shown.

[0209] In some other embodiments, such as Figure 15C As shown, one MDB standard unit includes a second splice strip 40, while the other MDB standard unit does not include the second splice strip 40.

[0210] For example, the first standard unit includes a second splicing strip 40, while the second standard unit does not include the second splicing strip 40. The centerline of the second splicing strip 40 serves as the splicing line of the first standard unit, and the transition line of the second standard unit serves as the splicing line of the second standard unit. The first and second standard units are directly spliced ​​at the splicing line. The spacing region M1 and the first trench isolation region STI1 of the second standard unit are in contact with the side of the second splicing strip 40 in the first standard unit.

[0211] Of course, in this case, the second standard unit may include the first splicing strip 30, or the second standard unit may not include the first splicing strip 30.

[0212] In other embodiments, this application also provides an integrated circuit, such as... Figure 16 As shown, the integrated circuit includes a first standard unit and a second standard unit, both of which are DDB standard units.

[0213] The structure of the integrated circuit when both the first and second standard units are DDB standard units is similar to that when both the first and second standard units are MDB standard units, except that the MDB standard units are replaced with DDB standard units. In other words, the structures of the second gate strip 20 and the spacer region M1 are simply replaced. Refer to the above description of when both the first and second standard units are MDB standard units; it will not be repeated here.

[0214] Of course, in addition to including two DDB standard units, integrated circuits can also include SDB standard units and MDB standard units. Figure 16 The structure shown is for illustrative purposes only and is not intended to impose any limitations.

[0215] As can be seen from the above description, the integrated circuit provided in the embodiments of this application can be any combination and splicing of the MDB standard unit, DDB standard unit and any SDB standard unit in the related technologies provided in the embodiments of this application.

[0216] In some embodiments, such as Figure 17A and Figure 17B As shown, the integrated circuit includes multiple standard cell rows. Figure 17A and Figure 17B The example of an integrated circuit consisting of two standard cell lines is used to illustrate this.

[0217] Each standard cell row may include at least one of the MDB standard cells, DDB standard cells, and SDB standard cells from any of the related technologies provided in the embodiments of this application.

[0218] In one embodiment, such as Figure 17A As shown, an isolation strip is provided between adjacent standard cell rows, and the first grid strip G between adjacent standard cell rows is separated by the isolation strip.

[0219] Among them, such as Figure 17A As shown, the isolation strip can be a continuous, uninterrupted structure. The isolation strip can also be an intermittent structure; for example, along the second direction X, the isolation strip includes multiple spaced-apart isolation segments.

[0220] In some embodiments, the active regions on both sides of the isolation strip are active regions of the same type. Alternatively, it can be understood that adjacent active regions in adjacent standard cell rows are active regions of the same type.

[0221] For example, such as Figure 17A As shown, both sides of the isolation strip are first active regions A1, and the first active region A1 is a P-type active region. Alternatively, both sides of the isolation strip are second active regions A2, and the second active region A2 is an N-type active region.

[0222] In some embodiments, a standard cell STC in an integrated circuit includes a first active region A1 and a second active region A2, and such a standard cell STC is located in a standard cell row.

[0223] In other embodiments, the standard cell STC in the integrated circuit includes multiple sets of first active regions A1 and second active regions A2, and such standard cell STC spans multiple standard cell rows.

[0224] For example, the border of a standard cell STC can be used to determine whether the standard cell STC is located in one standard cell row or spans multiple standard cell rows.

[0225] In another embodiment, such as Figure 17B As shown, the standard cells in adjacent standard cell rows are spaced apart, and there is a gap between the first grid bars G between adjacent standard cell rows.

[0226] In this case, such as Figure 17B As shown, the first active region A1 and the second active region A2 in the integrated circuit can be arranged alternately, and the first active region A1 and the second active region A2 in the integrated circuit can also be similar to Figure 17A Arranged as shown.

[0227] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A standard unit, characterized in that, include: The first active region and the second active region are disposed side by side on one side of the substrate along the first direction; the first active region and the second active region are N-type active region and P-type active region, respectively. At least one first gate strip, the first gate strip extending along the first direction and located on the side of the first active region and the second active region away from the substrate; Two second gate strips, and at least one first gate strip located between the two second gate strips, the two second gate strips and the at least one first gate strip are arranged at equal intervals along a second direction; the first direction intersects the second direction and is parallel to the substrate; along the second direction, the two ends of the second active region are located on the side of the two second gate strips closer to the substrate; Two interval zones and two first trench isolation zones; Along the second direction, the first active region is located between the two interval regions, the second active region is located between the two first trench isolation regions, and the width of the interval region and the width of the first trench isolation region are equal to the spacing.

2. The standard unit according to claim 1, characterized in that, The second grid bar includes a first barrier grid, a first barrier portion, and a first diffusion fracture; The first barrier portion is located between the first barrier grid and the first diffusion break; Along a direction perpendicular to the substrate, the first diffusion fracture extends to the bottom surface of the first active region near the substrate, and the first barrier gate is located on the side of the second active region away from the substrate.

3. The standard unit according to claim 1, characterized in that, The interval region is the same type of active region as the first active region.

4. The standard unit according to claim 1, characterized in that, The second gate strip is located on the side of the first active region and the second active region away from the substrate; the spacer region is the second trench isolation region.

5. The standard unit according to any one of claims 1-4, characterized in that, The standard unit also includes two first splicing strips; Along the second direction, the two second grid strips are located between the two first splicing strips, and the distance between the first splicing strips and the second grid strips is equal to the spacing.

6. The standard unit according to claim 5, characterized in that, The first splicing strip is disposed in the same layer as the first grid strip; or; Along a direction perpendicular to the substrate, the first splice strip extends to the spacer area and the first trench isolation area near the bottom surface of the substrate.

7. The standard unit according to any one of claims 1-4, characterized in that, The standard unit also includes two second splicing strips; Along the second direction, the two second gate strips are located between the two second splicing strips; along the direction perpendicular to the substrate, the second splicing strips extend to the bottom surface of the first active region and the second active region near the substrate.

8. The standard unit according to claim 7, characterized in that, The standard unit also includes two first extended active regions and two second extended active regions located on the side of the second splicing strip facing the second grid strip; Along the second direction, the two interval regions are located between the two first extended active regions, and the two first trench isolation regions are located between the two second extended active regions; the first extended active region and the first active region are active regions of the same type, and the second extended active region and the second active region are active regions of the same type.

9. The standard unit according to claim 7, characterized in that, The standard unit also includes multiple extended grid strips located between the second splicing strips on the side facing the second grid strip.

10. The standard unit according to claim 9, characterized in that, The standard unit further includes two first splicing strips; along the second direction, the two second grid strips are located between the two first splicing strips; along the second direction, the second splicing strips, the extended grid strips, the first splicing strips, the second grid strips, and the first grid strips are arranged at equal intervals.

11. The standard unit according to any one of claims 1-4, characterized in that, The standard unit also includes a grid connection hole, which communicates with the first grid bar.

12. An integrated circuit, characterized in that, It includes a first standard unit and a second standard unit, the first standard unit and the second standard unit being arranged side by side along the direction intersecting with the first grid bar; the first standard unit is the standard unit according to any one of claims 1-11, and / or, the second standard unit is the standard unit according to any one of claims 1-11.

13. The integrated circuit according to claim 12, characterized in that, The second standard unit is a single diffusion fracture standard unit; the single diffusion fracture standard unit includes two second diffusion fractures arranged parallel to the second grid bar; the interval region and the first trench isolation region are located between the adjacent second grid bar and the second diffusion fracture.

14. The integrated circuit according to claim 13, characterized in that, The interval region and the first trench isolation region are in contact with the side of the second diffusion fracture.

15. The integrated circuit according to claim 13, characterized in that, A first extended active region is provided between the second diffusion fracture and the interval region, and a second extended active region is provided between the second diffusion fracture and the first trench isolation region.

16. The integrated circuit according to claim 12, characterized in that, The integrated circuit includes two third diffusion breaks parallel to the first gate strip, the third diffusion breaks extending to the bottom surface of the first active region near the substrate; the spacing region of the first standard cell is disposed on the side of the third diffusion break facing the second gate strip, and the spacing region of the second standard cell is disposed on the side of the other third diffusion break facing the edge gate. The integrated circuit further includes a first splicing active region and a second splicing active region, which are located between the two third diffusion fractures.

17. The integrated circuit according to claim 12, characterized in that, The first standard unit and the second standard unit both include a second splicing strip; The second splicing strip of the first standard unit coincides with the second splicing strip of the second standard unit.

18. The integrated circuit according to claim 12, characterized in that, The first standard unit includes a second splicing strip; The spacing area and the first groove fracture area of ​​the second standard unit are in contact with the side of the second splicing strip.

19. The integrated circuit according to claim 17 or 18, characterized in that, The first standard unit and the second standard unit have the same structure; or, The second gate bar of the first standard cell includes a first barrier gate, a first barrier portion and a first diffusion break, and the second gate bar of the second standard cell is located on the side of the first active region and the second active region away from the substrate.

20. The integrated circuit according to any one of claims 12-18, characterized in that, The integrated circuit includes multiple standard cell rows, and each standard cell row is provided with at least one first standard cell and / or the second standard cell.

21. An electronic device, characterized in that, It includes a circuit board and an integrated circuit, wherein the integrated circuit is the integrated circuit according to any one of claims 12-20.

22. A standard unit library, characterized in that, It includes multiple standard units, including the standard unit as described in any one of claims 1-11 and the single diffusion fracture standard unit.

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