Pixel Circuit, Display Panel, and Driving Method of Pixel Circuit

Abstract

Embodiments of the present application provide a pixel circuit, a display panel, and a driving method for the pixel circuit, which relate to the field of display technologies. The pixel circuit includes a driving module, the driving module and a light-emitting element are connected in series between a first power supply voltage signal line and a second power supply voltage signal line, and the driving module is configured to drive the light-emitting element to emit light; a bias reset module, a first end of the bias reset module is electrically connected to a first end of the driving module, and a second end of the bias reset module is electrically connected to a first reference voltage signal line; the bias reset module is configured to transmit a first reference voltage signal provided by the first reference voltage signal line to the first end of the driving module during a bias reset phase. According to the embodiments of the present application, the ghosting problem of the display panel can be fully improved, thereby effectively enhancing the display effect and service performance of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display technology, and particularly relates to a pixel circuit, a display panel, and a driving method for the pixel circuit. Background Art

[0002] With the rapid development of display technology, full-screen display has become the development trend of mobile display devices such as mobile phones. Flat panel display devices based on technologies such as Organic Light Emitting Display (OLED) and Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptop computers, and desktop computers due to their advantages of high image quality, power saving, thin body, and wide application range, and have become the mainstream in display devices. However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0003] Embodiments of this application provide a pixel circuit, a display panel, and a driving method for the pixel circuit, which can fully improve the ghosting problem of the display panel, thereby effectively improving the display effect and performance of the display panel.

[0004] In a first aspect, embodiments of this application provide a pixel circuit, which includes:

[0005] A driving module, the driving module and a light-emitting element are connected in series between a first power supply voltage signal line and a second power supply voltage signal line, and the driving module is used to drive the light-emitting element to emit light;

[0006] A bias reset module, a first end of the bias reset module is electrically connected to a first end of the driving module, and a second end of the bias reset module is electrically connected to a first reference voltage signal line;

[0007] The bias reset module is used to transmit a first reference voltage signal provided by the first reference voltage signal line to the first end of the driving module during a bias reset stage.

[0008] According to an embodiment of the first aspect of this application, the pixel circuit further includes a first initialization module, a control end of the first initialization module is electrically connected to a first scan signal line, a first end of the first initialization module is electrically connected to a control end of the driving module, and a second end of the first initialization module is electrically connected to a second reference voltage signal line; the first initialization module is used to transmit a second reference voltage signal provided by the second reference voltage signal line to the control end of the driving module during a first initialization stage.

[0009] According to an embodiment of the first aspect of this application, the voltage value of the first reference voltage signal is less than or equal to the voltage value of the second reference voltage signal.

[0010] According to an embodiment of the first aspect of the present application, at least part of the time period of the first initialization stage is within the bias reset stage.

[0011] According to an embodiment of the first aspect of the present application, the entire time period of the first initialization stage is within the bias reset stage.

[0012] According to an embodiment of the first aspect of the present application, the duration of the bias reset stage is greater than the duration of the first initialization stage.

[0013] According to an embodiment of the first aspect of the present application, the pixel circuit further includes a storage module. The first end of the storage module is electrically connected to the first power supply voltage signal line, and the second end of the storage module is electrically connected to the control end of the driving module.

[0014] According to an embodiment of the first aspect of the present application, the pixel circuit further includes a data writing module. The control end of the data writing module is electrically connected to the second scanning signal line, the first end of the data writing module is electrically connected to the data signal line, and the second end of the data writing module is electrically connected to the first end of the driving module; the data writing module is configured to transmit the data voltage provided by the data signal line to the first end of the driving module during the data writing stage; wherein, the bias reset stage is outside the time range of the data writing stage.

[0015] According to an embodiment of the first aspect of the present application, the bias reset stage is within the non-emitting stage and outside the time range of the data writing stage.

[0016] According to an embodiment of the first aspect of the present application, the first control end of the bias reset module is electrically connected to the first control signal line, and the second control end of the bias reset module is electrically connected to the second control signal line.

[0017] According to an embodiment of the first aspect of the present application, one of the first control end and the second control end provides a conducting level to the bias reset module during the time period other than the data writing stage; the other of the first control end and the second control end provides a conducting level to the bias reset module during the non-emitting stage; when the first control end and the second control end provide a conducting level to the bias reset module, the bias reset module transmits the first reference voltage signal to the first end of the driving module.

[0018] According to an embodiment of the first aspect of the present application, the pixel circuit further includes a data writing module, a first light emission control module, and / or a second light emission control module; a control end of the first light emission control module is electrically connected to a light emission control signal line, a first end of the first light emission control module is electrically connected to a first power supply voltage signal line, and a second end of the first light emission control module is electrically connected to a first end of the driving module; a control end of the second light emission control module is electrically connected to the light emission control signal line, a first end of the second light emission control module is electrically connected to a second end of the driving module, and a second end of the second light emission control module is electrically connected to a first electrode of the light emitting element; a second electrode of the light emitting element is electrically connected to a second power supply voltage signal line; wherein, one of the first control signal line and the second control signal line multiplexes a second scanning signal line, and the other of the first control signal line and the second control signal line multiplexes the light emission control signal line.

[0019] According to an embodiment of the first aspect of the present application, within one display frame, the light emission control signal includes a plurality of pulse signals, and within one display frame, the bias reset module is turned on multiple times.

[0020] According to an embodiment of the first aspect of the present application, the bias reset module includes a first switch sub-module and a second switch sub-module; a control end of the first switch sub-module is electrically connected to the first control signal line, and a first end of the first switch sub-module is electrically connected to a first end of the driving module; a control end of the second switch sub-module is electrically connected to the second control signal line, a first end of the second switch sub-module is electrically connected to a second end of the first switch sub-module, and a second end of the second switch sub-module is electrically connected to a first reference voltage signal line.

[0021] According to an embodiment of the first aspect of the present application, the first switch sub-module includes a first transistor, and the second switch sub-module includes a second transistor; the channel types of the first transistor and the second transistor are the same or opposite.

[0022] According to an embodiment of the first aspect of the present application, the data writing module includes a third transistor, the first control signal line multiplexes the second scanning signal line, and the channel type of the first transistor is opposite to that of the third transistor; or, the second control signal line multiplexes the second scanning signal line, and the channel type of the second transistor is opposite to that of the third transistor.

[0023] According to an embodiment of the first aspect of the present application, the third transistor is a P-type transistor.

[0024] According to an embodiment of the first aspect of the present application, the first light-emitting control module includes a fourth transistor, the first control signal line multiplexes the light-emitting control signal line, and the channel types of the first transistor and the fourth transistor are opposite; alternatively, the second control signal line multiplexes the light-emitting control signal line, and the channel types of the second transistor and the fourth transistor are opposite; and / or, the second light-emitting control module includes a fifth transistor; the first control signal line multiplexes the light-emitting control signal line, and the channel types of the first transistor and the fifth transistor are opposite; alternatively, the second control signal line multiplexes the light-emitting control signal line, and the channel types of the second transistor and the fifth transistor are opposite.

[0025] According to an embodiment of the first aspect of the present application, the fourth transistor is a P-type transistor; and / or, the fifth transistor is a P-type transistor.

[0026] According to an embodiment of the first aspect of the present application, the first transistor is an N-type transistor; the second transistor is an N-type transistor.

[0027] According to an embodiment of the first aspect of the present application, the channel types of the third transistor, the fourth transistor, and the fifth transistor are the same.

[0028] According to an embodiment of the first aspect of the present application, the pixel circuit further includes a second initialization module; the control end of the second initialization module is electrically connected to the third scan signal line, the first end of the second initialization module is electrically connected to the first electrode of the light-emitting element, and the second end of the second initialization module is electrically connected to the third reference voltage signal line.

[0029] The second initialization module is configured to transmit the third reference voltage signal provided by the third reference voltage signal line to the first electrode of the light-emitting element during the second initialization stage; wherein, the duration of the second initialization stage is greater than the second preset duration.

[0030] According to an embodiment of the first aspect of the present application, the second initialization stage coincides with the non-light-emitting stage.

[0031] According to an embodiment of the first aspect of the present application, the pixel circuit further includes a first light-emitting control module and / or a second light-emitting control module; the control end of the first light-emitting control module is electrically connected to the light-emitting control signal line, the first end of the first light-emitting control module is electrically connected to the first power supply voltage signal line, and the second end of the first light-emitting control module is electrically connected to the first end of the driving module; the control end of the second light-emitting control module is electrically connected to the light-emitting control signal line, the first end of the second light-emitting control module is electrically connected to the second end of the driving module, and the second end of the second light-emitting control module is electrically connected to the first electrode of the light-emitting element; the third scan signal line multiplexes the light-emitting control signal line.

[0032] According to an embodiment of the first aspect of the present application, the second initialization module includes a sixth transistor, and the channel type of the sixth transistor is a first type of channel type; the first light emission control module includes a fourth transistor, and / or the second light emission control module includes a fifth transistor; the channel types of the fourth transistor and / or the fifth transistor are both a second type of channel type; the first type of channel type and the second type of channel type are opposite.

[0033] According to an embodiment of the first aspect of the present application, the bias reset module includes a first switch sub-module and a second switch sub-module;

[0034] The control end of the first switch sub-module is electrically connected to the first control signal line, and the first end of the first switch sub-module is electrically connected to the first end of the driving module;

[0035] The control end of the second switch sub-module is electrically connected to the second control signal line, the first end of the second switch sub-module is electrically connected to the second end of the first switch sub-module, and the second end of the second switch sub-module is electrically connected to the first reference voltage signal line;

[0036] According to an embodiment of the first aspect of the present application, the pixel circuit further includes a data writing module and / or a threshold compensation module. The control end of the data writing module is electrically connected to the second scanning signal line, the first end of the data writing module is electrically connected to the data signal line, and the second end of the data writing module is electrically connected to the first end of the driving module; the control end of the threshold compensation module is electrically connected to the fourth scanning signal line, the first end of the threshold compensation module is electrically connected to the second end of the driving module, and the second end of the threshold compensation module is electrically connected to the control end of the driving module;

[0037] According to an embodiment of the first aspect of the present application, the pixel circuit further includes a light emission control module;

[0038] The control end of the light emission control module is electrically connected to the light emission control signal line. The light emission control module, the driving module, and the light emitting element are connected in series between the first power supply voltage signal line and the second power supply voltage signal line.

[0039] According to an embodiment of the first aspect of the present application, one of the first control signal line and the second control signal line multiplexes the second scanning signal line or the fourth scanning signal line, and the other of the first control signal line and the second control signal line multiplexes the light emission control signal line;

[0040] According to an embodiment of the first aspect of the present application, the switching state of one of the first switch sub-module and the second switch sub-module is opposite to that of the data writing module and / or the threshold compensation module; the switching state of the other of the first switch sub-module and the second switch sub-module is opposite to that of the light emission control module.

[0041] According to an embodiment of the first aspect of the present application, the fourth scanning signal line multiplexes the second scanning signal line.

[0042] In a second aspect, an embodiment of the present application provides a display panel, which includes a pixel circuit provided in any of the foregoing embodiments of the first aspect of the present application.

[0043] According to an embodiment of the second aspect of the present application, a display frame of the display panel includes a data writing frame and a holding frame; when the display frame of the display panel is a data writing frame, a bias reset module in the pixel circuit is turned on in a non-light emitting stage other than the data writing stage, and a first reference voltage signal provided by a first reference voltage signal line is transmitted to a first end of the driving module; when the display frame of the display panel is a holding frame, the bias reset module in the pixel circuit is turned on in the non-light emitting stage, and the first reference voltage signal is transmitted to the first end of the driving module.

[0044] In a third aspect, an embodiment of the present application provides a driving method for a pixel circuit. The pixel circuit includes: a driving module, a first end of the driving module is electrically connected to a first power supply voltage signal line, a second end of the driving module is electrically connected to a first electrode of a light emitting element, and the driving module is configured to drive the light emitting element to emit light; a bias reset module, a first end of the bias reset module is electrically connected to the first end of the driving module, and a second end of the bias reset module is electrically connected to a first reference voltage signal line.

[0045] The driving method for the pixel circuit includes: in a bias reset stage, controlling the bias reset module to be turned on to transmit a first reference voltage signal provided by the first reference voltage signal line to the first end of the driving module.

[0046] In a fourth aspect, an embodiment of the present application provides a display device, which includes a display panel provided in any of the foregoing embodiments of the second aspect of the present application.

[0047] As can be seen from the above description, a pixel circuit, a display panel, and a driving method for a pixel circuit provided by an embodiment of the present application. In the pixel circuit, the driving module is configured to drive the light emitting element to emit light, and the bias reset module can be configured to transmit a first reference voltage signal provided by the first reference voltage signal line to the first end of the driving module in a bias reset stage. Compared with the prior art, in the embodiment of the present application, by setting the above-mentioned bias reset module, the first reference voltage signal provided by the first reference voltage signal line is transmitted to the first end of the driving module in the bias reset stage, so that the bias state of the driving module can be fully adjusted, and the threshold voltage shift of the driving module can be effectively alleviated or offset. A pixel circuit, a display panel, and a driving method for a pixel circuit according to an embodiment of the present application can fully improve the afterimage problem of the display panel, thereby effectively improving the display effect and service performance of the display panel. Description of the Drawings

[0048] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0049] Figure 1 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application;

[0050] Figure 2 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application;

[0051] Figure 3 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application;

[0052] Figure 4 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application;

[0053] Figure 5 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application;

[0054] Figure 6 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application;

[0055] Figure 7 It is a schematic timing diagram of a pixel circuit provided by an embodiment of the present application;

[0056] Figure 8 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application;

[0057] Figure 9 It is a schematic timing diagram of yet another pixel circuit provided by an embodiment of the present application;

[0058] Figure 10 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application;

[0059] Figure 11 It is a schematic timing diagram of yet another pixel circuit provided by an embodiment of the present application;

[0060] Figure 12 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application;

[0061] Figure 13 It is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0062] Figure 14 It is a schematic flow diagram of a driving method for a pixel circuit provided by an embodiment of the present application;

[0063] Figure 15 This is a schematic structural diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0064] The features of various aspects of the present application and exemplary embodiments will be described in detail below. To make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0065] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0066] It should be understood that the term "and / or" used herein is only an associative relationship describing associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0067] It should be noted that the transistor in the embodiments of the present application can be an N-type transistor or a P-type transistor. For an N-type transistor, the conduction level is a high level and the cut-off level is a low level. That is, when the gate of the N-type transistor is at a high level, the first and second poles thereof are conducting; when the gate of the N-type transistor is at a low level, the first and second poles thereof are turned off. For a P-type transistor, the conduction level is a low level and the cut-off level is a high level. That is, when the control electrode of the P-type transistor is at a low level, the first and second poles thereof are conducting; when the control terminal of the P-type transistor is at a high level, the first and second poles thereof are turned off. In specific implementation, the gate of each of the above transistors serves as its control electrode, and, according to the signal of the gate of each transistor and its type, its first pole can be used as the source electrode and the second pole as the drain electrode, or its first pole can be used as the drain electrode and the second pole as the source electrode, without distinction here. In addition, the conduction level and the cut-off level in the embodiments of the present invention are general terms. The conduction level refers to any level that can make the transistor conduct, and the cut-off level refers to any level that can make the transistor cut off / turn off.

[0068] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected, or that two components are electrically connected via one or more other components.

[0069] In the embodiments of the present application, the first node, the second node, and the third node are only defined for facilitating the description of the circuit structure, and the first node, the second node, and the third node are not an actual circuit unit.

[0070] Without departing from the spirit or scope of the present application, various modifications and variations can be made in the present application, which are obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and variations of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0071] Before elaborating on the technical solutions provided in the embodiments of the present application, for the convenience of understanding the embodiments of the present application, the present application first specifically describes the problems existing in the related technologies:

[0072] As described above, the inventors of the present application have found that with the development of display technology, the market's requirements for the panel performance of display panels are also getting higher and higher. For example, in the existing AMOLED (Active-matrix organic light emitting diode) screen using LTPS (Low Temperature Poly-silicon) TFT (Thin Film Transistor), during the display of a black-and-white picture and then switching to a grayscale picture, display traces of the black-and-white picture, that is, afterimages, can be seen, mainly due to the hysteresis voltage of the TFT.

[0073] After further research by the inventors of the present application, it is found that the current solution to the afterimage phenomenon of the above display panel is mainly to improve it through panel processes, but there are problems such as poor process repeatability and batch fluctuations, and the afterimage problem existing during the display operation of the display panel cannot be fundamentally solved.

[0074] To solve the problem of abnormal conditions such as afterimages occurring during the display operation of the display panel, an embodiment of the present application provides a pixel circuit, a display panel, and a driving method for the pixel circuit. First, the pixel circuit provided by the embodiment of the present application will be introduced below.

[0075] Figure 1 A schematic structural diagram of a pixel circuit provided by an embodiment of the present application is shown. As Figure 1 shown, a pixel circuit 10 provided by an embodiment of the present application includes a driving module 101 and a bias reset module 102.

[0076] Specifically, the first end of the driving module 101 is electrically connected to the first power supply voltage signal line VDD, and the second end of the driving module 101 is electrically connected to the first electrode of the light-emitting element D. The driving module 101 is used to drive the light-emitting element D to emit light.

[0077] The first end of the bias reset module 102 is electrically connected to the first end of the driving module 101, and the second end of the bias reset module 102 is electrically connected to the first reference voltage signal line Vref1.

[0078] This bias reset module 102 is used to transmit the first reference voltage signal provided by the first reference voltage signal line Vref1 to the first end of the driving module 101 during the bias reset stage.

[0079] As can be seen from the above description, a pixel circuit 10 provided by an embodiment of the present application. In the pixel circuit 10, a driving module 101 is used to drive a light-emitting element D to emit light, and a bias reset module 102 can be used to transmit a first reference voltage signal provided by a first reference voltage signal line Vref1 to a first end of the driving module 101 during a bias reset stage. Compared with the prior art, in this embodiment, by setting the above-mentioned bias reset module 102 to transmit the first reference voltage signal provided by the first reference voltage signal line Vref1 to the first end of the driving module 101 during the bias reset stage, the bias state of the driving module 101 can be fully adjusted, thereby being able to alleviate or offset the threshold voltage shift of the driving module. Overall, a pixel circuit 10 of an embodiment of the present application can fully improve the afterimage problem of the display panel, thereby effectively improving the display effect and service performance of the display panel.

[0080] Please refer to the following Figure 2 , Figure 2 which is a schematic structural diagram of another pixel circuit 10 provided by an embodiment of the present application. As Figure 2 shown, according to some embodiments of the present application, optionally, the pixel circuit 10 may further include a storage module 103. A first end of the storage module 103 is electrically connected to a first power supply voltage signal line VDD, and a second end of the storage module 103 is electrically connected to a control end of the driving module 101.

[0081] Optionally, the pixel circuit 10 may further include a first initialization module 104.

[0082] A control end of the first initialization module 104 is electrically connected to a first scan signal line S1, a first end of the first initialization module 104 is electrically connected to a control end of the driving module 101, and a second end of the first initialization module 104 is electrically connected to a second reference voltage signal line Vref2.

[0083] During a first initialization stage, the first initialization module 104 is turned on under the control of the first scan signal line S1, and transmits a second reference voltage signal provided by the second reference voltage signal line Vref2 to the control end of the driving module 101.

[0084] In some embodiments, optionally, in order to more fully improve the afterimage phenomenon existing in the display panel to improve the display effect of the display panel, a voltage value of the first reference voltage signal is less than or equal to a voltage value of this second reference voltage signal.

[0085] In this way, by setting the voltage value of the first reference voltage signal for bias reset to be less than or equal to the voltage value of the second reference voltage signal for initializing the control end of the driving module 101, the driving module 101 can more effectively reduce its hysteresis phenomenon, and thus the afterimage can be fully improved.

[0086] According to some embodiments of the present application, optionally, considering the actual working scenario of the pixel circuit, at least part of the time period of the above-mentioned first initialization stage is in the bias reset stage.

[0087] According to some embodiments of the present application, optionally, in order to more effectively alleviate or offset the threshold voltage offset phenomenon of the driving module 101, so as to further improve the afterimage problem of the display panel, the above-mentioned bias reset stage may include the first initialization stage, that is, all time periods of the first initialization stage are within the bias reset stage.

[0088] According to some embodiments of the present application, optionally, the duration of the above-mentioned bias reset stage is greater than the duration of the first initialization stage. In this embodiment, the bias reset time of the bias adjustment module 102 for the first end of the driving module 101 is set longer to more fully realize the adjustment of the bias state of the driving module 101.

[0089] Please refer to the following Figure 3 , Figure 3 which is a schematic structural diagram of another pixel circuit 10 provided by an embodiment of the present application. As Figure 3 shown, according to some embodiments of the present application, optionally, the pixel circuit 10 may further include a data writing module 105.

[0090] The control end of the data writing module 105 is electrically connected to the second scanning signal line S2, the first end of the data writing module 105 is electrically connected to the data signal line VDATA, and the second end of the data writing module 105 is electrically connected to the driving module 101.

[0091] Specifically, when connecting, the control end of the above-mentioned data writing module 105 is electrically connected to the second scanning signal line S2, the first end of the data writing module 105 is electrically connected to the data signal line VDATA, and the second end of the data writing module 105 is electrically connected to the first end of the driving module 101.

[0092] This data writing module 105 is used to transmit the data voltage provided by the data signal line VDATA to the first end of the driving module 101 during the data writing stage.

[0093] Specifically, the data writing module 105 is turned on under the control of the second scanning signal line S2 during the data writing stage, and the data writing module 105 in the on state transmits the data voltage provided by the data signal line VDATA to the first end of the driving module 101. Among them, in order to ensure the reasonable and normal operation of the pixel circuit 10, the bias reset stage is outside the time range of the data writing stage. The bias reset stage does not overlap with the data writing stage.

[0094] In some more specific embodiments, in order to more fully and thoroughly adjust the bias state of the driving module 101, the above-mentioned bias reset stage is within the non-emitting stage and outside the time range of the data writing stage.

[0095] According to some embodiments of the present application, optionally, in order to achieve reasonable conduction control of the above-mentioned bias reset module 102, the bias reset module 102 may include two control terminals: a first control terminal and a second control terminal. The first control terminal of the bias reset module 102 is electrically connected to the first control signal line EN1, and the second control terminal of the bias reset module 102 is electrically connected to the second control signal line EN2.

[0096] Optionally, one of the above-mentioned first control terminal and second control terminal provides a conduction level to the bias reset module 102 during a period other than the data writing stage. The other of the first control terminal and the second control terminal provides a conduction level to the bias reset module 102 during the non-emitting stage.

[0097] When the first control terminal and the second control terminal provide a conduction level to the bias reset module 102, the bias reset module 102 transmits the first reference voltage signal to the first end of the driving module 101. Please refer to the following Figure 4 , Figure 4 which is a schematic structural diagram of another pixel circuit provided by the embodiments of the present application. As Figure 4 shown, according to some embodiments of the present application, optionally, the pixel circuit 10 may further include a first light emission control module 106 and / or a second light emission control module 107.

[0098] The control terminal of the above-mentioned first light emission control module 106 is electrically connected to the light emission control signal line EM, the first end of the first light emission control module 106 is electrically connected to the first power supply voltage signal line VDD, and the second end of the first light emission control module 106 is electrically connected to the first end of the driving module 101.

[0099] The control terminal of the above-mentioned second light emission control module 107 is electrically connected to the light emission control signal line EM, the first end of the second light emission control module 107 is electrically connected to the second end of the driving module 101, and the second end of the second light emission control module 107 is electrically connected to the first electrode of the light emitting element D. The first electrode of the light emitting element D may be, for example, the anode of the light emitting element D. The second electrode of the light emitting element D is electrically connected to the second power supply voltage signal line VSS.

[0100] Among them, one of the first control signal line EN1 and the second control signal line EN2 may multiplex the second scan signal line S2, and the other of the first control signal line EN1 and the second control signal line EN2 may multiplex the light emission control signal line EM.

[0101] Thus, the above-mentioned bias reset stage may specifically include a non-emitting stage outside the data writing stage, more fully and thoroughly realizing the adjustment of the bias state of the driving module 101, thereby being more conducive to improving the ghosting problem of the display panel and further enhancing the display effect of the display panel.

[0102] Next, please continue to refer to Figure 4 , according to some embodiments of the present application, optionally, the bias reset module 102 may include a first switch sub-module and a second switch sub-module.

[0103] The control end of the first switch sub-module is electrically connected to the first control signal line EN1, and the first end of the first switch sub-module is electrically connected to the first end of the driving module 101. The control end of the second switch sub-module is electrically connected to the second control signal line EN2, the first end of the second switch sub-module is electrically connected to the second end of the first switch sub-module, and the second end of the second switch sub-module is electrically connected to the first reference voltage signal line Vref1.

[0104] Optionally, the pixel circuit further includes a light emission control module; the control end of the light emission control module is electrically connected to the light emission control signal line, and the light emission control module, the driving module, and the light emitting element are connected in series between the first power supply voltage signal line and the second power supply voltage signal line.

[0105] Optionally, one of the first control signal line and the second control signal line multiplexes the second scan signal line, and the other of the first control signal line and the second control signal line multiplexes the light emission control signal line.

[0106] Optionally, the light emission control module may include a first light emission control module 106 and / or a second light emission control module 107.

[0107] According to some embodiments of the present application, optionally, the first switch sub-module may specifically include a first transistor M8, and the second switch sub-module may specifically include a second transistor M9. Optionally, the channel types of the first transistor M8 and the second transistor M9 are the same or opposite.

[0108] According to some embodiments of the present application, optionally, the above-mentioned data writing module 105 may include a third transistor M2. The first control signal line EN1 multiplexes the second scan signal line S2, and the channel type of the first transistor M8 is opposite to that of the third transistor M2. Alternatively, the second control signal line EN2 multiplexes the second scan signal line S2, and the channel type of the second transistor M9 is opposite to that of the third transistor M2.

[0109] Optionally, the above-mentioned third transistor M2 may be a P-type transistor or an N-type transistor.

[0110] Optionally, the above-mentioned first light-emitting control module 106 may include a fourth transistor M5, the first control signal line EN1 multiplexes the light-emitting control signal line EM, and the channel type of the first transistor M8 is opposite to that of the fourth transistor M5. Alternatively, the second control signal line EN2 multiplexes the light-emitting control signal line EM, and the channel type of the second transistor M9 is opposite to that of the fourth transistor M5.

[0111] And / or, the second light-emitting control module 107 may include a fifth transistor M6; the first control signal line EN1 multiplexes the light-emitting control signal line EM, and the channel type of the first transistor M8 is opposite to that of the fifth transistor M6. Alternatively, the second control signal line EN2 multiplexes the light-emitting control signal line EM, and the channel type of the second transistor M9 is opposite to that of the fifth transistor M6.

[0112] According to some embodiments of the present application, optionally, the above-mentioned fourth transistor M5 is a P-type transistor; and / or, the above-mentioned fifth transistor M6 is a P-type transistor.

[0113] According to some embodiments of the present application, optionally, the first transistor M8 is an N-type transistor; the second transistor M9 is an N-type transistor.

[0114] According to some embodiments of the present application, optionally, the channel types of the third transistor M2, the fourth transistor M5, and the fifth transistor M6 are the same.

[0115] However, it should be added that in some other embodiments, the above-mentioned first transistor M8 may also be a P-type transistor; the second transistor M9 is a P-type transistor. The channel types of the above-mentioned third transistor M2, fourth transistor M5, and fifth transistor M6 are the same, and the third transistor M2, fourth transistor M5, and fifth transistor M6 are all N-type transistors. Alternatively, in some embodiments, the channel types of the above-mentioned first transistor M8 and second transistor M9 may also be opposite, and correspondingly, the channel type of the third transistor M2 is opposite to the channel type of the fourth transistor M5 and / or the fifth transistor M6, etc. The third transistor M2 can be a P-type transistor or an N-type transistor.

[0116] Overall, in this embodiment, the specific channel types of the above-mentioned transistors can be flexibly set and adjusted according to the actual circuit requirements, as long as it is ensured that the above-mentioned first transistor M8 and / or second transistor M9 can multiplex the signal lines of the above-mentioned light-emitting control signal line and / or the second scan signal line S2. This embodiment does not make strict restrictions here.

[0117] Please refer to the following Figure 5 , Figure 5 which is a schematic structural diagram of another pixel circuit 10 provided by the embodiment of the present application. As Figure 5As shown, according to some embodiments of the present application, more specifically, in order to further improve the performance of the display panel, the above-mentioned pixel circuit 10 may further include a second initialization module 108.

[0118] When specifically connected, the control end of the second initialization module 108 is electrically connected to the third scan signal line S3, the first end of the second initialization module 108 is electrically connected to the first electrode of the light-emitting element D, and the second end of the second initialization module 108 is electrically connected to the third reference voltage signal line Vref3.

[0119] The above-mentioned second initialization module 108 can be used to conduct under the control of the third scan signal line S3 during the second initialization stage, and transmit the third reference voltage signal provided by the third reference voltage signal line Vref3 to the first electrode of the light-emitting element D.

[0120] In some specific embodiments, the duration of the second initialization stage is greater than the duration of the first initialization stage, and the first initialization stage is within the second initialization stage.

[0121] In some embodiments, the duration of the second initialization stage can be greater than the duration of the data writing stage, and the data writing stage can be within the second initialization stage.

[0122] In this way, the reset duration of the first electrode of the light-emitting element D can be increased, so that the reset is more sufficient, which is beneficial to effectively ensuring the full release of the electrical stress of the light-emitting element D, and then the luminous life of the light-emitting element D in the display panel can be improved.

[0123] In some more specific embodiments, in order to more fully initialize the first electrode of the light-emitting element D, the second initialization stage can coincide with the non-light-emitting stage.

[0124] In other words, in this embodiment, the reset time of the light-emitting element D is increased to the greatest extent to more fully ensure the full initialization of the first electrode of the light-emitting element D, so as to ensure the full release of the electrical stress of the light-emitting element D, and then help to improve its luminous life.

[0125] According to some embodiments of the present application, in order to effectively improve the utilization rate of the signal line, the above-mentioned third scan signal line S3 can be multiplexed with the light emission control signal line EM.

[0126] Please refer to the following Figure 6 , Figure 6 which is a schematic structural diagram of another pixel circuit provided by the embodiment of the present application. As Figure 6As shown, in some more specific embodiments, the second initialization module 108 may include a sixth transistor M7. The channel type of the sixth transistor M7 is a first type of channel type. For example, the first type of channel type may be an N-channel type, that is, the sixth transistor may be an N-type thin film transistor.

[0127] The pixel circuit 10 may further include a first light emission control module 106 and / or a second light emission control module 107. The first light emission control module 106 may include a fourth transistor M5, and / or the second light emission control module 107 may include a fifth transistor M6. The channel types of the fourth transistor M5 and / or the fifth transistor M6 are both a second type of channel type; the first type of channel type and the second type of channel type are opposite.

[0128] Exemplarily, in the case where the sixth transistor is an N-type thin film transistor, the second type of channel type may be a P-channel type, that is, the fourth transistor M5 and the fifth transistor M6 are P-type thin film transistors.

[0129] In this way, in this embodiment, by setting the transistor channel type included in the second initialization module 108 to be different from that of the first light emission control module 106 and / or the second light emission control module 107, it is possible to multiplex the light emission control signal line as the third scan signal line S3, so that in the non-light emission stage, the first light emission control module 106 and / or the second light emission control module 107 are turned off under the control of the light emission control signal line EM, and at the same time, the second initialization module 108 is turned on under the control of the light emission control signal line EM, realizing sufficient initialization of the first electrode of the light emitting element D.

[0130] Please continue to refer to Figure 6 as Figure 6 shown. According to some embodiments of the present application, optionally, the pixel circuit 10 may further include a threshold compensation module 109.

[0131] When specifically connected, the control end of the threshold compensation module 109 is electrically connected to the fourth scan signal line S4, the first end of the threshold compensation module 109 is electrically connected to the second end of the driving module 101, and the second end of the threshold compensation module 109 is electrically connected to the control end of the driving module 101.

[0132] Optionally, the threshold compensation module 109 is used to perform threshold compensation on the driving module during the threshold compensation stage. The threshold compensation stage may overlap with the data writing stage, for example, coincide.

[0133] Optionally, the switch states of the data writing module and the threshold compensation module are the same.

[0134] Optionally, the threshold compensation module 109 may include an eighth transistor M4. The channel types of the eighth transistor M4 and the third transistor M2 may be the same or opposite. The eighth transistor M4 may be an N-type transistor or a P-type transistor.

[0135] Optionally, one of the first control signal line and the second control signal line multiplexes the second scan signal line or the fourth scan signal line, and the other of the first control signal line and the second control signal line multiplexes the emission control signal line.

[0136] Optionally, the switching state of one of the first switching sub-module and the second switching sub-module is opposite to that of the data writing module and / or the threshold compensation module; the switching state of the other of the first switching sub-module and the second switching sub-module is opposite to that of the emission control module.

[0137] To ensure the reasonable and normal operation of the pixel circuit 10, the bias reset phase is outside the time range of the data writing phase, and / or, the bias reset phase is outside the time range of the threshold compensation phase. The bias reset phase does not overlap with the data writing phase, and / or, the bias reset phase does not overlap with the threshold compensation phase.

[0138] Optionally, one of the first control signal line and the second control signal line multiplexes the second scan signal line S2, and the other of the first control signal line and the second control signal line multiplexes the emission control signal line EM. Optionally, the switching state of one of the first switching sub-module and the second switching sub-module is opposite to that of the data writing module; the switching state of the other of the first switching sub-module and the second switching sub-module is opposite to that of the emission control module.

[0139] Exemplarily, the first control signal line multiplexes the second scan signal line S2, and the second control signal line multiplexes the emission control signal line EM. Exemplarily, the switching state of the first switching sub-module is opposite to that of the data writing module; the switching state of the second switching sub-module is opposite to that of the emission control module. Exemplarily, the switching state of the second switching sub-module is opposite to that of the first emission control module, and / or, the switching state of the second switching sub-module is opposite to that of the second emission control module. Exemplarily, the channel types of the first transistor M8 and the third transistor M2 are opposite. Exemplarily, the channel types of the second transistor M9 and the fourth transistor M5 are opposite, and / or, the channel types of the second transistor M9 and the fifth transistor M6 are opposite.

[0140] Exemplarily, the second control signal line multiplexes the second scan signal line S2, and the first control signal line multiplexes the emission control signal line EM. Exemplarily, the switching state of the second switch sub-module is opposite to that of the data writing module; the switching state of the first switch sub-module is opposite to that of the emission control module. Exemplarily, the switching state of the first switch sub-module is opposite to that of the first emission control module, and / or the switching state of the first switch sub-module is opposite to that of the second emission control module. Exemplarily, the channel types of the second transistor M9 and the third transistor M2 are opposite. Exemplarily, the channel types of the first transistor M8 and the fourth transistor M5 are opposite, and / or the channel types of the first transistor M8 and the fifth transistor M6 are opposite.

[0141] Optionally, one of the first control signal line and the second control signal line multiplexes the fourth scan signal line S4, and the other of the first control signal line and the second control signal line multiplexes the emission control signal line EM. Optionally, the switching state of one of the first switch sub-module and the second switch sub-module is opposite to that of the threshold compensation module; the switching state of the other of the first switch sub-module and the second switch sub-module is opposite to that of the emission control module.

[0142] Exemplarily, the first control signal line multiplexes the fourth scan signal line S4, and the second control signal line multiplexes the emission control signal line EM. Exemplarily, the switching state of the first switch sub-module is opposite to that of the threshold compensation module; the switching state of the second switch sub-module is opposite to that of the emission control module. Exemplarily, the switching state of the second switch sub-module is opposite to that of the first emission control module, and / or the switching state of the second switch sub-module is opposite to that of the second emission control module. Exemplarily, the channel types of the first transistor M8 and the eighth transistor M4 are opposite. Exemplarily, the channel types of the second transistor M9 and the fourth transistor M5 are opposite, and / or the channel types of the second transistor M9 and the fifth transistor M6 are opposite.

[0143] Exemplarily, the second control signal line multiplexes the fourth scan signal line S4, and the first control signal line multiplexes the emission control signal line EM. Exemplarily, the switching state of the second switch sub-module is opposite to that of the threshold compensation module; the switching state of the first switch sub-module is opposite to that of the emission control module. Exemplarily, the switching state of the first switch sub-module is opposite to that of the first emission control module, and / or the switching state of the first switch sub-module is opposite to that of the second emission control module. Exemplarily, the channel types of the second transistor M9 and the eighth transistor M4 are opposite. Exemplarily, the channel types of the first transistor M8 and the fourth transistor M5 are opposite, and / or the channel types of the first transistor M8 and the fifth transistor M6 are opposite.

[0144] According to some embodiments of the present application, optionally, considering the actual working process of the pixel circuit 10, in order to further reduce the number of signal lines involved in the working process of the pixel circuit 10, the above-mentioned fourth scan signal line S4 can be multiplexed with the second scan signal line S2.

[0145] Optionally, the fourth scan signal line S4 and the second scan signal line S2 can be different signal lines.

[0146] According to some embodiments of the present application, optionally, please refer to Figure 7 , Figure 7 is a timing diagram of a light emission control signal provided by an embodiment of the present application. As Figure 7 shown, within one display frame, the light emission control signal includes multiple pulse signals. Optionally, within one display frame, the bias reset module 102 is turned on multiple times. Figure 7 Specifically, taking the example that the light emission control signal includes 3 pulse signals within one display frame, and Figure 7 in the above, the first control signal line EN2 is multiplexed with the second scan signal line S2, and the second control signal line EN2 is multiplexed with the light emission control signal line EM for display. It can be seen from Figure 7 this that within this display frame, as the high and low levels of the second scan signal S2 and the light emission control signal line EM are switched, this bias reset module 102 will be turned on (on) multiple times. The more the number of pulse signals of the light emission control signal, the more the number of black insertions, and the more the number of initializations of the first end of the driving transistor, the better the stress release effect.

[0147] Optionally, within one data writing frame, the light emission control signal includes multiple pulse signals. Optionally, within one data writing frame, the bias reset module 102 is turned on multiple times. Optionally, within one holding frame, the light emission control signal includes multiple pulse signals. Optionally, within one holding frame, the bias reset module 102 is turned on multiple times.

[0148] To facilitate the understanding of the pixel circuit 10 provided by the present application, the following will be described in conjunction with some specific application embodiments.

[0149] Next, please refer to Figure 8 , Figure 8 which is a structural diagram of another pixel circuit provided by an embodiment of the present application. In Figure 8Among them, the driving module 101 includes a driving transistor M1, the storage module 103 may include a storage capacitor C1, the data writing module 105 may include a third transistor M2, the first initialization module 104 may include a seventh transistor M3, the threshold compensation module 109 may include an eighth transistor M4, the first light emission control module 106 may include a fourth transistor M5, the second light emission control module 107 may include a fifth transistor M6, the second initialization module 108 may include a sixth transistor M7, and the bias adjustment module 102 may include a first transistor M8 and a second transistor M9. Among them, in this embodiment, the first transistor M8 and the second transistor M9 are both N-type thin film transistors, and the rest of the transistors are all P-type thin film transistors. The P-type thin film transistor is turned off when the signal received by the gate is high and turned on when the signal received by the gate is low; the N-type thin film transistor is turned off when the signal received by the gate is low and turned on when the signal received by the gate is high. And, in this embodiment, the fourth scan signal line S4 is multiplexed with the second scan signal line S2.

[0150] For ease of understanding Figure 8 the working process of the provided pixel circuit 10, the following may refer to Figure 9 . And Figure 9 corresponding to the pixel circuit shown, Figure 9 is a timing diagram of a pixel circuit 10 provided by an embodiment of the present application.

[0151] As Figure 9 shown, in some embodiments, Figure 9 the specific working stages of the shown pixel circuit 10 may include: a first initialization stage t1, a second initialization stage, a data writing stage t3, and a light emission stage t4. Exemplarily, both the first initialization stage t1 and the second initialization stage are within the bias reset stage.

[0152] Stage t1: The light emission control signal line EM provides a high level, the first control signal line EN1 and the second control signal line EN2 provide high levels, M5 and M6 are turned off, and M9 is turned on; S1 and S3 are at low levels, S2 is at a high level, M3, M7, and M8 are turned on, the Vref2 voltage initializes the gate of M1 and the potential of the storage capacitor C1 to prepare for the next signal writing, clear the residual potential of the previous frame, the Vref3 initializes the anode of the light emitting element D, the purpose is to eliminate the voltage of the previous frame, M8 and M9 are turned on simultaneously, so Vref1 is written to the source of M1, Vref1 is generally a negative voltage and is less than or equal to Vref2 to ensure that the Vgs voltage of M1 ≥ 0. This process completes the initialization of the M1 device, which can reduce the hysteresis of M1 and thus improve the afterimage.

[0153] Stage t2: The emission control signal line EM provides a high level, the first control signal line EN1 and the second control signal line EN2 provide high levels, M5 and M6 are turned off, and M9 and M8 are turned on; S3 is at a low level, S1 and S2 are at high levels, M3 is turned off, and M7 and M8 are turned on. The initialization time of the light-emitting element D is increased compared to the conventional circuit, ensuring that the electrical stress of the light-emitting element D is fully released, thereby improving the luminous lifetime of the light-emitting element D. At the same time, the voltage across M1 remains unchanged, and the initialization time of M1 is twice that of the conventional circuit, which is conducive to M1 fully recovering to a stress-free state and significantly reducing the hysteresis voltage. For high refresh rate panels, the improvement effect will be more prominent.

[0154] Stage t3: The emission control signal line EM provides a high level, M5 and M6 are turned off, the first emission control signal line EN1 provides a low level, the second emission control signal line EN2 provides a high level, and M9 is turned on; S1 and S3 are at high levels, S2 is at a low level, M8 is turned off, and Vdata is written into the gate of M1 and the storage capacitor C1 through M2, M1, and M4. When the gate node of M1 is approximately Vdata + Vth, the charging of M1 and Cst is completed, and the data writing and threshold compensation are completed.

[0155] Stage t4: The S2 signal turns to a high level, the emission control signal line EM provides a low level, M5 and M6 are turned on, and the gate voltage is Vdata + Vth. Therefore, the current of M1 at this time is The current is controlled by the Vdata voltage, and Vth is compensated.

[0156] Both stage t1 and stage t2 can be within the second initialization stage.

[0157] The data write frame can include the first initialization stage t1, the second initialization stage, the data write stage t3, and the emission stage t4. The hold frame can include the second initialization stage and the emission stage t4. The hold frame may not include the first initialization stage and the data write stage t3. In the emission stage t4, the emission control signal includes a plurality of pulse signals.

[0158] In this embodiment, the driving transistor M1 is a P-type transistor. By adding M9 and M8, and in the bias reset stage, making Vgs of M1 ≥ 0V. For example, in the bias reset stage, the voltage value of the first reference voltage signal is less than or equal to the voltage value of the second reference voltage signal, so that holes trapped at the TFT channel interface are released when the release device conducts, thereby reducing the hysteresis voltage of the M1 device and further improving the image sticking. Also, through the timing control of M7, the initialization time of the pixel circuit in this embodiment is increased compared to the conventional circuit, fully releasing the electrical and optical stress of the light-emitting element D and improving the lifespan of the light-emitting element D. By adopting the pixel circuit 10 in this embodiment, on the basis of ensuring the same Vth compensation effect, the effects of reducing the hysteresis voltage of the driving TFT, improving the image sticking, and improving the lifespan of the light-emitting element and the panel are achieved. If the driving transistor M1 is an N-type transistor, by adding M9 and M8, and in the bias reset stage, making Vgs of M1 ≤ 0V. For example, in the bias reset stage, the voltage value of the first reference voltage signal is greater than or equal to the voltage value of the second reference voltage signal, so that electrons trapped at the TFT channel interface are released when the release device conducts, thereby reducing the hysteresis voltage of the M1 device and further improving the image sticking.

[0159] Please refer to the following Figure 10 , Figure 10 which is a schematic structural diagram of another pixel circuit 10 provided by an embodiment of the present application. As Figure 10 shown, further, in order to fully realize the reasonable reuse of signal lines in the pixel circuit 10 to effectively reduce the number of signal lines, one of the first control signal line EN1 and the second control signal line EN2 can reuse the second scan signal line S2, and the other of the first control signal line EN1 and the second control signal line EN2 can reuse the light-emitting control signal line EM.

[0160] As Figure 10 shown, in this embodiment, take the first control signal line EN1 reusing the second scan signal line S2 and the second control signal line EN2 reusing the light-emitting control signal line EM as an example. That is to say, in this embodiment, by reusing the second scan signal line S2 and the light-emitting control signal line EM originally used to control data writing to control the M8 and M9 transistors, while saving signal lines, the stress of the DTFT (M1) can be adjusted to the greatest extent, and the hysteresis of the DTFT (M1) can be fully reduced to improve the image sticking.

[0161] Further, in this embodiment, M7 can also be adjusted to an N-type thin-film transistor and controlled by using the light-emitting control signal line EM at the same time. This can reduce the previous third scan signal line S3, which is beneficial to the narrow border effect and improves the quality of the screen body; at the same time, the initialization time of the light-emitting element D is synchronized with the time when the light-emitting control signal line EM provides a high level, which can ensure the luminous lifespan of the light-emitting element to the greatest extent.

[0162] For the convenience of understanding Figure 10 the working process of the provided pixel circuit 10, the following can be referred to Figure 11 . Corresponding to Figure 10 the shown pixel circuit Figure 11 is a timing diagram of another pixel circuit 10 provided by an embodiment of the present application. It should be understood here that, for the sake of brevity, the specific working process of this pixel circuit 10 is not elaborated in detail in this embodiment.

[0163] It can be understood that the driving timing given in the embodiment of the present application is only a possible example. In some other embodiments, the working timing of the above pixel circuit can also be flexibly adjusted according to the actual situation and requirements, and the present application does not make specific limitations thereto.

[0164] It can be understood that for similar reasons as the foregoing embodiments, considering the wide application of various basic pixel structures in the panel field, for the sake of brevity, in this embodiment Figure 9 the specific working processes of other devices in the shown pixel circuit are not elaborated.

[0165] It should be noted that in addition to the several pixel circuit structures listed above, the pixel circuit 10 of the present application may further include other numbers and electronic devices with other connection relationships. These electronic devices (such as transistors, capacitors, etc.) together constitute various types of pixel circuits, and the present application does not make specific limitations thereto. Exemplarily, please refer to Figure 12 , Figure 12 a schematic structural diagram of another pixel circuit 10 provided by an embodiment of the present application. Figure 12 In it, the pixel circuit 10 may not include the threshold compensation module in the foregoing embodiment, and the second end of the data writing module 106 is electrically connected to the control end of the driving module 101, and this embodiment does not elaborate too much on it here.

[0166] In summary, the embodiment of the present application proposes a novel pixel circuit 10 structure to fully improve the ghosting problem of the display panel from the aspect of pixel circuit 10 design, thereby effectively improving the display effect and service performance of the display panel.

[0167] Based on the pixel circuit provided in the above embodiment, correspondingly, the present application further provides a display panel, including the pixel circuit 10 provided in any one of the above embodiments of the present application. Please refer to Figure 13 , Figure 13 is a schematic structural diagram of a display panel provided by an embodiment of the present application. Figure 13The provided display panel can be an AMOLED, an OLED, or others. Those skilled in the art should understand that in other implementation manners of the present application, the display panel can also be a micro light-emitting diode display panel, a quantum dot display panel, etc.

[0168] According to some embodiments of the present application, optionally, the display frame of the above display panel includes a data writing frame and a holding frame. When the display frame of the display panel is a data writing frame, the bias reset module 102 in the pixel circuit 10 is turned on during non-light-emitting phases other than the data writing phase, and transmits the first reference voltage signal provided by the first reference voltage signal line Vref1 to the first end of the driving module 101.

[0169] When the display frame of the display panel is a holding frame, the bias reset module 102 in the pixel circuit 10 is turned on during the non-light-emitting phase, and transmits the first reference voltage signal to the first end of the driving module 101.

[0170] In this embodiment, exemplarily, still analyzing in combination with the foregoing Figure 10 shown pixel circuit, M8 and M9 are NMOS transistors, the second scan signal line S2 for controlling data writing is multiplexed as the gate signal line of M8, and the light emission control signal line EM is multiplexed as the gate control signal line of M9.

[0171] Thus, in the data writing frame, during the period when the light emission control signal line EM is at a high level and the second scan signal line S2 is at a high level (i.e., the period other than the data writing phase in the non-light-emitting phase), verf1 is written to adjust the bias state of the driving transistor M1. And, if the light emission control signal in the data writing frame includes multiple pulse signals, then in this data writing frame, as the number of black insertions of the light emission control signal line EM is higher, correspondingly, the number of initializations of the driving transistor M1 is more, and the stress release effect is better.

[0172] In the holding frame, since the second scan signal line S2 is always at a high level, the period when M8 and M9 are turned on simultaneously is: the non-light-emitting phase when the light emission control signal line EM is at a high level. That is to say, in the holding frame, as the number of black insertions of the light emission control signal line EM is higher, the number of initializations of the driving transistor M1 is more, and the stress release effect is good.

[0173] Based on the pixel circuit provided in the above embodiment, the embodiment of the present application provides a driving method for a pixel circuit. Please refer to the following Figure 14 , Figure 14 is a schematic flowchart of a driving method for a pixel circuit provided by the embodiment of the present application. As shown in Figure 14As shown, in the driving method of this pixel circuit, the pixel circuit may include: a driving module, a first end of the driving module is electrically connected to a first power supply voltage signal line, a second end of the driving module is electrically connected to a first electrode of a light-emitting element, and the driving module is configured to drive the light-emitting element to emit light; a bias reset module, a first end of the bias reset module is electrically connected to the first end of the driving module, and a second end of the bias reset module is electrically connected to a first reference voltage signal line.

[0174] The driving method of this pixel circuit may specifically include:

[0175] S1401, in the bias reset stage, control the bias reset module to turn on, so as to transmit the first reference voltage signal provided by the first reference voltage signal line to the first end of the driving module.

[0176] The embodiments of the present application provide a driving method for a pixel circuit, which has the beneficial effects of the pixel circuit provided by the embodiments of the present application. For the specific description of the pixel circuit, reference may be specifically made to the above embodiments, and details are not described herein again in this embodiment.

[0177] Optionally, the bias reset module includes a first switch sub-module and a second switch sub-module connected in series. Optionally, one of the first switch sub-module and the second switch sub-module has an opposite switching state to that of the data writing module; the other of the first switch sub-module and the second switch sub-module has an opposite switching state to that of the light-emitting control module.

[0178] Optionally, one of the first switch sub-module and the second switch sub-module has an opposite switching state to that of the threshold compensation module; the other of the first switch sub-module and the second switch sub-module has an opposite switching state to that of the light-emitting control module.

[0179] Based on the display panel provided in the above embodiments, correspondingly, the present application further provides a display device, including the display panel provided by the present application. Please refer to Figure 15 , Figure 15 which is a schematic structural diagram of a display device provided by an embodiment of the present application. Figure 15 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Figure 15 Taking a mobile phone as an example, the display device 1000 is described. It can be understood that the display device provided by the embodiments of the present application may be other display devices with a display function, such as wearable products, computers, televisions, in-vehicle display devices, etc. The present application does not make specific limitations thereto. The display device provided by the embodiments of the present application has the beneficial effects of the display panel 100 provided by the embodiments of the present application. For the specific description of the display panel 100, reference may be specifically made to the above embodiments, and details are not described herein again in this embodiment.

[0180] It should be understood that the specific structure of the circuit and the cross-sectional structure of the display panel provided in the accompanying drawings of the embodiments of the present application are only some examples and are not used to limit the present application. In addition, the above-mentioned various embodiments provided by the present application can be combined with each other without conflict.

[0181] It should be clear that the various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, reference can be made to each other. The key point of each embodiment is to illustrate the differences from other embodiments. In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made according to the above description. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

[0182] Those skilled in the art should understand that the above embodiments are all exemplary rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Those skilled in the art should be able to understand and implement other variations of the disclosed embodiments based on the study of the drawings, the specification, and the claims. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude a plurality; the terms "first" and "second" are used to label names rather than to indicate any specific order. Any reference signs in the claims should not be construed as limiting the scope of protection. The fact that certain technical features appear in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A pixel circuit, characterized in that: include: A driving module, wherein the driving module and the light-emitting element are connected in series between the first power supply voltage signal line and the second power supply voltage signal line, and the driving module is used to drive the light-emitting element to emit light; A bias reset module, wherein a first end of the bias reset module is electrically connected to a first end of the driving module, and a second end of the bias reset module is electrically connected to a first reference voltage signal line; The bias reset module is used to transmit the first reference voltage signal provided by the first reference voltage signal line to the first end of the driving module during the bias reset phase; the bias reset module includes a first switch submodule and a second switch submodule; The control end of the first switch submodule is electrically connected to the first control signal line, and the first end of the first switch submodule is electrically connected to the first end of the driving module; the control end of the second switch submodule is electrically connected to the second control signal line, the first end of the second switch submodule is electrically connected to the second end of the first switch submodule, and the second end of the second switch submodule is electrically connected to the first reference voltage signal line; the signals of the first control signal line and the second control signal line are different; the first switch submodule includes a first transistor, and the second switch submodule includes a second transistor; a data writing module and / or a threshold compensation module, wherein the control end of the data writing module is electrically connected to the second scanning signal line, the first end of the data writing module is electrically connected to the data signal line, and the second end of the data writing module is electrically connected to the first end of the driving module; the control end of the threshold compensation module is electrically connected to the fourth scanning signal line, the first end of the threshold compensation module is electrically connected to the second end of the driving module, and the second end of the threshold compensation module is electrically connected to the control end of the driving module; the data writing module includes a third transistor; and / or the threshold compensation module includes an eighth transistor; A light-emitting control module, wherein a control end of the light-emitting control module is electrically connected to a light-emitting control signal line, the light-emitting control module, the driving module and the light-emitting element are connected in series between a first power supply voltage signal line and a second power supply voltage signal line, one of the first control signal line and the second control signal line multiplexes the second scanning signal line or the fourth scanning signal line, and the other of the first control signal line and the second control signal line multiplexes the light-emitting control signal line; the light-emitting control module includes a first light-emitting control module and / or a second light-emitting control module; the first light-emitting control module includes a fourth transistor, and the second light-emitting control module includes a fifth transistor, one of the first transistor and the second transistor has a channel type opposite to that of the third transistor and / or the eighth transistor, and the other of the first transistor and the second transistor has a channel type opposite to that of the fourth transistor and / or the fifth transistor; a second initialization module, wherein the control end of the second initialization module is electrically connected to the third scanning signal line, the first end of the second initialization module is electrically connected to the first electrode of the light-emitting element, and the second end of the second initialization module is electrically connected to the third reference voltage signal line; the second initialization module is used to transmit the third reference voltage signal provided by the third reference voltage signal line to the first electrode of the light-emitting element in the second initialization stage; the third scanning signal line multiplexes the light-emitting control signal line; The second initialization module includes a sixth transistor, the sixth transistor having a channel type opposite to that of the fourth transistor and / or the fifth transistor; The bias reset phase is within the non-luminescence phase and outside the time range of the data writing phase. In a display frame, the bias reset phase includes a period located in a non-light-emitting phase and before a data writing phase, and a period between a light-emitting phase adjacent to and after the data writing phase and the data writing phase.

2. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes: a first initialization module, wherein a control end of the first initialization module is electrically connected to a first scanning signal line, a first end of the first initialization module is electrically connected to a control end of the driving module, and a second end of the first initialization module is electrically connected to a second reference voltage signal line; The first initialization module is used for transmitting the second reference voltage signal provided by the second reference voltage signal line to the control end of the driving module in a first initialization phase.

3. The pixel circuit according to claim 2, characterized in that: A voltage value of the first reference voltage signal is less than or equal to a voltage value of the second reference voltage signal.

4. The pixel circuit according to claim 2, characterized in that: At least a partial period of the first initialization phase is within the bias reset phase.

5. The pixel circuit according to claim 2, characterized in that: The entire period of the first initialization phase is within the bias reset phase.

6. The pixel circuit according to claim 2, characterized in that: The duration of the bias reset phase is longer than the duration of the first initialization phase.

7. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes a storage module, a first end of the storage module is electrically connected to the first power supply voltage signal line, and a second end of the storage module is electrically connected to the control end of the driving module.

8. The pixel circuit according to claim 1, characterized in that: The pixel circuit further comprises a data writing module, wherein a control end of the data writing module is electrically connected to the second scanning signal line, a first end of the data writing module is electrically connected to the data signal line, and a second end of the data writing module is electrically connected to the first end of the driving module; The data writing module is used to transmit the data voltage provided by the data signal line to the first end of the driving module during the data writing phase.

9. The pixel circuit according to claim 8, characterized in that: The first control end of the bias reset module is electrically connected to the first control signal line, and the second control end of the bias reset module is electrically connected to the second control signal line.

10. The pixel circuit according to claim 9, characterized in that: One of the first control terminal and the second control terminal provides a conduction level to the bias reset module in a period other than a data writing phase; the other of the first control terminal and the second control terminal provides a conduction level to the bias reset module in a non-light emitting phase; In a case where both the first control terminal and the second control terminal provide a conduction level to the bias reset module, the bias reset module transmits the first reference voltage signal to the first terminal of the driving module.

11. The pixel circuit according to claim 10, characterized in that: The light control module includes a first light control module and / or a second light control module; The control end of the first light-emitting control module is electrically connected to the light-emitting control signal line, the first end of the first light-emitting control module is electrically connected to the first power supply voltage signal line, and the second end of the first light-emitting control module is electrically connected to the first end of the driving module; The control end of the second light emitting control module is electrically connected to the light emitting control signal line, the first end of the second light emitting control module is electrically connected to the second end of the driving module, the second end of the second light emitting control module is electrically connected to the first electrode of the light emitting element; the second electrode of the light emitting element is electrically connected to the second power supply voltage signal line; One of the first control signal line and the second control signal line multiplexes with the second scanning signal line, and the other of the first control signal line and the second control signal line multiplexes with the light emission control signal line.

12. The pixel circuit according to claim 11, characterized in that: In a display frame, the light-emitting control signal on the light-emitting control signal line includes a plurality of pulse signals, and in a display frame, the bias reset module is turned on for a plurality of times.

13. The pixel circuit according to claim 1, characterized in that: The first switch submodule includes a first transistor, and the second switch submodule includes a second transistor; channel types of the first transistor and the second transistor are the same or opposite.

14. The pixel circuit according to claim 1, characterized in that: The data writing module includes a third transistor, the first control signal line multiplexes the second scanning signal line, and the channel type of the first transistor is opposite to that of the third transistor; or, the second control signal line multiplexes the second scanning signal line, and the channel type of the second transistor is opposite to that of the third transistor.

15. The pixel circuit according to claim 1, characterized in that: The third transistor is a P-type transistor.

16. The pixel circuit according to claim 1, characterized in that: The first light-emitting control module includes a fourth transistor, the first control signal line multiplexes the light-emitting control signal line, and the first transistor and the fourth transistor have opposite channel types; or, the second control signal line multiplexes the light-emitting control signal line, and the second transistor and the fourth transistor have opposite channel types; And / or, the second light emitting control module includes a fifth transistor; The first control signal line multiplexes the light emission control signal line, and the first transistor and the fifth transistor have opposite channel types; or the second control signal line multiplexes the light emission control signal line, and the second transistor and the fifth transistor have opposite channel types.

17. The pixel circuit according to claim 1, characterized in that: The fourth transistor is a P-type transistor; and / or the fifth transistor is a P-type transistor.

18. The pixel circuit according to claim 1, characterized in that: The first transistor is an N-type transistor; the second transistor is an N-type transistor.

19. The pixel circuit according to claim 1, characterized in that: The third transistor, the fourth transistor, and the fifth transistor have the same channel type.

20. The pixel circuit according to claim 1, characterized in that: The second initialization phase coincides with the non-light emitting phase.

21. The pixel circuit according to claim 1, characterized in that: The light control module includes a first light control module and / or a second light control module; The control end of the first light-emitting control module is electrically connected to the light-emitting control signal line, the first end of the first light-emitting control module is electrically connected to the first power supply voltage signal line, and the second end of the first light-emitting control module is electrically connected to the first end of the driving module; The control end of the second light emitting control module is electrically connected to the light emitting control signal line, the first end of the second light emitting control module is electrically connected to the second end of the driving module, and the second end of the second light emitting control module is electrically connected to the first electrode of the light emitting element; The third scanning signal line multiplexes with the light emission control signal line.

22. The pixel circuit according to claim 21, characterized in that: The second initialization module includes a sixth transistor, and the channel type of the sixth transistor is a first channel type; The first light emitting control module includes a fourth transistor, and / or the second light emitting control module includes a fifth transistor; the channel type of the fourth transistor and / or the fifth transistor is the second channel type; The first channel type is opposite to the second channel type.

23. The pixel circuit according to claim 1, characterized in that: One of the first switch submodule and the second switch submodule has a switch state opposite to that of the data writing module and / or the threshold compensation module; the other of the first switch submodule and the second switch submodule has a switch state opposite to that of the light emitting control module.

24. The pixel circuit according to claim 23, characterized in that: The fourth scan signal line multiplexes with the second scan signal line.

25. A pixel circuit, characterized in that: include: A driving module, wherein the driving module and the light-emitting element are connected in series between the first power supply voltage signal line and the second power supply voltage signal line, and the driving module is used to drive the light-emitting element to emit light; A bias reset module, wherein a first end of the bias reset module is electrically connected to a first end of the driving module, and a second end of the bias reset module is electrically connected to a first reference voltage signal line; The bias reset module is used to transmit the first reference voltage signal provided by the first reference voltage signal line to the first end of the driving module during the bias reset phase; the bias reset module includes a first switch submodule and a second switch submodule; The control end of the first switch submodule is electrically connected to the first control signal line, and the first end of the first switch submodule is electrically connected to the first end of the driving module; the control end of the second switch submodule is electrically connected to the second control signal line, the first end of the second switch submodule is electrically connected to the second end of the first switch submodule, and the second end of the second switch submodule is electrically connected to the first reference voltage signal line; the signals of the first control signal line and the second control signal line are different; a data writing module and / or a threshold compensation module, wherein the control end of the data writing module is electrically connected to the second scanning signal line, the first end of the data writing module is electrically connected to the data signal line, and the second end of the data writing module is electrically connected to the first end of the driving module; the control end of the threshold compensation module is electrically connected to the fourth scanning signal line, the first end of the threshold compensation module is electrically connected to the second end of the driving module, and the second end of the threshold compensation module is electrically connected to the control end of the driving module; A light-emitting control module, wherein the control end of the light-emitting control module is electrically connected to the light-emitting control signal line, the light-emitting control module, the driving module and the light-emitting element are connected in series between the first power supply voltage signal line and the second power supply voltage signal line, one of the first control signal line and the second control signal line reuses the second scanning signal line or the fourth scanning signal line, and the other of the first control signal line and the second control signal line reuses the light-emitting control signal line; one of the first switch submodule and the second switch submodule has a switch state opposite to that of the data writing module and the threshold compensation module; the other of the first switch submodule and the second switch submodule has a switch state opposite to that of the light-emitting control module, the bias reset phase is within the non-light-emitting phase and outside the time range of the data writing phase, and within a display frame, the bias reset phase includes a time period located in the non-light-emitting phase and before the data writing phase, and a time period between the light-emitting phase adjacent to the data writing phase and after the data writing phase and the data writing phase.

26. A display panel, characterized in that: The display panel comprises: a pixel circuit as described in any one of claims 1-25.

27. The display panel according to claim 26, characterized in that: The display frame of the display panel includes a data writing frame and a holding frame; When the display frame of the display panel is a data writing frame, the bias reset module in the pixel circuit is turned on in a non-light emitting phase except for a data writing phase, and transmits a first reference voltage signal provided by a first reference voltage signal line to a first end of a driving module; When the display frame of the display panel is a hold frame, the bias reset module in the pixel circuit is turned on in a non-light-emitting phase to transmit the first reference voltage signal to the first end of the driving module.

28. A method for driving a pixel circuit, characterized in that: The pixel circuit comprises: A driving module, wherein a first end of the driving module is electrically connected to a first power supply voltage signal line, a second end of the driving module is electrically connected to a first electrode of a light-emitting element, and the driving module is used to drive the light-emitting element to emit light; A bias reset module, wherein a first end of the bias reset module is electrically connected to a first end of the driving module, and a second end of the bias reset module is electrically connected to a first reference voltage signal line; The driving method of the pixel circuit includes: In the bias reset stage, the bias reset module is controlled to be turned on to transmit the first reference voltage signal provided by the first reference voltage signal line to the first end of the driving module; the bias reset module includes a first switch submodule and a second switch submodule; the control end of the first switch submodule is electrically connected to the first control signal line, and the first end of the first switch submodule is electrically connected to the first end of the driving module; the control end of the second switch submodule is electrically connected to the second control signal line, the first end of the second switch submodule is electrically connected to the second end of the first switch submodule, and the second end of the second switch submodule is electrically connected to the first reference voltage signal line; the signals of the first control signal line and the second control signal line are different; the first switch submodule includes a first transistor, and the second switch submodule includes a second transistor; a data writing module and / or a threshold compensation module, wherein the control end of the data writing module is electrically connected to the second scanning signal line, the first end of the data writing module is electrically connected to the data signal line, and the second end of the data writing module is electrically connected to the first end of the driving module; the control end of the threshold compensation module is electrically connected to the fourth scanning signal line, the first end of the threshold compensation module is electrically connected to the second end of the driving module, and the second end of the threshold compensation module is electrically connected to the control end of the driving module; the data writing module includes a third transistor; and / or the threshold compensation module includes an eighth transistor; A light-emitting control module, wherein a control end of the light-emitting control module is electrically connected to a light-emitting control signal line, the light-emitting control module, the driving module and the light-emitting element are connected in series between a first power supply voltage signal line and a second power supply voltage signal line, one of the first control signal line and the second control signal line multiplexes the second scanning signal line or the fourth scanning signal line, and the other of the first control signal line and the second control signal line multiplexes the light-emitting control signal line; the light-emitting control module includes a first light-emitting control module and / or a second light-emitting control module; the first light-emitting control module includes a fourth transistor, and the second light-emitting control module includes a fifth transistor, one of the first transistor and the second transistor has a channel type opposite to that of the third transistor and / or the eighth transistor, and the other of the first transistor and the second transistor has a channel type opposite to that of the fourth transistor and / or the fifth transistor; a second initialization module, wherein the control end of the second initialization module is electrically connected to the third scanning signal line, the first end of the second initialization module is electrically connected to the first electrode of the light-emitting element, and the second end of the second initialization module is electrically connected to the third reference voltage signal line; the second initialization module is used to transmit the third reference voltage signal provided by the third reference voltage signal line to the first electrode of the light-emitting element in the second initialization stage; the third scanning signal line multiplexes the light-emitting control signal line; The second initialization module includes a sixth transistor, the sixth transistor having a channel type opposite to that of the fourth transistor and / or the fifth transistor; The bias reset phase is within the non-luminescence phase and outside the time range of the data writing phase. In a display frame, the bias reset phase includes a period located in a non-light-emitting phase and before a data writing phase, and a period between a light-emitting phase adjacent to and after the data writing phase and the data writing phase.

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