Gallium arsenide chip delayering method

Abstract

The application provides a gallium arsenide chip delamination method. It relates to the technical field of semiconductor testing. The method comprises the following steps: determining a sample to be delaminated; etching the passivation layer by using a plasma etching technology to remove the passivation layer and expose the metal layer; etching the metal layer by using a gold etching solution to remove the metal layer and expose the dielectric layer; etching the dielectric layer by using a plasma etching technology to remove the dielectric layer and obtain a delaminated sample. The method can realize delamination of the gallium arsenide chip by using a physical and chemical fusion method, and is more reasonable for delamination of the gallium arsenide chip and less destructive to the gallium arsenide layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing, and more specifically, to a method for removing layers from gallium arsenide chips. Background Technology

[0002] Gallium arsenide (GaAs) is a dark gray solid with a melting point of 1238°C. It is stable in air below 600°C. Gallium arsenide is an important semiconductor material, belonging to group III-V compound semiconductors. It has a zincblende crystal structure with a lattice constant of 5.65 × 10⁻⁶. -10 Gallium arsenide (GaAs) has a melting point of 1237°C and a bandgap of 1.4 eV. It entered practical application in 1964. GaAs can be fabricated into a semi-insulating, high-resistivity material with resistivity more than three orders of magnitude higher than silicon and germanium, used to make integrated circuit substrates, infrared detectors, and gamma-photon detectors. Due to its electron mobility being 5-6 times greater than silicon, it has important applications in the fabrication of microwave devices and high-speed digital circuits. Semiconductor devices made from GaAs have advantages such as good high-frequency, high-temperature, and low-temperature performance, low noise, and strong radiation resistance. Furthermore, it can be used to fabricate transfer devices—bulk effect devices.

[0003] Gallium arsenide (GaAs) chips typically employ non-planarization processes. Traditional planar grinding methods for delamination can damage the chip structure. Furthermore, GaAs is a very brittle material that is easily corroded by acids and alkalis, making chemical delamination methods quite challenging. Summary of the Invention

[0004] The purpose of this application is to provide a method for removing gallium arsenide (GaAs) chips, which can remove GaAs chips more reasonably and cause less damage to the GaAs layer.

[0005] In a first aspect, this application provides a method for removing layers from a gallium arsenide chip, comprising:

[0006] A sample to be removed is identified. The sample to be removed comprises a multilayer structure prepared by multiple non-planarization processes. The multilayer structure includes a gallium arsenide layer, a dielectric layer, a metal layer, and a passivation layer. The passivation layer is located on the surface of the sample to be removed, the metal layer is located below the passivation layer, the dielectric layer is located below the metal layer, and the gallium arsenide layer is located below the dielectric layer.

[0007] The passivation layer is etched using plasma etching technology to remove the passivation layer and expose the metal layer;

[0008] The metal layer is etched using a gold etching solution to remove the metal layer and expose the dielectric layer;

[0009] The dielectric layer is etched using plasma etching technology to remove the dielectric layer, resulting in a delayered sample.

[0010] In an optional embodiment, the step of etching the passivation layer using plasma etching technology to remove the passivation layer and expose the metal layer includes:

[0011] Etching is performed at a power of 50±5W and under CF4 / O2 / Ar gas conditions for a first preset time to remove the passivation layer and expose the metal layer.

[0012] In an optional implementation, the first preset time is determined based on the thickness of the passivation layer; the thicker the passivation layer, the longer the first preset time.

[0013] In an optional embodiment, the gold etching solution comprises iodine, potassium iodide, and water.

[0014] In an optional embodiment, the ratio of iodine to potassium iodide in the gold etching solution is less than or equal to 1 / 2.

[0015] In an optional embodiment, the weight ratio of the components of the gold etching solution is: iodine: potassium iodide: water = 1:2:200.

[0016] In an optional embodiment, the etching time of the metal layer using gold etching solution is controlled to be 2 ± 0.5 minutes.

[0017] In an optional embodiment, the dielectric layer is a TaN material; the step of etching the dielectric layer using plasma etching technology to remove the dielectric layer includes:

[0018] Etching was performed at a power of 50±5W and under CF4 / O2 / Ar gas conditions for a second preset time to remove the dielectric layer.

[0019] In an optional implementation, the second preset time is determined based on the thickness of the dielectric layer; the thicker the dielectric layer, the longer the second preset time.

[0020] This application provides a method for removing layers from a gallium arsenide (GaAs) chip. The method involves: identifying the sample to be delayered; using plasma etching to remove the passivation layer and expose the metal layer; using a gold etchant to etch the metal layer and expose the dielectric layer; and finally using plasma etching to remove the dielectric layer, resulting in a delayered sample. This method achieves a combination of physical and chemical methods for delayering the GaAs chip, resulting in a more efficient delayer removal process with less damage to the GaAs layer. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic flowchart of a gallium arsenide chip delamination method provided in an embodiment of this application;

[0023] Figure 2 This is a schematic diagram of a sample structure to be removed, provided as an embodiment of this application. Detailed Implementation

[0024] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic flowchart of a gallium arsenide chip delamination method provided in an embodiment of this application. It is used for... Figure 2 The sample to be delayered is shown below. For example... Figure 2 As shown, the sample to be removed includes multiple multilayer structures prepared by a non-planarization process. The multilayer structure includes a substrate 204, gallium arsenide 203, a dielectric layer 202, and a passivation layer 201. The metal layer (not shown in the figure) can be a metal interconnect or a metal bridge. The passivation layer is located on the surface of the sample to be removed, the metal layer is located below the passivation layer, the dielectric layer is located below the metal layer, and the gallium arsenide layer is located below the dielectric layer.

[0026] like Figure 1 As shown, the method includes:

[0027] S110, Identify the sample to be delayered.

[0028] The sample to be delayered here can refer to a gallium arsenide (GaAs) chip. This GaAs chip can be removed from the device under test, and the delayer can be removed by grinding, chemical methods, or a combination of both.

[0029] S120 uses plasma etching technology to etch the passivation layer.

[0030] In some embodiments, etching can be performed at a power of 50±5W and under CF4 / O2 / Ar gas conditions for a first preset time to remove the passivation layer and expose the metal layer.

[0031] The first preset time can be determined based on the thickness of the passivation layer. The thicker the passivation layer, the longer the first preset time. For example, the first preset time can be 3 minutes.

[0032] In the CF4 / O2 / Ar gas conditions here, the flow rate ratio of CF4 / O2 / Ar gas can be 30 sccm / 15 sccm / 10 sccm, where sccm refers to the standard liter per minute flow rate.

[0033] As an example, the thickness of the passivation layer of the sample to be removed can be determined according to the type of sample, and a first preset time length can be determined based on the thickness of the passivation layer.

[0034] The type of the sample to be removed can be a model number. The correspondence between different gallium arsenide (GaAs) chip models and passivation layer thicknesses can be pre-collected. Based on this correspondence, the thickness of the passivation layer corresponding to the sample to be removed can be determined. This correspondence can be stored in a database. During model matching, if the type of the sample to be removed has not been collected, the thickness data of each layer of the sample to be removed is obtained from the chip designer or manufacturer, and the correspondence between the GaAs chip model and the passivation layer thickness is updated based on this data.

[0035] This process can be pre-tested using experiments or simulations to determine the correlation between the thickness of multiple passivation layers and the time duration. Based on this correlation, a curve showing the relationship between the reference thickness of the passivation layer and the reference time duration can be fitted; alternatively, this correlation can be organized into a table showing the relationship between the reference thickness of the passivation layer and the reference time duration. Optionally, the multiple reference thicknesses of the passivation layers in this table can be distributed in an arithmetic sequence.

[0036] For example, when using the relationship table, the thickness of the passivation layer of the sample to be removed can be matched in the relationship table to determine the two passivation layer reference thicknesses adjacent to the thickness of the passivation layer of the sample to be removed. The smaller of the two passivation layer reference thicknesses adjacent to the thickness of the passivation layer of the sample to be removed is then used as the first preset time length of the sample to be removed.

[0037] For example, when using the relationship curve, the thickness of the passivation layer of the sample to be removed can be input into the curve to obtain the first preset time length corresponding to the sample to be removed.

[0038] In some embodiments, the etching time per unit thickness of the passivation layer by plasma etching technology can be predetermined. The first preset time is determined based on the product of the thickness of the passivation layer of the sample to be removed and the etching time per unit thickness. For example, when the main component of the passivation layer is silicon nitride, it can be determined that a thickness of 1 μm can be etched in 1 minute at the RIE etching rate.

[0039] Furthermore, the passivation layer thickness on the sample surface to be removed is typically 5µm-10µm, based on which the etching time can be determined to be typically 5-10 minutes. That is, RIE etching for 5-10 minutes is sufficient to remove the passivation layer and expose the metal layer. Therefore, the aforementioned curve or table relating the passivation layer thickness to the etching time can be constrained to this range of 5µm-10µm and 5-10 minutes.

[0040] After removing the passivation layer to expose the metal layer, analysis activities such as electrical testing and photography can be performed. After the analysis is completed, the sample can be delayered again.

[0041] S130 uses a gold etching solution to etch the metal layer, removing the metal layer to expose the dielectric layer.

[0042] The traces of gallium arsenide metal layers are generally made of gold, and gold-removing etchants can be used to etch the metal layers.

[0043] The gold etching solution here may contain iodine, potassium iodide and water mixed in a certain proportion.

[0044] In the gold etching solution, the ratio of iodine to potassium iodide is less than or equal to 1 / 2.

[0045] For example, the weight ratio of the components in the gold etching solution is: iodine: potassium iodide: water = 1:2:200.

[0046] For example, you can first dissolve 5g of potassium iodide in 500mL of water to obtain a potassium iodide solution, and then dissolve 2.5g of iodine in the potassium iodide solution to obtain an iodine-potassium iodide solution. Alternatively, you can prepare the solution in equal proportions.

[0047] The etching time for the metal layer can be controlled within 2 ± 0.5 minutes using a gold-removing etchant.

[0048] S140 uses plasma etching technology to etch the dielectric layer, remove the dielectric layer, and obtain the delayered sample.

[0049] The upper and lower surfaces of each metal layer are covered by a dielectric layer. The purpose of this layer is to act as an insulating layer between the upper and lower metal layers. After the dielectric layer is removed, the metal layers can be exposed.

[0050] As an example, the main component of this dielectric layer is silicon oxide, which can be approximately 1µm-3µm thick.

[0051] As another example, the dielectric layer can also be a TaN material.

[0052] The etching process can be performed at a power of 50±5W and under CF4 / O2 / Ar gas conditions for a second preset time to remove the dielectric layer.

[0053] In the plasma etching process, CF4 / O2 / Ar gases physically bombard the dielectric layer, thus removing the dielectric layer through physical and chemical reactions.

[0054] The second preset time can be determined based on the thickness of the dielectric layer; the thicker the dielectric layer, the longer the second preset time.

[0055] As an example, the thickness of the dielectric layer of the sample to be removed can be determined according to the type of the sample, and a second preset time length can be determined based on the thickness of the dielectric layer.

[0056] The type of the sample to be removed can be a model number. The correspondence between different gallium arsenide (GaAs) chip models and dielectric layer thicknesses can be pre-collected. Based on this correspondence, the thickness of the dielectric layer corresponding to the sample to be removed can be determined. This correspondence can be stored in a database. During model matching, if the type of the sample to be removed has not been collected, the thickness data of each layer of the sample to be removed is obtained from the chip designer or manufacturer, and the correspondence between the GaAs chip model and dielectric layer thickness is updated based on this data.

[0057] This process can be pre-conducted through experiments or simulations to determine the correspondence between the thickness of multiple dielectric layers and the duration of time. Based on this correspondence, a curve showing the relationship between the reference thickness of the dielectric layer and the reference duration of time can be fitted; alternatively, this correspondence can be organized into a table showing the relationship between the reference thickness of the dielectric layer and the reference duration of time. Optionally, the reference thicknesses of multiple dielectric layers in this table can be distributed in an arithmetic sequence.

[0058] For example, when using the relationship table, the thickness of the dielectric layer of the sample to be removed can be matched in the relationship table to determine the reference thickness of the two dielectric layers adjacent to the thickness of the dielectric layer of the sample to be removed. The smaller reference time length of the dielectric layer reference thickness adjacent to the thickness of the passivation layer of the sample to be removed is determined as the second preset time length of the sample to be removed.

[0059] For example, when using the relationship curve, the thickness of the medium layer of the sample to be removed can be input into the curve to obtain the second preset time length corresponding to the sample to be removed.

[0060] In some embodiments, the etching time per unit thickness of the dielectric layer by plasma etching technology can also be predetermined, and a second preset time can be determined based on the product of the thickness of the dielectric layer of the sample to be removed and the etching time per unit thickness. For example, when the main component of the dielectric layer is silicon oxide, it can be determined that a thickness of 1 μm can be etched in 1 minute at the RIE etching rate.

[0061] Furthermore, the thickness of the dielectric layer on the surface of the sample to be etched is typically 1µm-3µm, based on which the etching time can be determined to be typically 1 minute-3 minutes. That is, RIE etching for 1 minute-3 minutes is sufficient to remove the dielectric layer and expose the metal layer. Therefore, the aforementioned curve or table relating dielectric layer thickness to etching time can be constrained to this range of 1µm-3µm and 1 minute-3 minutes.

[0062] In some embodiments, when the passivation layer and the dielectric layer are made of the same material, a thickness-time relationship can be maintained. Based on this relationship, a first preset time length or a second preset time length can be determined respectively. This thickness-time relationship can be the relationship curve, relationship table, or etching time per unit thickness described in the aforementioned embodiments, etc.

[0063] During the testing process, it is necessary to remove layers so that the delayered sample can be analyzed. The delayering method described above can be used to remove layers based on the structure of each layer of the sample to be delayered, and then the analysis can be performed. The delayering and analysis process can be executed iteratively until all the analysis is completed.

[0064] This invention enables the removal of gallium arsenide (GaAs) chips using a combination of physical and chemical methods, resulting in a more rational removal process and less damage to the GaAs layer.

[0065] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0066] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for removing layers from a gallium arsenide chip, characterized in that, include: A sample to be removed is identified. The sample to be removed includes a multilayer structure prepared by multiple non-planarization processes. The multilayer structure includes a gallium arsenide layer, a dielectric layer, a metal layer, and a passivation layer. The passivation layer is located on the surface of the sample to be removed, the metal layer is located below the passivation layer, the dielectric layer is located below the metal layer, and the gallium arsenide layer is located below the dielectric layer. The passivation layer is etched using plasma etching technology under the conditions of 50±5W power and CF4 / O2 / Ar gas for a first preset time to remove the passivation layer and expose the metal layer. The flow rate ratio of the CF4 / O2 / Ar gas is 30sccm / 15sccm / 10sccm. The first preset time is determined according to the thickness of the passivation layer. The thicker the passivation layer, the longer the first preset time. The metal layer is etched using a gold etching solution to remove the metal layer and expose the dielectric layer; The dielectric layer is etched using plasma etching technology under 50±5W power and CF4 / O2 / Ar gas conditions for a second preset time to remove the dielectric layer and obtain the de-layered sample. The second preset time is determined according to the thickness of the dielectric layer; the thicker the dielectric layer, the longer the second preset time.

2. The method according to claim 1, characterized in that, The gold etching solution consists of iodine, potassium iodide, and water.

3. The method according to claim 2, characterized in that, The ratio of iodine to potassium iodide in the gold etching solution is less than or equal to 1 / 2.

4. The method according to claim 3, characterized in that, The weight ratio of the components in the gold etching solution is: iodine: potassium iodide: water = 1:2:

200.

5. The method according to claim 2, characterized in that, The etching time of the metal layer using gold etching solution was controlled within 2 ± 0.5 minutes.

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