Layout structure of low-noise amplifier circuit, RF chip and RF front-end module

Abstract

This application discloses a low-noise amplifier circuit, an RF chip, and an RF front-end module. The low-noise amplifier circuit includes an amplifying transistor and a bias transistor. The amplifying transistor includes a first amplifying unit and a second amplifying unit arranged along a first direction. The first amplifying unit is a normally-on unit, and the second amplifying unit is turned on according to a corresponding gain level control signal. The bias transistor is connected to the amplifying transistor and includes a first bias unit and a second bias unit. The first bias unit and the second bias unit are arranged on both sides of the first amplifying unit along the first direction, wherein either the first bias unit or the second bias unit is disposed between the first amplifying unit and the second amplifying unit. By splitting the bias transistor into at least two bias units, the influence of process variations on the gain of the bias transistor and the amplifying transistor cancels each other out, thereby improving the gain accuracy of the low-noise amplifier circuit.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a layout structure of a low-noise amplifier circuit, a radio frequency chip, and a radio frequency front-end module. Background Technology

[0002] A low-noise amplifier (LNO) is an amplifier with a very low noise figure. In the radio frequency (RF) field, it is typically used as a preamplifier in the receiving channel. It can acquire extremely weak, uncertain signals from the antenna and then amplify those signals to a more usable level.

[0003] Generally, a low-noise amplifier includes a bias transistor and an amplifying transistor. The bias transistor provides a bias signal to the amplifying transistor, and the size of the bias transistor and the amplifying transistor affects the gain of the low-noise amplifier.

[0004] However, manufacturing processes often involve deviations that can affect the gain of low-noise amplifiers. Therefore, minimizing the impact of these deviations on the gain accuracy of low-noise amplifiers is a pressing issue that needs to be addressed. Summary of the Invention

[0005] This application proposes a layout structure, RF chip, and RF front-end module for a low-noise amplifier circuit, which can reduce the impact of process errors on the gain of the low-noise amplifier circuit and improve the gain accuracy of the low-noise amplifier circuit.

[0006] In a first aspect, embodiments of this application provide a low-noise amplifier circuit, including:

[0007] An amplifying transistor, the amplifying transistor including a first amplifying unit;

[0008] A bias transistor is connected to the amplifying transistor, and the bias transistor includes a first bias unit and a second bias unit, wherein the first bias unit is disposed on the side adjacent to the first amplifying unit; and the second bias unit is disposed at a distance from the first bias unit.

[0009] Secondly, embodiments of this application provide a low-noise amplifier circuit, including:

[0010] The amplification transistor is located in the second layout area;

[0011] The ninth dummy unit and the tenth dummy unit are distributed on both sides of the second layout area along a first direction or a second direction.

[0012] Thirdly, embodiments of this application provide a radio frequency chip, including a low-noise amplifier circuit as described in the first or second aspect above.

[0013] Fourthly, embodiments of this application provide a radio frequency front-end module, including the radio frequency chip as described in the third aspect.

[0014] The low-noise amplifier circuit, RF chip, and RF front-end module of this application improve the gain accuracy of the low-noise amplifier circuit by setting dummy units on both sides of the amplifier module to avoid process deviations in the amplifier module, or by splitting the bias transistor into at least two bias units and setting them on both sides of the normally-on amplifier unit, so that the process deviations of the normally-on amplifier unit and the process deviations of the bias transistor can cancel each other out. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A circuit diagram of a low-noise amplifier circuit provided in an embodiment of this application is shown.

[0017] Figure 2 A circuit layout schematic diagram of a low-noise amplifier circuit provided in an embodiment of this application is shown.

[0018] Figure 3 This paper shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0019] Figure 4 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0020] Figure 5 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0021] Figure 6 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0022] Figure 7 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0023] Figure 8 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0024] Figure 9 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0025] Figure 10 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0026] Figure 11 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0027] Figure 12 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0028] Figure 13 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0029] Figure 14 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0030] Figure 15 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0031] Figure 16 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0032] Figure 17 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0033] Figure 18 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0034] Figure 19 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0035] Figure 20 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0036] Figure 21 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0037] Figure 22 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0038] Figure 23 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0039] Figure 24This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0040] Figure 25 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0041] Figure 26 This shows another circuit layout schematic diagram of the low-noise amplifier circuit provided in an embodiment of this application.

[0042] Figure 27 A circuit diagram of an amplifying transistor in a low-noise amplifier circuit provided in an embodiment of this application is shown. Detailed Implementation

[0043] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0044] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. The term "multiple" refers to two or more. The term "and / or" refers to at least one of the listed multiple objects; for example, "A and / or B" can be any of the following three cases: including A but not B, including B but not A, or including both A and B.

[0045] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0046] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0047] With the development of communication technology and the increasing popularity of 5G (5th Generation Mobile Communication Technology), more stringent requirements have been placed on the performance specifications of radio frequency (RF) front-ends. Among them, the low-noise amplifier (LNA), as a core component of the RF front-end receiving channel, needs to acquire extremely weak signals from the antenna and amplify them; therefore, its gain factor is a very important parameter.

[0048] Generally, a low-noise amplifier (LNO) consists of a bias transistor and an amplification transistor. The bias transistor provides a bias signal to the amplification transistor, and the size ratio of the bias transistor to the amplification transistor affects the gain accuracy and consistency of the LNO. In related technologies, for ease of routing, the bias transistor and the amplification transistor are usually laid out separately during layout design. This leads to inconsistent process variations between the two, resulting in inaccurate gain coefficients and unsatisfactory gain consistency in the LNO. In particular, when the LNO design has multiple gain levels, the inaccurate gain difference between different gain levels is a very serious problem for LNO amplifiers.

[0049] To address the aforementioned issues, embodiments of this application provide a low-noise amplifier circuit, an RF chip, and an RF front-end module, which can reduce the impact of process variations on the gain accuracy of the low-noise amplifier circuit and improve the gain accuracy of the low-noise amplifier circuit. The following description will be provided in conjunction with the accompanying drawings.

[0050] The first aspect of this application provides a low-noise amplifier circuit 10, such as... Figure 1 As shown, the low-noise amplifier circuit 10 includes an amplifying transistor Ma and a bias transistor Mb. The first terminal of the amplifying transistor Ma is connected to the bias transistor Mb to receive the bias signal provided by the bias transistor Mb. Furthermore, the first terminal of the amplifying transistor Ma is also connected to the input terminal of the low-noise amplifier circuit 10 to receive the radio frequency input signal RF-in. The first terminal of the amplifying transistor Ma is also connected to the output terminal of the low-noise amplifier circuit 10 to output the amplified radio frequency output signal RF-out. The third terminal of the amplifying transistor Ma is grounded.

[0051] Optionally, the amplifying transistor Ma and the bias transistor Mb can be bipolar junction transistors (BJTs) or field-effect transistors (FETs). When the amplifying transistor Ma and the bias transistor Mb are BJTs, the first terminal is the base, the second terminal is the collector, and the third terminal is the emitter. When the amplifying transistor Ma and the bias transistor Mb are FETs, the first terminal is the gate, the second terminal is the source / drain, and the third terminal is the drain / source. Taking a FET as an example, the amplifying transistor Ma and the bias transistor Mb can be MOS (metal-oxide-semiconductor) transistors fabricated on a silicon substrate; or MOS transistors fabricated on an SOI (silicon-on-insulator) substrate. The amplifying transistor Ma can be composed of multiple amplifying units connected in series and parallel, and the bias transistor Mb can also be composed of multiple biasing units connected in series and parallel.

[0052] like Figure 1 As shown, the amplifying transistor Ma and the bias transistor Mb are connected to form a current mirror structure. Taking a MOSFET as an example, the output current Idd of the amplifying transistor Ma is the product of the reference current Iref of the bias transistor Mb and the mirror ratio. Since the gain accuracy of the amplifying transistor is related to the accuracy of the output current Idd, i.e., the accuracy of the mirror ratio, and the mirror ratio depends on the size ratio between the amplifying transistor Ma and the bias transistor Mb, inconsistent manufacturing process deviations between the amplifying transistor Ma and the bias transistor Mb will affect the gain accuracy of the low-noise amplifier circuit. For low-noise amplifiers with multiple gain levels, ensuring gain consistency requires good gain accuracy at each gain level, or at least consistent gain deviations across different gain levels.

[0053] For example, the size of the amplifying transistor Ma can refer to the width-to-length ratio of the MOS transistor when both the amplifying transistor Ma and the bias transistor Mb are MOS transistors.

[0054] As one implementation method, such as Figure 1 As shown, the amplifying transistor Ma and the bias transistor Mb can be connected via a bias resistor R. The bias resistor R exhibits high impedance to radio frequency signals, preventing leakage of the radio frequency signal to the bias transistor. Optionally, the bias resistor R may include one or more resistor units. The resistance value of the bias resistor R can be fixed or variable; for example, the resistance value of the bias resistor R can be adjusted by controlling the number of conducting resistor units. Exemplarily, a DC blocking capacitor C can also be provided at the input terminal of the low-noise amplifier circuit to prevent DC bias signals from leaking to the input port of the low-noise amplifier circuit.

[0055] It should be understood that, in the low-noise amplifier circuit of this application, in addition to... Figure 1In addition to the amplifying transistor Ma, bias transistor Mb, resistor R, and DC blocking capacitor C shown, other circuit elements can be added as needed. For example, the low-noise amplifier circuit can also include one or more capacitors, inductors, resistors, transistors, etc. These elements can be configured into one or more circuits, including but not limited to input matching circuits, output matching circuits, filtering circuits, bypass circuits, and switches, according to the circuit design requirements. This application does not impose any restrictions on this.

[0056] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram of the circuit layout of a low-noise amplifier circuit 10. (See diagram below.) Figure 2 As shown, the amplifying transistor includes a first amplifying unit Ma1, and the biasing transistor Mb includes a first biasing unit Mb1 and a second biasing unit Mb2. The first biasing unit Mb1 and the second biasing unit Mb2 are spaced apart, and the first biasing unit Mb1 is disposed on the side adjacent to the first amplifying unit Ma1.

[0057] In this embodiment, the first bias unit Mb1 and the second bias unit Mb2 are spaced apart, meaning that the first bias unit Mb1 and the second bias unit Mb2 are not arranged as a continuous whole, but as different units that are relatively independent in position. Optionally, the first bias unit Mb1 and the second bias unit Mb2 may be spaced apart by a certain distance or by at least one circuit unit. For example, the first bias unit Mb1 and the second bias unit Mb2 may be spaced apart by a first amplification unit Ma1 or other circuit units.

[0058] Taking a MOSFET as an example, the amplifying transistor and the bias transistor each include a gate, a source, and a drain. The gate, source, and drain are designed with interdigitated fingers, and the direction of the interdigitated fingers is the width direction of the transistor. In related technologies, all interdigitated fingers of the same electrode are arranged continuously in the same direction in a row. However, in this embodiment, the bias transistor Mb is divided into a first bias unit Mb1 and a second bias unit Mb2. For example, the gate, source, and drain of the bias transistor Mb can be divided into multiple segments, each segment including a certain number of interdigitated fingers. The interdigitated fingers of the same electrode are connected to each other, so that the first bias unit Mb1 and the second bias unit Mb2 are connected in parallel. Optionally, the number of interdigitated fingers at the gate of the first bias unit Mb1 and the second bias unit Mb2 can be the same or different. For example, the gate of the first bias unit Mb1 and the gate of the second bias unit Mb2 can each include 2-5 interdigitated fingers, and the size of each gate interdigitated finger is approximately equal. (The last sentence is a simplified explanation and can be left as is.) Figure 2 The bias transistor with 6 gate interdigitates is split into a first bias unit Mb1 and a second bias unit Mb2, each with 3 gate interdigitates.

[0059] Optionally, to achieve a uniform layout density of the bias transistors, the gate interdigitates of different bias units can be arranged along the same direction. These gate interdigitates can be arranged in the same row or multiple rows. For example, the first bias unit Mb1 and the second bias unit Mb2 each include at least two gate interdigitates, wherein at least two gate interdigitates in the first bias unit Mb1 are arranged along a first direction, and at least two gate interdigitates in the second bias unit Mb2 are also arranged along the first direction. When the second bias unit Mb2 is located on one side of the first bias unit Mb1 in the first direction, the gate interdigitates in the first bias unit Mb1 and the second bias unit Mb2 are arranged in a row. When the second bias unit Mb2 is located on one side of the first bias unit Mb1 in a second direction, the gate interdigitates in the first bias unit Mb1 and the second bias unit Mb2 are arranged in different rows.

[0060] In one implementation, the gate interdigitation direction in the first amplification unit is the same as that in the bias transistor, so as to make the layout of the low-noise amplifier circuit more orderly and the density more uniform.

[0061] During manufacturing, process deviations typically occur where circuit density changes significantly; therefore, the closer to the edge of the layout area, the greater the process deviation tends to be. In related technologies, the bias transistor is arranged continuously as a whole along a fixed direction, and the amplifying transistor is also arranged as a whole along the same direction as the bias transistor. Consequently, process deviations are often concentrated on either the bias transistor or the amplifying transistor, and the difference in their process deviations is significant, causing changes in their size ratio and thus affecting the gain of the low-noise amplifier. In particular, the size of the bias transistor Mb is usually smaller than that of the amplifying transistor Ma. When the process deviation on the bias transistor Mb is greater than that on the amplifying transistor Ma, the error in their size ratio will be further aggravated, with a particularly severe impact on gain accuracy and consistency.

[0062] In this embodiment, the smaller bias transistor Mb is divided into at least two bias units, and the at least two bias units are spaced apart. This avoids the concentration of process deviations on the bias transistor Mb. Moreover, the first bias unit Mb1 and the first amplification unit Ma1 are located close to each other, and their process deviations are also relatively close, having little impact on the size ratio. Therefore, the impact of their process deviations on the gain of the low-noise amplifier circuit can be offset to a certain extent, thereby improving the gain accuracy of the low-noise amplifier circuit.

[0063] In some embodiments, such as Figure 2As shown, the first bias unit Mb1 is disposed on one side of the first amplification unit Ma1 in the first direction, and the second bias unit Mb2 is disposed on the other side of the first amplification unit Ma1 in the first direction. In other words, the first bias unit Mb1 and the second bias unit Mb2 are distributed on both sides of the first amplification unit Ma1 along the first direction. For example, the first direction is the width direction of the bias transistor Mb. Taking a MOS transistor as an example, the width direction is the arrangement direction of the gate interdigitators.

[0064] In this embodiment, the first bias unit Mb1 and the second bias unit Mb2 are disposed on both sides of the first amplification unit Ma1. Since they are close to each other, the process deviations of the two bias units Mb1 and Mb2 are basically the same as the process deviations of the first amplification unit Ma1. The influence of the process deviations of the bias unit and the amplification unit on the gain can be basically completely canceled, which can effectively improve the gain accuracy of the low-noise amplifier circuit.

[0065] Optionally, when the low-noise amplifier circuit includes multiple gain levels, the amplifying transistor may further include one or more other amplifying units besides the first amplifying unit, such as a second or third amplifying unit. In this case, the first amplifying unit Ma1 can be configured as a normally-on unit, and the other amplifying units can be configured as normally-off units. For example, the first amplifying unit Ma1 is turned on at all gain levels, while the second and third amplifying units are turned on only at their corresponding gain levels. Each second / third amplifying unit may correspond to one or more gain levels. When there are multiple second / third amplifying units, the low-noise amplifier circuit can turn on the corresponding number of second / third amplifying units according to the received gain level control signal to adjust the gain level of the low-noise amplifier circuit 10. For example, when the low-noise amplifier circuit 10 is configured to the lowest gain level, only the first amplification unit Ma1 can be turned on, while all the second amplification units Ma2 are turned off; when the low-noise amplifier circuit 10 is configured to the second lowest gain level, the first amplification unit Ma1 and one second amplification unit Ma2 can be turned on; when the low-noise amplifier circuit 10 is configured to the highest gain level, the first amplification unit Ma1 and all the second amplification units Ma2 can be turned on. The bias current can be the same or different at different gain levels, and this application does not impose any restrictions on this.

[0066] By setting the first bias unit Mb1 and the second bias unit Mb2 on both sides of the normally-on first amplification unit Ma1, the effects of the process deviations of the first bias unit Mb1 and the second bias unit Mb2 can be offset by the first amplification unit Ma1, regardless of how the gain level of the low-noise amplifier circuit is switched. This can improve the gain accuracy and consistency of the low-noise amplifier to a greater extent.

[0067] As one implementation method, such as Figure 3 As shown, the low-noise amplifier circuit also includes a second amplification unit Ma2. When there are one or more second amplification units Ma2, the first bias unit Mb1, the first amplification unit Ma1, and the second bias unit Mb2 are sequentially disposed on one side of the second amplification unit Ma2 in the first direction. When there are multiple second amplification units Ma2, the multiple second amplification units Ma2 can be disposed on the same side of the first amplification unit Ma1, which facilitates the wiring arrangement between the amplification transistor and the bias transistor.

[0068] For example, such as Figure 4 As shown, the first bias unit Mb1 is located on the side of the first amplification unit Ma1 away from the second amplification unit Ma2, and the second bias unit Mb2 is located between the first amplification unit Ma1 and the second amplification unit Ma2. By interleaving at least one bias unit between different amplification units, the process deviations during manufacturing can be more evenly distributed on the amplification transistor and the bias transistor, making the process deviations of the amplification transistor and the bias transistor closer, thereby offsetting the impact of process deviations on gain.

[0069] Since the first bias unit Mb1 is relatively close to the edge of the layout area, in order to reduce the process deviation of the first bias unit Mb1, the low-noise amplifier circuit also provides a first dummy unit Dummy1. The first dummy unit Dummy1 is located on the side of the first bias unit Mb1 that is far away from the first amplification unit Ma1, and is closer to the edge of the layout area than the first bias unit Mb1. This allows most of the process deviation to occur in the first dummy unit Dummy1, reducing the process deviation of the first bias unit Mb1 and other units, further reducing the impact of process deviation on the gain of the low-noise amplifier circuit, and improving the gain accuracy and consistency of the low-noise amplifier circuit.

[0070] Optionally, the size of the first dummy unit Dummy1 is greater than or equal to the size of the first bias unit Mb1. For example, the width of the first dummy unit Dummy1 is greater than or equal to the width of the first bias unit Mb1. This allows process deviations to be concentrated more in the first dummy unit Dummy1, ensuring that the first bias unit Mb1 and other units maintain relatively accurate dimensions. Here, the width refers to the dimension in the first direction X.

[0071] As one implementation method, such as Figure 5 and Figure 6As shown, the low-noise amplifier circuit also includes a second dummy unit Dummy2, which is disposed on the side of the second amplification unit Ma2 away from the second bias circuit Mb2. When the low-noise amplifier circuit includes multiple second amplification units Ma2, the second dummy unit Dummy2 can be disposed on the side of all second amplification units Ma2 away from the second bias circuit Mb2, or in other words, all second amplification units Ma2 are located on the same side of the second dummy unit Dummy2. By disposing of the second dummy unit Dummy2 outside the second amplification unit Ma2, the embodiments of this application can significantly reduce or even avoid process deviations in the second amplification unit Ma2, thereby further improving the gain accuracy and consistency of the low-noise amplifier circuit. When the low-noise amplifier circuit is simultaneously provided with the first dummy unit Dummy1 and the second dummy unit Dummy2, the amplification transistor Ma and the bias transistor Mb are sandwiched between the first dummy unit Dummy1 and the second dummy unit Dummy2, and the probability of process deviations in each unit of the amplification transistor Ma and the bias transistor Mb is greatly reduced, thereby effectively avoiding gain errors caused by process deviations, and further improving the gain accuracy of the low-noise amplifier circuit. When a low-noise amplifier circuit has multiple gain levels, it can also optimize the consistency of the output current Idd of the amplifying transistor Ma under different gain levels, thereby improving the gain consistency of the low-noise amplifier circuit.

[0072] It is understood that in some embodiments, where the size of the bias transistor allows, the bias transistor can be further divided into more bias units, such as three or more bias units, and these additional bias units can be interleaved with different amplification units. This can further offset the impact of process errors on gain. For example, when the overall size of the bias transistor is large, the number of bias units can be the same as the number of amplification units, with one bias unit placed between every two amplification units. When the overall size of the bias transistor is small, the number of bias units can, for example, be less than the number of amplification units. For example, the bias transistor can be divided to the width of 2-3 gate interdigitates per bias unit. For instance, when the overall size of the bias transistor is designed to be 10 gate interdigitates, the bias transistor can be divided into 3-5 bias units and interleaved with multiple amplification units.

[0073] As one implementation method, such as Figure 7As shown, when there are at least two second amplification units Ma2, the bias transistor Mb also includes a third bias unit Mb3, which is disposed between two adjacent second amplification units. Due to their proximity, the process deviations of the two second amplification units Ma2 and the third bias unit Mb3 are essentially the same. The influence of these process deviations on the gain is essentially canceled out. Therefore, when the low-noise amplifier circuit is configured to conduct at least some of the gain levels of the second amplification units Ma2, this embodiment can further cancel out the influence of process deviations on the gain, making the gain difference between different gain levels more accurate.

[0074] In one implementation, the low-noise amplifier has multiple gain levels. The first amplification unit Ma1 is a normally active amplification unit, conducting at all gain levels. The second amplification unit Ma2 is a non-normally active amplification unit, activated only according to the corresponding gain level control signal. Each second amplification unit can correspond to one or more gain levels and can conduct at one or more gain levels. When the number of third bias units Mb3 is at least two fewer than the number of second amplification units Ma1, the third bias units Mb3 are positioned between the two second amplification units with more corresponding gain levels. This is to compensate for the effects of process variations between the bias transistor and the amplification transistor across as many gain levels as possible.

[0075] In some embodiments, when the number of second amplification units Ma2 is multiple, such as Figure 8 As shown, the first amplification unit Ma1 can be disposed between two of the second amplification units Ma2, or in other words, multiple second amplification units Ma2 are distributed along the first direction X on both sides of the first amplification unit Ma1. Specifically, some of the second amplification units Ma2 are disposed on the side of the first bias unit Mb1 away from the first amplification unit Ma1, and other second amplification units Ma2 are disposed on the side of the second bias unit Mb2 away from the first amplification unit Ma1. In this embodiment, the first amplification unit Ma1 is located away from the edge of the layout area. The bias transistor is split into two bias units and disposed on both sides of the first amplification unit Ma1, so that the bias units are away from the edge of the low-noise amplifier circuit layout area, thereby greatly reducing the probability of process deviations in the bias transistor. Even if there are still a small amount of process deviations on the two bias units, their impact on the gain can be offset by the process deviations of the first amplification unit Ma1, thus effectively reducing the mismatch between the bias transistor and the amplification transistor and improving the gain consistency of the low-noise amplifier circuit.

[0076] In one implementation, the first amplification unit Ma1 is a normally-on amplification unit, meaning it is turned on at all gain levels. Placing the normally-on first amplification unit Ma1 among multiple second amplification units, and positioning it close to the center of the layout area, not only offsets the effects of process variations in the bias transistors at the maximum number of gain levels, but also significantly reduces the probability of process variations in the normally-on amplification unit. This method improves gain accuracy and consistency more effectively than placing the normally-on first amplification unit Ma1 at the edge of the layout area.

[0077] As one implementation, when there are multiple second amplification units Ma2, the second amplification units Ma2 with more corresponding gain levels can be placed closer to the center of the low-noise amplifier circuit layout area to optimize the consistency of Idd current under as many gain levels as possible, thereby optimizing the gain consistency.

[0078] As one implementation method, such as Figure 9 As shown, the bias transistor Mb further includes at least one fourth bias unit Mb4, which is disposed on the side of the second amplification unit away from the first bias unit and / or the second bias unit. Optionally, the number of fourth bias units Mb4 can be equal to or less than the number of second amplification units Ma2. When the number of fourth bias units Mb4 is equal to the number of second amplification units Ma2, one fourth bias unit Mb4 can be disposed on the side of each second amplification unit Ma2 away from the first amplification unit Ma1, that is, the bias units and amplification units are staggered, so that there are bias units on both sides of each amplification unit. In this way, the influence of process deviation on the gain of each amplification unit can be offset by the influence of the bias units on both sides, thereby maximizing the Idd current consistency and optimizing the gain consistency.

[0079] Optionally, when the number of fourth bias units Mb4 is less than the number of second amplification units Ma2, the fourth bias units Mb4 are placed next to the second amplification units Ma2 with the most corresponding gain levels. For example, when there is only one fourth bias unit Mb4, it is placed to the side of the second amplification unit Ma2 with the most corresponding gain levels. In this way, at most gain levels, the effects of the process deviations between the second amplification unit Ma2 and the fourth bias unit Mb4 can cancel each other out.

[0080] In some embodiments, dummy units can be provided to make the layout density inside the low-noise amplifier circuit more uniform.

[0081] In some implementations, at least one dummy unit, such as a fourth dummy unit and / or a fifth dummy unit, may be provided on at least one side of the fourth bias unit Mb4.

[0082] As one implementation method, such as Figure 10 As shown, the low-noise amplifier circuit also includes a third dummy unit 3, which is disposed on the side of the fourth bias unit Mb4 away from the second amplification unit Ma2. Optionally, the number of third dummy units 3 can be one or more. The number of third dummy units 3 can be the same as the number of fourth bias units Mb4, for example, a third dummy unit 3 can be disposed on one side of each fourth bias unit Mb4. The number of third dummy units 3 can also be less than the number of fourth bias units Mb4, for example, a third dummy unit 3 can be disposed on only one side of some of the fourth bias units Mb4. For example, as... Figure 10 As shown, when there are two third dummy units (Dummy3), they can be positioned on either side furthest from the first amplification unit Ma1, i.e., at the edge of the transistor layout area. This ensures that all units in the amplification transistor Ma and the bias transistor Mb are far from the edge, significantly reducing the probability of process deviations in the amplification transistor Ma and the bias transistor Mb, and minimizing mismatch between them, thereby optimizing the gain consistency of the low-noise amplifier circuit. Optionally, the size of the third dummy unit Dummy3 can be greater than or equal to the size of the fourth bias unit Mb4.

[0083] As an optional implementation method, such as Figure 11 As shown, the low-noise amplifier circuit also includes a fourth dummy unit 4, which is disposed on the side of the fourth bias unit Mb4 near the second amplification unit Ma2. Optionally, the number of fourth dummy units 4 can be one or more. The number of fourth dummy units 4 can be the same as the number of fourth bias units Mb4, for example, a fourth dummy unit 4 can be disposed on the side of each fourth bias unit Mb4 near the second amplification unit Ma2. The number of fourth dummy units 4 can also be less than the number of fourth bias units Mb4, for example, a fourth dummy unit 4 can be disposed only on the side of some fourth bias units Mb4 near the second amplification unit. By adding fourth dummy units 4, at least some of the fourth bias units Mb4 are disposed between two dummy units, thereby making the layout density of the area where the fourth bias units Mb4 are located more uniform and reducing the probability of process deviations in the fourth bias units Mb4.

[0084] Alternatively, the fourth dummy unit Dummy4 has the same size as the third dummy unit Dummy3, and both of their sizes are greater than or equal to the size of the fourth bias unit Mb4.

[0085] In some implementations, a pair of dummy units may be provided on both sides of the first bias unit Mb1 and / or the second bias unit Mb2, such as the fifth dummy unit Dummy5 and / or the sixth dummy unit Dummy6.

[0086] For example, such as Figure 12 and Figure 13 As shown, the low-noise amplifier circuit further includes at least two fifth dummy units (Dummy5) and at least two sixth dummy units (Dummy6), wherein the at least two fifth dummy units (Dummy5) are disposed on both sides of the first bias unit Mb1; and the at least two sixth dummy units (Dummy6) are disposed on both sides of the second bias unit. Optionally, the size of each fifth dummy unit (Dummy5) is the same as the size of the first bias unit Mb1, and the size of each sixth dummy unit (Dummy6) is the same as the size of the second bias unit Mb2. By distributing corresponding dummy units on both sides of the first bias unit Mb1 and the second bias unit Mb2, the layout density of the regions where the first bias unit Mb1 and the second bias unit Mb2 are located can be made more uniform, and the finger topography of the bias transistors can be made more consistent, thereby reducing the probability of process deviations in the first bias unit Mb1 and the second bias unit Mb2, and further optimizing the gain consistency of the low-noise amplifier circuit.

[0087] In some embodiments, in addition to the first amplification unit Ma1, the amplification transistor also includes a third amplification unit Ma3, wherein the third amplification unit Ma3 is located on one or both sides of the first amplification unit Ma1 in the second direction Y.

[0088] Optionally, the number of third amplification units Ma3 can be one or more. When there is only one third amplification unit Ma3, it is located on one side of the first amplification unit Ma1 in the second direction Y. When there are multiple third amplification units Ma3, they can be located on the same side of the first amplification unit Ma1 in the second direction Y, or they can be distributed on both sides of the first amplification unit Ma1 along the second direction Y. Here, the first direction X is the width direction of the transistor. Taking a MOSFET as an example, the first direction is the arrangement direction of the gate interdigitates. The second direction Y is a direction approximately perpendicular to the first direction X, such as the length direction of the gate interdigitates.

[0089] When the amplifying transistor Ma also includes a third amplifying unit Ma3, one biasing unit is disposed on one side of the first amplifying unit Ma1, and the other biasing unit is disposed on one side of the third amplifying unit Ma1. For example, as shown... Figure 14 As shown, the first bias unit Mb1 is disposed on one side of the first amplification unit Ma1 in the first direction X, and the second bias unit Mb2 is disposed on one side of the third amplification unit Ma3 in the first direction X. Since the first bias unit Mb1 and the first amplification unit Ma1 are located close to each other, the influence of their process deviations on the gain can cancel each other out; the second bias unit Mb2 and the third amplification unit Ma3 are located close to each other, and the influence of their process deviations on the gain can cancel each other out, thereby improving the gain accuracy and consistency of the low-noise amplifier circuit.

[0090] Optionally, the first bias unit Mb1 and the second bias unit Mb2 can be arranged relative to each other in the second direction, such as... Figure 14 As shown in (a), this facilitates the connection between the first bias unit Mb1 and the second bias unit Mb2.

[0091] Optionally, the first bias unit Mb1 and the second bias unit Mb2 can be staggered in the second direction, such as... Figure 14 As shown in (b), this allows the process deviations of the amplifying transistor to be closer to those of the bias transistor, thus better offsetting the impact on gain and further optimizing gain consistency.

[0092] As one implementation method, such as Figure 15 , Figure 16 As shown, the number of second bias units Mb2 can be at least two, wherein each second bias unit Mb2 is disposed on one side of a third amplification unit Ma3 in the first direction. Optionally, the number of second bias units Mb2 is less than or equal to the number of third amplification units Ma3.

[0093] When the number of second bias units Mb2 is equal to the number of third amplification units Ma3, such as Figure 15 As shown, a second bias unit Mb2 is provided next to each third amplification unit Ma3. In this way, the effects of process errors of each amplification unit and its adjacent bias unit can be canceled out, which can greatly improve the gain accuracy and consistency of the low-noise amplifier circuit.

[0094] When the bias transistor is small and the number of available bias units is less than the number of gain levels in the low-noise amplifier, and the number of second bias units Mb2 is less than the number of third amplification units Ma3, a second bias unit Mb2 can be placed next to some of the third amplification units Ma3. Optionally, each third amplification unit Ma3 corresponds to one or more gain levels. When the number of second bias units Mb2 is less than the number of third amplification units Ma3, the second bias units Mb2 are placed next to the third amplification units Ma3 with more corresponding gain levels to offset the impact of process errors on gain across as many gain levels as possible.

[0095] As one implementation method, such as Figure 16 As shown, the low-noise amplifier circuit further includes at least one seventh dummy unit 7; the number of third amplification units is at least two, the at least two third amplification units are arranged along the second direction, and at least one of the third amplification units has the seventh dummy unit 7 disposed on one side of the first direction. For example, when the number of second bias units Mb2 is less than the number of third amplification units Ma3, some third bias units Mb2 do not have second bias units Mb2 disposed in the first direction. In this case, a seventh dummy unit can be disposed in the first direction of the third bias units Mb2, so that the layout area of ​​the low-noise amplifier circuit is approximately rectangular, making the transistor density in the layout more uniform and the consistency of the finger topography better, thereby reducing process deviation and further improving the consistency of Idd current and gain consistency.

[0096] In one implementation, when there are multiple third amplification units Ma3, and each third amplification unit Ma3 corresponds to one or more gain levels, the third amplification units Ma3 with more corresponding gain levels can be arranged closer to the center of the layout area of ​​the low-noise amplifier circuit, so as to avoid or reduce the generation of process deviations under as many gain levels as possible.

[0097] As one implementation method, such as Figure 17 , Figure 18As shown, the low-noise amplifier circuit includes a first amplification unit Ma1, at least one second amplification unit Ma2, and at least two third amplification units Ma3. The second amplification units Ma2 are positioned along a first direction X of the first amplification unit Ma1, and the third amplification units Ma3 are positioned along a second direction Y of the first amplification unit Ma1. The number of third amplification units Ma3 can be greater than the number of second amplification units Ma2. At least two third amplification units Ma3 can be arranged along the first direction X and distributed in an array with the first and second amplification units Ma1 and Ma2. This allows the layout area of ​​the low-noise amplifier circuit to be approximately rectangular, resulting in a more uniform transistor density and better consistency in the finger topography, thereby reducing process deviations and further improving the consistency of Idd current and gain.

[0098] Optionally, such as Figure 17 As shown, the first bias unit Mb1 can be disposed between the first amplification unit Ma1 and one of the second amplification units Ma2, so that the first bias unit Mb1 is far from the edge of the layout area, avoiding or reducing process deviations on the first bias unit Mb1. Since the size of the bias unit is small, its process deviation has a relatively large impact on the gain. Therefore, by reducing the process deviation on the bias unit, the mismatch between the bias transistor and the amplification transistor can be effectively reduced, improving the accuracy and consistency of the gain. Similar to the first bias unit Mb1, the second bias unit Mb2 can also be disposed between the two third amplification units Ma4 to reduce the mismatch between the bias transistor and the amplification transistor, improving the accuracy and consistency of the gain.

[0099] Optionally, such as Figure 18 As shown, the first bias unit Mb1 can also be set on the side of the first amplification unit Ma1 near the edge of the layout area to facilitate the routing of circuit traces; similarly, the second bias unit Mb2 can also be set on the side of the third amplification unit Ma3 near the edge of the layout area.

[0100] Optionally, in this embodiment, the first bias unit Mb1 and any one of the second bias units Mb2 can be opposite to each other or offset in the second direction Y. When the first bias unit Mb1 and the second bias unit Mb2 are opposite to each other in the second direction Y, it is convenient for them to be connected in parallel. When the first bias unit Mb1 and the second bias unit Mb2 are offset in the second direction Y, it is possible to better compensate for the gain error caused by process deviations and further optimize the gain consistency.

[0101] In one implementation, the first amplification unit Ma1 is a normally-on amplification unit, while other amplification units besides the first amplification unit, such as the second amplification unit Ma2 and the third amplification unit Ma3, are not normally-on amplification units, only conducting at certain gain levels. To avoid process deviations at as many gain levels as possible, the second amplification unit Ma2 and the third amplification unit Ma3, which correspond to more gain levels, can optionally be placed closer to the center of the low-noise amplifier circuit layout area.

[0102] In some embodiments, to avoid or reduce process deviations in the amplifying transistor and the bias transistor, some dummy units may be provided around the amplifying transistor and the bias transistor.

[0103] As one implementation method, such as Figure 19 , Figure 20 As shown, the low-noise amplifier circuit also includes two eighth dummy units (Dummy 8), which are arranged opposite each other in a first direction and / or in a second direction. The bias transistor Mb and the amplifying transistor Ma are sandwiched between the two oppositely arranged eighth dummy units (Dummy 8). By adding the eighth dummy units (Dummy 8) on the periphery, the amplifying transistor Ma and the bias transistor Mb can be located in a region with uniform layout density in at least one direction. This results in better consistency of the finger strip morphology in the regions where the amplifying transistor Ma and the bias transistor Mb are located, effectively avoiding or reducing process deviations and improving the gain accuracy and consistency of the low-noise amplifier circuit.

[0104] In one implementation, the bias transistor and the amplification transistor are located in the first layout region, such as... Figure 20 As shown, there are four eighth dummy units (Dummy 8), which are arranged around the perimeter of the first layout area. This results in a more uniform layout density and more consistent finger morphology in the areas where the amplifying transistor Ma and the bias transistor Mb are located, thereby further avoiding or reducing process deviations and improving the gain accuracy and consistency of the low-noise amplifier circuit.

[0105] Optionally, the size of the eighth dummy unit Dummy8 in the second direction Y can be equal to the size of the first layout region in the second direction, thereby making the layout density of the first layout region more uniform and the morphology of the fingers more consistent.

[0106] Optionally, for the two eighth dummy units 8 arranged opposite each other in the first direction of the first layout region, their size in the first direction can be greater than or equal to the size of the first layout region, so as to cover the projection of the first amplification unit Ma1 in the width direction. This can greatly reduce or even avoid the process deviation between the amplification transistor Ma and the bias transistor Mb. When there are some other dummy units in the first layout region, the eighth dummy units 8 also cover the projection of these dummy units in the width direction, so as to make the layout density of the entire low-noise amplifier circuit more uniform and the finger shape more consistent, thereby reducing the probability of process deviation occurring on the amplification transistor and the bias transistor.

[0107] Optionally, each eighth dummy unit Dummy8 can be an independent unit, wherein some or all of the eighth dummy units Dummy8 can also be interconnected to form a structure such as... Figure 21 The application does not limit the scope of the work as a whole.

[0108] Similarly, any dummy cell Dummy8 can be either a continuous whole or divided into multiple sub-cells. Taking a MOSFET as an example, if the gate interdigitation / source interdigitation / drain interdigitation of the eighth dummy cell Dummy8 is continuously arranged in one direction, then the eighth dummy cell Dummy8 can be considered a whole. If the gate interdigitation / source interdigitation / drain interdigitation of the eighth dummy cell Dummy8 is divided into multiple discontinuous segments, then each segment can be considered a sub-cell. For example, as... Figure 22 As shown, the eighth dummy unit Dummy8 includes multiple sub-units. Different sub-units are respectively opposite to different amplification units or bias units or dummy units sandwiched between amplification units and bias units. This makes the layout density around the amplification units and bias units more uniform and the finger morphology more consistent.

[0109] In some embodiments, such as Figure 23 and Figure 24 As shown, the low-noise amplifier circuit 10 includes an amplifying transistor Ma, a ninth dummy unit 9, and a tenth dummy unit 10. The amplifying transistor Ma is disposed in the second layout region 101. The ninth dummy unit 9 and the tenth dummy unit 10 are distributed on both sides of the second layout region 101 along a first direction X or a second direction Y. By adding dummy units on both sides of the second layout region 101, process deviations of the amplifying transistor Ma can be avoided or reduced, thereby improving the gain accuracy of the low-noise amplifier circuit. When the amplifying transistor Ma includes multiple amplification units, i.e., when the low-noise amplifier circuit has multiple gain levels, the consistency of gain at different gain levels can also be improved.

[0110] Alternatively, the amplifying transistor Ma can be current-biased or voltage-biased.

[0111] When the amplifying transistor Ma is voltage-biased, the low-noise amplifier circuit 10 may not require a bias transistor. In this case, the amplifying transistor Ma can directly receive the bias voltage, which can be provided by other bias circuits, or it can be the supply voltage Vdd or a voltage obtained by dividing the supply voltage Vdd. This application does not limit this. When voltage biasing is used, the accuracy of the output current Idd of the amplifying transistor Ma is related to its dimensional accuracy. Therefore, reducing the process deviation on the amplifying transistor Ma can also improve the gain accuracy of the low-noise amplifier circuit. When the low-noise amplifier circuit has multiple gain levels, it can also improve the consistency of the output current Idd and the gain consistency at different gain levels.

[0112] In one implementation, the amplifying transistor Ma employs a current-biased method. The low-noise amplifier circuit 10 also includes a bias transistor Mb, which is disposed in the second layout region 101 and connected to the amplifying transistor Ma. By placing the bias transistor Mb and the amplifying transistor Ma together in the second layout region 101, the mismatch between the bias transistor Mb and the amplifying transistor Ma can be reduced, improving the accuracy of the output current Idd of the amplifying transistor Ma, thereby optimizing the gain accuracy of the low-noise amplifier circuit. When the amplifying transistor Ma has multiple gain levels, the accuracy of the output current Idd at different gain levels can also be improved, thereby optimizing the gain consistency of the low-noise amplifier circuit 10.

[0113] For example, such as Figure 23 As shown, when the ninth dummy unit 9 and the tenth dummy unit 10 are distributed along the second direction Y on both sides of the second layout region 101, the width of the ninth dummy unit 9 and the width of the tenth dummy unit 10 are greater than or equal to the width of the second layout region 101, and cover the projection of the second layout region 101 in the width direction. Here, width refers to the dimension along the first direction X, which is the first direction X. Optionally, the dimensions of the ninth dummy unit 9 and the tenth dummy unit 10 in the second direction Y can be the same or different.

[0114] For example, such as Figure 24 As shown, when the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are distributed on both sides of the amplification module along the first direction X, the lengths of the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are greater than or equal to the length of the amplification module, and they cover the projection of the amplification module 101 in the length direction. Here, length refers to the dimension along the second direction Y, which is the second direction Y.

[0115] Optionally, similar to the eighth dummy unit Dummy8, either the ninth dummy unit Dummy9 or the tenth dummy unit Dummy10 in this embodiment can be a continuous whole or can be divided into multiple discontinuous sub-units.

[0116] As one implementation method, such as Figure 25 As shown, the dummy module also includes an eleventh dummy unit and a twelfth dummy unit; wherein the eleventh dummy unit Dummy11, the twelfth dummy unit Dummy12, and the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are arranged around the second layout area 101. For example, if the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are arranged along the first direction X on both sides of the second layout area 101, then the eleventh dummy unit Dummy11 and the twelfth dummy unit Dummy12 are arranged along the second direction Y on both sides of the second layout area 101. If the ninth dummy unit Dummy9 and the tenth dummy unit Dummy10 are arranged along the second direction Y on both sides of the second layout area 101, then the eleventh dummy unit Dummy11 and the twelfth dummy unit Dummy12 are arranged along the first direction X on both sides of the second layout area 101.

[0117] Optionally, similar to the plurality of eighth dummy units 8, the ninth dummy unit 9, the tenth dummy unit 10, the eleventh dummy unit 11, and the twelfth dummy unit 12 can be dummy units that are spaced apart from each other and are discontinuous. Alternatively, at least some of these dummy units can be arranged continuously. For example, the four can be arranged continuously to form a loop-shaped whole surrounding the second layout area 101.

[0118] In this embodiment, the amplifying transistor Ma may include at least one amplifying unit, such as at least a first amplifying unit Ma1, and may also include at least one of a second amplifying unit Ma2 and a third amplifying unit Ma3. The biasing transistor Mb may include at least two biasing units, such as at least one of a second biasing unit Mb2, a third biasing unit Mb3, and a fourth biasing unit Mb4, and a first biasing unit Mb1.

[0119] For details on the specific implementation methods of each bias unit and each amplification unit, please refer to [reference needed]. Figures 2-22 As mentioned in the previous text, it will not be repeated here.

[0120] It is understood that in the low-noise amplifier circuit of this application embodiment, the number of amplifying transistors can be one or more, and similarly, the number of bias transistors can be one or more. This application does not limit the number of amplifying transistors or bias transistors, as long as at least one amplifying transistor and its corresponding bias transistor adopt the layout of any of the above embodiments.

[0121] As one implementation, when a low-noise amplifier circuit includes at least two amplifying transistors, if the two transistors have different dimensions in a second direction, they can be arranged along the length of the transistor. Taking a MOSFET as an example, when the gate lengths of the two amplifying units are different, arranging them along the gate width direction would result in an irregular shape and uneven density in the layout area. However, arranging them along the gate length direction, even with different gate widths, allows for the splitting or addition of dummy units, making the layout area roughly rectangular. This results in more uniform density and more consistent finger morphology within the layout area, reducing the likelihood of process deviations. For example, two amplifying transistors can be connected to form a common-source, common-gate structure. If the gate lengths of the two transistors are different, one transistor can be positioned in the second direction (i.e., the gate length direction) of the other. This improves the voltage gain of the low-noise amplifier circuit while avoiding or reducing the gain impact caused by process errors.

[0122] As one implementation, when multiple amplifying transistors are arranged along the second direction, the second layout region can be divided into multiple sub-regions arranged along the second direction, for example... Figure 26 The diagram shows a first sub-region and a second sub-region. Each sub-region corresponds to at least one amplifying transistor, which is disposed within the corresponding sub-region. If the amplifying transistor uses a current-biased method, its corresponding bias transistor is also disposed in the same sub-region. Furthermore, when different sub-regions have different dimensions along the second direction, one or more dummy units can be disposed between adjacent sub-regions to make the layout density around each sub-region similar to or consistent with the layout density of that sub-region, thereby avoiding process deviations in the amplifying transistors and their bias transistors within the sub-regions. For example, the low-noise amplifier circuit also includes at least one thirteenth dummy unit (Dummy 13), which is disposed in the second layout region and located between two adjacent sub-regions. For example, as shown... Figure 26As shown, a fourteenth dummy unit (Dummy 14) is also provided between the first and second sub-regions. The thirteenth dummy unit (Dummy 14) is adjacent to the fourteenth dummy unit (Dummy 14), and the size of the thirteenth dummy unit (Dummy 13) can be the same as the size of its adjacent sub-region, such as the first sub-region, to make the layout density of the first sub-region closer to its surroundings. Similarly, the size of the fourteenth dummy unit (Dummy 14) can be the same as the size of its adjacent sub-region, such as the second sub-region, to make the layout density of the second sub-region closer to its surroundings. This further improves the gain accuracy of the low-noise amplifier.

[0123] As one implementation method, more dummy units can be set in the second layout area. For example, in some sub-areas, at least one of the second dummy unit Dummy2, the third dummy unit Dummy3, the fourth dummy unit Dummy4, the fifth dummy unit Dummy5, ​​the sixth dummy unit Dummy6, and the seventh dummy unit Dummy7 mentioned in the previous embodiments can be set. The specific manner of these dummy units can be referred to above and will not be repeated here.

[0124] It is understood that the aforementioned dummy units can have the same structure as the amplification or bias units, such as including a gate, source, and drain. However, unlike the amplification and bias units, the dummy units are not connected to the circuit and do not participate in the operation of the low-noise amplifier circuit. It is understood that since the dummy units do not participate in the operation of the low-noise amplifier circuit, this application does not restrict the electrical connection relationship between the source, drain, and gate of the dummy units, as long as it does not affect the operation of the low-noise amplifier circuit. For example, the source, drain, and gate of each dummy unit can be set to a floating state, not connected to other transistors or traces in the low-noise amplifier circuit. Furthermore, the source, drain, and gate of each dummy unit can be shorted to each other or grounded, etc.

[0125] Optionally, the different amplifying transistors may use the same or different biasing methods. At least some of the amplifying transistors are current-biased and connected to corresponding biasing transistors, and the amplifying transistors using at least some current biasing and their biasing transistors are biased in the following manner: Figure 2-25 The layout can be adopted using any of the above embodiments.

[0126] Optionally, some of the amplifying transistors in the low-noise amplifier circuit can be voltage-biased, allowing them to directly receive a bias voltage without needing to be connected to a bias transistor. This bias voltage can be provided by other bias circuits, or it can be the supply voltage Vdd or a voltage obtained by dividing the supply voltage Vdd; this application does not limit this.

[0127] For example, when two amplifying transistors are connected to form a cascode structure, one amplifying transistor Ma in the cascode structure is connected to the bias transistor Mb, and the other amplifying transistor in the cascode structure receives the bias voltage.

[0128] Alternatively, the low-noise amplifier circuit includes at least two bias transistors, with the two amplifying transistors Ma in the cascode structure connected to their respective bias transistors Mb.

[0129] As an example, such as Figure 26 As shown, the low-noise amplifier circuit includes an amplifying transistor Ma, an amplifying transistor Mc, and a bias transistor Mb, wherein the amplifying transistor Ma is connected to the bias transistor Mb, and the bias transistor Mb provides bias to the amplifying transistor Ma. The amplifying transistor Ma and the bias transistor Mb can adopt the layout described in any of the embodiments above. The amplifying transistor Mc is connected to the amplifying transistor Ma to form a common-source, common-gate structure. In this example, the amplifying transistor Mc is voltage biased, and its gate directly receives the bias power supply Vbias without being connected to the bias transistor.

[0130] In other implementations, the amplifying transistor Mc can also be current biased, and its gate can be connected to another bias transistor. The layout between the bias transistor and the amplifying transistor Mc can refer to the layout between the bias transistor Mb and the amplifying transistor Ma, or it can be different.

[0131] It should be noted that the embodiments of this application do not limit the circuit architecture of the low-noise amplifier circuit. For example, taking the use of MOSFETs as an example, the low-noise amplifier circuit of the embodiments of this application can adopt architectures including but not limited to the following: common gate architecture, conventional common source common gate architecture, folded common source common gate architecture, negative feedback architecture, distributed architecture, architecture with source degradation inductor, architecture based on GM boost technology, etc.

[0132] A third aspect of this application also provides an RF chip that may include a low-noise amplifier circuit as described in any of the above embodiments. The low-noise amplifier circuit in this chip avoids process deviations by providing dummy units on both sides of the amplifying transistor layout region, or by splitting the bias transistor into at least two bias units spaced apart. This prevents process deviations from concentrating on the bias transistors. Furthermore, since the bias units are located close to the amplifying units, the effects of their process deviations on the gain of the low-noise amplifier circuit can be mutually offset to a certain extent, thereby improving the gain accuracy of the low-noise amplifier circuit. When the low-noise amplifier circuit has multiple gain levels, it can also optimize the consistency of the output current Idd of the amplifying transistor Ma at different gain levels, thereby improving the gain consistency of the low-noise amplifier circuit.

[0133] The fourth aspect of this application also provides a radio frequency (RF) front-end module. An RF front-end module is a component that integrates two or more discrete devices, such as RF switches, low-noise amplifiers, filters, duplexers, and power amplifiers, into a single independent module. This improves integration and hardware performance while miniaturizing the device. Specifically, the RF front-end module can be applied to 4G and 5G communication devices such as smartphones, tablets, and smartwatches.

[0134] The RF front-end module of this application embodiment may include the aforementioned chip, or include a low-noise amplifier circuit as described in any of the above embodiments. The low-noise amplifier circuit in this RF front-end module avoids process deviations by setting dummy units on both sides of the amplifying transistor layout area, or by splitting the bias transistor into at least two bias units, with the at least two bias units spaced apart. This prevents process deviations from concentrating on the bias transistors. Furthermore, since the bias units are located close to the amplifying units, the impact of their process deviations on the gain of the low-noise amplifier circuit can be mutually canceled to a certain extent, thereby improving the gain accuracy of the low-noise amplifier circuit. When the low-noise amplifier circuit has multiple gain levels, it can also optimize the consistency of the output current Idd of the amplifying transistor Ma under different gain levels, thereby improving the gain consistency of the low-noise amplifier circuit.

[0135] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A layout structure for a low-noise amplifier circuit, characterized in that, include: An amplifying transistor, the amplifying transistor including a first amplifying unit; A bias transistor includes a first bias unit and a second bias unit. The gate of the first bias unit is connected to the gate of the first amplification unit, the gate of the second bias unit is connected to the gate of the first amplification unit, the source of the first bias unit is connected to the source of the second bias unit, and the drain of the first bias unit is connected to the drain of the second bias unit. The first bias unit is disposed on a side adjacent to the first amplification unit. The second bias unit is spaced apart from the first bias unit by the first amplification unit.

2. The layout structure of the low-noise amplifier circuit according to claim 1, characterized in that, The first bias unit is disposed on one side of the first amplification unit in the first direction, and the second bias unit is disposed on the other side of the first amplification unit in the first direction.

3. The layout structure of the low-noise amplifier circuit according to claim 2, characterized in that, The amplifying transistor also includes a second amplifying unit; The first bias unit, the first amplification unit, and the second bias unit are sequentially disposed on one side of the second amplification unit in a first direction, and the first bias unit is located on the side of the first amplification unit away from the second amplification unit; The low-noise amplifier circuit further includes a first dummy unit, which is disposed on the side of the first bias unit away from the first amplification unit.

4. The layout structure of the low-noise amplifier circuit according to claim 3, characterized in that, The low-noise amplifier circuit further includes a second dummy unit, which is disposed on the side of the second amplifier unit away from the second bias circuit.

5. The layout structure of the low-noise amplifier circuit according to claim 3, characterized in that, The number of the second amplification unit is at least two; The bias transistor further includes a third bias unit, which is disposed between two adjacent second amplification units.

6. The layout structure of the low-noise amplifier circuit according to claim 2, characterized in that, The number of the second amplification units is at least two, and the first bias unit, the first amplification unit and the second bias unit are arranged sequentially between the two second amplification units.

7. The layout structure of the low-noise amplifier circuit according to any one of claims 3-6, characterized in that, The first amplification unit is a normally-on amplification unit, and the second amplification unit is used to be turned on according to the corresponding gain level control signal.

8. The layout structure of the low-noise amplifier circuit according to claim 1, characterized in that, The amplifying transistor further includes at least one third amplifying unit, which is located on one or both sides of the first amplifying unit in the second direction; The first bias unit is disposed on one side of the first amplification unit in the first direction; The second bias unit is disposed on one side of the third amplification unit in the first direction.

9. The layout structure of the low-noise amplifier circuit according to claim 8, characterized in that, The number of the second bias units is at least two, and each of the second bias units is disposed on one side of the third amplification unit in the first direction.

10. The layout structure of the low-noise amplifier circuit according to claim 8 or 9, characterized in that, The low-noise amplifier circuit also includes at least one seventh dummy unit; The number of the third amplification units is at least two, the at least two third amplification units are arranged along the second direction, and at least one of the third amplification units is provided with the seventh dummy unit on one side of the first direction.

11. The layout structure of the low-noise amplifier circuit according to claim 8, characterized in that, The low-noise amplifier circuit further includes a second amplification unit, which is located on one side of the first amplification unit in the first direction; At least two of the third amplification units are arranged along the first direction, and the first amplification unit, the second amplification unit, and the at least two of the third amplification units are arranged in an array.

12. The layout structure of the low-noise amplifier circuit according to any one of claims 8-11, characterized in that, The first amplification unit is a normally-on amplification unit; other amplification units besides the first amplification unit are used to be turned on according to the corresponding gain level control signal.

13. The layout structure of the low-noise amplifier circuit according to any one of claims 1-11, characterized in that, The low-noise amplifier circuit further includes at least two eighth dummy units, which are arranged opposite each other in a first direction and / or opposite each other in a second direction; The bias transistor and the amplification transistor are sandwiched between two oppositely arranged eighth dummy units.

14. The layout structure of the low-noise amplifier circuit according to claim 13, characterized in that, The bias transistor and the amplification transistor are located in the first layout region; The number of the eighth dummy units is four, and the four eighth dummy units are arranged around the perimeter of the first layout area.

15. The layout structure of the low-noise amplifier circuit according to claim 1, characterized in that, The low-noise amplifier circuit includes at least two amplifying transistors, wherein the two amplifying transistors are connected to form a common source and common gate structure.

16. The layout structure of the low-noise amplifier circuit according to claim 15, characterized in that, One amplifying transistor in the cascode structure is connected to the bias transistor, and the other amplifying transistor in the cascode structure receives the bias voltage.

17. The layout structure of the low-noise amplifier circuit according to claim 15, characterized in that, The low-noise amplifier circuit includes at least two bias transistors, and the two amplifying transistors in the cascode structure are respectively connected to the corresponding bias transistors.

18. The layout structure of the low-noise amplifier circuit according to claim 1, characterized in that: The amplifying transistor is disposed in the second layout region; The low-noise amplifier circuit further includes a ninth dummy unit and a tenth dummy unit, which are distributed on both sides of the second layout region along a first direction or a second direction; The ninth dummy unit and the tenth dummy unit are not connected to the amplifying transistor.

19. The layout structure of the low-noise amplifier circuit according to claim 18, characterized in that, The low-noise amplifier circuit also includes an eleventh dummy unit and a twelfth dummy unit; The eleventh dummy unit, the twelfth dummy unit, the ninth dummy unit, and the tenth dummy unit are arranged around the second layout area.

20. The layout structure of the low-noise amplifier circuit according to claim 18, characterized in that, The second layout region includes at least two sub-regions arranged along the second direction, each sub-region corresponding to at least one of the amplifying transistors, the amplifying transistors being disposed within the corresponding sub-region.

21. The layout structure of the low-noise amplifier circuit according to claim 20, characterized in that, The low-noise amplifier circuit further includes at least one thirteenth dummy unit, which is disposed in the second layout region and located between two adjacent sub-regions.

22. The layout structure of the low-noise amplifier circuit according to claim 18, characterized in that, The bias transistor is disposed in the second layout region.

23. A radio frequency chip, characterized in that, The layout structure includes the low-noise amplifier circuit as described in any one of claims 1-22.

24. A radio frequency front-end module, characterized in that, Including the radio frequency chip as described in claim 23.

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